1#-
2# Copyright (c) 2016 Landon Fuller <landon@landonf.org>
3# Copyright (c) 2017 The FreeBSD Foundation
4# All rights reserved.
5#
6# Portions of this software were developed by Landon Fuller
7# under sponsorship from the FreeBSD Foundation.
8#
9# Redistribution and use in source and binary forms, with or without
10# modification, are permitted provided that the following conditions
11# are met:
12# 1. Redistributions of source code must retain the above copyright
13#    notice, this list of conditions and the following disclaimer.
14# 2. Redistributions in binary form must reproduce the above copyright
15#    notice, this list of conditions and the following disclaimer in the
16#    documentation and/or other materials provided with the distribution.
17#
18# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21# IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
22# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
27# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# $FreeBSD$
30
31#include <sys/types.h>
32#include <sys/bus.h>
33
34#include <dev/bhnd/bhnd.h>
35
36INTERFACE bhnd_pwrctl_hostb;
37
38#
39# bhnd(4) PWRCTL host bridge interface.
40#
41# Provides a common interface to the clock hardware managed by a parent host
42# bridge (e.g. bhndb_pci(4)).
43#
44# Early PWRCTL chipsets[1] expose clock management via their host bridge
45# interface, requiring that a host bridge driver (e.g. bhndb(4)) work in
46# tandem with the ChipCommon-attached PWRCTL driver.
47#
48# [1] Currently, this is known to include PCI (not PCIe) devices, with
49# ChipCommon core revisions 0-9.
50#
51
52HEADER {
53	#include <dev/bhnd/bhnd.h>
54};
55
56CODE {
57	static bhnd_clksrc
58	bhnd_pwrctl_hostb_get_clksrc(device_t dev, device_t child,
59	    bhnd_clock clock)
60	{
61		return (BHND_CLKSRC_UNKNOWN);
62	}
63
64	static int
65	bhnd_pwrctl_hostb_gate_clock(device_t dev, device_t child,
66	    bhnd_clock clock)
67	{
68		return (ENODEV);
69	}
70
71	static int
72	bhnd_pwrctl_hostb_ungate_clock(device_t dev, device_t child,
73	    bhnd_clock clock)
74	{
75		return (ENODEV);
76	}
77
78};
79
80/**
81 * If supported by the chipset, return the clock source for the given clock.
82 *
83 * @param dev	The parent of @p child.
84 * @param child	The bhnd device requesting a clock source.
85 * @param clock	The clock for which a clock source will be returned.
86 *
87 * @retval	bhnd_clksrc		The clock source for @p clock.
88 * @retval	BHND_CLKSRC_UNKNOWN	If @p clock is unsupported, or its
89 *					clock source is not known to the bus.
90 */
91METHOD bhnd_clksrc get_clksrc {
92	device_t	dev;
93	device_t	child;
94	bhnd_clock	clock;
95} DEFAULT bhnd_pwrctl_hostb_get_clksrc;
96
97/**
98 * If supported by the chipset, gate the clock source for @p clock.
99 *
100 * @param dev	The parent of @p child.
101 * @param child	The bhnd device requesting clock gating.
102 * @param clock	The clock to be disabled.
103 *
104 * @retval 0		success
105 * @retval ENODEV	If bus-level clock source management is not supported.
106 * @retval ENXIO	If bus-level management of @p clock is not supported.
107 */
108METHOD int gate_clock {
109	device_t	dev;
110	device_t	child;
111	bhnd_clock	clock;
112} DEFAULT bhnd_pwrctl_hostb_gate_clock;
113
114/**
115 * If supported by the chipset, ungate the clock source for @p clock.
116 *
117 * @param dev	The parent of @p child.
118 * @param child	The bhnd device requesting clock gating.
119 * @param clock	The clock to be enabled.
120 *
121 * @retval 0		success
122 * @retval ENODEV	If bus-level clock source management is not supported.
123 * @retval ENXIO	If bus-level management of @p clock is not supported.
124 */
125METHOD int ungate_clock {
126	device_t	dev;
127	device_t	child;
128	bhnd_clock	clock;
129} DEFAULT bhnd_pwrctl_hostb_ungate_clock;