1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Broadcom Common PCI/PCIe Support. 35 * 36 * This base driver implementation is shared by the bhnd_pcib (root complex) 37 * and bhnd_pci_hostb (host bridge) drivers. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/systm.h> 46 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <machine/resource.h> 50 51 #include <dev/bhnd/bhnd.h> 52 #include <dev/mdio/mdio.h> 53 54 #include "bhnd_pcireg.h" 55 #include "bhnd_pcivar.h" 56 57 static int bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc); 58 static int bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc *sc, uint32_t cmd); 59 static int bhnd_pcie_mdio_enable(struct bhnd_pci_softc *sc); 60 static void bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc); 61 static int bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc *sc, 62 uint32_t cmd); 63 static int bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd, 64 uint16_t *data_read); 65 66 static struct bhnd_device_quirk bhnd_pci_quirks[]; 67 static struct bhnd_device_quirk bhnd_pcie_quirks[]; 68 69 #define BHND_PCI_QUIRKS bhnd_pci_quirks 70 #define BHND_PCIE_QUIRKS bhnd_pcie_quirks 71 #define BHND_PCI_DEV(_core, _desc, ...) \ 72 { BHND_DEVICE(BCM, _core, _desc, BHND_ ## _core ## _QUIRKS, \ 73 ## __VA_ARGS__), BHND_PCI_REGFMT_ ## _core } 74 75 static const struct bhnd_pci_device { 76 struct bhnd_device device; 77 bhnd_pci_regfmt_t regfmt; /**< register format */ 78 } bhnd_pci_devs[] = { 79 BHND_PCI_DEV(PCI, "Host-PCI bridge", BHND_DF_HOSTB), 80 BHND_PCI_DEV(PCI, "PCI-BHND bridge", BHND_DF_SOC), 81 BHND_PCI_DEV(PCIE, "PCIe-G1 Host-PCI bridge", BHND_DF_HOSTB), 82 BHND_PCI_DEV(PCIE, "PCIe-G1 PCI-BHND bridge", BHND_DF_SOC), 83 84 { BHND_DEVICE_END, 0 } 85 }; 86 87 /* Device quirks tables */ 88 static struct bhnd_device_quirk bhnd_pci_quirks[] = { BHND_DEVICE_QUIRK_END }; 89 static struct bhnd_device_quirk bhnd_pcie_quirks[] = { 90 BHND_CORE_QUIRK(HWREV_GTE(10), BHND_PCI_QUIRK_SD_C22_EXTADDR), 91 92 BHND_DEVICE_QUIRK_END 93 }; 94 95 #define BHND_PCIE_MDIO_CTL_DELAY 10 /**< usec delay required between 96 * MDIO_CTL/MDIO_DATA accesses. */ 97 #define BHND_PCIE_MDIO_RETRY_DELAY 2000 /**< usec delay before retrying 98 * BHND_PCIE_MDIOCTL_DONE. */ 99 #define BHND_PCIE_MDIO_RETRY_COUNT 200 /**< number of times to loop waiting 100 * for BHND_PCIE_MDIOCTL_DONE. */ 101 102 #define BHND_PCI_READ_4(_sc, _reg) \ 103 bhnd_bus_read_4((_sc)->mem_res, (_reg)) 104 #define BHND_PCI_WRITE_4(_sc, _reg, _val) \ 105 bhnd_bus_write_4((_sc)->mem_res, (_reg), (_val)) 106 107 #define BHND_PCIE_ASSERT(sc) \ 108 KASSERT(bhnd_get_class(sc->dev) == BHND_DEVCLASS_PCIE, \ 109 ("not a pcie device!")); 110 111 int 112 bhnd_pci_generic_probe(device_t dev) 113 { 114 const struct bhnd_device *id; 115 116 id = bhnd_device_lookup(dev, &bhnd_pci_devs[0].device, 117 sizeof(bhnd_pci_devs[0])); 118 if (id == NULL) 119 return (ENXIO); 120 121 bhnd_set_custom_core_desc(dev, id->desc); 122 return (BUS_PROBE_DEFAULT); 123 } 124 125 int 126 bhnd_pci_generic_attach(device_t dev) 127 { 128 struct bhnd_pci_softc *sc; 129 int error; 130 131 sc = device_get_softc(dev); 132 sc->dev = dev; 133 sc->quirks = bhnd_device_quirks(dev, &bhnd_pci_devs[0].device, 134 sizeof(bhnd_pci_devs[0])); 135 136 /* Allocate bus resources */ 137 sc->mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 138 RF_ACTIVE); 139 if (sc->mem_res == NULL) 140 return (ENXIO); 141 142 BHND_PCI_LOCK_INIT(sc); 143 144 /* Probe and attach children */ 145 if ((error = bus_generic_attach(dev))) 146 goto cleanup; 147 148 return (0); 149 150 cleanup: 151 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); 152 BHND_PCI_LOCK_DESTROY(sc); 153 154 return (error); 155 } 156 157 int 158 bhnd_pci_generic_detach(device_t dev) 159 { 160 struct bhnd_pci_softc *sc; 161 int error; 162 163 sc = device_get_softc(dev); 164 165 if ((error = bus_generic_detach(dev))) 166 return (error); 167 168 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); 169 170 BHND_PCI_LOCK_DESTROY(sc); 171 172 return (0); 173 } 174 175 static struct resource_list * 176 bhnd_pci_get_resource_list(device_t dev, device_t child) 177 { 178 struct bhnd_pci_devinfo *dinfo; 179 180 if (device_get_parent(child) != dev) 181 return (NULL); 182 183 dinfo = device_get_ivars(child); 184 return (&dinfo->resources); 185 } 186 187 static device_t 188 bhnd_pci_add_child(device_t dev, u_int order, const char *name, int unit) 189 { 190 struct bhnd_pci_devinfo *dinfo; 191 device_t child; 192 193 child = device_add_child_ordered(dev, order, name, unit); 194 if (child == NULL) 195 return (NULL); 196 197 dinfo = malloc(sizeof(struct bhnd_pci_devinfo), M_DEVBUF, M_NOWAIT); 198 if (dinfo == NULL) { 199 device_delete_child(dev, child); 200 return (NULL); 201 } 202 203 resource_list_init(&dinfo->resources); 204 205 device_set_ivars(child, dinfo); 206 return (child); 207 } 208 209 static void 210 bhnd_pci_child_deleted(device_t dev, device_t child) 211 { 212 struct bhnd_pci_devinfo *dinfo; 213 214 if (device_get_parent(child) != dev) 215 return; 216 217 dinfo = device_get_ivars(child); 218 if (dinfo != NULL) { 219 resource_list_free(&dinfo->resources); 220 free(dinfo, M_DEVBUF); 221 } 222 223 device_set_ivars(child, NULL); 224 } 225 226 int 227 bhnd_pci_generic_suspend(device_t dev) 228 { 229 return (bus_generic_suspend(dev)); 230 } 231 232 int 233 bhnd_pci_generic_resume(device_t dev) 234 { 235 return (bus_generic_resume(dev)); 236 } 237 238 /** 239 * Read a 32-bit PCIe TLP/DLLP/PLP protocol register. 240 * 241 * @param sc The bhndb_pci driver state. 242 * @param addr The protocol register offset. 243 */ 244 uint32_t 245 bhnd_pcie_read_proto_reg(struct bhnd_pci_softc *sc, uint32_t addr) 246 { 247 uint32_t val; 248 249 BHND_PCIE_ASSERT(sc); 250 251 BHND_PCI_LOCK(sc); 252 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_ADDR, addr); 253 val = BHND_PCI_READ_4(sc, BHND_PCIE_IND_DATA); 254 BHND_PCI_UNLOCK(sc); 255 256 return (val); 257 } 258 259 /** 260 * Write a 32-bit PCIe TLP/DLLP/PLP protocol register value. 261 * 262 * @param sc The bhndb_pci driver state. 263 * @param addr The protocol register offset. 264 * @param val The value to write to @p addr. 265 */ 266 void 267 bhnd_pcie_write_proto_reg(struct bhnd_pci_softc *sc, uint32_t addr, 268 uint32_t val) 269 { 270 BHND_PCIE_ASSERT(sc); 271 272 BHND_PCI_LOCK(sc); 273 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_ADDR, addr); 274 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_DATA, val); 275 BHND_PCI_UNLOCK(sc); 276 } 277 278 /* Spin until the MDIO device reports itself as idle, or timeout is reached. */ 279 static int 280 bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc) 281 { 282 uint32_t ctl; 283 284 /* Spin waiting for the BUSY flag to clear */ 285 for (int i = 0; i < BHND_PCIE_MDIO_RETRY_COUNT; i++) { 286 ctl = BHND_PCI_READ_4(sc, BHND_PCIE_MDIO_CTL); 287 if ((ctl & BHND_PCIE_MDIOCTL_DONE)) 288 return (0); 289 290 DELAY(BHND_PCIE_MDIO_RETRY_DELAY); 291 } 292 293 return (ETIMEDOUT); 294 } 295 296 297 /** 298 * Write an MDIO IOCTL and wait for completion. 299 */ 300 static int 301 bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc *sc, uint32_t cmd) 302 { 303 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED); 304 305 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_CTL, cmd); 306 DELAY(BHND_PCIE_MDIO_CTL_DELAY); 307 return (0); 308 } 309 310 /** 311 * Enable MDIO device 312 */ 313 static int 314 bhnd_pcie_mdio_enable(struct bhnd_pci_softc *sc) 315 { 316 uint32_t ctl; 317 318 BHND_PCIE_ASSERT(sc); 319 320 /* Enable MDIO clock and preamble mode */ 321 ctl = BHND_PCIE_MDIOCTL_PREAM_EN|BHND_PCIE_MDIOCTL_DIVISOR_VAL; 322 return (bhnd_pcie_mdio_ioctl(sc, ctl)); 323 } 324 325 /** 326 * Disable MDIO device. 327 */ 328 static void 329 bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc) 330 { 331 if (bhnd_pcie_mdio_ioctl(sc, 0)) 332 device_printf(sc->dev, "failed to disable MDIO clock\n"); 333 } 334 335 336 /** 337 * Issue a write command and wait for completion 338 */ 339 static int 340 bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc *sc, uint32_t cmd) 341 { 342 int error; 343 344 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED); 345 346 cmd |= BHND_PCIE_MDIODATA_START|BHND_PCIE_MDIODATA_TA|BHND_PCIE_MDIODATA_CMD_WRITE; 347 348 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_DATA, cmd); 349 DELAY(BHND_PCIE_MDIO_CTL_DELAY); 350 351 if ((error = bhnd_pcie_mdio_wait_idle(sc))) 352 return (error); 353 354 return (0); 355 } 356 357 /** 358 * Issue an an MDIO read command, wait for completion, and return 359 * the result in @p data_read. 360 */ 361 static int 362 bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd, 363 uint16_t *data_read) 364 { 365 int error; 366 367 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED); 368 369 cmd |= BHND_PCIE_MDIODATA_START|BHND_PCIE_MDIODATA_TA|BHND_PCIE_MDIODATA_CMD_READ; 370 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_DATA, cmd); 371 DELAY(BHND_PCIE_MDIO_CTL_DELAY); 372 373 if ((error = bhnd_pcie_mdio_wait_idle(sc))) 374 return (error); 375 376 *data_read = (BHND_PCI_READ_4(sc, BHND_PCIE_MDIO_DATA) & 377 BHND_PCIE_MDIODATA_DATA_MASK); 378 return (0); 379 } 380 381 382 int 383 bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy, int reg) 384 { 385 uint32_t cmd; 386 uint16_t val; 387 int error; 388 389 /* Enable MDIO access */ 390 BHND_PCI_LOCK(sc); 391 bhnd_pcie_mdio_enable(sc); 392 393 /* Issue the read */ 394 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg); 395 error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val); 396 397 /* Disable MDIO access */ 398 bhnd_pcie_mdio_disable(sc); 399 BHND_PCI_UNLOCK(sc); 400 401 if (error) 402 return (~0U); 403 404 return (val); 405 } 406 407 int 408 bhnd_pcie_mdio_write(struct bhnd_pci_softc *sc, int phy, int reg, int val) 409 { 410 uint32_t cmd; 411 int error; 412 413 /* Enable MDIO access */ 414 BHND_PCI_LOCK(sc); 415 bhnd_pcie_mdio_enable(sc); 416 417 /* Issue the write */ 418 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) | (val & BHND_PCIE_MDIODATA_DATA_MASK); 419 error = bhnd_pcie_mdio_cmd_write(sc, cmd); 420 421 /* Disable MDIO access */ 422 bhnd_pcie_mdio_disable(sc); 423 BHND_PCI_UNLOCK(sc); 424 425 return (error); 426 } 427 428 int 429 bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc *sc, int phy, int devaddr, 430 int reg) 431 { 432 uint32_t cmd; 433 uint16_t val; 434 int error; 435 436 if (devaddr == MDIO_DEVADDR_NONE) 437 return (bhnd_pcie_mdio_read(sc, phy, reg)); 438 439 /* Extended register access is only supported for the SerDes device, 440 * using the non-standard C22 extended address mechanism */ 441 if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR) || 442 phy != BHND_PCIE_PHYADDR_SD) 443 { 444 return (~0U); 445 } 446 447 /* Enable MDIO access */ 448 BHND_PCI_LOCK(sc); 449 bhnd_pcie_mdio_enable(sc); 450 451 /* Write the block address to the address extension register */ 452 cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr; 453 if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd))) 454 goto cleanup; 455 456 /* Issue the read */ 457 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg); 458 error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val); 459 460 cleanup: 461 bhnd_pcie_mdio_disable(sc); 462 BHND_PCI_UNLOCK(sc); 463 464 if (error) 465 return (~0U); 466 467 return (val); 468 } 469 470 int 471 bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc *sc, int phy, int devaddr, 472 int reg, int val) 473 { 474 uint32_t cmd; 475 int error; 476 477 if (devaddr == MDIO_DEVADDR_NONE) 478 return (bhnd_pcie_mdio_write(sc, phy, reg, val)); 479 480 /* Extended register access is only supported for the SerDes device, 481 * using the non-standard C22 extended address mechanism */ 482 if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR) || 483 phy != BHND_PCIE_PHYADDR_SD) 484 { 485 return (~0U); 486 } 487 488 /* Enable MDIO access */ 489 BHND_PCI_LOCK(sc); 490 bhnd_pcie_mdio_enable(sc); 491 492 /* Write the block address to the address extension register */ 493 cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr; 494 if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd))) 495 goto cleanup; 496 497 /* Issue the write */ 498 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) | 499 (val & BHND_PCIE_MDIODATA_DATA_MASK); 500 error = bhnd_pcie_mdio_cmd_write(sc, cmd); 501 502 cleanup: 503 bhnd_pcie_mdio_disable(sc); 504 BHND_PCI_UNLOCK(sc); 505 506 return (error); 507 } 508 509 static device_method_t bhnd_pci_methods[] = { 510 /* Device interface */ 511 DEVMETHOD(device_probe, bhnd_pci_generic_probe), 512 DEVMETHOD(device_attach, bhnd_pci_generic_attach), 513 DEVMETHOD(device_detach, bhnd_pci_generic_detach), 514 DEVMETHOD(device_suspend, bhnd_pci_generic_suspend), 515 DEVMETHOD(device_resume, bhnd_pci_generic_resume), 516 517 /* Bus interface */ 518 DEVMETHOD(bus_add_child, bhnd_pci_add_child), 519 DEVMETHOD(bus_child_deleted, bhnd_pci_child_deleted), 520 DEVMETHOD(bus_print_child, bus_generic_print_child), 521 DEVMETHOD(bus_get_resource_list, bhnd_pci_get_resource_list), 522 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 523 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 524 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 525 526 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 527 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 528 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 529 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 530 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 531 532 DEVMETHOD_END 533 }; 534 535 DEFINE_CLASS_0(bhnd_pci, bhnd_pci_driver, bhnd_pci_methods, sizeof(struct bhnd_pci_softc)); 536 MODULE_DEPEND(bhnd_pci, bhnd, 1, 1, 1); 537 MODULE_DEPEND(bhnd_pci, pci, 1, 1, 1); 538 MODULE_VERSION(bhnd_pci, 1); 539