1bb64eeccSAdrian Chadd /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 36e778a7eSPedro F. Giffuni * 4bb64eeccSAdrian Chadd * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5bb64eeccSAdrian Chadd * All rights reserved. 6bb64eeccSAdrian Chadd * 7bb64eeccSAdrian Chadd * Redistribution and use in source and binary forms, with or without 8bb64eeccSAdrian Chadd * modification, are permitted provided that the following conditions 9bb64eeccSAdrian Chadd * are met: 10bb64eeccSAdrian Chadd * 1. Redistributions of source code must retain the above copyright 11bb64eeccSAdrian Chadd * notice, this list of conditions and the following disclaimer, 12bb64eeccSAdrian Chadd * without modification. 13bb64eeccSAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14bb64eeccSAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15bb64eeccSAdrian Chadd * redistribution must be conditioned upon including a substantially 16bb64eeccSAdrian Chadd * similar Disclaimer requirement for further binary redistribution. 17bb64eeccSAdrian Chadd * 18bb64eeccSAdrian Chadd * NO WARRANTY 19bb64eeccSAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20bb64eeccSAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21bb64eeccSAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22bb64eeccSAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23bb64eeccSAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24bb64eeccSAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25bb64eeccSAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26bb64eeccSAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27bb64eeccSAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28bb64eeccSAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29bb64eeccSAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES. 30bb64eeccSAdrian Chadd * 31bb64eeccSAdrian Chadd */ 32bb64eeccSAdrian Chadd 33bb64eeccSAdrian Chadd #ifndef _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ 34bb64eeccSAdrian Chadd #define _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ 35bb64eeccSAdrian Chadd 36bb64eeccSAdrian Chadd /* 37bb64eeccSAdrian Chadd * PCI/PCIe-Gen1 Host Bridge definitions. 38bb64eeccSAdrian Chadd */ 39bb64eeccSAdrian Chadd 40bb64eeccSAdrian Chadd #include <sys/param.h> 41bb64eeccSAdrian Chadd #include <sys/bus.h> 42bb64eeccSAdrian Chadd 43bb64eeccSAdrian Chadd #include "bhnd_pcivar.h" 44bb64eeccSAdrian Chadd 45bb64eeccSAdrian Chadd DECLARE_CLASS(bhnd_pci_hostb_driver); 46bb64eeccSAdrian Chadd 478ef24a0dSAdrian Chadd /** 48bb64eeccSAdrian Chadd * PCI/PCIe-Gen1 endpoint-mode device quirks 49bb64eeccSAdrian Chadd */ 50bb64eeccSAdrian Chadd enum { 51bb64eeccSAdrian Chadd /** No quirks */ 52bb64eeccSAdrian Chadd BHND_PCI_QUIRK_NONE = 0, 53bb64eeccSAdrian Chadd 54bb64eeccSAdrian Chadd /** 55bb64eeccSAdrian Chadd * SBTOPCI_PREF and SBTOPCI_BURST must be set on the 56bb64eeccSAdrian Chadd * SSB_PCICORE_SBTOPCI2 register. 57bb64eeccSAdrian Chadd */ 58bb64eeccSAdrian Chadd BHND_PCI_QUIRK_SBTOPCI2_PREF_BURST = (1<<1), 59bb64eeccSAdrian Chadd 60bb64eeccSAdrian Chadd /** 61bb64eeccSAdrian Chadd * SBTOPCI_RC_READMULTI must be set on the SSB_PCICORE_SBTOPCI2 62bb64eeccSAdrian Chadd * register. 63bb64eeccSAdrian Chadd */ 64bb64eeccSAdrian Chadd BHND_PCI_QUIRK_SBTOPCI2_READMULTI = (1<<2), 65bb64eeccSAdrian Chadd 66bb64eeccSAdrian Chadd /** 67bb64eeccSAdrian Chadd * PCI CLKRUN# should be disabled on attach (via CLKRUN_DSBL). 68bb64eeccSAdrian Chadd * 69bb64eeccSAdrian Chadd * The purpose of this work-around is unclear; there is some 70bb64eeccSAdrian Chadd * documentation regarding earlier Broadcom drivers supporting 71bb64eeccSAdrian Chadd * a "force CLKRUN#" *enable* registry key for use on mobile 72bb64eeccSAdrian Chadd * hardware. 73bb64eeccSAdrian Chadd */ 74bb64eeccSAdrian Chadd BHND_PCI_QUIRK_CLKRUN_DSBL = (1<<3), 75bb64eeccSAdrian Chadd 76bb64eeccSAdrian Chadd /** 778ef24a0dSAdrian Chadd * On PCI-attached BCM4321CB* boards, the PCI latency timer must be set 788ef24a0dSAdrian Chadd * to 960ns on initial attach. 798ef24a0dSAdrian Chadd */ 808ef24a0dSAdrian Chadd BHND_PCI_QUIRK_960NS_LATTIM_OVR = (1<<4), 818ef24a0dSAdrian Chadd 828ef24a0dSAdrian Chadd /** 83bb64eeccSAdrian Chadd * TLP workaround for unmatched address handling is required. 84bb64eeccSAdrian Chadd * 85bb64eeccSAdrian Chadd * This TLP workaround will enable setting of the PCIe UR status bit 86bb64eeccSAdrian Chadd * on memory access to an unmatched address. 87bb64eeccSAdrian Chadd */ 888ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_UR_STATUS_FIX = (1<<5), 89bb64eeccSAdrian Chadd 90bb64eeccSAdrian Chadd /** 91bb64eeccSAdrian Chadd * PCI-PM power management must be explicitly enabled via 92bb64eeccSAdrian Chadd * the data link control register. 93bb64eeccSAdrian Chadd */ 948ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_PCIPM_REQEN = (1<<6), 95bb64eeccSAdrian Chadd 96bb64eeccSAdrian Chadd /** 97bb64eeccSAdrian Chadd * Fix L0s to L0 exit transition on SerDes <= rev9 devices. 98bb64eeccSAdrian Chadd * 99bb64eeccSAdrian Chadd * On these devices, PCIe/SerDes symbol lock can be lost if the 100bb64eeccSAdrian Chadd * reference clock has not fully stabilized during the L0s to L0 101bb64eeccSAdrian Chadd * exit transition, triggering an internal reset of the chip. 102bb64eeccSAdrian Chadd * 103bb64eeccSAdrian Chadd * The SerDes RX CDR phase lock timers and proportional/integral 104bb64eeccSAdrian Chadd * filters must be tweaked to ensure the CDR has fully stabilized 105bb64eeccSAdrian Chadd * before asserting receive sequencer completion. 106bb64eeccSAdrian Chadd */ 1078ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_SDR9_L0s_HANG = (1<<7), 108bb64eeccSAdrian Chadd 109bb64eeccSAdrian Chadd /** 110bb64eeccSAdrian Chadd * The idle time for entering L1 low-power state must be 111bb64eeccSAdrian Chadd * explicitly set (to 114ns) to fix slow L1->L0 transition issues. 112bb64eeccSAdrian Chadd */ 1138ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_L1_IDLE_THRESH = (1<<8), 114bb64eeccSAdrian Chadd 115bb64eeccSAdrian Chadd /** 116bb64eeccSAdrian Chadd * The ASPM L1 entry timer should be extended for better performance, 117bb64eeccSAdrian Chadd * and restored for better power savings. 118bb64eeccSAdrian Chadd */ 1198ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_L1_TIMER_PERF = (1<<9), 120bb64eeccSAdrian Chadd 121bb64eeccSAdrian Chadd /** 122bb64eeccSAdrian Chadd * ASPM and ECPM settings must be overridden manually. 1238ef24a0dSAdrian Chadd * Applies to 4311B0/4321B1 chipset revisions. 124bb64eeccSAdrian Chadd * 125bb64eeccSAdrian Chadd * The override behavior is controlled by the BHND_BFL2_PCIEWAR_OVR 1268ef24a0dSAdrian Chadd * flag; if set, ASPM and CLKREQ should be explicitly disabled. If not 1278ef24a0dSAdrian Chadd * set, they should be explicitly enabled. 128bb64eeccSAdrian Chadd * 129bb64eeccSAdrian Chadd * Attach/Resume: 1308ef24a0dSAdrian Chadd * - Update SRSH_ASPM_ENB flag in the SPROM ASPM register. 1318ef24a0dSAdrian Chadd * - Update SRSH_CLKREQ_ENB flag in the SPROM CLKREQ_REV5 1328ef24a0dSAdrian Chadd * register. 1338ef24a0dSAdrian Chadd * - Update ASPM L0S/L1 flags in PCIER_LINK_CTL register. 1348ef24a0dSAdrian Chadd * - Clear CLKREQ (ECPM) flag in PCIER_LINK_CTL register. 135bb64eeccSAdrian Chadd * 1368ef24a0dSAdrian Chadd * Suspend: 1378ef24a0dSAdrian Chadd * - Clear ASPM L1 flag in the PCIER_LINK_CTL register. 1388ef24a0dSAdrian Chadd * - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register. 1398ef24a0dSAdrian Chadd * 1408ef24a0dSAdrian Chadd * Detach: 1418ef24a0dSAdrian Chadd * - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register. 142bb64eeccSAdrian Chadd */ 1438ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_ASPM_OVR = (1<<10), 144bb64eeccSAdrian Chadd 145bb64eeccSAdrian Chadd /** 146d567592bSAdrian Chadd * A subset of Apple devices did not set the BHND_BFL2_PCIEWAR_OVR 147d567592bSAdrian Chadd * flag in SPROM; on these devices, the BHND_BFL2_PCIEWAR_OVR flag 148d567592bSAdrian Chadd * should always be treated as if set. 149d567592bSAdrian Chadd */ 1508ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_BFL2_PCIEWAR_EN = (1<<11), 151d567592bSAdrian Chadd 152d567592bSAdrian Chadd /** 153bb64eeccSAdrian Chadd * Fix SerDes polarity on SerDes <= rev9 devices. 154bb64eeccSAdrian Chadd * 155bb64eeccSAdrian Chadd * The SerDes polarity must be saved at device attachment, and 156bb64eeccSAdrian Chadd * restored on suspend/resume. 157bb64eeccSAdrian Chadd */ 1588ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_SDR9_POLARITY = (1<<12), 159bb64eeccSAdrian Chadd 160bb64eeccSAdrian Chadd /** 161bb64eeccSAdrian Chadd * SerDes PLL down flag must be manually disabled (by ChipCommon) on 162bb64eeccSAdrian Chadd * resume. 163bb64eeccSAdrian Chadd */ 1648ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_SERDES_NOPLLDOWN = (1<<13), 165bb64eeccSAdrian Chadd 166bb64eeccSAdrian Chadd /** 167bb64eeccSAdrian Chadd * On attach and resume, consult the SPROM to determine whether 168bb64eeccSAdrian Chadd * the L2/L3-Ready w/o PCI RESET work-around must be applied. 169bb64eeccSAdrian Chadd * 170bb64eeccSAdrian Chadd * If L23READY_EXIT_NOPRST is not already set in the SPROM, set it 171bb64eeccSAdrian Chadd */ 1728ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET = (1<<14), 173bb64eeccSAdrian Chadd 174bb64eeccSAdrian Chadd /** 175bb64eeccSAdrian Chadd * The PCIe SerDes PLL must be configured to not retry the startup 176bb64eeccSAdrian Chadd * sequence upon frequency detection failure on SerDes <= rev9 devices 177bb64eeccSAdrian Chadd * 1788ef24a0dSAdrian Chadd * The issue this workaround resolves is unknown. 179bb64eeccSAdrian Chadd */ 180d567592bSAdrian Chadd BHND_PCIE_QUIRK_SDR9_NO_FREQRETRY = (1<<15), 1818ef24a0dSAdrian Chadd 1828ef24a0dSAdrian Chadd /** 1838ef24a0dSAdrian Chadd * Common flag for quirks that require PCIe SerDes TX 1848ef24a0dSAdrian Chadd * drive strength adjustment. 1858ef24a0dSAdrian Chadd * 1868ef24a0dSAdrian Chadd * Only applies to PCIe >= rev10 devices. 1878ef24a0dSAdrian Chadd */ 1888ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST = (1<<16), 1898ef24a0dSAdrian Chadd 1908ef24a0dSAdrian Chadd /** 1918ef24a0dSAdrian Chadd * On Apple BCM94322X9 devices, the PCIe SerDes TX drive strength 1928ef24a0dSAdrian Chadd * should be set to 700mV. 1938ef24a0dSAdrian Chadd * 1948ef24a0dSAdrian Chadd * The exact issue is unknown, but presumably this workaround 1958ef24a0dSAdrian Chadd * resolves signal integrity issues with these devices. 1968ef24a0dSAdrian Chadd * 1978ef24a0dSAdrian Chadd * Only applies to PCIe >= rev10 devices. 1988ef24a0dSAdrian Chadd */ 1998ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_SERDES_TXDRV_700MV = (1<<17) | 2008ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST, 2018ef24a0dSAdrian Chadd 2028ef24a0dSAdrian Chadd /** 2038ef24a0dSAdrian Chadd * On some Apple BCM4331-based devices, the PCIe SerDes TX drive 2048ef24a0dSAdrian Chadd * strength should be set to its maximum. 2058ef24a0dSAdrian Chadd * 2068ef24a0dSAdrian Chadd * The exact issue is unknown, but presumably this workaround 2078ef24a0dSAdrian Chadd * resolves signal integrity issues with these devices. 2088ef24a0dSAdrian Chadd */ 2098ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_SERDES_TXDRV_MAX = (1<<18) | 2108ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST, 2118ef24a0dSAdrian Chadd 2128ef24a0dSAdrian Chadd /** 2138ef24a0dSAdrian Chadd * PCIe cores prior to rev18 do not support an MRRS larger than 2148ef24a0dSAdrian Chadd * 128 bytes. 2158ef24a0dSAdrian Chadd */ 2168ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_MAX_MRRS_128 = (1<<19), 2178ef24a0dSAdrian Chadd 2188ef24a0dSAdrian Chadd /** 2198ef24a0dSAdrian Chadd * The PCIe core should be configured with an MRRS of 512 bytes. 2208ef24a0dSAdrian Chadd */ 2218ef24a0dSAdrian Chadd BHND_PCIE_QUIRK_DEFAULT_MRRS_512 = (1<<20), 222bb64eeccSAdrian Chadd }; 223bb64eeccSAdrian Chadd 224bb64eeccSAdrian Chadd /** 225bb64eeccSAdrian Chadd * bhnd_pci_hostb driver instance state. 226bb64eeccSAdrian Chadd */ 227bb64eeccSAdrian Chadd struct bhnd_pcihb_softc { 228bb64eeccSAdrian Chadd struct bhnd_pci_softc common; /**< common bhnd_pci state */ 2298ef24a0dSAdrian Chadd device_t dev; 2308ef24a0dSAdrian Chadd device_t pci_dev; /**< host PCI device */ 231bb64eeccSAdrian Chadd uint32_t quirks; /**< hostb device quirks */ 232bb64eeccSAdrian Chadd 2338ef24a0dSAdrian Chadd /** BHND_PCIE_QUIRK_ASPM_OVR state. */ 2348ef24a0dSAdrian Chadd struct { 2358ef24a0dSAdrian Chadd /** 2368ef24a0dSAdrian Chadd * ASPM/CLKREQ override setting. 2378ef24a0dSAdrian Chadd * 2388ef24a0dSAdrian Chadd * If true, ASPM/CLKREQ should be overridden as enabled. 2398ef24a0dSAdrian Chadd * If false, ASPM/CLKREQ should be overridden as disabled. 2408ef24a0dSAdrian Chadd */ 2418ef24a0dSAdrian Chadd bool aspm_en; 2428ef24a0dSAdrian Chadd } aspm_quirk_override; 2438ef24a0dSAdrian Chadd 244bb64eeccSAdrian Chadd /** BHND_PCIE_QUIRK_SDR9_POLARITY state. */ 245bb64eeccSAdrian Chadd struct { 246bb64eeccSAdrian Chadd /** 247bb64eeccSAdrian Chadd * PCIe SerDes RX polarity. 248bb64eeccSAdrian Chadd * 249bb64eeccSAdrian Chadd * Initialized to the PCIe link's RX polarity 250bb64eeccSAdrian Chadd * at attach time. This is used to restore the 251bb64eeccSAdrian Chadd * correct polarity on resume */ 252bb64eeccSAdrian Chadd bool inv; 253bb64eeccSAdrian Chadd } sdr9_quirk_polarity; 254bb64eeccSAdrian Chadd }; 255bb64eeccSAdrian Chadd 256bb64eeccSAdrian Chadd #endif /* _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ */ 257