1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ 35 #define _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ 36 37 /* 38 * PCI/PCIe-Gen1 Host Bridge definitions. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 44 #include "bhnd_pcivar.h" 45 46 DECLARE_CLASS(bhnd_pci_hostb_driver); 47 48 /** 49 * PCI/PCIe-Gen1 endpoint-mode device quirks 50 */ 51 enum { 52 /** No quirks */ 53 BHND_PCI_QUIRK_NONE = 0, 54 55 /** 56 * SBTOPCI_PREF and SBTOPCI_BURST must be set on the 57 * SSB_PCICORE_SBTOPCI2 register. 58 */ 59 BHND_PCI_QUIRK_SBTOPCI2_PREF_BURST = (1<<1), 60 61 /** 62 * SBTOPCI_RC_READMULTI must be set on the SSB_PCICORE_SBTOPCI2 63 * register. 64 */ 65 BHND_PCI_QUIRK_SBTOPCI2_READMULTI = (1<<2), 66 67 /** 68 * PCI CLKRUN# should be disabled on attach (via CLKRUN_DSBL). 69 * 70 * The purpose of this work-around is unclear; there is some 71 * documentation regarding earlier Broadcom drivers supporting 72 * a "force CLKRUN#" *enable* registry key for use on mobile 73 * hardware. 74 */ 75 BHND_PCI_QUIRK_CLKRUN_DSBL = (1<<3), 76 77 /** 78 * On PCI-attached BCM4321CB* boards, the PCI latency timer must be set 79 * to 960ns on initial attach. 80 */ 81 BHND_PCI_QUIRK_960NS_LATTIM_OVR = (1<<4), 82 83 /** 84 * TLP workaround for unmatched address handling is required. 85 * 86 * This TLP workaround will enable setting of the PCIe UR status bit 87 * on memory access to an unmatched address. 88 */ 89 BHND_PCIE_QUIRK_UR_STATUS_FIX = (1<<5), 90 91 /** 92 * PCI-PM power management must be explicitly enabled via 93 * the data link control register. 94 */ 95 BHND_PCIE_QUIRK_PCIPM_REQEN = (1<<6), 96 97 /** 98 * Fix L0s to L0 exit transition on SerDes <= rev9 devices. 99 * 100 * On these devices, PCIe/SerDes symbol lock can be lost if the 101 * reference clock has not fully stabilized during the L0s to L0 102 * exit transition, triggering an internal reset of the chip. 103 * 104 * The SerDes RX CDR phase lock timers and proportional/integral 105 * filters must be tweaked to ensure the CDR has fully stabilized 106 * before asserting receive sequencer completion. 107 */ 108 BHND_PCIE_QUIRK_SDR9_L0s_HANG = (1<<7), 109 110 /** 111 * The idle time for entering L1 low-power state must be 112 * explicitly set (to 114ns) to fix slow L1->L0 transition issues. 113 */ 114 BHND_PCIE_QUIRK_L1_IDLE_THRESH = (1<<8), 115 116 /** 117 * The ASPM L1 entry timer should be extended for better performance, 118 * and restored for better power savings. 119 */ 120 BHND_PCIE_QUIRK_L1_TIMER_PERF = (1<<9), 121 122 /** 123 * ASPM and ECPM settings must be overridden manually. 124 * Applies to 4311B0/4321B1 chipset revisions. 125 * 126 * The override behavior is controlled by the BHND_BFL2_PCIEWAR_OVR 127 * flag; if set, ASPM and CLKREQ should be explicitly disabled. If not 128 * set, they should be explicitly enabled. 129 * 130 * Attach/Resume: 131 * - Update SRSH_ASPM_ENB flag in the SPROM ASPM register. 132 * - Update SRSH_CLKREQ_ENB flag in the SPROM CLKREQ_REV5 133 * register. 134 * - Update ASPM L0S/L1 flags in PCIER_LINK_CTL register. 135 * - Clear CLKREQ (ECPM) flag in PCIER_LINK_CTL register. 136 * 137 * Suspend: 138 * - Clear ASPM L1 flag in the PCIER_LINK_CTL register. 139 * - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register. 140 * 141 * Detach: 142 * - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register. 143 */ 144 BHND_PCIE_QUIRK_ASPM_OVR = (1<<10), 145 146 /** 147 * A subset of Apple devices did not set the BHND_BFL2_PCIEWAR_OVR 148 * flag in SPROM; on these devices, the BHND_BFL2_PCIEWAR_OVR flag 149 * should always be treated as if set. 150 */ 151 BHND_PCIE_QUIRK_BFL2_PCIEWAR_EN = (1<<11), 152 153 /** 154 * Fix SerDes polarity on SerDes <= rev9 devices. 155 * 156 * The SerDes polarity must be saved at device attachment, and 157 * restored on suspend/resume. 158 */ 159 BHND_PCIE_QUIRK_SDR9_POLARITY = (1<<12), 160 161 /** 162 * SerDes PLL down flag must be manually disabled (by ChipCommon) on 163 * resume. 164 */ 165 BHND_PCIE_QUIRK_SERDES_NOPLLDOWN = (1<<13), 166 167 /** 168 * On attach and resume, consult the SPROM to determine whether 169 * the L2/L3-Ready w/o PCI RESET work-around must be applied. 170 * 171 * If L23READY_EXIT_NOPRST is not already set in the SPROM, set it 172 */ 173 BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET = (1<<14), 174 175 /** 176 * The PCIe SerDes PLL must be configured to not retry the startup 177 * sequence upon frequency detection failure on SerDes <= rev9 devices 178 * 179 * The issue this workaround resolves is unknown. 180 */ 181 BHND_PCIE_QUIRK_SDR9_NO_FREQRETRY = (1<<15), 182 183 /** 184 * Common flag for quirks that require PCIe SerDes TX 185 * drive strength adjustment. 186 * 187 * Only applies to PCIe >= rev10 devices. 188 */ 189 BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST = (1<<16), 190 191 /** 192 * On Apple BCM94322X9 devices, the PCIe SerDes TX drive strength 193 * should be set to 700mV. 194 * 195 * The exact issue is unknown, but presumably this workaround 196 * resolves signal integrity issues with these devices. 197 * 198 * Only applies to PCIe >= rev10 devices. 199 */ 200 BHND_PCIE_QUIRK_SERDES_TXDRV_700MV = (1<<17) | 201 BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST, 202 203 /** 204 * On some Apple BCM4331-based devices, the PCIe SerDes TX drive 205 * strength should be set to its maximum. 206 * 207 * The exact issue is unknown, but presumably this workaround 208 * resolves signal integrity issues with these devices. 209 */ 210 BHND_PCIE_QUIRK_SERDES_TXDRV_MAX = (1<<18) | 211 BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST, 212 213 /** 214 * PCIe cores prior to rev18 do not support an MRRS larger than 215 * 128 bytes. 216 */ 217 BHND_PCIE_QUIRK_MAX_MRRS_128 = (1<<19), 218 219 /** 220 * The PCIe core should be configured with an MRRS of 512 bytes. 221 */ 222 BHND_PCIE_QUIRK_DEFAULT_MRRS_512 = (1<<20), 223 }; 224 225 /** 226 * bhnd_pci_hostb driver instance state. 227 */ 228 struct bhnd_pcihb_softc { 229 struct bhnd_pci_softc common; /**< common bhnd_pci state */ 230 device_t dev; 231 device_t pci_dev; /**< host PCI device */ 232 uint32_t quirks; /**< hostb device quirks */ 233 234 /** BHND_PCIE_QUIRK_ASPM_OVR state. */ 235 struct { 236 /** 237 * ASPM/CLKREQ override setting. 238 * 239 * If true, ASPM/CLKREQ should be overridden as enabled. 240 * If false, ASPM/CLKREQ should be overridden as disabled. 241 */ 242 bool aspm_en; 243 } aspm_quirk_override; 244 245 /** BHND_PCIE_QUIRK_SDR9_POLARITY state. */ 246 struct { 247 /** 248 * PCIe SerDes RX polarity. 249 * 250 * Initialized to the PCIe link's RX polarity 251 * at attach time. This is used to restore the 252 * correct polarity on resume */ 253 bool inv; 254 } sdr9_quirk_polarity; 255 }; 256 257 258 #endif /* _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ */ 259