14ad7e9b0SAdrian Chadd /*- 26e778a7eSPedro F. Giffuni * SPDX-License-Identifier: ISC 36e778a7eSPedro F. Giffuni * 44ad7e9b0SAdrian Chadd * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 54ad7e9b0SAdrian Chadd * Copyright (c) 2010 Broadcom Corporation 64ad7e9b0SAdrian Chadd * All rights reserved. 74ad7e9b0SAdrian Chadd * 84ad7e9b0SAdrian Chadd * This file is derived from the hndsoc.h, pci_core.h, and pcie_core.h headers 94ad7e9b0SAdrian Chadd * distributed with Broadcom's initial brcm80211 Linux driver release, as 104ad7e9b0SAdrian Chadd * contributed to the Linux staging repository. 114ad7e9b0SAdrian Chadd * 124ad7e9b0SAdrian Chadd * Permission to use, copy, modify, and/or distribute this software for any 134ad7e9b0SAdrian Chadd * purpose with or without fee is hereby granted, provided that the above 144ad7e9b0SAdrian Chadd * copyright notice and this permission notice appear in all copies. 154ad7e9b0SAdrian Chadd * 164ad7e9b0SAdrian Chadd * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 174ad7e9b0SAdrian Chadd * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 184ad7e9b0SAdrian Chadd * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 194ad7e9b0SAdrian Chadd * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 204ad7e9b0SAdrian Chadd * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 214ad7e9b0SAdrian Chadd * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 224ad7e9b0SAdrian Chadd * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 234ad7e9b0SAdrian Chadd */ 244ad7e9b0SAdrian Chadd 254ad7e9b0SAdrian Chadd #ifndef _BHND_CORES_PCI_BHND_PCIREG_H_ 264ad7e9b0SAdrian Chadd #define _BHND_CORES_PCI_BHND_PCIREG_H_ 274ad7e9b0SAdrian Chadd 284ad7e9b0SAdrian Chadd /* 294ad7e9b0SAdrian Chadd * PCI/PCIe-Gen1 DMA Constants 304ad7e9b0SAdrian Chadd */ 314ad7e9b0SAdrian Chadd 329ed45324SLandon J. Fuller #define BHND_PCI_DMA32_TRANSLATION 0x40000000 /**< PCI DMA32 address translation (sbtopci2) */ 339ed45324SLandon J. Fuller #define BHND_PCI_DMA32_MASK BHND_PCI_SBTOPCI2_MASK /**< PCI DMA32 translation mask */ 344ad7e9b0SAdrian Chadd 359ed45324SLandon J. Fuller #define BHND_PCIE_DMA32_TRANSLATION 0x80000000 /**< PCIe-Gen1 DMA32 address translation (sb2pcitranslation2) */ 369ed45324SLandon J. Fuller #define BHND_PCIE_DMA32_MASK BHND_PCIE_SBTOPCI2_MASK /**< PCIe-Gen1 DMA32 translation mask */ 374ad7e9b0SAdrian Chadd 389ed45324SLandon J. Fuller #define BHND_PCIE_DMA64_TRANSLATION _BHND_PCIE_DMA64(TRANSLATION) /**< PCIe-Gen1 DMA64 address translation (sb2pcitranslation2) */ 399ed45324SLandon J. Fuller #define BHND_PCIE_DMA64_MASK _BHND_PCIE_DMA64(MASK) /**< PCIe-Gen1 DMA64 translation mask */ 409ed45324SLandon J. Fuller #define _BHND_PCIE_DMA64(_x) ((uint64_t)BHND_PCIE_DMA32_ ## _x << 32) 414ad7e9b0SAdrian Chadd /* 424ad7e9b0SAdrian Chadd * PCI Core Registers 434ad7e9b0SAdrian Chadd */ 444ad7e9b0SAdrian Chadd 454ad7e9b0SAdrian Chadd #define BHND_PCI_CTL 0x000 /**< PCI core control*/ 464ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_CTL 0x010 /**< PCI arbiter control */ 474ad7e9b0SAdrian Chadd #define BHND_PCI_CLKRUN_CTL 0x014 /**< PCI clckrun control (>= rev11) */ 484ad7e9b0SAdrian Chadd #define BHND_PCI_INTR_STATUS 0x020 /**< Interrupt status */ 494ad7e9b0SAdrian Chadd #define BHND_PCI_INTR_MASK 0x024 /**< Interrupt mask */ 504ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_MBOX 0x028 /**< Sonics to PCI mailbox */ 514ad7e9b0SAdrian Chadd #define BHND_PCI_BCAST_ADDR 0x050 /**< Sonics broadcast address (pci) */ 524ad7e9b0SAdrian Chadd #define BHND_PCI_BCAST_DATA 0x054 /**< Sonics broadcast data (pci) */ 534ad7e9b0SAdrian Chadd #define BHND_PCI_GPIO_IN 0x060 /**< GPIO input (>= rev2) */ 544ad7e9b0SAdrian Chadd #define BHND_PCI_GPIO_OUT 0x064 /**< GPIO output (>= rev2) */ 554ad7e9b0SAdrian Chadd #define BHND_PCI_GPIO_EN 0x068 /**< GPIO output enable (>= rev2) */ 564ad7e9b0SAdrian Chadd #define BHND_PCI_GPIO_CTL 0x06C /**< GPIO control (>= rev2) */ 574ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI0 0x100 /**< Sonics to PCI translation 0 */ 584ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI1 0x104 /**< Sonics to PCI translation 1 */ 594ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI2 0x108 /**< Sonics to PCI translation 2 */ 604ad7e9b0SAdrian Chadd #define BHND_PCI_FUNC0_CFG 0x400 /**< PCI function 0 cfg space (>= rev8) */ 614ad7e9b0SAdrian Chadd #define BHND_PCI_FUNC1_CFG 0x500 /**< PCI function 1 cfg space (>= rev8) */ 624ad7e9b0SAdrian Chadd #define BHND_PCI_FUNC2_CFG 0x600 /**< PCI function 2 cfg space (>= rev8) */ 634ad7e9b0SAdrian Chadd #define BHND_PCI_FUNC3_CFG 0x700 /**< PCI function 3 cfg space (>= rev8) */ 644ad7e9b0SAdrian Chadd #define BHND_PCI_SPROM_SHADOW 0x800 /**< PCI SPROM shadow */ 654ad7e9b0SAdrian Chadd 664ad7e9b0SAdrian Chadd /* BHND_PCI_CTL */ 674ad7e9b0SAdrian Chadd #define BHND_PCI_CTL_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */ 684ad7e9b0SAdrian Chadd #define BHND_PCI_CTL_RST 0x02 /* Value driven out to pin */ 694ad7e9b0SAdrian Chadd #define BHND_PCI_CTL_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */ 704ad7e9b0SAdrian Chadd #define BHND_PCI_CTL_CLK 0x08 /* Gate for clock driven out to pin */ 714ad7e9b0SAdrian Chadd 724ad7e9b0SAdrian Chadd /* BHND_PCI_ARB_CTL */ 734ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_INT 0x01 /* When set, use an internal arbiter */ 744ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_EXT 0x02 /* When set, use an external arbiter */ 754ad7e9b0SAdrian Chadd 764ad7e9b0SAdrian Chadd /* BHND_PCI_ARB_CTL - ParkID (>= rev8) */ 774ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */ 784ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_PARKID_SHIFT 2 794ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_PARKID_EXT0 0 /* External master 0 */ 804ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_PARKID_EXT1 1 /* External master 1 */ 814ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_PARKID_EXT2 2 /* External master 2 */ 824ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_PARKID_EXT3 3 /* External master 3 (rev >= 11) */ 834ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_PARKID_INT_r10 3 /* Internal master (rev < 11) */ 844ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_PARKID_INT_r11 4 /* Internal master (rev >= 11) */ 854ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_PARKID_LAST_r10 4 /* Last active master (rev < 11) */ 864ad7e9b0SAdrian Chadd #define BHND_PCI_ARB_PARKID_LAST_r11 5 /* Last active master (rev >= 11) */ 874ad7e9b0SAdrian Chadd 884ad7e9b0SAdrian Chadd /* BHND_PCI_CLKRUN_CTL */ 894ad7e9b0SAdrian Chadd #define BHND_PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */ 904ad7e9b0SAdrian Chadd 914ad7e9b0SAdrian Chadd /* BHND_PCI_INTR_STATUS / BHND_PCI_INTR_MASK */ 924ad7e9b0SAdrian Chadd #define BHND_PCI_INTR_A 0x01 /* PCI INTA# is asserted */ 934ad7e9b0SAdrian Chadd #define BHND_PCI_INTR_B 0x02 /* PCI INTB# is asserted */ 944ad7e9b0SAdrian Chadd #define BHND_PCI_INTR_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */ 954ad7e9b0SAdrian Chadd #define BHND_PCI_INTR_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */ 964ad7e9b0SAdrian Chadd 974ad7e9b0SAdrian Chadd /* BHND_PCI_SBTOPCI_MBOX 984ad7e9b0SAdrian Chadd * (General) PCI/SB mailbox interrupts, two bits per pci function */ 994ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_MBOX_F0_0 0x100 /* function 0, int 0 */ 1004ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_MBOX_F0_1 0x200 /* function 0, int 1 */ 1014ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_MBOX_F1_0 0x400 /* function 1, int 0 */ 1024ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_MBOX_F1_1 0x800 /* function 1, int 1 */ 1034ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_MBOX_F2_0 0x1000 /* function 2, int 0 */ 1044ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_MBOX_F2_1 0x2000 /* function 2, int 1 */ 1054ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_MBOX_F3_0 0x4000 /* function 3, int 0 */ 1064ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_MBOX_F3_1 0x8000 /* function 3, int 1 */ 1074ad7e9b0SAdrian Chadd 1084ad7e9b0SAdrian Chadd /* BHND_PCI_BCAST_ADDR */ 1094ad7e9b0SAdrian Chadd #define BHNC_PCI_BCAST_ADDR_MASK 0xFF /* Broadcast register address */ 1104ad7e9b0SAdrian Chadd 1114ad7e9b0SAdrian Chadd /* Sonics to PCI translation types */ 1124ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI0_MASK 0xfc000000 1134ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI1_MASK 0xfc000000 1144ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI2_MASK 0xc0000000 1154ad7e9b0SAdrian Chadd 1164ad7e9b0SAdrian Chadd /* Access type bits (0:1) */ 1174ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_MEM 0 1184ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_IO 1 1194ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_CFG0 2 1204ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_CFG1 3 1214ad7e9b0SAdrian Chadd 1224ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_PREF 0x4 /* prefetch enable */ 1234ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_BURST 0x8 /* burst enable */ 1244ad7e9b0SAdrian Chadd 1254ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */ 1264ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_RC_READ 0x00 /* memory read */ 1274ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_RC_READLINE 0x10 /* memory read line */ 1284ad7e9b0SAdrian Chadd #define BHND_PCI_SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */ 1294ad7e9b0SAdrian Chadd 13084d6a5d4SLandon J. Fuller /* PCI base address bits in SPROM shadow area */ 1314ad7e9b0SAdrian Chadd #define BHND_PCI_SRSH_PI_OFFSET 0 /* first word */ 1324ad7e9b0SAdrian Chadd #define BHND_PCI_SRSH_PI_MASK 0xf000 /* bit 15:12 */ 1334ad7e9b0SAdrian Chadd #define BHND_PCI_SRSH_PI_SHIFT 12 /* bit 15:12 */ 13484d6a5d4SLandon J. Fuller #define BHND_PCI_SRSH_PI_ADDR_MASK 0x0000F000 13584d6a5d4SLandon J. Fuller #define BHND_PCI_SRSH_PI_ADDR_SHIFT 12 1364ad7e9b0SAdrian Chadd 1374ad7e9b0SAdrian Chadd /* 1384ad7e9b0SAdrian Chadd * PCIe-Gen1 Core Registers 1394ad7e9b0SAdrian Chadd */ 1404ad7e9b0SAdrian Chadd 1414ad7e9b0SAdrian Chadd #define BHND_PCIE_CTL BHND_PCI_CTL /**< PCI core control*/ 1424ad7e9b0SAdrian Chadd #define BHND_PCIE_BIST_STATUS 0x00C /**< BIST status */ 1434ad7e9b0SAdrian Chadd #define BHND_PCIE_GPIO_SEL 0x010 /**< GPIO select */ 1444ad7e9b0SAdrian Chadd #define BHND_PCIE_GPIO_OUT_EN 0x014 /**< GPIO output enable */ 1454ad7e9b0SAdrian Chadd #define BHND_PCIE_INTR_STATUS BHND_PCI_INTR_STATUS /**< Interrupt status */ 1464ad7e9b0SAdrian Chadd #define BHND_PCIE_INTR_MASK BHND_PCI_INTR_MASK /**< Interrupt mask */ 1474ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI_MBOX BHND_PCI_SBTOPCI_MBOX /**< Sonics to PCI mailbox */ 1484ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI0 BHND_PCI_SBTOPCI0 /**< Sonics to PCI translation 0 */ 1494ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI1 BHND_PCI_SBTOPCI1 /**< Sonics to PCI translation 1 */ 1504ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI2 BHND_PCI_SBTOPCI2 /**< Sonics to PCI translation 2 */ 1514ad7e9b0SAdrian Chadd 1524ad7e9b0SAdrian Chadd /* indirect pci config space access */ 1534ad7e9b0SAdrian Chadd #define BHND_PCIE_CFG_ADDR 0x120 /**< pcie config space address */ 1544ad7e9b0SAdrian Chadd #define BHND_PCIE_CFG_DATA 0x124 /**< pcie config space data */ 1554ad7e9b0SAdrian Chadd 1564ad7e9b0SAdrian Chadd /* mdio register access */ 1574ad7e9b0SAdrian Chadd #define BHND_PCIE_MDIO_CTL 0x128 /**< mdio control */ 1584ad7e9b0SAdrian Chadd #define BHND_PCIE_MDIO_DATA 0x12C /**< mdio data */ 1594ad7e9b0SAdrian Chadd 1604ad7e9b0SAdrian Chadd /* indirect protocol phy/dllp/tlp register access */ 1614ad7e9b0SAdrian Chadd #define BHND_PCIE_IND_ADDR 0x130 /**< internal protocol register address */ 1624ad7e9b0SAdrian Chadd #define BHND_PCIE_IND_DATA 0x134 /**< internal protocol register data */ 1634ad7e9b0SAdrian Chadd 1644ad7e9b0SAdrian Chadd #define BHND_PCIE_CLKREQEN_CTL 0x138 /**< clkreq rdma control */ 1654ad7e9b0SAdrian Chadd #define BHND_PCIE_FUNC0_CFG BHND_PCI_FUNC0_CFG /**< PCI function 0 cfg space */ 1664ad7e9b0SAdrian Chadd #define BHND_PCIE_FUNC1_CFG BHND_PCI_FUNC1_CFG /**< PCI function 1 cfg space */ 1674ad7e9b0SAdrian Chadd #define BHND_PCIE_FUNC2_CFG BHND_PCI_FUNC2_CFG /**< PCI function 2 cfg space */ 1684ad7e9b0SAdrian Chadd #define BHND_PCIE_FUNC3_CFG BHND_PCI_FUNC3_CFG /**< PCI function 3 cfg space */ 1694ad7e9b0SAdrian Chadd #define BHND_PCIE_SPROM_SHADOW BHND_PCI_SPROM_SHADOW /**< PCI SPROM shadow */ 1704ad7e9b0SAdrian Chadd 1714ad7e9b0SAdrian Chadd /* BHND_PCIE_CTL */ 1724ad7e9b0SAdrian Chadd #define BHND_PCIE_CTL_RST_OE BHND_PCI_CTL_RST_OE /* When set, drives PCI_RESET out to pin */ 1734ad7e9b0SAdrian Chadd #define BHND_PCIE_CTL_RST BHND_PCI_CTL_RST_OE /* Value driven out to pin */ 1744ad7e9b0SAdrian Chadd 1754ad7e9b0SAdrian Chadd /* BHND_PCI_INTR_STATUS / BHND_PCI_INTR_MASK */ 1764ad7e9b0SAdrian Chadd #define BHND_PCIE_INTR_A BHND_PCI_INTR_A /* PCIE INTA message is received */ 1774ad7e9b0SAdrian Chadd #define BHND_PCIE_INTR_B BHND_PCI_INTR_B /* PCIE INTB message is received */ 1784ad7e9b0SAdrian Chadd #define BHND_PCIE_INTR_FATAL 0x04 /* PCIE INTFATAL message is received */ 1794ad7e9b0SAdrian Chadd #define BHND_PCIE_INTR_NFATAL 0x08 /* PCIE INTNONFATAL message is received */ 1804ad7e9b0SAdrian Chadd #define BHND_PCIE_INTR_CORR 0x10 /* PCIE INTCORR message is received */ 1814ad7e9b0SAdrian Chadd #define BHND_PCIE_INTR_PME 0x20 /* PCIE INTPME message is received */ 1824ad7e9b0SAdrian Chadd 1834ad7e9b0SAdrian Chadd /* SB to PCIE translation masks */ 1844ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI0_MASK BHND_PCI_SBTOPCI0_MASK 1854ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI1_MASK BHND_PCI_SBTOPCI1_MASK 1864ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI2_MASK BHND_PCI_SBTOPCI2_MASK 1874ad7e9b0SAdrian Chadd 1884ad7e9b0SAdrian Chadd /* Access type bits (0:1) */ 1894ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI_MEM BHND_PCI_SBTOPCI_MEM 1904ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI_IO BHND_PCI_SBTOPCI_IO 1914ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI_CFG0 BHND_PCI_SBTOPCI_CFG0 1924ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI_CFG1 BHND_PCI_SBTOPCI_CFG1 1934ad7e9b0SAdrian Chadd 1944ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI_PREF BHND_PCI_SBTOPCI_PREF /* prefetch enable */ 1954ad7e9b0SAdrian Chadd #define BHND_PCIE_SBTOPCI_BURST BHND_PCI_SBTOPCI_BURST /* burst enable */ 1964ad7e9b0SAdrian Chadd 1974ad7e9b0SAdrian Chadd /* BHND_PCIE_CFG_ADDR / BHND_PCIE_CFG_DATA */ 1984ad7e9b0SAdrian Chadd #define BHND_PCIE_CFG_ADDR_FUNC_MASK 0x7000 1994ad7e9b0SAdrian Chadd #define BHND_PCIE_CFG_ADDR_FUNC_SHIFT 12 2004ad7e9b0SAdrian Chadd #define BHND_PCIE_CFG_ADDR_REG_MASK 0x0FFF 2014ad7e9b0SAdrian Chadd #define BHND_PCIE_CFG_ADDR_REG_SHIFT 0 2024ad7e9b0SAdrian Chadd 2034ad7e9b0SAdrian Chadd #define BHND_PCIE_CFG_OFFSET(f, r) \ 2044ad7e9b0SAdrian Chadd ((((f) & BHND_PCIE_CFG_ADDR_FUNC_MASK) << BHND_PCIE_CFG_ADDR_FUNC_SHIFT) | \ 2054ad7e9b0SAdrian Chadd (((r) & BHND_PCIE_CFG_ADDR_FUNC_SHIFT) << BHND_PCIE_CFG_ADDR_REG_SHIFT)) 206bb64eeccSAdrian Chadd 207bb64eeccSAdrian Chadd /* BHND_PCIE_MDIO_CTL control */ 208bb64eeccSAdrian Chadd #define BHND_PCIE_MDIOCTL_DIVISOR_MASK 0x7f /* clock divisor mask */ 209bb64eeccSAdrian Chadd #define BHND_PCIE_MDIOCTL_DIVISOR_VAL 0x2 /* default clock divisor */ 210bb64eeccSAdrian Chadd #define BHND_PCIE_MDIOCTL_PREAM_EN 0x80 /* enable preamble mode */ 211bb64eeccSAdrian Chadd #define BHND_PCIE_MDIOCTL_DONE 0x100 /* tranaction completed */ 212bb64eeccSAdrian Chadd 213bb64eeccSAdrian Chadd /* PCIe BHND_PCIE_MDIO_DATA Data */ 214bb64eeccSAdrian Chadd #define BHND_PCIE_MDIODATA_PHYADDR_MASK 0x0f800000 /* phy addr */ 215bb64eeccSAdrian Chadd #define BHND_PCIE_MDIODATA_PHYADDR_SHIFT 23 216bb64eeccSAdrian Chadd #define BHND_PCIE_MDIODATA_REGADDR_MASK 0x007c0000 /* reg/dev addr */ 217bb64eeccSAdrian Chadd #define BHND_PCIE_MDIODATA_REGADDR_SHIFT 18 218bb64eeccSAdrian Chadd #define BHND_PCIE_MDIODATA_DATA_MASK 0x0000ffff /* data */ 219bb64eeccSAdrian Chadd 220bb64eeccSAdrian Chadd #define BHND_PCIE_MDIODATA_TA 0x00020000 /* slave turnaround time */ 221bb64eeccSAdrian Chadd #define BHND_PCIE_MDIODATA_START 0x40000000 /* start of transaction */ 222bb64eeccSAdrian Chadd #define BHND_PCIE_MDIODATA_CMD_WRITE 0x10000000 /* write command */ 223bb64eeccSAdrian Chadd #define BHND_PCIE_MDIODATA_CMD_READ 0x20000000 /* read command */ 224bb64eeccSAdrian Chadd 225bb64eeccSAdrian Chadd #define BHND_PCIE_MDIODATA_ADDR(_phyaddr, _regaddr) ( \ 226bb64eeccSAdrian Chadd (((_phyaddr) << BHND_PCIE_MDIODATA_PHYADDR_SHIFT) & \ 227bb64eeccSAdrian Chadd BHND_PCIE_MDIODATA_PHYADDR_MASK) | \ 228bb64eeccSAdrian Chadd (((_regaddr) << BHND_PCIE_MDIODATA_REGADDR_SHIFT) & \ 229bb64eeccSAdrian Chadd BHND_PCIE_MDIODATA_REGADDR_MASK) \ 230bb64eeccSAdrian Chadd ) 2314ad7e9b0SAdrian Chadd 2324ad7e9b0SAdrian Chadd /* PCIE protocol PHY diagnostic registers */ 2334ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_MODEREG 0x200 /* Mode */ 2344ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_STATUSREG 0x204 /* Status */ 2354ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */ 2364ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */ 2374ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */ 2384ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */ 2394ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_ATTNREG 0x218 /* Attention */ 2404ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */ 2414ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_RXERRCTR 0x220 /* Rx Error */ 2424ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */ 2434ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */ 2444ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */ 2454ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */ 2464ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */ 2474ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */ 2484ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */ 2494ad7e9b0SAdrian Chadd 2504ad7e9b0SAdrian Chadd /* PCIE protocol DLLP diagnostic registers */ 2514ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_LCREG 0x100 /* Link Control */ 2524ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_LCREG_PCIPM_EN 0x40 /* Enable PCI-PM power management */ 2534ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_LSREG 0x104 /* Link Status */ 2544ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_LAREG 0x108 /* Link Attention */ 2554ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */ 2564ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */ 2574ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */ 2584ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */ 2594ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */ 2604ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_LRREG 0x120 /* Link Replay */ 2614ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */ 2624ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */ 2634ad7e9b0SAdrian Chadd #define BHND_PCIE_L0THRESHOLDTIME_MASK 0xFF00 /* bits 0 - 7 */ 2644ad7e9b0SAdrian Chadd #define BHND_PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */ 2654ad7e9b0SAdrian Chadd #define BHND_PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */ 2664ad7e9b0SAdrian Chadd #define BHND_PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */ 2674ad7e9b0SAdrian Chadd #define BHND_PCIE_ASPMTIMER_EXTEND 0x1000000 /* > rev7: enable extend ASPM timer */ 2684ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */ 2694ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */ 2704ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */ 2714ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */ 2724ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */ 2734ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */ 2744ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */ 2754ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */ 2764ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_TESTREG 0x14C /* Test */ 2774ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */ 2784ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */ 2794ad7e9b0SAdrian Chadd 2804ad7e9b0SAdrian Chadd #define BHND_PCIE_DLLP_LSREG_LINKUP (1 << 16) 2814ad7e9b0SAdrian Chadd 2824ad7e9b0SAdrian Chadd /* PCIE protocol TLP diagnostic registers */ 2834ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_CONFIGREG 0x000 /* Configuration */ 2844ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */ 2854ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_WORKAROUND_URBIT 0x8 /* If enabled, UR status bit is set 2864ad7e9b0SAdrian Chadd * on memory access of an unmatched 2874ad7e9b0SAdrian Chadd * address */ 2884ad7e9b0SAdrian Chadd 2894ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */ 2904ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */ 2914ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */ 2924ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */ 2934ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */ 2944ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */ 2954ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */ 2964ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */ 2974ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */ 2984ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */ 2994ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */ 3004ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */ 3014ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */ 3024ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */ 3034ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */ 3044ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */ 3054ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */ 3064ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */ 3074ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */ 3084ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */ 3094ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */ 3104ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */ 3114ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */ 3124ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_RESETCTR 0x06C /* Reset Counter */ 3134ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */ 3144ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */ 3154ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */ 3164ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */ 3174ad7e9b0SAdrian Chadd #define BHND_PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */ 3184ad7e9b0SAdrian Chadd 3194ad7e9b0SAdrian Chadd /* 3204ad7e9b0SAdrian Chadd * PCIe-G1 SerDes MDIO Registers (>= rev10) 3214ad7e9b0SAdrian Chadd */ 3224ad7e9b0SAdrian Chadd #define BHND_PCIE_PHYADDR_SD 0x0 /* serdes PHY address */ 3234ad7e9b0SAdrian Chadd 3244ad7e9b0SAdrian Chadd #define BHND_PCIE_SD_ADDREXT 0x1F /* serdes address extension register */ 3254ad7e9b0SAdrian Chadd 3264ad7e9b0SAdrian Chadd #define BHND_PCIE_SD_REGS_IEEE0 0x0000 /* IEEE0 AN CTRL block */ 3274ad7e9b0SAdrian Chadd #define BHND_PCIE_SD_REGS_IEEE1 0x0010 /* IEEE1 AN ADV block */ 3284ad7e9b0SAdrian Chadd #define BHND_PCIE_SD_REGS_BLK0 0x8000 /* ??? */ 3294ad7e9b0SAdrian Chadd #define BHND_PCIE_SD_REGS_BLK1 0x8010 /* ??? */ 3304ad7e9b0SAdrian Chadd #define BHND_PCIE_SD_REGS_BLK2 0x8020 /* ??? */ 3314ad7e9b0SAdrian Chadd #define BHND_PCIE_SD_REGS_BLK3 0x8030 /* ??? */ 3324ad7e9b0SAdrian Chadd #define BHND_PCIE_SD_REGS_BLK4 0x8040 /* ??? */ 3338ef24a0dSAdrian Chadd #define BHND_PCIE_SD_REGS_PLL 0x8080 /* (?) PLL register block */ 3348ef24a0dSAdrian Chadd #define BHND_PCIE_SD_REGS_TX0 0x8200 /* (?) Transmit 0 block */ 3354ad7e9b0SAdrian Chadd #define BHND_PCIE_SD_REGS_SERDESID 0x8310 /* ??? */ 3368ef24a0dSAdrian Chadd #define BHND_PCIE_SD_REGS_RX0 0x8400 /* (?) Receive 0 register block */ 3378ef24a0dSAdrian Chadd 3388ef24a0dSAdrian Chadd /* The interpretation of these registers and values are just guesses based on 3398ef24a0dSAdrian Chadd * the limited available documentation from other (likely similar) Broadcom 3408ef24a0dSAdrian Chadd * SerDes IP. */ 3418ef24a0dSAdrian Chadd #define BHND_PCIE_SD_TX_DRIVER 0x17 /* TX transmit driver register */ 3428ef24a0dSAdrian Chadd #define BHND_PCIE_SD_TX_DRIVER_IFIR_MASK 0x000E /* unconfirmed */ 3438ef24a0dSAdrian Chadd #define BHND_PCIE_SD_TX_DRIVER_IFIR_SHIFT 1 /* unconfirmed */ 3448ef24a0dSAdrian Chadd #define BHND_PCIE_SD_TX_DRIVER_IPRE_MASK 0x00F0 /* unconfirmed */ 3458ef24a0dSAdrian Chadd #define BHND_PCIE_SD_TX_DRIVER_IPRE_SHIFT 4 /* unconfirmed */ 3468ef24a0dSAdrian Chadd #define BHND_PCIE_SD_TX_DRIVER_IDRIVER_MASK 0x0F00 /* unconfirmed */ 3478ef24a0dSAdrian Chadd #define BHND_PCIE_SD_TX_DRIVER_IDRIVER_SHIFT 8 /* unconfirmed */ 3488ef24a0dSAdrian Chadd #define BHND_PCIE_SD_TX_DRIVER_P2_COEFF_SHIFT 12 /* unconfirmed */ 3498ef24a0dSAdrian Chadd #define BHND_PCIE_SD_TX_DRIVER_P2_COEFF_MASK 0xF000 /* unconfirmed */ 3508ef24a0dSAdrian Chadd 3518ef24a0dSAdrian Chadd /* Constants used with host bridge quirk handling */ 3528ef24a0dSAdrian Chadd #define BHND_PCIE_APPLE_TX_P2_COEFF_MAX 0x7 /* 9.6dB pre-emphassis coeff (???) */ 3538ef24a0dSAdrian Chadd #define BHND_PCIE_APPLE_TX_IDRIVER_MAX 0xF /* 1400mV voltage range (???) */ 3548ef24a0dSAdrian Chadd 3558ef24a0dSAdrian Chadd #define BHND_PCIE_APPLE_TX_P2_COEFF_700MV 0x7 /* 2.3dB pre-emphassis coeff (???) */ 3568ef24a0dSAdrian Chadd #define BHND_PCIE_APPLE_TX_IDRIVER_700MV 0x0 /* 670mV voltage range (???) */ 3574ad7e9b0SAdrian Chadd 3584ad7e9b0SAdrian Chadd /* 3594ad7e9b0SAdrian Chadd * PCIe-G1 SerDes-R9 MDIO Registers (<= rev9) 3604ad7e9b0SAdrian Chadd * 3614ad7e9b0SAdrian Chadd * These register definitions appear to match those provided in the 3624ad7e9b0SAdrian Chadd * "PCI Express SerDes Registers" section of the BCM5761 Ethernet Controller 3634ad7e9b0SAdrian Chadd * Programmer's Reference Guide. 3644ad7e9b0SAdrian Chadd */ 3654ad7e9b0SAdrian Chadd #define BHND_PCIE_PHY_SDR9_PLL 0x1C /* SerDes PLL PHY Address*/ 3664ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_PLL_CTRL 0x17 /* PLL control reg */ 3674ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */ 3684ad7e9b0SAdrian Chadd #define BHND_PCIE_PHY_SDR9_TXRX 0x0F /* SerDes RX/TX PHY Address */ 3694ad7e9b0SAdrian Chadd 3704ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CTRL 0x11 /* RX ctrl register */ 3714ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CTRL_FORCE 0x80 /* rxpolarity_force */ 3724ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CTRL_POLARITY_INV 0x40 /* rxpolarity_value (if set, inverse polarity) */ 3734ad7e9b0SAdrian Chadd 3744ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDR 0x16 /* RX CDR ctrl register */ 3754ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_EN 0x0100 /* freq_override_en flag */ 3764ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_MASK 0x00FF /* freq_override_val */ 3774ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDR_FREQ_OVR_SHIFT 0 3784ad7e9b0SAdrian Chadd 3794ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDRBW 0x17 /* RX CDR bandwidth (PLL tuning) */ 3804ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDRBW_INTGTRK_MASK 0x7000 /* integral loop bandwidth (phase tracking mode) */ 3814ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDRBW_INTGTRK_SHIFT 11 3824ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDRBW_INTGACQ_MASK 0x0700 /* integral loop bandwidth (phase acquisition mode) */ 3834ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDRBW_INTGACQ_SHIFT 8 3844ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDRBW_PROPTRK_MASK 0x0070 /* proportional loop bandwidth (phase tracking mode) */ 3854ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDRBW_PROPTRK_SHIFT 4 3864ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDRBW_PROPACQ_MASK 0x0007 /* proportional loop bandwidth (phase acquisition mode) */ 3874ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_CDRBW_PROPACQ_SHIFT 0 3884ad7e9b0SAdrian Chadd 3894ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_TIMER1 0x12 /* timer1 register */ 3904ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_TIMER1_LKTRK_MASK 0xFF00 /* phase tracking delay before asserting RX seq completion (in 16ns units) */ 3914ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_TIMER1_LKTRK_SHIFT 8 3924ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_TIMER1_LKACQ_MASK 0x00FF /* phase acquisition mode time (in 1024ns units) */ 3934ad7e9b0SAdrian Chadd #define BHND_PCIE_SDR9_RX_TIMER1_LKACQ_SHIFT 0 3944ad7e9b0SAdrian Chadd 3954ad7e9b0SAdrian Chadd /* SPROM offsets */ 39684d6a5d4SLandon J. Fuller #define BHND_PCIE_SRSH_PI_OFFSET BHND_PCI_SRSH_PI_OFFSET /**< PCI base address bits in SPROM shadow area */ 39784d6a5d4SLandon J. Fuller #define BHND_PCIE_SRSH_PI_MASK BHND_PCI_SRSH_PI_MASK /**< bits 15:12 of the PCI core address */ 3984ad7e9b0SAdrian Chadd #define BHND_PCIE_SRSH_PI_SHIFT BHND_PCI_SRSH_PI_SHIFT 39984d6a5d4SLandon J. Fuller #define BHND_PCIE_SRSH_PI_ADDR_MASK BHND_PCI_SRSH_PI_ADDR_MASK 40084d6a5d4SLandon J. Fuller #define BHND_PCIE_SRSH_PI_ADDR_SHIFT BHND_PCI_SRSH_PI_ADDR_SHIFT 4014ad7e9b0SAdrian Chadd 4024ad7e9b0SAdrian Chadd #define BHND_PCIE_SRSH_ASPM_OFFSET 8 /* word 4 */ 4034ad7e9b0SAdrian Chadd #define BHND_PCIE_SRSH_ASPM_ENB 0x18 /* bit 3, 4 */ 4044ad7e9b0SAdrian Chadd #define BHND_PCIE_SRSH_ASPM_L1_ENB 0x10 /* bit 4 */ 4054ad7e9b0SAdrian Chadd #define BHND_PCIE_SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */ 4064ad7e9b0SAdrian Chadd #define BHND_PCIE_SRSH_PCIE_MISC_CONFIG 10 /* word 5 */ 4074ad7e9b0SAdrian Chadd #define BHND_PCIE_SRSH_L23READY_EXIT_NOPRST 0x8000 /* bit 15 */ 4088ef24a0dSAdrian Chadd #define BHND_PCIE_SRSH_CLKREQ_OFFSET_R5 40 /* word 20 for srom rev <= 5 */ 4098ef24a0dSAdrian Chadd #define BHND_PCIE_SRSH_CLKREQ_OFFSET_R8 104 /* word 52 for srom rev 8 */ 4104ad7e9b0SAdrian Chadd #define BHND_PCIE_SRSH_CLKREQ_ENB 0x0800 /* bit 11 */ 4114ad7e9b0SAdrian Chadd #define BHND_PCIE_SRSH_BD_OFFSET 12 /* word 6 */ 4124ad7e9b0SAdrian Chadd #define BHND_PCIE_SRSH_AUTOINIT_OFFSET 36 /* auto initialization enable */ 4134ad7e9b0SAdrian Chadd 4144ad7e9b0SAdrian Chadd /* Status reg PCIE_PLP_STATUSREG */ 4154ad7e9b0SAdrian Chadd #define BHND_PCIE_PLP_POLARITY_INV 0x10 /* lane polarity is inverted */ 4164ad7e9b0SAdrian Chadd 4174ad7e9b0SAdrian Chadd #endif /* _BHND_CORES_PCI_BHND_PCIREG_H_ */ 418