1 /************************************************************************** 2 3 Copyright (c) 2007-2008, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 30 ***************************************************************************/ 31 #ifndef __CHELSIO_COMMON_H 32 #define __CHELSIO_COMMON_H 33 34 #include <cxgb_osdep.h> 35 36 enum { 37 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */ 38 EEPROMSIZE = 8192, /* Serial EEPROM size */ 39 SERNUM_LEN = 16, /* Serial # length */ 40 ECNUM_LEN = 16, /* EC # length */ 41 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 42 TCB_SIZE = 128, /* TCB size */ 43 NMTUS = 16, /* size of MTU table */ 44 NCCTRL_WIN = 32, /* # of congestion control windows */ 45 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 46 PROTO_SRAM_LINES = 128, /* size of protocol sram */ 47 EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */ 48 }; 49 50 #define MAX_RX_COALESCING_LEN 12288U 51 52 enum { 53 PAUSE_RX = 1 << 0, 54 PAUSE_TX = 1 << 1, 55 PAUSE_AUTONEG = 1 << 2 56 }; 57 58 enum { 59 SUPPORTED_IRQ = 1 << 24 60 }; 61 62 enum { /* adapter interrupt-maintained statistics */ 63 STAT_ULP_CH0_PBL_OOB, 64 STAT_ULP_CH1_PBL_OOB, 65 STAT_PCI_CORR_ECC, 66 67 IRQ_NUM_STATS /* keep last */ 68 }; 69 70 enum { 71 TP_VERSION_MAJOR = 1, 72 TP_VERSION_MINOR = 1, 73 TP_VERSION_MICRO = 0 74 }; 75 76 #define S_TP_VERSION_MAJOR 16 77 #define M_TP_VERSION_MAJOR 0xFF 78 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 79 #define G_TP_VERSION_MAJOR(x) \ 80 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 81 82 #define S_TP_VERSION_MINOR 8 83 #define M_TP_VERSION_MINOR 0xFF 84 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 85 #define G_TP_VERSION_MINOR(x) \ 86 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 87 88 #define S_TP_VERSION_MICRO 0 89 #define M_TP_VERSION_MICRO 0xFF 90 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 91 #define G_TP_VERSION_MICRO(x) \ 92 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 93 94 enum { 95 FW_VERSION_MAJOR = 5, 96 FW_VERSION_MINOR = 0, 97 FW_VERSION_MICRO = 0 98 }; 99 100 enum { 101 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 102 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 103 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 104 }; 105 106 enum sge_context_type { /* SGE egress context types */ 107 SGE_CNTXT_RDMA = 0, 108 SGE_CNTXT_ETH = 2, 109 SGE_CNTXT_OFLD = 4, 110 SGE_CNTXT_CTRL = 5 111 }; 112 113 enum { 114 AN_PKT_SIZE = 32, /* async notification packet size */ 115 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 116 }; 117 118 struct sg_ent { /* SGE scatter/gather entry */ 119 __be32 len[2]; 120 __be64 addr[2]; 121 }; 122 123 #ifndef SGE_NUM_GENBITS 124 /* Must be 1 or 2 */ 125 # define SGE_NUM_GENBITS 2 126 #endif 127 128 #define TX_DESC_FLITS 16U 129 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 130 131 #define MAX_PHYINTRS 4 132 133 struct cphy; 134 135 struct mdio_ops { 136 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, 137 int reg_addr, unsigned int *val); 138 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, 139 int reg_addr, unsigned int val); 140 }; 141 142 struct adapter_info { 143 unsigned char nports0; /* # of ports on channel 0 */ 144 unsigned char nports1; /* # of ports on channel 1 */ 145 unsigned char phy_base_addr; /* MDIO PHY base address */ 146 unsigned char mdien:1; 147 unsigned char mdiinv:1; 148 unsigned int gpio_out; /* GPIO output settings */ 149 unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */ 150 unsigned long caps; /* adapter capabilities */ 151 const struct mdio_ops *mdio_ops; /* MDIO operations */ 152 const char *desc; /* product description */ 153 }; 154 155 struct mc5_stats { 156 unsigned long parity_err; 157 unsigned long active_rgn_full; 158 unsigned long nfa_srch_err; 159 unsigned long unknown_cmd; 160 unsigned long reqq_parity_err; 161 unsigned long dispq_parity_err; 162 unsigned long del_act_empty; 163 }; 164 165 struct mc7_stats { 166 unsigned long corr_err; 167 unsigned long uncorr_err; 168 unsigned long parity_err; 169 unsigned long addr_err; 170 }; 171 172 struct mac_stats { 173 u64 tx_octets; /* total # of octets in good frames */ 174 u64 tx_octets_bad; /* total # of octets in error frames */ 175 u64 tx_frames; /* all good frames */ 176 u64 tx_mcast_frames; /* good multicast frames */ 177 u64 tx_bcast_frames; /* good broadcast frames */ 178 u64 tx_pause; /* # of transmitted pause frames */ 179 u64 tx_deferred; /* frames with deferred transmissions */ 180 u64 tx_late_collisions; /* # of late collisions */ 181 u64 tx_total_collisions; /* # of total collisions */ 182 u64 tx_excess_collisions; /* frame errors from excessive collissions */ 183 u64 tx_underrun; /* # of Tx FIFO underruns */ 184 u64 tx_len_errs; /* # of Tx length errors */ 185 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 186 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 187 u64 tx_fcs_errs; /* # of frames with bad FCS */ 188 189 u64 tx_frames_64; /* # of Tx frames in a particular range */ 190 u64 tx_frames_65_127; 191 u64 tx_frames_128_255; 192 u64 tx_frames_256_511; 193 u64 tx_frames_512_1023; 194 u64 tx_frames_1024_1518; 195 u64 tx_frames_1519_max; 196 197 u64 rx_octets; /* total # of octets in good frames */ 198 u64 rx_octets_bad; /* total # of octets in error frames */ 199 u64 rx_frames; /* all good frames */ 200 u64 rx_mcast_frames; /* good multicast frames */ 201 u64 rx_bcast_frames; /* good broadcast frames */ 202 u64 rx_pause; /* # of received pause frames */ 203 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 204 u64 rx_align_errs; /* alignment errors */ 205 u64 rx_symbol_errs; /* symbol errors */ 206 u64 rx_data_errs; /* data errors */ 207 u64 rx_sequence_errs; /* sequence errors */ 208 u64 rx_runt; /* # of runt frames */ 209 u64 rx_jabber; /* # of jabber frames */ 210 u64 rx_short; /* # of short frames */ 211 u64 rx_too_long; /* # of oversized frames */ 212 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 213 214 u64 rx_frames_64; /* # of Rx frames in a particular range */ 215 u64 rx_frames_65_127; 216 u64 rx_frames_128_255; 217 u64 rx_frames_256_511; 218 u64 rx_frames_512_1023; 219 u64 rx_frames_1024_1518; 220 u64 rx_frames_1519_max; 221 222 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 223 224 unsigned long tx_fifo_parity_err; 225 unsigned long rx_fifo_parity_err; 226 unsigned long tx_fifo_urun; 227 unsigned long rx_fifo_ovfl; 228 unsigned long serdes_signal_loss; 229 unsigned long xaui_pcs_ctc_err; 230 unsigned long xaui_pcs_align_change; 231 232 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 233 unsigned long num_resets; /* # times reset due to stuck TX */ 234 }; 235 236 struct tp_mib_stats { 237 u32 ipInReceive_hi; 238 u32 ipInReceive_lo; 239 u32 ipInHdrErrors_hi; 240 u32 ipInHdrErrors_lo; 241 u32 ipInAddrErrors_hi; 242 u32 ipInAddrErrors_lo; 243 u32 ipInUnknownProtos_hi; 244 u32 ipInUnknownProtos_lo; 245 u32 ipInDiscards_hi; 246 u32 ipInDiscards_lo; 247 u32 ipInDelivers_hi; 248 u32 ipInDelivers_lo; 249 u32 ipOutRequests_hi; 250 u32 ipOutRequests_lo; 251 u32 ipOutDiscards_hi; 252 u32 ipOutDiscards_lo; 253 u32 ipOutNoRoutes_hi; 254 u32 ipOutNoRoutes_lo; 255 u32 ipReasmTimeout; 256 u32 ipReasmReqds; 257 u32 ipReasmOKs; 258 u32 ipReasmFails; 259 260 u32 reserved[8]; 261 262 u32 tcpActiveOpens; 263 u32 tcpPassiveOpens; 264 u32 tcpAttemptFails; 265 u32 tcpEstabResets; 266 u32 tcpOutRsts; 267 u32 tcpCurrEstab; 268 u32 tcpInSegs_hi; 269 u32 tcpInSegs_lo; 270 u32 tcpOutSegs_hi; 271 u32 tcpOutSegs_lo; 272 u32 tcpRetransSeg_hi; 273 u32 tcpRetransSeg_lo; 274 u32 tcpInErrs_hi; 275 u32 tcpInErrs_lo; 276 u32 tcpRtoMin; 277 u32 tcpRtoMax; 278 }; 279 280 struct tp_params { 281 unsigned int nchan; /* # of channels */ 282 unsigned int pmrx_size; /* total PMRX capacity */ 283 unsigned int pmtx_size; /* total PMTX capacity */ 284 unsigned int cm_size; /* total CM capacity */ 285 unsigned int chan_rx_size; /* per channel Rx size */ 286 unsigned int chan_tx_size; /* per channel Tx size */ 287 unsigned int rx_pg_size; /* Rx page size */ 288 unsigned int tx_pg_size; /* Tx page size */ 289 unsigned int rx_num_pgs; /* # of Rx pages */ 290 unsigned int tx_num_pgs; /* # of Tx pages */ 291 unsigned int ntimer_qs; /* # of timer queues */ 292 unsigned int tre; /* log2 of core clocks per TP tick */ 293 unsigned int dack_re; /* DACK timer resolution */ 294 }; 295 296 struct qset_params { /* SGE queue set parameters */ 297 unsigned int polling; /* polling/interrupt service for rspq */ 298 unsigned int lro; /* large receive offload */ 299 unsigned int coalesce_usecs; /* irq coalescing timer */ 300 unsigned int rspq_size; /* # of entries in response queue */ 301 unsigned int fl_size; /* # of entries in regular free list */ 302 unsigned int jumbo_size; /* # of entries in jumbo free list */ 303 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 304 unsigned int cong_thres; /* FL congestion threshold */ 305 unsigned int vector; /* Interrupt (line or vector) number */ 306 }; 307 308 struct sge_params { 309 unsigned int max_pkt_size; /* max offload pkt size */ 310 struct qset_params qset[SGE_QSETS]; 311 }; 312 313 struct mc5_params { 314 unsigned int mode; /* selects MC5 width */ 315 unsigned int nservers; /* size of server region */ 316 unsigned int nfilters; /* size of filter region */ 317 unsigned int nroutes; /* size of routing region */ 318 }; 319 320 /* Default MC5 region sizes */ 321 enum { 322 DEFAULT_NSERVERS = 512, 323 DEFAULT_NFILTERS = 128 324 }; 325 326 /* MC5 modes, these must be non-0 */ 327 enum { 328 MC5_MODE_144_BIT = 1, 329 MC5_MODE_72_BIT = 2 330 }; 331 332 /* MC5 min active region size */ 333 enum { MC5_MIN_TIDS = 16 }; 334 335 struct vpd_params { 336 unsigned int cclk; 337 unsigned int mclk; 338 unsigned int uclk; 339 unsigned int mdc; 340 unsigned int mem_timing; 341 u8 sn[SERNUM_LEN + 1]; 342 u8 ec[ECNUM_LEN + 1]; 343 u8 eth_base[6]; 344 u8 port_type[MAX_NPORTS]; 345 unsigned short xauicfg[2]; 346 }; 347 348 struct pci_params { 349 unsigned int vpd_cap_addr; 350 unsigned int pcie_cap_addr; 351 unsigned short speed; 352 unsigned char width; 353 unsigned char variant; 354 }; 355 356 enum { 357 PCI_VARIANT_PCI, 358 PCI_VARIANT_PCIX_MODE1_PARITY, 359 PCI_VARIANT_PCIX_MODE1_ECC, 360 PCI_VARIANT_PCIX_266_MODE2, 361 PCI_VARIANT_PCIE 362 }; 363 364 struct adapter_params { 365 struct sge_params sge; 366 struct mc5_params mc5; 367 struct tp_params tp; 368 struct vpd_params vpd; 369 struct pci_params pci; 370 371 const struct adapter_info *info; 372 373 #ifdef CONFIG_CHELSIO_T3_CORE 374 unsigned short mtus[NMTUS]; 375 unsigned short a_wnd[NCCTRL_WIN]; 376 unsigned short b_wnd[NCCTRL_WIN]; 377 #endif 378 unsigned int nports; /* # of ethernet ports */ 379 unsigned int chan_map; /* bitmap of in-use Tx channels */ 380 unsigned int stats_update_period; /* MAC stats accumulation period */ 381 unsigned int linkpoll_period; /* link poll period in 0.1s */ 382 unsigned int rev; /* chip revision */ 383 unsigned int offload; 384 }; 385 386 enum { /* chip revisions */ 387 T3_REV_A = 0, 388 T3_REV_B = 2, 389 T3_REV_B2 = 3, 390 T3_REV_C = 4, 391 }; 392 393 struct trace_params { 394 u32 sip; 395 u32 sip_mask; 396 u32 dip; 397 u32 dip_mask; 398 u16 sport; 399 u16 sport_mask; 400 u16 dport; 401 u16 dport_mask; 402 u32 vlan:12; 403 u32 vlan_mask:12; 404 u32 intf:4; 405 u32 intf_mask:4; 406 u8 proto; 407 u8 proto_mask; 408 }; 409 410 struct link_config { 411 unsigned int supported; /* link capabilities */ 412 unsigned int advertising; /* advertised capabilities */ 413 unsigned short requested_speed; /* speed user has requested */ 414 unsigned short speed; /* actual link speed */ 415 unsigned char requested_duplex; /* duplex user has requested */ 416 unsigned char duplex; /* actual link duplex */ 417 unsigned char requested_fc; /* flow control user has requested */ 418 unsigned char fc; /* actual link flow control */ 419 unsigned char autoneg; /* autonegotiating? */ 420 unsigned int link_ok; /* link up? */ 421 }; 422 423 #define SPEED_INVALID 0xffff 424 #define DUPLEX_INVALID 0xff 425 426 struct mc5 { 427 adapter_t *adapter; 428 unsigned int tcam_size; 429 unsigned char part_type; 430 unsigned char parity_enabled; 431 unsigned char mode; 432 struct mc5_stats stats; 433 }; 434 435 static inline unsigned int t3_mc5_size(const struct mc5 *p) 436 { 437 return p->tcam_size; 438 } 439 440 struct mc7 { 441 adapter_t *adapter; /* backpointer to adapter */ 442 unsigned int size; /* memory size in bytes */ 443 unsigned int width; /* MC7 interface width */ 444 unsigned int offset; /* register address offset for MC7 instance */ 445 const char *name; /* name of MC7 instance */ 446 struct mc7_stats stats; /* MC7 statistics */ 447 }; 448 449 static inline unsigned int t3_mc7_size(const struct mc7 *p) 450 { 451 return p->size; 452 } 453 454 struct cmac { 455 adapter_t *adapter; 456 unsigned int offset; 457 unsigned char nucast; /* # of address filters for unicast MACs */ 458 unsigned char multiport; /* multiple ports connected to this MAC */ 459 unsigned char ext_port; /* external MAC port */ 460 unsigned char promisc_map; /* which external ports are promiscuous */ 461 unsigned int tx_tcnt; 462 unsigned int tx_xcnt; 463 u64 tx_mcnt; 464 unsigned int rx_xcnt; 465 unsigned int rx_ocnt; 466 u64 rx_mcnt; 467 unsigned int toggle_cnt; 468 unsigned int txen; 469 u64 rx_pause; 470 struct mac_stats stats; 471 }; 472 473 enum { 474 MAC_DIRECTION_RX = 1, 475 MAC_DIRECTION_TX = 2, 476 MAC_RXFIFO_SIZE = 32768 477 }; 478 479 /* IEEE 802.3 specified MDIO devices */ 480 enum { 481 MDIO_DEV_PMA_PMD = 1, 482 MDIO_DEV_WIS = 2, 483 MDIO_DEV_PCS = 3, 484 MDIO_DEV_XGXS = 4, 485 MDIO_DEV_ANEG = 7, 486 MDIO_DEV_VEND1 = 30, 487 MDIO_DEV_VEND2 = 31 488 }; 489 490 /* LASI control and status registers */ 491 enum { 492 RX_ALARM_CTRL = 0x9000, 493 TX_ALARM_CTRL = 0x9001, 494 LASI_CTRL = 0x9002, 495 RX_ALARM_STAT = 0x9003, 496 TX_ALARM_STAT = 0x9004, 497 LASI_STAT = 0x9005 498 }; 499 500 /* PHY loopback direction */ 501 enum { 502 PHY_LOOPBACK_TX = 1, 503 PHY_LOOPBACK_RX = 2 504 }; 505 506 /* PHY interrupt types */ 507 enum { 508 cphy_cause_link_change = 1, 509 cphy_cause_fifo_error = 2, 510 cphy_cause_module_change = 4, 511 }; 512 513 /* PHY module types */ 514 enum { 515 phy_modtype_none, 516 phy_modtype_sr, 517 phy_modtype_lr, 518 phy_modtype_lrm, 519 phy_modtype_twinax, 520 phy_modtype_twinax_long, 521 phy_modtype_unknown 522 }; 523 524 /* PHY operations */ 525 struct cphy_ops { 526 int (*reset)(struct cphy *phy, int wait); 527 528 int (*intr_enable)(struct cphy *phy); 529 int (*intr_disable)(struct cphy *phy); 530 int (*intr_clear)(struct cphy *phy); 531 int (*intr_handler)(struct cphy *phy); 532 533 int (*autoneg_enable)(struct cphy *phy); 534 int (*autoneg_restart)(struct cphy *phy); 535 536 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 537 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 538 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 539 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 540 int *duplex, int *fc); 541 int (*power_down)(struct cphy *phy, int enable); 542 }; 543 544 /* A PHY instance */ 545 struct cphy { 546 u8 addr; /* PHY address */ 547 u8 modtype; /* PHY module type */ 548 short priv; /* scratch pad */ 549 unsigned int caps; /* PHY capabilities */ 550 adapter_t *adapter; /* associated adapter */ 551 const char *desc; /* PHY description */ 552 unsigned long fifo_errors; /* FIFO over/under-flows */ 553 const struct cphy_ops *ops; /* PHY operations */ 554 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 555 int reg_addr, unsigned int *val); 556 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, 557 int reg_addr, unsigned int val); 558 }; 559 560 /* Convenience MDIO read/write wrappers */ 561 static inline int mdio_read(struct cphy *phy, int mmd, int reg, 562 unsigned int *valp) 563 { 564 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 565 } 566 567 static inline int mdio_write(struct cphy *phy, int mmd, int reg, 568 unsigned int val) 569 { 570 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 571 } 572 573 /* Convenience initializer */ 574 static inline void cphy_init(struct cphy *phy, adapter_t *adapter, 575 int phy_addr, struct cphy_ops *phy_ops, 576 const struct mdio_ops *mdio_ops, unsigned int caps, 577 const char *desc) 578 { 579 phy->addr = (u8)phy_addr; 580 phy->caps = caps; 581 phy->adapter = adapter; 582 phy->desc = desc; 583 phy->ops = phy_ops; 584 if (mdio_ops) { 585 phy->mdio_read = mdio_ops->read; 586 phy->mdio_write = mdio_ops->write; 587 } 588 } 589 590 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 591 #define MAC_STATS_ACCUM_SECS 180 592 593 /* The external MAC needs accumulation every 30 seconds */ 594 #define VSC_STATS_ACCUM_SECS 30 595 596 #define XGM_REG(reg_addr, idx) \ 597 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 598 599 struct addr_val_pair { 600 unsigned int reg_addr; 601 unsigned int val; 602 }; 603 604 #include <cxgb_adapter.h> 605 606 #ifndef PCI_VENDOR_ID_CHELSIO 607 # define PCI_VENDOR_ID_CHELSIO 0x1425 608 #endif 609 610 #define for_each_port(adapter, iter) \ 611 for (iter = 0; iter < (adapter)->params.nports; ++iter) 612 613 #define adapter_info(adap) ((adap)->params.info) 614 615 static inline int uses_xaui(const adapter_t *adap) 616 { 617 return adapter_info(adap)->caps & SUPPORTED_AUI; 618 } 619 620 static inline int is_10G(const adapter_t *adap) 621 { 622 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 623 } 624 625 static inline int is_offload(const adapter_t *adap) 626 { 627 #if defined(CONFIG_CHELSIO_T3_CORE) 628 return adap->params.offload; 629 #else 630 return 0; 631 #endif 632 } 633 634 static inline unsigned int core_ticks_per_usec(const adapter_t *adap) 635 { 636 return adap->params.vpd.cclk / 1000; 637 } 638 639 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap, 640 unsigned int ticks) 641 { 642 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 643 } 644 645 static inline unsigned int is_pcie(const adapter_t *adap) 646 { 647 return adap->params.pci.variant == PCI_VARIANT_PCIE; 648 } 649 650 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); 651 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, 652 unsigned int offset); 653 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, 654 int attempts, int delay, u32 *valp); 655 656 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, 657 int polarity, int attempts, int delay) 658 { 659 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 660 delay, NULL); 661 } 662 663 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 664 unsigned int set); 665 int t3_phy_reset(struct cphy *phy, int mmd, int wait); 666 int t3_phy_advertise(struct cphy *phy, unsigned int advert); 667 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 668 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 669 int t3_phy_lasi_intr_enable(struct cphy *phy); 670 int t3_phy_lasi_intr_disable(struct cphy *phy); 671 int t3_phy_lasi_intr_clear(struct cphy *phy); 672 int t3_phy_lasi_intr_handler(struct cphy *phy); 673 674 void t3_intr_enable(adapter_t *adapter); 675 void t3_intr_disable(adapter_t *adapter); 676 void t3_intr_clear(adapter_t *adapter); 677 void t3_port_intr_enable(adapter_t *adapter, int idx); 678 void t3_port_intr_disable(adapter_t *adapter, int idx); 679 void t3_port_intr_clear(adapter_t *adapter, int idx); 680 int t3_slow_intr_handler(adapter_t *adapter); 681 int t3_phy_intr_handler(adapter_t *adapter); 682 683 void t3_link_changed(adapter_t *adapter, int port_id); 684 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 685 const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 686 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); 687 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); 688 int t3_seeprom_wp(adapter_t *adapter, int enable); 689 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, 690 u32 *data, int byte_oriented); 691 int t3_get_tp_version(adapter_t *adapter, u32 *vers); 692 int t3_check_tpsram_version(adapter_t *adapter, int *must_load); 693 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); 694 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); 695 int t3_get_fw_version(adapter_t *adapter, u32 *vers); 696 int t3_check_fw_version(adapter_t *adapter, int *must_load); 697 int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size); 698 int t3_init_hw(adapter_t *adapter, u32 fw_params); 699 void mac_prep(struct cmac *mac, adapter_t *adapter, int index); 700 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai); 701 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); 702 int t3_reinit_adapter(adapter_t *adap); 703 void t3_led_ready(adapter_t *adapter); 704 void t3_fatal_err(adapter_t *adapter); 705 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); 706 void t3_enable_filters(adapter_t *adap); 707 void t3_tp_set_offload_mode(adapter_t *adap, int enable); 708 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, 709 const u16 *rspq); 710 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); 711 int t3_set_proto_sram(adapter_t *adap, const u8 *data); 712 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); 713 void t3_port_failover(adapter_t *adapter, int port); 714 void t3_failover_done(adapter_t *adapter, int port); 715 void t3_failover_clear(adapter_t *adapter); 716 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, 717 unsigned int *valp); 718 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 719 u64 *buf); 720 721 int t3_mac_reset(struct cmac *mac); 722 void t3b_pcs_reset(struct cmac *mac); 723 int t3_mac_enable(struct cmac *mac, int which); 724 int t3_mac_disable(struct cmac *mac, int which); 725 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 726 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 727 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 728 int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n); 729 const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 730 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, 731 int fc); 732 int t3b2_mac_watchdog_task(struct cmac *mac); 733 734 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); 735 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 736 unsigned int nroutes); 737 void t3_mc5_intr_handler(struct mc5 *mc5); 738 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 739 u32 *buf); 740 741 #ifdef CONFIG_CHELSIO_T3_CORE 742 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); 743 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); 744 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); 745 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], 746 unsigned short alpha[NCCTRL_WIN], 747 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 748 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); 749 void t3_get_cong_cntl_tab(adapter_t *adap, 750 unsigned short incr[NMTUS][NCCTRL_WIN]); 751 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, 752 int filter_index, int invert, int enable); 753 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); 754 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); 755 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, 756 unsigned int *ipg); 757 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); 758 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, 759 unsigned int start, unsigned int n); 760 #endif 761 762 void t3_sge_prep(adapter_t *adap, struct sge_params *p); 763 void t3_sge_init(adapter_t *adap, struct sge_params *p); 764 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, 765 enum sge_context_type type, int respq, u64 base_addr, 766 unsigned int size, unsigned int token, int gen, 767 unsigned int cidx); 768 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, 769 u64 base_addr, unsigned int size, unsigned int esize, 770 unsigned int cong_thres, int gen, unsigned int cidx); 771 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, 772 u64 base_addr, unsigned int size, 773 unsigned int fl_thres, int gen, unsigned int cidx); 774 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, 775 unsigned int size, int rspq, int ovfl_mode, 776 unsigned int credits, unsigned int credit_thres); 777 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); 778 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id); 779 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); 780 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); 781 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); 782 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); 783 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); 784 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); 785 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, 786 unsigned int credits); 787 788 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n); 789 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n); 790 int t3_vsc7323_init(adapter_t *adap, int nports); 791 int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port); 792 int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port); 793 int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); 794 int t3_vsc7323_enable(adapter_t *adap, int port, int which); 795 int t3_vsc7323_disable(adapter_t *adap, int port, int which); 796 const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); 797 798 int t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 799 const struct mdio_ops *mdio_ops); 800 int t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 801 const struct mdio_ops *mdio_ops); 802 int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 803 const struct mdio_ops *mdio_ops); 804 int t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 805 const struct mdio_ops *mdio_ops); 806 int t3_ael2005_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 807 const struct mdio_ops *mdio_ops); 808 int t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 809 const struct mdio_ops *mdio_ops); 810 int t3_tn1010_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 811 const struct mdio_ops *mdio_ops); 812 int t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 813 const struct mdio_ops *mdio_ops); 814 #endif /* __CHELSIO_COMMON_H */ 815