xref: /freebsd/sys/dev/cxgbe/adapter.h (revision 0957b409)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011 Chelsio Communications, Inc.
5  * All rights reserved.
6  * Written by: Navdeep Parhar <np@FreeBSD.org>
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $FreeBSD$
30  *
31  */
32 
33 #ifndef __T4_ADAPTER_H__
34 #define __T4_ADAPTER_H__
35 
36 #include <sys/kernel.h>
37 #include <sys/bus.h>
38 #include <sys/rman.h>
39 #include <sys/types.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/rwlock.h>
43 #include <sys/sx.h>
44 #include <sys/vmem.h>
45 #include <vm/uma.h>
46 
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <machine/bus.h>
50 #include <sys/socket.h>
51 #include <sys/sysctl.h>
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_var.h>
55 #include <net/if_media.h>
56 #include <netinet/in.h>
57 #include <netinet/tcp_lro.h>
58 
59 #include "offload.h"
60 #include "t4_ioctl.h"
61 #include "common/t4_msg.h"
62 #include "firmware/t4fw_interface.h"
63 
64 #define KTR_CXGBE	KTR_SPARE3
65 MALLOC_DECLARE(M_CXGBE);
66 #define CXGBE_UNIMPLEMENTED(s) \
67     panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
68 
69 #if defined(__i386__) || defined(__amd64__)
70 static __inline void
71 prefetch(void *x)
72 {
73 	__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
74 }
75 #else
76 #define prefetch(x) __builtin_prefetch(x)
77 #endif
78 
79 #ifndef SYSCTL_ADD_UQUAD
80 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
81 #define sysctl_handle_64 sysctl_handle_quad
82 #define CTLTYPE_U64 CTLTYPE_QUAD
83 #endif
84 
85 SYSCTL_DECL(_hw_cxgbe);
86 
87 struct adapter;
88 typedef struct adapter adapter_t;
89 
90 enum {
91 	/*
92 	 * All ingress queues use this entry size.  Note that the firmware event
93 	 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
94 	 * be at least 64.
95 	 */
96 	IQ_ESIZE = 64,
97 
98 	/* Default queue sizes for all kinds of ingress queues */
99 	FW_IQ_QSIZE = 256,
100 	RX_IQ_QSIZE = 1024,
101 
102 	/* All egress queues use this entry size */
103 	EQ_ESIZE = 64,
104 
105 	/* Default queue sizes for all kinds of egress queues */
106 	CTRL_EQ_QSIZE = 1024,
107 	TX_EQ_QSIZE = 1024,
108 
109 #if MJUMPAGESIZE != MCLBYTES
110 	SW_ZONE_SIZES = 4,	/* cluster, jumbop, jumbo9k, jumbo16k */
111 #else
112 	SW_ZONE_SIZES = 3,	/* cluster, jumbo9k, jumbo16k */
113 #endif
114 	CL_METADATA_SIZE = CACHE_LINE_SIZE,
115 
116 	SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
117 	TX_SGL_SEGS = 39,
118 	TX_SGL_SEGS_TSO = 38,
119 	TX_SGL_SEGS_EO_TSO = 30,	/* XXX: lower for IPv6. */
120 	TX_WR_FLITS = SGE_MAX_WR_LEN / 8
121 };
122 
123 enum {
124 	/* adapter intr_type */
125 	INTR_INTX	= (1 << 0),
126 	INTR_MSI 	= (1 << 1),
127 	INTR_MSIX	= (1 << 2)
128 };
129 
130 enum {
131 	XGMAC_MTU	= (1 << 0),
132 	XGMAC_PROMISC	= (1 << 1),
133 	XGMAC_ALLMULTI	= (1 << 2),
134 	XGMAC_VLANEX	= (1 << 3),
135 	XGMAC_UCADDR	= (1 << 4),
136 	XGMAC_MCADDRS	= (1 << 5),
137 
138 	XGMAC_ALL	= 0xffff
139 };
140 
141 enum {
142 	/* flags understood by begin_synchronized_op */
143 	HOLD_LOCK	= (1 << 0),
144 	SLEEP_OK	= (1 << 1),
145 	INTR_OK		= (1 << 2),
146 
147 	/* flags understood by end_synchronized_op */
148 	LOCK_HELD	= HOLD_LOCK,
149 };
150 
151 enum {
152 	/* adapter flags */
153 	FULL_INIT_DONE	= (1 << 0),
154 	FW_OK		= (1 << 1),
155 	CHK_MBOX_ACCESS	= (1 << 2),
156 	MASTER_PF	= (1 << 3),
157 	ADAP_SYSCTL_CTX	= (1 << 4),
158 	ADAP_ERR	= (1 << 5),
159 	BUF_PACKING_OK	= (1 << 6),
160 	IS_VF		= (1 << 7),
161 
162 	CXGBE_BUSY	= (1 << 9),
163 
164 	/* port flags */
165 	HAS_TRACEQ	= (1 << 3),
166 	FIXED_IFMEDIA	= (1 << 4),	/* ifmedia list doesn't change. */
167 
168 	/* VI flags */
169 	DOOMED		= (1 << 0),
170 	VI_INIT_DONE	= (1 << 1),
171 	VI_SYSCTL_CTX	= (1 << 2),
172 
173 	/* adapter debug_flags */
174 	DF_DUMP_MBOX		= (1 << 0),	/* Log all mbox cmd/rpl. */
175 	DF_LOAD_FW_ANYTIME	= (1 << 1),	/* Allow LOAD_FW after init */
176 	DF_DISABLE_TCB_CACHE	= (1 << 2),	/* Disable TCB cache (T6+) */
177 	DF_DISABLE_CFG_RETRY	= (1 << 3),	/* Disable fallback config */
178 	DF_VERBOSE_SLOWINTR	= (1 << 4),	/* Chatty slow intr handler */
179 };
180 
181 #define IS_DOOMED(vi)	((vi)->flags & DOOMED)
182 #define SET_DOOMED(vi)	do {(vi)->flags |= DOOMED;} while (0)
183 #define IS_BUSY(sc)	((sc)->flags & CXGBE_BUSY)
184 #define SET_BUSY(sc)	do {(sc)->flags |= CXGBE_BUSY;} while (0)
185 #define CLR_BUSY(sc)	do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
186 
187 struct vi_info {
188 	device_t dev;
189 	struct port_info *pi;
190 
191 	struct ifnet *ifp;
192 
193 	unsigned long flags;
194 	int if_flags;
195 
196 	uint16_t *rss, *nm_rss;
197 	int smt_idx;		/* for convenience */
198 	uint16_t viid;
199 	int16_t  xact_addr_filt;/* index of exact MAC address filter */
200 	uint16_t rss_size;	/* size of VI's RSS table slice */
201 	uint16_t rss_base;	/* start of VI's RSS table slice */
202 	int hashen;
203 
204 	int nintr;
205 	int first_intr;
206 
207 	/* These need to be int as they are used in sysctl */
208 	int ntxq;		/* # of tx queues */
209 	int first_txq;		/* index of first tx queue */
210 	int rsrv_noflowq; 	/* Reserve queue 0 for non-flowid packets */
211 	int nrxq;		/* # of rx queues */
212 	int first_rxq;		/* index of first rx queue */
213 	int nofldtxq;		/* # of offload tx queues */
214 	int first_ofld_txq;	/* index of first offload tx queue */
215 	int nofldrxq;		/* # of offload rx queues */
216 	int first_ofld_rxq;	/* index of first offload rx queue */
217 	int nnmtxq;
218 	int first_nm_txq;
219 	int nnmrxq;
220 	int first_nm_rxq;
221 	int tmr_idx;
222 	int ofld_tmr_idx;
223 	int pktc_idx;
224 	int ofld_pktc_idx;
225 	int qsize_rxq;
226 	int qsize_txq;
227 
228 	struct timeval last_refreshed;
229 	struct fw_vi_stats_vf stats;
230 
231 	struct callout tick;
232 	struct sysctl_ctx_list ctx;	/* from ifconfig up to driver detach */
233 
234 	uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
235 };
236 
237 struct tx_ch_rl_params {
238 	enum fw_sched_params_rate ratemode;	/* %port (REL) or kbps (ABS) */
239 	uint32_t maxrate;
240 };
241 
242 enum {
243 	CLRL_USER	= (1 << 0),	/* allocated manually. */
244 	CLRL_SYNC	= (1 << 1),	/* sync hw update in progress. */
245 	CLRL_ASYNC	= (1 << 2),	/* async hw update requested. */
246 	CLRL_ERR	= (1 << 3),	/* last hw setup ended in error. */
247 };
248 
249 struct tx_cl_rl_params {
250 	int refcount;
251 	uint8_t flags;
252 	enum fw_sched_params_rate ratemode;	/* %port REL or ABS value */
253 	enum fw_sched_params_unit rateunit;	/* kbps or pps (when ABS) */
254 	enum fw_sched_params_mode mode;		/* aggr or per-flow */
255 	uint32_t maxrate;
256 	uint16_t pktsize;
257 	uint16_t burstsize;
258 };
259 
260 /* Tx scheduler parameters for a channel/port */
261 struct tx_sched_params {
262 	/* Channel Rate Limiter */
263 	struct tx_ch_rl_params ch_rl;
264 
265 	/* Class WRR */
266 	/* XXX */
267 
268 	/* Class Rate Limiter (including the default pktsize and burstsize). */
269 	int pktsize;
270 	int burstsize;
271 	struct tx_cl_rl_params cl_rl[];
272 };
273 
274 struct port_info {
275 	device_t dev;
276 	struct adapter *adapter;
277 
278 	struct vi_info *vi;
279 	int nvi;
280 	int up_vis;
281 	int uld_vis;
282 
283 	struct tx_sched_params *sched_params;
284 
285 	struct mtx pi_lock;
286 	char lockname[16];
287 	unsigned long flags;
288 
289 	uint8_t  lport;		/* associated offload logical port */
290 	int8_t   mdio_addr;
291 	uint8_t  port_type;
292 	uint8_t  mod_type;
293 	uint8_t  port_id;
294 	uint8_t  tx_chan;
295 	uint8_t  mps_bg_map;	/* rx MPS buffer group bitmap */
296 	uint8_t  rx_e_chan_map;	/* rx TP e-channel bitmap */
297 
298 	struct link_config link_cfg;
299 	struct ifmedia media;
300 
301 	struct timeval last_refreshed;
302  	struct port_stats stats;
303 	u_int tnl_cong_drops;
304 	u_int tx_parse_error;
305 	u_long	tx_tls_records;
306 	u_long	tx_tls_octets;
307 	u_long	rx_tls_records;
308 	u_long	rx_tls_octets;
309 
310 	struct callout tick;
311 };
312 
313 #define	IS_MAIN_VI(vi)		((vi) == &((vi)->pi->vi[0]))
314 
315 /* Where the cluster came from, how it has been carved up. */
316 struct cluster_layout {
317 	int8_t zidx;
318 	int8_t hwidx;
319 	uint16_t region1;	/* mbufs laid out within this region */
320 				/* region2 is the DMA region */
321 	uint16_t region3;	/* cluster_metadata within this region */
322 };
323 
324 struct cluster_metadata {
325 	u_int refcount;
326 	struct fl_sdesc *sd;	/* For debug only.  Could easily be stale */
327 };
328 
329 struct fl_sdesc {
330 	caddr_t cl;
331 	uint16_t nmbuf;	/* # of driver originated mbufs with ref on cluster */
332 	struct cluster_layout cll;
333 };
334 
335 struct tx_desc {
336 	__be64 flit[8];
337 };
338 
339 struct tx_sdesc {
340 	struct mbuf *m;		/* m_nextpkt linked chain of frames */
341 	uint8_t desc_used;	/* # of hardware descriptors used by the WR */
342 };
343 
344 
345 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
346 struct iq_desc {
347 	struct rss_header rss;
348 	uint8_t cpl[IQ_PAD];
349 	struct rsp_ctrl rsp;
350 };
351 #undef IQ_PAD
352 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
353 
354 enum {
355 	/* iq flags */
356 	IQ_ALLOCATED	= (1 << 0),	/* firmware resources allocated */
357 	IQ_HAS_FL	= (1 << 1),	/* iq associated with a freelist */
358 	IQ_RX_TIMESTAMP	= (1 << 2),	/* provide the SGE rx timestamp */
359 	IQ_LRO_ENABLED	= (1 << 3),	/* iq is an eth rxq with LRO enabled */
360 	IQ_ADJ_CREDIT	= (1 << 4),	/* hw is off by 1 credit for this iq */
361 
362 	/* iq state */
363 	IQS_DISABLED	= 0,
364 	IQS_BUSY	= 1,
365 	IQS_IDLE	= 2,
366 
367 	/* netmap related flags */
368 	NM_OFF	= 0,
369 	NM_ON	= 1,
370 	NM_BUSY	= 2,
371 };
372 
373 enum {
374 	CPL_COOKIE_RESERVED = 0,
375 	CPL_COOKIE_FILTER,
376 	CPL_COOKIE_DDP0,
377 	CPL_COOKIE_DDP1,
378 	CPL_COOKIE_TOM,
379 	CPL_COOKIE_HASHFILTER,
380 	CPL_COOKIE_ETHOFLD,
381 	CPL_COOKIE_AVAILABLE3,
382 
383 	NUM_CPL_COOKIES = 8	/* Limited by M_COOKIE.  Do not increase. */
384 };
385 
386 struct sge_iq;
387 struct rss_header;
388 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
389     struct mbuf *);
390 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
391 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
392 
393 /*
394  * Ingress Queue: T4 is producer, driver is consumer.
395  */
396 struct sge_iq {
397 	uint32_t flags;
398 	volatile int state;
399 	struct adapter *adapter;
400 	struct iq_desc  *desc;	/* KVA of descriptor ring */
401 	int8_t   intr_pktc_idx;	/* packet count threshold index */
402 	uint8_t  gen;		/* generation bit */
403 	uint8_t  intr_params;	/* interrupt holdoff parameters */
404 	uint8_t  intr_next;	/* XXX: holdoff for next interrupt */
405 	uint16_t qsize;		/* size (# of entries) of the queue */
406 	uint16_t sidx;		/* index of the entry with the status page */
407 	uint16_t cidx;		/* consumer index */
408 	uint16_t cntxt_id;	/* SGE context id for the iq */
409 	uint16_t abs_id;	/* absolute SGE id for the iq */
410 
411 	STAILQ_ENTRY(sge_iq) link;
412 
413 	bus_dma_tag_t desc_tag;
414 	bus_dmamap_t desc_map;
415 	bus_addr_t ba;		/* bus address of descriptor ring */
416 };
417 
418 enum {
419 	EQ_CTRL		= 1,
420 	EQ_ETH		= 2,
421 	EQ_OFLD		= 3,
422 
423 	/* eq flags */
424 	EQ_TYPEMASK	= 0x3,		/* 2 lsbits hold the type (see above) */
425 	EQ_ALLOCATED	= (1 << 2),	/* firmware resources allocated */
426 	EQ_ENABLED	= (1 << 3),	/* open for business */
427 	EQ_QFLUSH	= (1 << 4),	/* if_qflush in progress */
428 };
429 
430 /* Listed in order of preference.  Update t4_sysctls too if you change these */
431 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
432 
433 /*
434  * Egress Queue: driver is producer, T4 is consumer.
435  *
436  * Note: A free list is an egress queue (driver produces the buffers and T4
437  * consumes them) but it's special enough to have its own struct (see sge_fl).
438  */
439 struct sge_eq {
440 	unsigned int flags;	/* MUST be first */
441 	unsigned int cntxt_id;	/* SGE context id for the eq */
442 	unsigned int abs_id;	/* absolute SGE id for the eq */
443 	struct mtx eq_lock;
444 
445 	struct tx_desc *desc;	/* KVA of descriptor ring */
446 	uint8_t doorbells;
447 	volatile uint32_t *udb;	/* KVA of doorbell (lies within BAR2) */
448 	u_int udb_qid;		/* relative qid within the doorbell page */
449 	uint16_t sidx;		/* index of the entry with the status page */
450 	uint16_t cidx;		/* consumer idx (desc idx) */
451 	uint16_t pidx;		/* producer idx (desc idx) */
452 	uint16_t equeqidx;	/* EQUEQ last requested at this pidx */
453 	uint16_t dbidx;		/* pidx of the most recent doorbell */
454 	uint16_t iqid;		/* iq that gets egr_update for the eq */
455 	uint8_t tx_chan;	/* tx channel used by the eq */
456 	volatile u_int equiq;	/* EQUIQ outstanding */
457 
458 	bus_dma_tag_t desc_tag;
459 	bus_dmamap_t desc_map;
460 	bus_addr_t ba;		/* bus address of descriptor ring */
461 	char lockname[16];
462 };
463 
464 struct sw_zone_info {
465 	uma_zone_t zone;	/* zone that this cluster comes from */
466 	int size;		/* size of cluster: 2K, 4K, 9K, 16K, etc. */
467 	int type;		/* EXT_xxx type of the cluster */
468 	int8_t head_hwidx;
469 	int8_t tail_hwidx;
470 };
471 
472 struct hw_buf_info {
473 	int8_t zidx;		/* backpointer to zone; -ve means unused */
474 	int8_t next;		/* next hwidx for this zone; -1 means no more */
475 	int size;
476 };
477 
478 enum {
479 	NUM_MEMWIN = 3,
480 
481 	MEMWIN0_APERTURE = 2048,
482 	MEMWIN0_BASE     = 0x1b800,
483 
484 	MEMWIN1_APERTURE = 32768,
485 	MEMWIN1_BASE     = 0x28000,
486 
487 	MEMWIN2_APERTURE_T4 = 65536,
488 	MEMWIN2_BASE_T4     = 0x30000,
489 
490 	MEMWIN2_APERTURE_T5 = 128 * 1024,
491 	MEMWIN2_BASE_T5     = 0x60000,
492 };
493 
494 struct memwin {
495 	struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
496 	uint32_t mw_base;	/* constant after setup_memwin */
497 	uint32_t mw_aperture;	/* ditto */
498 	uint32_t mw_curpos;	/* protected by mw_lock */
499 };
500 
501 enum {
502 	FL_STARVING	= (1 << 0), /* on the adapter's list of starving fl's */
503 	FL_DOOMED	= (1 << 1), /* about to be destroyed */
504 	FL_BUF_PACKING	= (1 << 2), /* buffer packing enabled */
505 	FL_BUF_RESUME	= (1 << 3), /* resume from the middle of the frame */
506 };
507 
508 #define FL_RUNNING_LOW(fl) \
509     (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
510 #define FL_NOT_RUNNING_LOW(fl) \
511     (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
512 
513 struct sge_fl {
514 	struct mtx fl_lock;
515 	__be64 *desc;		/* KVA of descriptor ring, ptr to addresses */
516 	struct fl_sdesc *sdesc;	/* KVA of software descriptor ring */
517 	struct cluster_layout cll_def;	/* default refill zone, layout */
518 	uint16_t lowat;		/* # of buffers <= this means fl needs help */
519 	int flags;
520 	uint16_t buf_boundary;
521 
522 	/* The 16b idx all deal with hw descriptors */
523 	uint16_t dbidx;		/* hw pidx after last doorbell */
524 	uint16_t sidx;		/* index of status page */
525 	volatile uint16_t hw_cidx;
526 
527 	/* The 32b idx are all buffer idx, not hardware descriptor idx */
528 	uint32_t cidx;		/* consumer index */
529 	uint32_t pidx;		/* producer index */
530 
531 	uint32_t dbval;
532 	u_int rx_offset;	/* offset in fl buf (when buffer packing) */
533 	volatile uint32_t *udb;
534 
535 	uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
536 	uint64_t mbuf_inlined;	/* # of mbuf created within clusters */
537 	uint64_t cl_allocated;	/* # of clusters allocated */
538 	uint64_t cl_recycled;	/* # of clusters recycled */
539 	uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
540 
541 	/* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
542 	struct mbuf *m0;
543 	struct mbuf **pnext;
544 	u_int remaining;
545 
546 	uint16_t qsize;		/* # of hw descriptors (status page included) */
547 	uint16_t cntxt_id;	/* SGE context id for the freelist */
548 	TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
549 	bus_dma_tag_t desc_tag;
550 	bus_dmamap_t desc_map;
551 	char lockname[16];
552 	bus_addr_t ba;		/* bus address of descriptor ring */
553 	struct cluster_layout cll_alt;	/* alternate refill zone, layout */
554 };
555 
556 struct mp_ring;
557 
558 /* txq: SGE egress queue + what's needed for Ethernet NIC */
559 struct sge_txq {
560 	struct sge_eq eq;	/* MUST be first */
561 
562 	struct ifnet *ifp;	/* the interface this txq belongs to */
563 	struct mp_ring *r;	/* tx software ring */
564 	struct tx_sdesc *sdesc;	/* KVA of software descriptor ring */
565 	struct sglist *gl;
566 	__be32 cpl_ctrl0;	/* for convenience */
567 	int tc_idx;		/* traffic class */
568 
569 	struct task tx_reclaim_task;
570 	/* stats for common events first */
571 
572 	uint64_t txcsum;	/* # of times hardware assisted with checksum */
573 	uint64_t tso_wrs;	/* # of TSO work requests */
574 	uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
575 	uint64_t imm_wrs;	/* # of work requests with immediate data */
576 	uint64_t sgl_wrs;	/* # of work requests with direct SGL */
577 	uint64_t txpkt_wrs;	/* # of txpkt work requests (not coalesced) */
578 	uint64_t txpkts0_wrs;	/* # of type0 coalesced tx work requests */
579 	uint64_t txpkts1_wrs;	/* # of type1 coalesced tx work requests */
580 	uint64_t txpkts0_pkts;	/* # of frames in type0 coalesced tx WRs */
581 	uint64_t txpkts1_pkts;	/* # of frames in type1 coalesced tx WRs */
582 	uint64_t raw_wrs;	/* # of raw work requests (alloc_wr_mbuf) */
583 
584 	/* stats for not-that-common events */
585 } __aligned(CACHE_LINE_SIZE);
586 
587 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
588 struct sge_rxq {
589 	struct sge_iq iq;	/* MUST be first */
590 	struct sge_fl fl;	/* MUST follow iq */
591 
592 	struct ifnet *ifp;	/* the interface this rxq belongs to */
593 #if defined(INET) || defined(INET6)
594 	struct lro_ctrl lro;	/* LRO state */
595 #endif
596 
597 	/* stats for common events first */
598 
599 	uint64_t rxcsum;	/* # of times hardware assisted with checksum */
600 	uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
601 
602 	/* stats for not-that-common events */
603 
604 } __aligned(CACHE_LINE_SIZE);
605 
606 static inline struct sge_rxq *
607 iq_to_rxq(struct sge_iq *iq)
608 {
609 
610 	return (__containerof(iq, struct sge_rxq, iq));
611 }
612 
613 
614 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
615 struct sge_ofld_rxq {
616 	struct sge_iq iq;	/* MUST be first */
617 	struct sge_fl fl;	/* MUST follow iq */
618 } __aligned(CACHE_LINE_SIZE);
619 
620 static inline struct sge_ofld_rxq *
621 iq_to_ofld_rxq(struct sge_iq *iq)
622 {
623 
624 	return (__containerof(iq, struct sge_ofld_rxq, iq));
625 }
626 
627 struct wrqe {
628 	STAILQ_ENTRY(wrqe) link;
629 	struct sge_wrq *wrq;
630 	int wr_len;
631 	char wr[] __aligned(16);
632 };
633 
634 struct wrq_cookie {
635 	TAILQ_ENTRY(wrq_cookie) link;
636 	int ndesc;
637 	int pidx;
638 };
639 
640 /*
641  * wrq: SGE egress queue that is given prebuilt work requests.  Both the control
642  * and offload tx queues are of this type.
643  */
644 struct sge_wrq {
645 	struct sge_eq eq;	/* MUST be first */
646 
647 	struct adapter *adapter;
648 	struct task wrq_tx_task;
649 
650 	/* Tx desc reserved but WR not "committed" yet. */
651 	TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
652 
653 	/* List of WRs ready to go out as soon as descriptors are available. */
654 	STAILQ_HEAD(, wrqe) wr_list;
655 	u_int nwr_pending;
656 	u_int ndesc_needed;
657 
658 	/* stats for common events first */
659 
660 	uint64_t tx_wrs_direct;	/* # of WRs written directly to desc ring. */
661 	uint64_t tx_wrs_ss;	/* # of WRs copied from scratch space. */
662 	uint64_t tx_wrs_copied;	/* # of WRs queued and copied to desc ring. */
663 
664 	/* stats for not-that-common events */
665 
666 	/*
667 	 * Scratch space for work requests that wrap around after reaching the
668 	 * status page, and some information about the last WR that used it.
669 	 */
670 	uint16_t ss_pidx;
671 	uint16_t ss_len;
672 	uint8_t ss[SGE_MAX_WR_LEN];
673 
674 } __aligned(CACHE_LINE_SIZE);
675 
676 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
677 struct sge_nm_rxq {
678 	volatile int nm_state;	/* NM_OFF, NM_ON, or NM_BUSY */
679 	struct vi_info *vi;
680 
681 	struct iq_desc *iq_desc;
682 	uint16_t iq_abs_id;
683 	uint16_t iq_cntxt_id;
684 	uint16_t iq_cidx;
685 	uint16_t iq_sidx;
686 	uint8_t iq_gen;
687 
688 	__be64  *fl_desc;
689 	uint16_t fl_cntxt_id;
690 	uint32_t fl_cidx;
691 	uint32_t fl_pidx;
692 	uint32_t fl_sidx;
693 	uint32_t fl_db_val;
694 	u_int fl_hwidx:4;
695 
696 	u_int fl_db_saved;
697 	u_int nid;		/* netmap ring # for this queue */
698 
699 	/* infrequently used items after this */
700 
701 	bus_dma_tag_t iq_desc_tag;
702 	bus_dmamap_t iq_desc_map;
703 	bus_addr_t iq_ba;
704 	int intr_idx;
705 
706 	bus_dma_tag_t fl_desc_tag;
707 	bus_dmamap_t fl_desc_map;
708 	bus_addr_t fl_ba;
709 } __aligned(CACHE_LINE_SIZE);
710 
711 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
712 struct sge_nm_txq {
713 	struct tx_desc *desc;
714 	uint16_t cidx;
715 	uint16_t pidx;
716 	uint16_t sidx;
717 	uint16_t equiqidx;	/* EQUIQ last requested at this pidx */
718 	uint16_t equeqidx;	/* EQUEQ last requested at this pidx */
719 	uint16_t dbidx;		/* pidx of the most recent doorbell */
720 	uint8_t doorbells;
721 	volatile uint32_t *udb;
722 	u_int udb_qid;
723 	u_int cntxt_id;
724 	__be32 cpl_ctrl0;	/* for convenience */
725 	u_int nid;		/* netmap ring # for this queue */
726 
727 	/* infrequently used items after this */
728 
729 	bus_dma_tag_t desc_tag;
730 	bus_dmamap_t desc_map;
731 	bus_addr_t ba;
732 	int iqidx;
733 } __aligned(CACHE_LINE_SIZE);
734 
735 struct sge {
736 	int nrxq;	/* total # of Ethernet rx queues */
737 	int ntxq;	/* total # of Ethernet tx queues */
738 	int nofldrxq;	/* total # of TOE rx queues */
739 	int nofldtxq;	/* total # of TOE tx queues */
740 	int nnmrxq;	/* total # of netmap rx queues */
741 	int nnmtxq;	/* total # of netmap tx queues */
742 	int niq;	/* total # of ingress queues */
743 	int neq;	/* total # of egress queues */
744 
745 	struct sge_iq fwq;	/* Firmware event queue */
746 	struct sge_wrq *ctrlq;	/* Control queues */
747 	struct sge_txq *txq;	/* NIC tx queues */
748 	struct sge_rxq *rxq;	/* NIC rx queues */
749 	struct sge_wrq *ofld_txq;	/* TOE tx queues */
750 	struct sge_ofld_rxq *ofld_rxq;	/* TOE rx queues */
751 	struct sge_nm_txq *nm_txq;	/* netmap tx queues */
752 	struct sge_nm_rxq *nm_rxq;	/* netmap rx queues */
753 
754 	uint16_t iq_start;	/* first cntxt_id */
755 	uint16_t iq_base;	/* first abs_id */
756 	int eq_start;		/* first cntxt_id */
757 	int eq_base;		/* first abs_id */
758 	struct sge_iq **iqmap;	/* iq->cntxt_id to iq mapping */
759 	struct sge_eq **eqmap;	/* eq->cntxt_id to eq mapping */
760 
761 	int8_t safe_hwidx1;	/* may not have room for metadata */
762 	int8_t safe_hwidx2;	/* with room for metadata and maybe more */
763 	struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
764 	struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
765 };
766 
767 struct devnames {
768 	const char *nexus_name;
769 	const char *ifnet_name;
770 	const char *vi_ifnet_name;
771 	const char *pf03_drv_name;
772 	const char *vf_nexus_name;
773 	const char *vf_ifnet_name;
774 };
775 
776 struct clip_entry;
777 
778 struct adapter {
779 	SLIST_ENTRY(adapter) link;
780 	device_t dev;
781 	struct cdev *cdev;
782 	const struct devnames *names;
783 
784 	/* PCIe register resources */
785 	int regs_rid;
786 	struct resource *regs_res;
787 	int msix_rid;
788 	struct resource *msix_res;
789 	bus_space_handle_t bh;
790 	bus_space_tag_t bt;
791 	bus_size_t mmio_len;
792 	int udbs_rid;
793 	struct resource *udbs_res;
794 	volatile uint8_t *udbs_base;
795 
796 	unsigned int pf;
797 	unsigned int mbox;
798 	unsigned int vpd_busy;
799 	unsigned int vpd_flag;
800 
801 	/* Interrupt information */
802 	int intr_type;
803 	int intr_count;
804 	struct irq {
805 		struct resource *res;
806 		int rid;
807 		void *tag;
808 		struct sge_rxq *rxq;
809 		struct sge_nm_rxq *nm_rxq;
810 	} __aligned(CACHE_LINE_SIZE) *irq;
811 	int sge_gts_reg;
812 	int sge_kdoorbell_reg;
813 
814 	bus_dma_tag_t dmat;	/* Parent DMA tag */
815 
816 	struct sge sge;
817 	int lro_timeout;
818 	int sc_do_rxcopy;
819 
820 	struct taskqueue *tq[MAX_NCHAN];	/* General purpose taskqueues */
821 	struct port_info *port[MAX_NPORTS];
822 	uint8_t chan_map[MAX_NCHAN];		/* channel -> port */
823 
824 	struct mtx clip_table_lock;
825 	TAILQ_HEAD(, clip_entry) clip_table;
826 	int clip_gen;
827 
828 	void *tom_softc;	/* (struct tom_data *) */
829 	struct tom_tunables tt;
830 	struct t4_offload_policy *policy;
831 	struct rwlock policy_lock;
832 
833 	void *iwarp_softc;	/* (struct c4iw_dev *) */
834 	struct iw_tunables iwt;
835 	void *iscsi_ulp_softc;	/* (struct cxgbei_data *) */
836 	void *ccr_softc;	/* (struct ccr_softc *) */
837 	struct l2t_data *l2t;	/* L2 table */
838 	struct smt_data *smt;	/* Source MAC Table */
839 	struct tid_info tids;
840 	vmem_t *key_map;
841 
842 	uint8_t doorbells;
843 	int offload_map;	/* ports with IFCAP_TOE enabled */
844 	int active_ulds;	/* ULDs activated on this adapter */
845 	int flags;
846 	int debug_flags;
847 
848 	char ifp_lockname[16];
849 	struct mtx ifp_lock;
850 	struct ifnet *ifp;	/* tracer ifp */
851 	struct ifmedia media;
852 	int traceq;		/* iq used by all tracers, -1 if none */
853 	int tracer_valid;	/* bitmap of valid tracers */
854 	int tracer_enabled;	/* bitmap of enabled tracers */
855 
856 	char fw_version[16];
857 	char tp_version[16];
858 	char er_version[16];
859 	char bs_version[16];
860 	char cfg_file[32];
861 	u_int cfcsum;
862 	struct adapter_params params;
863 	const struct chip_params *chip_params;
864 	struct t4_virt_res vres;
865 
866 	uint16_t nbmcaps;
867 	uint16_t linkcaps;
868 	uint16_t switchcaps;
869 	uint16_t niccaps;
870 	uint16_t toecaps;
871 	uint16_t rdmacaps;
872 	uint16_t cryptocaps;
873 	uint16_t iscsicaps;
874 	uint16_t fcoecaps;
875 
876 	struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
877 
878 	struct mtx sc_lock;
879 	char lockname[16];
880 
881 	/* Starving free lists */
882 	struct mtx sfl_lock;	/* same cache-line as sc_lock? but that's ok */
883 	TAILQ_HEAD(, sge_fl) sfl;
884 	struct callout sfl_callout;
885 
886 	struct mtx reg_lock;	/* for indirect register access */
887 
888 	struct memwin memwin[NUM_MEMWIN];	/* memory windows */
889 
890 	struct mtx tc_lock;
891 	struct task tc_task;
892 
893 	const char *last_op;
894 	const void *last_op_thr;
895 	int last_op_flags;
896 };
897 
898 #define ADAPTER_LOCK(sc)		mtx_lock(&(sc)->sc_lock)
899 #define ADAPTER_UNLOCK(sc)		mtx_unlock(&(sc)->sc_lock)
900 #define ADAPTER_LOCK_ASSERT_OWNED(sc)	mtx_assert(&(sc)->sc_lock, MA_OWNED)
901 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
902 
903 #define ASSERT_SYNCHRONIZED_OP(sc)	\
904     KASSERT(IS_BUSY(sc) && \
905 	(mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
906 	("%s: operation not synchronized.", __func__))
907 
908 #define PORT_LOCK(pi)			mtx_lock(&(pi)->pi_lock)
909 #define PORT_UNLOCK(pi)			mtx_unlock(&(pi)->pi_lock)
910 #define PORT_LOCK_ASSERT_OWNED(pi)	mtx_assert(&(pi)->pi_lock, MA_OWNED)
911 #define PORT_LOCK_ASSERT_NOTOWNED(pi)	mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
912 
913 #define FL_LOCK(fl)			mtx_lock(&(fl)->fl_lock)
914 #define FL_TRYLOCK(fl)			mtx_trylock(&(fl)->fl_lock)
915 #define FL_UNLOCK(fl)			mtx_unlock(&(fl)->fl_lock)
916 #define FL_LOCK_ASSERT_OWNED(fl)	mtx_assert(&(fl)->fl_lock, MA_OWNED)
917 #define FL_LOCK_ASSERT_NOTOWNED(fl)	mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
918 
919 #define RXQ_FL_LOCK(rxq)		FL_LOCK(&(rxq)->fl)
920 #define RXQ_FL_UNLOCK(rxq)		FL_UNLOCK(&(rxq)->fl)
921 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq)	FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
922 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
923 
924 #define EQ_LOCK(eq)			mtx_lock(&(eq)->eq_lock)
925 #define EQ_TRYLOCK(eq)			mtx_trylock(&(eq)->eq_lock)
926 #define EQ_UNLOCK(eq)			mtx_unlock(&(eq)->eq_lock)
927 #define EQ_LOCK_ASSERT_OWNED(eq)	mtx_assert(&(eq)->eq_lock, MA_OWNED)
928 #define EQ_LOCK_ASSERT_NOTOWNED(eq)	mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
929 
930 #define TXQ_LOCK(txq)			EQ_LOCK(&(txq)->eq)
931 #define TXQ_TRYLOCK(txq)		EQ_TRYLOCK(&(txq)->eq)
932 #define TXQ_UNLOCK(txq)			EQ_UNLOCK(&(txq)->eq)
933 #define TXQ_LOCK_ASSERT_OWNED(txq)	EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
934 #define TXQ_LOCK_ASSERT_NOTOWNED(txq)	EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
935 
936 #define for_each_txq(vi, iter, q) \
937 	for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
938 	    iter < vi->ntxq; ++iter, ++q)
939 #define for_each_rxq(vi, iter, q) \
940 	for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
941 	    iter < vi->nrxq; ++iter, ++q)
942 #define for_each_ofld_txq(vi, iter, q) \
943 	for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
944 	    iter < vi->nofldtxq; ++iter, ++q)
945 #define for_each_ofld_rxq(vi, iter, q) \
946 	for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
947 	    iter < vi->nofldrxq; ++iter, ++q)
948 #define for_each_nm_txq(vi, iter, q) \
949 	for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
950 	    iter < vi->nnmtxq; ++iter, ++q)
951 #define for_each_nm_rxq(vi, iter, q) \
952 	for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
953 	    iter < vi->nnmrxq; ++iter, ++q)
954 #define for_each_vi(_pi, _iter, _vi) \
955 	for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
956 	     ++(_iter), ++(_vi))
957 
958 #define IDXINCR(idx, incr, wrap) do { \
959 	idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
960 } while (0)
961 #define IDXDIFF(head, tail, wrap) \
962 	((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
963 
964 /* One for errors, one for firmware events */
965 #define T4_EXTRA_INTR 2
966 
967 /* One for firmware events */
968 #define T4VF_EXTRA_INTR 1
969 
970 static inline int
971 forwarding_intr_to_fwq(struct adapter *sc)
972 {
973 
974 	return (sc->intr_count == 1);
975 }
976 
977 static inline uint32_t
978 t4_read_reg(struct adapter *sc, uint32_t reg)
979 {
980 
981 	return bus_space_read_4(sc->bt, sc->bh, reg);
982 }
983 
984 static inline void
985 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
986 {
987 
988 	bus_space_write_4(sc->bt, sc->bh, reg, val);
989 }
990 
991 static inline uint64_t
992 t4_read_reg64(struct adapter *sc, uint32_t reg)
993 {
994 
995 #ifdef __LP64__
996 	return bus_space_read_8(sc->bt, sc->bh, reg);
997 #else
998 	return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
999 	    ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1000 
1001 #endif
1002 }
1003 
1004 static inline void
1005 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1006 {
1007 
1008 #ifdef __LP64__
1009 	bus_space_write_8(sc->bt, sc->bh, reg, val);
1010 #else
1011 	bus_space_write_4(sc->bt, sc->bh, reg, val);
1012 	bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1013 #endif
1014 }
1015 
1016 static inline void
1017 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1018 {
1019 
1020 	*val = pci_read_config(sc->dev, reg, 1);
1021 }
1022 
1023 static inline void
1024 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1025 {
1026 
1027 	pci_write_config(sc->dev, reg, val, 1);
1028 }
1029 
1030 static inline void
1031 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1032 {
1033 
1034 	*val = pci_read_config(sc->dev, reg, 2);
1035 }
1036 
1037 static inline void
1038 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1039 {
1040 
1041 	pci_write_config(sc->dev, reg, val, 2);
1042 }
1043 
1044 static inline void
1045 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1046 {
1047 
1048 	*val = pci_read_config(sc->dev, reg, 4);
1049 }
1050 
1051 static inline void
1052 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1053 {
1054 
1055 	pci_write_config(sc->dev, reg, val, 4);
1056 }
1057 
1058 static inline struct port_info *
1059 adap2pinfo(struct adapter *sc, int idx)
1060 {
1061 
1062 	return (sc->port[idx]);
1063 }
1064 
1065 static inline void
1066 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1067 {
1068 
1069 	bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1070 }
1071 
1072 static inline int
1073 tx_resume_threshold(struct sge_eq *eq)
1074 {
1075 
1076 	/* not quite the same as qsize / 4, but this will do. */
1077 	return (eq->sidx / 4);
1078 }
1079 
1080 static inline int
1081 t4_use_ldst(struct adapter *sc)
1082 {
1083 
1084 #ifdef notyet
1085 	return (sc->flags & FW_OK || !sc->use_bd);
1086 #else
1087 	return (0);
1088 #endif
1089 }
1090 
1091 static inline void
1092 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,
1093     const char *msg, const __be64 *const p, const bool err)
1094 {
1095 
1096 	if (!(sc->debug_flags & DF_DUMP_MBOX) && !err)
1097 		return;
1098 	if (p != NULL) {
1099 		log(err ? LOG_ERR : LOG_DEBUG,
1100 		    "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1101 		    "%016llx %016llx %016llx %016llx\n",
1102 		    device_get_nameunit(sc->dev), mbox, msg,
1103 		    (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]),
1104 		    (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]),
1105 		    (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]),
1106 		    (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7]));
1107 	} else {
1108 		log(err ? LOG_ERR : LOG_DEBUG,
1109 		    "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1110 		    "%016llx %016llx %016llx %016llx\n",
1111 		    device_get_nameunit(sc->dev), mbox, msg,
1112 		    (long long)t4_read_reg64(sc, reg),
1113 		    (long long)t4_read_reg64(sc, reg + 8),
1114 		    (long long)t4_read_reg64(sc, reg + 16),
1115 		    (long long)t4_read_reg64(sc, reg + 24),
1116 		    (long long)t4_read_reg64(sc, reg + 32),
1117 		    (long long)t4_read_reg64(sc, reg + 40),
1118 		    (long long)t4_read_reg64(sc, reg + 48),
1119 		    (long long)t4_read_reg64(sc, reg + 56));
1120 	}
1121 }
1122 
1123 /* t4_main.c */
1124 extern int t4_ntxq;
1125 extern int t4_nrxq;
1126 extern int t4_intr_types;
1127 extern int t4_tmr_idx;
1128 extern int t4_pktc_idx;
1129 extern unsigned int t4_qsize_rxq;
1130 extern unsigned int t4_qsize_txq;
1131 extern device_method_t cxgbe_methods[];
1132 
1133 int t4_os_find_pci_capability(struct adapter *, int);
1134 int t4_os_pci_save_state(struct adapter *);
1135 int t4_os_pci_restore_state(struct adapter *);
1136 void t4_os_portmod_changed(struct port_info *);
1137 void t4_os_link_changed(struct port_info *);
1138 void t4_iterate(void (*)(struct adapter *, void *), void *);
1139 void t4_init_devnames(struct adapter *);
1140 void t4_add_adapter(struct adapter *);
1141 void t4_aes_getdeckey(void *, const void *, unsigned int);
1142 int t4_detach_common(device_t);
1143 int t4_map_bars_0_and_4(struct adapter *);
1144 int t4_map_bar_2(struct adapter *);
1145 int t4_setup_intr_handlers(struct adapter *);
1146 void t4_sysctls(struct adapter *);
1147 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1148 void doom_vi(struct adapter *, struct vi_info *);
1149 void end_synchronized_op(struct adapter *, int);
1150 int update_mac_settings(struct ifnet *, int);
1151 int adapter_full_init(struct adapter *);
1152 int adapter_full_uninit(struct adapter *);
1153 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1154 int vi_full_init(struct vi_info *);
1155 int vi_full_uninit(struct vi_info *);
1156 void vi_sysctls(struct vi_info *);
1157 void vi_tick(void *);
1158 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1159 int alloc_atid_tab(struct tid_info *, int);
1160 void free_atid_tab(struct tid_info *);
1161 int alloc_atid(struct adapter *, void *);
1162 void *lookup_atid(struct adapter *, int);
1163 void free_atid(struct adapter *, int);
1164 void release_tid(struct adapter *, int, struct sge_wrq *);
1165 int cxgbe_media_change(struct ifnet *);
1166 void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
1167 bool t4_os_dump_cimla(struct adapter *, int, bool);
1168 void t4_os_dump_devlog(struct adapter *);
1169 
1170 #ifdef DEV_NETMAP
1171 /* t4_netmap.c */
1172 struct sge_nm_rxq;
1173 void cxgbe_nm_attach(struct vi_info *);
1174 void cxgbe_nm_detach(struct vi_info *);
1175 void service_nm_rxq(struct sge_nm_rxq *);
1176 #endif
1177 
1178 /* t4_sge.c */
1179 void t4_sge_modload(void);
1180 void t4_sge_modunload(void);
1181 uint64_t t4_sge_extfree_refs(void);
1182 void t4_tweak_chip_settings(struct adapter *);
1183 int t4_read_chip_settings(struct adapter *);
1184 int t4_create_dma_tag(struct adapter *);
1185 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1186     struct sysctl_oid_list *);
1187 int t4_destroy_dma_tag(struct adapter *);
1188 int t4_setup_adapter_queues(struct adapter *);
1189 int t4_teardown_adapter_queues(struct adapter *);
1190 int t4_setup_vi_queues(struct vi_info *);
1191 int t4_teardown_vi_queues(struct vi_info *);
1192 void t4_intr_all(void *);
1193 void t4_intr(void *);
1194 #ifdef DEV_NETMAP
1195 void t4_nm_intr(void *);
1196 void t4_vi_intr(void *);
1197 #endif
1198 void t4_intr_err(void *);
1199 void t4_intr_evt(void *);
1200 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1201 void t4_update_fl_bufsize(struct ifnet *);
1202 struct mbuf *alloc_wr_mbuf(int, int);
1203 int parse_pkt(struct adapter *, struct mbuf **);
1204 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1205 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1206 int tnl_cong(struct port_info *, int);
1207 void t4_register_an_handler(an_handler_t);
1208 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1209 void t4_register_cpl_handler(int, cpl_handler_t);
1210 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1211 #ifdef RATELIMIT
1212 int ethofld_transmit(struct ifnet *, struct mbuf *);
1213 void send_etid_flush_wr(struct cxgbe_snd_tag *);
1214 #endif
1215 
1216 /* t4_tracer.c */
1217 struct t4_tracer;
1218 void t4_tracer_modload(void);
1219 void t4_tracer_modunload(void);
1220 void t4_tracer_port_detach(struct adapter *);
1221 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1222 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1223 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1224 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1225 
1226 /* t4_sched.c */
1227 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1228 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1229 int t4_init_tx_sched(struct adapter *);
1230 int t4_free_tx_sched(struct adapter *);
1231 void t4_update_tx_sched(struct adapter *);
1232 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1233 void t4_release_cl_rl(struct adapter *, int, int);
1234 int sysctl_tc(SYSCTL_HANDLER_ARGS);
1235 int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
1236 #ifdef RATELIMIT
1237 void t4_init_etid_table(struct adapter *);
1238 void t4_free_etid_table(struct adapter *);
1239 struct cxgbe_snd_tag *lookup_etid(struct adapter *, int);
1240 int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1241     struct m_snd_tag **);
1242 int cxgbe_snd_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *);
1243 int cxgbe_snd_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *);
1244 void cxgbe_snd_tag_free(struct m_snd_tag *);
1245 void cxgbe_snd_tag_free_locked(struct cxgbe_snd_tag *);
1246 #endif
1247 
1248 /* t4_filter.c */
1249 int get_filter_mode(struct adapter *, uint32_t *);
1250 int set_filter_mode(struct adapter *, uint32_t);
1251 int get_filter(struct adapter *, struct t4_filter *);
1252 int set_filter(struct adapter *, struct t4_filter *);
1253 int del_filter(struct adapter *, struct t4_filter *);
1254 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1255 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1256 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1257 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1258 void free_hftid_hash(struct tid_info *);
1259 
1260 static inline struct wrqe *
1261 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1262 {
1263 	int len = offsetof(struct wrqe, wr) + wr_len;
1264 	struct wrqe *wr;
1265 
1266 	wr = malloc(len, M_CXGBE, M_NOWAIT);
1267 	if (__predict_false(wr == NULL))
1268 		return (NULL);
1269 	wr->wr_len = wr_len;
1270 	wr->wrq = wrq;
1271 	return (wr);
1272 }
1273 
1274 static inline void *
1275 wrtod(struct wrqe *wr)
1276 {
1277 	return (&wr->wr[0]);
1278 }
1279 
1280 static inline void
1281 free_wrqe(struct wrqe *wr)
1282 {
1283 	free(wr, M_CXGBE);
1284 }
1285 
1286 static inline void
1287 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1288 {
1289 	struct sge_wrq *wrq = wr->wrq;
1290 
1291 	TXQ_LOCK(wrq);
1292 	t4_wrq_tx_locked(sc, wrq, wr);
1293 	TXQ_UNLOCK(wrq);
1294 }
1295 
1296 static inline int
1297 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1298     int len)
1299 {
1300 
1301 	return (rw_via_memwin(sc, idx, addr, val, len, 0));
1302 }
1303 
1304 static inline int
1305 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1306     const uint32_t *val, int len)
1307 {
1308 
1309 	return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
1310 }
1311 #endif
1312