1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "t4_ioctl.h" 58 #include "common/t4_msg.h" 59 #include "firmware/t4fw_interface.h" 60 61 #define KTR_CXGBE KTR_SPARE3 62 MALLOC_DECLARE(M_CXGBE); 63 #define CXGBE_UNIMPLEMENTED(s) \ 64 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 65 66 #if defined(__i386__) || defined(__amd64__) 67 static __inline void 68 prefetch(void *x) 69 { 70 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 71 } 72 #else 73 #define prefetch(x) 74 #endif 75 76 #ifndef SYSCTL_ADD_UQUAD 77 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 78 #define sysctl_handle_64 sysctl_handle_quad 79 #define CTLTYPE_U64 CTLTYPE_QUAD 80 #endif 81 82 #if (__FreeBSD_version >= 900030) || \ 83 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 84 #define SBUF_DRAIN 1 85 #endif 86 87 struct adapter; 88 typedef struct adapter adapter_t; 89 90 enum { 91 /* 92 * All ingress queues use this entry size. Note that the firmware event 93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 94 * be at least 64. 95 */ 96 IQ_ESIZE = 64, 97 98 /* Default queue sizes for all kinds of ingress queues */ 99 FW_IQ_QSIZE = 256, 100 RX_IQ_QSIZE = 1024, 101 102 /* All egress queues use this entry size */ 103 EQ_ESIZE = 64, 104 105 /* Default queue sizes for all kinds of egress queues */ 106 CTRL_EQ_QSIZE = 128, 107 TX_EQ_QSIZE = 1024, 108 109 #if MJUMPAGESIZE != MCLBYTES 110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 111 #else 112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 113 #endif 114 CL_METADATA_SIZE = CACHE_LINE_SIZE, 115 116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 117 TX_SGL_SEGS = 39, 118 TX_SGL_SEGS_TSO = 38, 119 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 120 }; 121 122 enum { 123 /* adapter intr_type */ 124 INTR_INTX = (1 << 0), 125 INTR_MSI = (1 << 1), 126 INTR_MSIX = (1 << 2) 127 }; 128 129 enum { 130 XGMAC_MTU = (1 << 0), 131 XGMAC_PROMISC = (1 << 1), 132 XGMAC_ALLMULTI = (1 << 2), 133 XGMAC_VLANEX = (1 << 3), 134 XGMAC_UCADDR = (1 << 4), 135 XGMAC_MCADDRS = (1 << 5), 136 137 XGMAC_ALL = 0xffff 138 }; 139 140 enum { 141 /* flags understood by begin_synchronized_op */ 142 HOLD_LOCK = (1 << 0), 143 SLEEP_OK = (1 << 1), 144 INTR_OK = (1 << 2), 145 146 /* flags understood by end_synchronized_op */ 147 LOCK_HELD = HOLD_LOCK, 148 }; 149 150 enum { 151 /* adapter flags */ 152 FULL_INIT_DONE = (1 << 0), 153 FW_OK = (1 << 1), 154 /* INTR_DIRECT = (1 << 2), No longer used. */ 155 MASTER_PF = (1 << 3), 156 ADAP_SYSCTL_CTX = (1 << 4), 157 /* TOM_INIT_DONE= (1 << 5), No longer used */ 158 BUF_PACKING_OK = (1 << 6), 159 IS_VF = (1 << 7), 160 161 CXGBE_BUSY = (1 << 9), 162 163 /* port flags */ 164 HAS_TRACEQ = (1 << 3), 165 166 /* VI flags */ 167 DOOMED = (1 << 0), 168 VI_INIT_DONE = (1 << 1), 169 VI_SYSCTL_CTX = (1 << 2), 170 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 171 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 172 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 173 174 /* adapter debug_flags */ 175 DF_DUMP_MBOX = (1 << 0), 176 }; 177 178 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 179 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 180 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 181 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 182 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 183 184 struct vi_info { 185 device_t dev; 186 struct port_info *pi; 187 188 struct ifnet *ifp; 189 struct ifmedia media; 190 191 unsigned long flags; 192 int if_flags; 193 194 uint16_t *rss, *nm_rss; 195 int smt_idx; /* for convenience */ 196 uint16_t viid; 197 int16_t xact_addr_filt;/* index of exact MAC address filter */ 198 uint16_t rss_size; /* size of VI's RSS table slice */ 199 uint16_t rss_base; /* start of VI's RSS table slice */ 200 201 eventhandler_tag vlan_c; 202 203 int nintr; 204 int first_intr; 205 206 /* These need to be int as they are used in sysctl */ 207 int ntxq; /* # of tx queues */ 208 int first_txq; /* index of first tx queue */ 209 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 210 int nrxq; /* # of rx queues */ 211 int first_rxq; /* index of first rx queue */ 212 int nofldtxq; /* # of offload tx queues */ 213 int first_ofld_txq; /* index of first offload tx queue */ 214 int nofldrxq; /* # of offload rx queues */ 215 int first_ofld_rxq; /* index of first offload rx queue */ 216 int nnmtxq; 217 int first_nm_txq; 218 int nnmrxq; 219 int first_nm_rxq; 220 int tmr_idx; 221 int pktc_idx; 222 int qsize_rxq; 223 int qsize_txq; 224 225 struct timeval last_refreshed; 226 struct fw_vi_stats_vf stats; 227 228 struct callout tick; 229 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 230 231 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 232 }; 233 234 struct tx_ch_rl_params { 235 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 236 uint32_t maxrate; 237 }; 238 239 enum { 240 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */ 241 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */ 242 }; 243 244 struct tx_cl_rl_params { 245 int refcount; 246 u_int flags; 247 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 248 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 249 enum fw_sched_params_mode mode; /* aggr or per-flow */ 250 uint32_t maxrate; 251 uint16_t pktsize; 252 }; 253 254 /* Tx scheduler parameters for a channel/port */ 255 struct tx_sched_params { 256 /* Channel Rate Limiter */ 257 struct tx_ch_rl_params ch_rl; 258 259 /* Class WRR */ 260 /* XXX */ 261 262 /* Class Rate Limiter */ 263 struct tx_cl_rl_params cl_rl[]; 264 }; 265 266 struct port_info { 267 device_t dev; 268 struct adapter *adapter; 269 270 struct vi_info *vi; 271 int nvi; 272 int up_vis; 273 int uld_vis; 274 275 struct tx_sched_params *sched_params; 276 277 struct mtx pi_lock; 278 char lockname[16]; 279 unsigned long flags; 280 281 uint8_t lport; /* associated offload logical port */ 282 int8_t mdio_addr; 283 uint8_t port_type; 284 uint8_t mod_type; 285 uint8_t port_id; 286 uint8_t tx_chan; 287 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 288 289 struct link_config link_cfg; 290 291 struct timeval last_refreshed; 292 struct port_stats stats; 293 u_int tnl_cong_drops; 294 u_int tx_parse_error; 295 296 struct callout tick; 297 }; 298 299 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 300 301 /* Where the cluster came from, how it has been carved up. */ 302 struct cluster_layout { 303 int8_t zidx; 304 int8_t hwidx; 305 uint16_t region1; /* mbufs laid out within this region */ 306 /* region2 is the DMA region */ 307 uint16_t region3; /* cluster_metadata within this region */ 308 }; 309 310 struct cluster_metadata { 311 u_int refcount; 312 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 313 }; 314 315 struct fl_sdesc { 316 caddr_t cl; 317 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 318 struct cluster_layout cll; 319 }; 320 321 struct tx_desc { 322 __be64 flit[8]; 323 }; 324 325 struct tx_sdesc { 326 struct mbuf *m; /* m_nextpkt linked chain of frames */ 327 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 328 }; 329 330 331 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 332 struct iq_desc { 333 struct rss_header rss; 334 uint8_t cpl[IQ_PAD]; 335 struct rsp_ctrl rsp; 336 }; 337 #undef IQ_PAD 338 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 339 340 enum { 341 /* iq flags */ 342 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 343 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 344 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 345 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 346 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 347 348 /* iq state */ 349 IQS_DISABLED = 0, 350 IQS_BUSY = 1, 351 IQS_IDLE = 2, 352 353 /* netmap related flags */ 354 NM_OFF = 0, 355 NM_ON = 1, 356 NM_BUSY = 2, 357 }; 358 359 struct sge_iq; 360 struct rss_header; 361 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 362 struct mbuf *); 363 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 364 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 365 366 /* 367 * Ingress Queue: T4 is producer, driver is consumer. 368 */ 369 struct sge_iq { 370 uint32_t flags; 371 volatile int state; 372 struct adapter *adapter; 373 cpl_handler_t set_tcb_rpl; 374 cpl_handler_t l2t_write_rpl; 375 struct iq_desc *desc; /* KVA of descriptor ring */ 376 int8_t intr_pktc_idx; /* packet count threshold index */ 377 uint8_t gen; /* generation bit */ 378 uint8_t intr_params; /* interrupt holdoff parameters */ 379 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 380 uint16_t qsize; /* size (# of entries) of the queue */ 381 uint16_t sidx; /* index of the entry with the status page */ 382 uint16_t cidx; /* consumer index */ 383 uint16_t cntxt_id; /* SGE context id for the iq */ 384 uint16_t abs_id; /* absolute SGE id for the iq */ 385 386 STAILQ_ENTRY(sge_iq) link; 387 388 bus_dma_tag_t desc_tag; 389 bus_dmamap_t desc_map; 390 bus_addr_t ba; /* bus address of descriptor ring */ 391 }; 392 393 enum { 394 EQ_CTRL = 1, 395 EQ_ETH = 2, 396 EQ_OFLD = 3, 397 398 /* eq flags */ 399 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 400 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 401 EQ_ENABLED = (1 << 3), /* open for business */ 402 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 403 }; 404 405 /* Listed in order of preference. Update t4_sysctls too if you change these */ 406 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 407 408 /* 409 * Egress Queue: driver is producer, T4 is consumer. 410 * 411 * Note: A free list is an egress queue (driver produces the buffers and T4 412 * consumes them) but it's special enough to have its own struct (see sge_fl). 413 */ 414 struct sge_eq { 415 unsigned int flags; /* MUST be first */ 416 unsigned int cntxt_id; /* SGE context id for the eq */ 417 unsigned int abs_id; /* absolute SGE id for the eq */ 418 struct mtx eq_lock; 419 420 struct tx_desc *desc; /* KVA of descriptor ring */ 421 uint16_t doorbells; 422 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 423 u_int udb_qid; /* relative qid within the doorbell page */ 424 uint16_t sidx; /* index of the entry with the status page */ 425 uint16_t cidx; /* consumer idx (desc idx) */ 426 uint16_t pidx; /* producer idx (desc idx) */ 427 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 428 uint16_t dbidx; /* pidx of the most recent doorbell */ 429 uint16_t iqid; /* iq that gets egr_update for the eq */ 430 uint8_t tx_chan; /* tx channel used by the eq */ 431 volatile u_int equiq; /* EQUIQ outstanding */ 432 433 bus_dma_tag_t desc_tag; 434 bus_dmamap_t desc_map; 435 bus_addr_t ba; /* bus address of descriptor ring */ 436 char lockname[16]; 437 }; 438 439 struct sw_zone_info { 440 uma_zone_t zone; /* zone that this cluster comes from */ 441 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 442 int type; /* EXT_xxx type of the cluster */ 443 int8_t head_hwidx; 444 int8_t tail_hwidx; 445 }; 446 447 struct hw_buf_info { 448 int8_t zidx; /* backpointer to zone; -ve means unused */ 449 int8_t next; /* next hwidx for this zone; -1 means no more */ 450 int size; 451 }; 452 453 enum { 454 NUM_MEMWIN = 3, 455 456 MEMWIN0_APERTURE = 2048, 457 MEMWIN0_BASE = 0x1b800, 458 459 MEMWIN1_APERTURE = 32768, 460 MEMWIN1_BASE = 0x28000, 461 462 MEMWIN2_APERTURE_T4 = 65536, 463 MEMWIN2_BASE_T4 = 0x30000, 464 465 MEMWIN2_APERTURE_T5 = 128 * 1024, 466 MEMWIN2_BASE_T5 = 0x60000, 467 }; 468 469 struct memwin { 470 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 471 uint32_t mw_base; /* constant after setup_memwin */ 472 uint32_t mw_aperture; /* ditto */ 473 uint32_t mw_curpos; /* protected by mw_lock */ 474 }; 475 476 enum { 477 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 478 FL_DOOMED = (1 << 1), /* about to be destroyed */ 479 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 480 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 481 }; 482 483 #define FL_RUNNING_LOW(fl) \ 484 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 485 #define FL_NOT_RUNNING_LOW(fl) \ 486 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 487 488 struct sge_fl { 489 struct mtx fl_lock; 490 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 491 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 492 struct cluster_layout cll_def; /* default refill zone, layout */ 493 uint16_t lowat; /* # of buffers <= this means fl needs help */ 494 int flags; 495 uint16_t buf_boundary; 496 497 /* The 16b idx all deal with hw descriptors */ 498 uint16_t dbidx; /* hw pidx after last doorbell */ 499 uint16_t sidx; /* index of status page */ 500 volatile uint16_t hw_cidx; 501 502 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 503 uint32_t cidx; /* consumer index */ 504 uint32_t pidx; /* producer index */ 505 506 uint32_t dbval; 507 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 508 volatile uint32_t *udb; 509 510 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 511 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 512 uint64_t cl_allocated; /* # of clusters allocated */ 513 uint64_t cl_recycled; /* # of clusters recycled */ 514 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 515 516 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 517 struct mbuf *m0; 518 struct mbuf **pnext; 519 u_int remaining; 520 521 uint16_t qsize; /* # of hw descriptors (status page included) */ 522 uint16_t cntxt_id; /* SGE context id for the freelist */ 523 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 524 bus_dma_tag_t desc_tag; 525 bus_dmamap_t desc_map; 526 char lockname[16]; 527 bus_addr_t ba; /* bus address of descriptor ring */ 528 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 529 }; 530 531 struct mp_ring; 532 533 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 534 struct sge_txq { 535 struct sge_eq eq; /* MUST be first */ 536 537 struct ifnet *ifp; /* the interface this txq belongs to */ 538 struct mp_ring *r; /* tx software ring */ 539 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 540 struct sglist *gl; 541 __be32 cpl_ctrl0; /* for convenience */ 542 int tc_idx; /* traffic class */ 543 544 struct task tx_reclaim_task; 545 /* stats for common events first */ 546 547 uint64_t txcsum; /* # of times hardware assisted with checksum */ 548 uint64_t tso_wrs; /* # of TSO work requests */ 549 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 550 uint64_t imm_wrs; /* # of work requests with immediate data */ 551 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 552 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 553 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 554 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 555 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 556 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 557 558 /* stats for not-that-common events */ 559 } __aligned(CACHE_LINE_SIZE); 560 561 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 562 struct sge_rxq { 563 struct sge_iq iq; /* MUST be first */ 564 struct sge_fl fl; /* MUST follow iq */ 565 566 struct ifnet *ifp; /* the interface this rxq belongs to */ 567 #if defined(INET) || defined(INET6) 568 struct lro_ctrl lro; /* LRO state */ 569 #endif 570 571 /* stats for common events first */ 572 573 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 574 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 575 576 /* stats for not-that-common events */ 577 578 } __aligned(CACHE_LINE_SIZE); 579 580 static inline struct sge_rxq * 581 iq_to_rxq(struct sge_iq *iq) 582 { 583 584 return (__containerof(iq, struct sge_rxq, iq)); 585 } 586 587 588 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 589 struct sge_ofld_rxq { 590 struct sge_iq iq; /* MUST be first */ 591 struct sge_fl fl; /* MUST follow iq */ 592 } __aligned(CACHE_LINE_SIZE); 593 594 static inline struct sge_ofld_rxq * 595 iq_to_ofld_rxq(struct sge_iq *iq) 596 { 597 598 return (__containerof(iq, struct sge_ofld_rxq, iq)); 599 } 600 601 struct wrqe { 602 STAILQ_ENTRY(wrqe) link; 603 struct sge_wrq *wrq; 604 int wr_len; 605 char wr[] __aligned(16); 606 }; 607 608 struct wrq_cookie { 609 TAILQ_ENTRY(wrq_cookie) link; 610 int ndesc; 611 int pidx; 612 }; 613 614 /* 615 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 616 * and offload tx queues are of this type. 617 */ 618 struct sge_wrq { 619 struct sge_eq eq; /* MUST be first */ 620 621 struct adapter *adapter; 622 struct task wrq_tx_task; 623 624 /* Tx desc reserved but WR not "committed" yet. */ 625 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 626 627 /* List of WRs ready to go out as soon as descriptors are available. */ 628 STAILQ_HEAD(, wrqe) wr_list; 629 u_int nwr_pending; 630 u_int ndesc_needed; 631 632 /* stats for common events first */ 633 634 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 635 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 636 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 637 638 /* stats for not-that-common events */ 639 640 /* 641 * Scratch space for work requests that wrap around after reaching the 642 * status page, and some information about the last WR that used it. 643 */ 644 uint16_t ss_pidx; 645 uint16_t ss_len; 646 uint8_t ss[SGE_MAX_WR_LEN]; 647 648 } __aligned(CACHE_LINE_SIZE); 649 650 651 struct sge_nm_rxq { 652 struct vi_info *vi; 653 654 struct iq_desc *iq_desc; 655 uint16_t iq_abs_id; 656 uint16_t iq_cntxt_id; 657 uint16_t iq_cidx; 658 uint16_t iq_sidx; 659 uint8_t iq_gen; 660 661 __be64 *fl_desc; 662 uint16_t fl_cntxt_id; 663 uint32_t fl_cidx; 664 uint32_t fl_pidx; 665 uint32_t fl_sidx; 666 uint32_t fl_db_val; 667 u_int fl_hwidx:4; 668 669 u_int nid; /* netmap ring # for this queue */ 670 671 /* infrequently used items after this */ 672 673 bus_dma_tag_t iq_desc_tag; 674 bus_dmamap_t iq_desc_map; 675 bus_addr_t iq_ba; 676 int intr_idx; 677 678 bus_dma_tag_t fl_desc_tag; 679 bus_dmamap_t fl_desc_map; 680 bus_addr_t fl_ba; 681 } __aligned(CACHE_LINE_SIZE); 682 683 struct sge_nm_txq { 684 struct tx_desc *desc; 685 uint16_t cidx; 686 uint16_t pidx; 687 uint16_t sidx; 688 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 689 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 690 uint16_t dbidx; /* pidx of the most recent doorbell */ 691 uint16_t doorbells; 692 volatile uint32_t *udb; 693 u_int udb_qid; 694 u_int cntxt_id; 695 __be32 cpl_ctrl0; /* for convenience */ 696 u_int nid; /* netmap ring # for this queue */ 697 698 /* infrequently used items after this */ 699 700 bus_dma_tag_t desc_tag; 701 bus_dmamap_t desc_map; 702 bus_addr_t ba; 703 int iqidx; 704 } __aligned(CACHE_LINE_SIZE); 705 706 struct sge { 707 int nrxq; /* total # of Ethernet rx queues */ 708 int ntxq; /* total # of Ethernet tx queues */ 709 int nofldrxq; /* total # of TOE rx queues */ 710 int nofldtxq; /* total # of TOE tx queues */ 711 int nnmrxq; /* total # of netmap rx queues */ 712 int nnmtxq; /* total # of netmap tx queues */ 713 int niq; /* total # of ingress queues */ 714 int neq; /* total # of egress queues */ 715 716 struct sge_iq fwq; /* Firmware event queue */ 717 struct sge_wrq mgmtq; /* Management queue (control queue) */ 718 struct sge_wrq *ctrlq; /* Control queues */ 719 struct sge_txq *txq; /* NIC tx queues */ 720 struct sge_rxq *rxq; /* NIC rx queues */ 721 struct sge_wrq *ofld_txq; /* TOE tx queues */ 722 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 723 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 724 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 725 726 uint16_t iq_start; /* first cntxt_id */ 727 uint16_t iq_base; /* first abs_id */ 728 int eq_start; /* first cntxt_id */ 729 int eq_base; /* first abs_id */ 730 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 731 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 732 733 int8_t safe_hwidx1; /* may not have room for metadata */ 734 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 735 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 736 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 737 }; 738 739 struct devnames { 740 const char *nexus_name; 741 const char *ifnet_name; 742 const char *vi_ifnet_name; 743 const char *pf03_drv_name; 744 const char *vf_nexus_name; 745 const char *vf_ifnet_name; 746 }; 747 748 struct adapter { 749 SLIST_ENTRY(adapter) link; 750 device_t dev; 751 struct cdev *cdev; 752 const struct devnames *names; 753 754 /* PCIe register resources */ 755 int regs_rid; 756 struct resource *regs_res; 757 int msix_rid; 758 struct resource *msix_res; 759 bus_space_handle_t bh; 760 bus_space_tag_t bt; 761 bus_size_t mmio_len; 762 int udbs_rid; 763 struct resource *udbs_res; 764 volatile uint8_t *udbs_base; 765 766 unsigned int pf; 767 unsigned int mbox; 768 unsigned int vpd_busy; 769 unsigned int vpd_flag; 770 771 /* Interrupt information */ 772 int intr_type; 773 int intr_count; 774 struct irq { 775 struct resource *res; 776 int rid; 777 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 778 void *tag; 779 struct sge_rxq *rxq; 780 struct sge_nm_rxq *nm_rxq; 781 } __aligned(CACHE_LINE_SIZE) *irq; 782 int sge_gts_reg; 783 int sge_kdoorbell_reg; 784 785 bus_dma_tag_t dmat; /* Parent DMA tag */ 786 787 struct sge sge; 788 int lro_timeout; 789 int sc_do_rxcopy; 790 791 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 792 struct port_info *port[MAX_NPORTS]; 793 uint8_t chan_map[MAX_NCHAN]; 794 795 void *tom_softc; /* (struct tom_data *) */ 796 struct tom_tunables tt; 797 void *iwarp_softc; /* (struct c4iw_dev *) */ 798 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 799 void *ccr_softc; /* (struct ccr_softc *) */ 800 struct l2t_data *l2t; /* L2 table */ 801 struct tid_info tids; 802 803 uint16_t doorbells; 804 int offload_map; /* ports with IFCAP_TOE enabled */ 805 int active_ulds; /* ULDs activated on this adapter */ 806 int flags; 807 int debug_flags; 808 809 char ifp_lockname[16]; 810 struct mtx ifp_lock; 811 struct ifnet *ifp; /* tracer ifp */ 812 struct ifmedia media; 813 int traceq; /* iq used by all tracers, -1 if none */ 814 int tracer_valid; /* bitmap of valid tracers */ 815 int tracer_enabled; /* bitmap of enabled tracers */ 816 817 char fw_version[16]; 818 char tp_version[16]; 819 char er_version[16]; 820 char bs_version[16]; 821 char cfg_file[32]; 822 u_int cfcsum; 823 struct adapter_params params; 824 const struct chip_params *chip_params; 825 struct t4_virt_res vres; 826 827 uint16_t nbmcaps; 828 uint16_t linkcaps; 829 uint16_t switchcaps; 830 uint16_t niccaps; 831 uint16_t toecaps; 832 uint16_t rdmacaps; 833 uint16_t cryptocaps; 834 uint16_t iscsicaps; 835 uint16_t fcoecaps; 836 837 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 838 839 struct mtx sc_lock; 840 char lockname[16]; 841 842 /* Starving free lists */ 843 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 844 TAILQ_HEAD(, sge_fl) sfl; 845 struct callout sfl_callout; 846 847 struct mtx reg_lock; /* for indirect register access */ 848 849 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 850 851 struct mtx tc_lock; 852 struct task tc_task; 853 854 const char *last_op; 855 const void *last_op_thr; 856 int last_op_flags; 857 }; 858 859 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 860 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 861 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 862 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 863 864 #define ASSERT_SYNCHRONIZED_OP(sc) \ 865 KASSERT(IS_BUSY(sc) && \ 866 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 867 ("%s: operation not synchronized.", __func__)) 868 869 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 870 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 871 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 872 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 873 874 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 875 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 876 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 877 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 878 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 879 880 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 881 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 882 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 883 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 884 885 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 886 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 887 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 888 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 889 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 890 891 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 892 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 893 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 894 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 895 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 896 897 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 898 do { \ 899 if (sc->debug_flags & DF_DUMP_MBOX) { \ 900 log(LOG_NOTICE, \ 901 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 902 "%016llx %016llx %016llx %016llx\n", \ 903 device_get_nameunit(sc->dev), mbox, \ 904 (unsigned long long)t4_read_reg64(sc, data_reg), \ 905 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 906 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 907 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 908 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 909 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 910 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 911 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 912 } \ 913 } while (0) 914 915 #define for_each_txq(vi, iter, q) \ 916 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 917 iter < vi->ntxq; ++iter, ++q) 918 #define for_each_rxq(vi, iter, q) \ 919 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 920 iter < vi->nrxq; ++iter, ++q) 921 #define for_each_ofld_txq(vi, iter, q) \ 922 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 923 iter < vi->nofldtxq; ++iter, ++q) 924 #define for_each_ofld_rxq(vi, iter, q) \ 925 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 926 iter < vi->nofldrxq; ++iter, ++q) 927 #define for_each_nm_txq(vi, iter, q) \ 928 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 929 iter < vi->nnmtxq; ++iter, ++q) 930 #define for_each_nm_rxq(vi, iter, q) \ 931 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 932 iter < vi->nnmrxq; ++iter, ++q) 933 #define for_each_vi(_pi, _iter, _vi) \ 934 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 935 ++(_iter), ++(_vi)) 936 937 #define IDXINCR(idx, incr, wrap) do { \ 938 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 939 } while (0) 940 #define IDXDIFF(head, tail, wrap) \ 941 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 942 943 /* One for errors, one for firmware events */ 944 #define T4_EXTRA_INTR 2 945 946 /* One for firmware events */ 947 #define T4VF_EXTRA_INTR 1 948 949 static inline uint32_t 950 t4_read_reg(struct adapter *sc, uint32_t reg) 951 { 952 953 return bus_space_read_4(sc->bt, sc->bh, reg); 954 } 955 956 static inline void 957 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 958 { 959 960 bus_space_write_4(sc->bt, sc->bh, reg, val); 961 } 962 963 static inline uint64_t 964 t4_read_reg64(struct adapter *sc, uint32_t reg) 965 { 966 967 #ifdef __LP64__ 968 return bus_space_read_8(sc->bt, sc->bh, reg); 969 #else 970 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 971 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 972 973 #endif 974 } 975 976 static inline void 977 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 978 { 979 980 #ifdef __LP64__ 981 bus_space_write_8(sc->bt, sc->bh, reg, val); 982 #else 983 bus_space_write_4(sc->bt, sc->bh, reg, val); 984 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 985 #endif 986 } 987 988 static inline void 989 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 990 { 991 992 *val = pci_read_config(sc->dev, reg, 1); 993 } 994 995 static inline void 996 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 997 { 998 999 pci_write_config(sc->dev, reg, val, 1); 1000 } 1001 1002 static inline void 1003 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1004 { 1005 1006 *val = pci_read_config(sc->dev, reg, 2); 1007 } 1008 1009 static inline void 1010 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1011 { 1012 1013 pci_write_config(sc->dev, reg, val, 2); 1014 } 1015 1016 static inline void 1017 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1018 { 1019 1020 *val = pci_read_config(sc->dev, reg, 4); 1021 } 1022 1023 static inline void 1024 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1025 { 1026 1027 pci_write_config(sc->dev, reg, val, 4); 1028 } 1029 1030 static inline struct port_info * 1031 adap2pinfo(struct adapter *sc, int idx) 1032 { 1033 1034 return (sc->port[idx]); 1035 } 1036 1037 static inline void 1038 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 1039 { 1040 1041 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN); 1042 } 1043 1044 static inline bool 1045 is_10G_port(const struct port_info *pi) 1046 { 1047 1048 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1049 } 1050 1051 static inline bool 1052 is_25G_port(const struct port_info *pi) 1053 { 1054 1055 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1056 } 1057 1058 static inline bool 1059 is_40G_port(const struct port_info *pi) 1060 { 1061 1062 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1063 } 1064 1065 static inline bool 1066 is_100G_port(const struct port_info *pi) 1067 { 1068 1069 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1070 } 1071 1072 static inline int 1073 port_top_speed(const struct port_info *pi) 1074 { 1075 1076 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1077 return (100); 1078 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1079 return (40); 1080 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1081 return (25); 1082 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1083 return (10); 1084 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1085 return (1); 1086 1087 return (0); 1088 } 1089 1090 static inline int 1091 port_top_speed_raw(const struct port_info *pi) 1092 { 1093 1094 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1095 return (FW_PORT_CAP_SPEED_100G); 1096 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1097 return (FW_PORT_CAP_SPEED_40G); 1098 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1099 return (FW_PORT_CAP_SPEED_25G); 1100 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1101 return (FW_PORT_CAP_SPEED_10G); 1102 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1103 return (FW_PORT_CAP_SPEED_1G); 1104 1105 return (0); 1106 } 1107 1108 static inline int 1109 tx_resume_threshold(struct sge_eq *eq) 1110 { 1111 1112 /* not quite the same as qsize / 4, but this will do. */ 1113 return (eq->sidx / 4); 1114 } 1115 1116 static inline int 1117 t4_use_ldst(struct adapter *sc) 1118 { 1119 1120 #ifdef notyet 1121 return (sc->flags & FW_OK || !sc->use_bd); 1122 #else 1123 return (0); 1124 #endif 1125 } 1126 1127 /* t4_main.c */ 1128 extern int t4_ntxq10g; 1129 extern int t4_nrxq10g; 1130 extern int t4_ntxq1g; 1131 extern int t4_nrxq1g; 1132 extern int t4_intr_types; 1133 extern int t4_tmr_idx_10g; 1134 extern int t4_pktc_idx_10g; 1135 extern int t4_tmr_idx_1g; 1136 extern int t4_pktc_idx_1g; 1137 extern unsigned int t4_qsize_rxq; 1138 extern unsigned int t4_qsize_txq; 1139 extern device_method_t cxgbe_methods[]; 1140 1141 int t4_os_find_pci_capability(struct adapter *, int); 1142 int t4_os_pci_save_state(struct adapter *); 1143 int t4_os_pci_restore_state(struct adapter *); 1144 void t4_os_portmod_changed(const struct adapter *, int); 1145 void t4_os_link_changed(struct adapter *, int, int); 1146 void t4_iterate(void (*)(struct adapter *, void *), void *); 1147 void t4_init_devnames(struct adapter *); 1148 void t4_add_adapter(struct adapter *); 1149 int t4_detach_common(device_t); 1150 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1151 int t4_map_bars_0_and_4(struct adapter *); 1152 int t4_map_bar_2(struct adapter *); 1153 int t4_setup_intr_handlers(struct adapter *); 1154 void t4_sysctls(struct adapter *); 1155 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1156 void doom_vi(struct adapter *, struct vi_info *); 1157 void end_synchronized_op(struct adapter *, int); 1158 int update_mac_settings(struct ifnet *, int); 1159 int adapter_full_init(struct adapter *); 1160 int adapter_full_uninit(struct adapter *); 1161 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1162 int vi_full_init(struct vi_info *); 1163 int vi_full_uninit(struct vi_info *); 1164 void vi_sysctls(struct vi_info *); 1165 void vi_tick(void *); 1166 1167 #ifdef DEV_NETMAP 1168 /* t4_netmap.c */ 1169 void cxgbe_nm_attach(struct vi_info *); 1170 void cxgbe_nm_detach(struct vi_info *); 1171 void t4_nm_intr(void *); 1172 #endif 1173 1174 /* t4_sge.c */ 1175 void t4_sge_modload(void); 1176 void t4_sge_modunload(void); 1177 uint64_t t4_sge_extfree_refs(void); 1178 void t4_tweak_chip_settings(struct adapter *); 1179 int t4_read_chip_settings(struct adapter *); 1180 int t4_create_dma_tag(struct adapter *); 1181 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1182 struct sysctl_oid_list *); 1183 int t4_destroy_dma_tag(struct adapter *); 1184 int t4_setup_adapter_queues(struct adapter *); 1185 int t4_teardown_adapter_queues(struct adapter *); 1186 int t4_setup_vi_queues(struct vi_info *); 1187 int t4_teardown_vi_queues(struct vi_info *); 1188 void t4_intr_all(void *); 1189 void t4_intr(void *); 1190 void t4_vi_intr(void *); 1191 void t4_intr_err(void *); 1192 void t4_intr_evt(void *); 1193 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1194 void t4_update_fl_bufsize(struct ifnet *); 1195 int parse_pkt(struct adapter *, struct mbuf **); 1196 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1197 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1198 int tnl_cong(struct port_info *, int); 1199 int t4_register_an_handler(an_handler_t); 1200 int t4_register_fw_msg_handler(int, fw_msg_handler_t); 1201 int t4_register_cpl_handler(int, cpl_handler_t); 1202 1203 /* t4_tracer.c */ 1204 struct t4_tracer; 1205 void t4_tracer_modload(void); 1206 void t4_tracer_modunload(void); 1207 void t4_tracer_port_detach(struct adapter *); 1208 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1209 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1210 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1211 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1212 1213 /* t4_sched.c */ 1214 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1215 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1216 int t4_init_tx_sched(struct adapter *); 1217 int t4_free_tx_sched(struct adapter *); 1218 void t4_update_tx_sched(struct adapter *); 1219 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1220 void t4_release_cl_rl_kbps(struct adapter *, int, int); 1221 1222 static inline struct wrqe * 1223 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1224 { 1225 int len = offsetof(struct wrqe, wr) + wr_len; 1226 struct wrqe *wr; 1227 1228 wr = malloc(len, M_CXGBE, M_NOWAIT); 1229 if (__predict_false(wr == NULL)) 1230 return (NULL); 1231 wr->wr_len = wr_len; 1232 wr->wrq = wrq; 1233 return (wr); 1234 } 1235 1236 static inline void * 1237 wrtod(struct wrqe *wr) 1238 { 1239 return (&wr->wr[0]); 1240 } 1241 1242 static inline void 1243 free_wrqe(struct wrqe *wr) 1244 { 1245 free(wr, M_CXGBE); 1246 } 1247 1248 static inline void 1249 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1250 { 1251 struct sge_wrq *wrq = wr->wrq; 1252 1253 TXQ_LOCK(wrq); 1254 t4_wrq_tx_locked(sc, wrq, wr); 1255 TXQ_UNLOCK(wrq); 1256 } 1257 1258 #endif 1259