1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #ifndef T4_MSG_H 33 #define T4_MSG_H 34 35 enum { 36 CPL_PASS_OPEN_REQ = 0x1, 37 CPL_PASS_ACCEPT_RPL = 0x2, 38 CPL_ACT_OPEN_REQ = 0x3, 39 CPL_SET_TCB = 0x4, 40 CPL_SET_TCB_FIELD = 0x5, 41 CPL_GET_TCB = 0x6, 42 CPL_CLOSE_CON_REQ = 0x8, 43 CPL_CLOSE_LISTSRV_REQ = 0x9, 44 CPL_ABORT_REQ = 0xA, 45 CPL_ABORT_RPL = 0xB, 46 CPL_TX_DATA = 0xC, 47 CPL_RX_DATA_ACK = 0xD, 48 CPL_TX_PKT = 0xE, 49 CPL_RTE_DELETE_REQ = 0xF, 50 CPL_RTE_WRITE_REQ = 0x10, 51 CPL_RTE_READ_REQ = 0x11, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_L2T_READ_REQ = 0x13, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_SMT_READ_REQ = 0x15, 56 CPL_TAG_WRITE_REQ = 0x16, 57 CPL_BARRIER = 0x18, 58 CPL_TID_RELEASE = 0x1A, 59 CPL_TAG_READ_REQ = 0x1B, 60 CPL_SRQ_TABLE_REQ = 0x1C, 61 CPL_TX_PKT_FSO = 0x1E, 62 CPL_TX_DATA_ISO = 0x1F, 63 64 CPL_CLOSE_LISTSRV_RPL = 0x20, 65 CPL_ERROR = 0x21, 66 CPL_GET_TCB_RPL = 0x22, 67 CPL_L2T_WRITE_RPL = 0x23, 68 CPL_PASS_OPEN_RPL = 0x24, 69 CPL_ACT_OPEN_RPL = 0x25, 70 CPL_PEER_CLOSE = 0x26, 71 CPL_RTE_DELETE_RPL = 0x27, 72 CPL_RTE_WRITE_RPL = 0x28, 73 CPL_RX_URG_PKT = 0x29, 74 CPL_TAG_WRITE_RPL = 0x2A, 75 CPL_ABORT_REQ_RSS = 0x2B, 76 CPL_RX_URG_NOTIFY = 0x2C, 77 CPL_ABORT_RPL_RSS = 0x2D, 78 CPL_SMT_WRITE_RPL = 0x2E, 79 CPL_TX_DATA_ACK = 0x2F, 80 81 CPL_RX_PHYS_ADDR = 0x30, 82 CPL_PCMD_READ_RPL = 0x31, 83 CPL_CLOSE_CON_RPL = 0x32, 84 CPL_ISCSI_HDR = 0x33, 85 CPL_L2T_READ_RPL = 0x34, 86 CPL_RDMA_CQE = 0x35, 87 CPL_RDMA_CQE_READ_RSP = 0x36, 88 CPL_RDMA_CQE_ERR = 0x37, 89 CPL_RTE_READ_RPL = 0x38, 90 CPL_RX_DATA = 0x39, 91 CPL_SET_TCB_RPL = 0x3A, 92 CPL_RX_PKT = 0x3B, 93 CPL_TAG_READ_RPL = 0x3C, 94 CPL_HIT_NOTIFY = 0x3D, 95 CPL_PKT_NOTIFY = 0x3E, 96 CPL_RX_DDP_COMPLETE = 0x3F, 97 98 CPL_ACT_ESTABLISH = 0x40, 99 CPL_PASS_ESTABLISH = 0x41, 100 CPL_RX_DATA_DDP = 0x42, 101 CPL_SMT_READ_RPL = 0x43, 102 CPL_PASS_ACCEPT_REQ = 0x44, 103 CPL_RX_ISCSI_CMP = 0x45, 104 CPL_RX_FCOE_DDP = 0x46, 105 CPL_FCOE_HDR = 0x47, 106 CPL_T5_TRACE_PKT = 0x48, 107 CPL_RX_ISCSI_DDP = 0x49, 108 CPL_RX_FCOE_DIF = 0x4A, 109 CPL_RX_DATA_DIF = 0x4B, 110 CPL_ERR_NOTIFY = 0x4D, 111 CPL_RX_TLS_CMP = 0x4E, 112 113 CPL_RDMA_READ_REQ = 0x60, 114 CPL_RX_ISCSI_DIF = 0x60, 115 116 CPL_SET_LE_REQ = 0x80, 117 CPL_PASS_OPEN_REQ6 = 0x81, 118 CPL_ACT_OPEN_REQ6 = 0x83, 119 CPL_TX_TLS_PDU = 0x88, 120 CPL_TX_TLS_SFO = 0x89, 121 122 CPL_TX_SEC_PDU = 0x8A, 123 CPL_TX_TLS_ACK = 0x8B, 124 125 CPL_RDMA_TERMINATE = 0xA2, 126 CPL_RDMA_WRITE = 0xA4, 127 CPL_SGE_EGR_UPDATE = 0xA5, 128 CPL_SET_LE_RPL = 0xA6, 129 CPL_FW2_MSG = 0xA7, 130 CPL_FW2_PLD = 0xA8, 131 CPL_T5_RDMA_READ_REQ = 0xA9, 132 CPL_RDMA_ATOMIC_REQ = 0xAA, 133 CPL_RDMA_ATOMIC_RPL = 0xAB, 134 CPL_RDMA_IMM_DATA = 0xAC, 135 CPL_RDMA_IMM_DATA_SE = 0xAD, 136 CPL_RX_MPS_PKT = 0xAF, 137 138 CPL_TRACE_PKT = 0xB0, 139 CPL_RX2TX_DATA = 0xB1, 140 CPL_TLS_DATA = 0xB1, 141 CPL_ISCSI_DATA = 0xB2, 142 CPL_FCOE_DATA = 0xB3, 143 144 CPL_FW4_MSG = 0xC0, 145 CPL_FW4_PLD = 0xC1, 146 CPL_FW4_ACK = 0xC3, 147 CPL_SRQ_TABLE_RPL = 0xCC, 148 CPL_RX_PHYS_DSGL = 0xD0, 149 150 CPL_FW6_MSG = 0xE0, 151 CPL_FW6_PLD = 0xE1, 152 CPL_TX_TNL_LSO = 0xEC, 153 CPL_TX_PKT_LSO = 0xED, 154 CPL_TX_PKT_XT = 0xEE, 155 156 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 157 }; 158 159 enum CPL_error { 160 CPL_ERR_NONE = 0, 161 CPL_ERR_TCAM_PARITY = 1, 162 CPL_ERR_TCAM_MISS = 2, 163 CPL_ERR_TCAM_FULL = 3, 164 CPL_ERR_BAD_LENGTH = 15, 165 CPL_ERR_BAD_ROUTE = 18, 166 CPL_ERR_CONN_RESET = 20, 167 CPL_ERR_CONN_EXIST_SYNRECV = 21, 168 CPL_ERR_CONN_EXIST = 22, 169 CPL_ERR_ARP_MISS = 23, 170 CPL_ERR_BAD_SYN = 24, 171 CPL_ERR_CONN_TIMEDOUT = 30, 172 CPL_ERR_XMIT_TIMEDOUT = 31, 173 CPL_ERR_PERSIST_TIMEDOUT = 32, 174 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 175 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 176 CPL_ERR_RTX_NEG_ADVICE = 35, 177 CPL_ERR_PERSIST_NEG_ADVICE = 36, 178 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 179 CPL_ERR_WAIT_ARP_RPL = 41, 180 CPL_ERR_ABORT_FAILED = 42, 181 CPL_ERR_IWARP_FLM = 50, 182 CPL_CONTAINS_READ_RPL = 60, 183 CPL_CONTAINS_WRITE_RPL = 61, 184 }; 185 186 /* 187 * Some of the error codes above implicitly indicate that there is no TID 188 * allocated with the result of an ACT_OPEN. We use this predicate to make 189 * that explicit. 190 */ 191 static inline int act_open_has_tid(int status) 192 { 193 return (status != CPL_ERR_TCAM_PARITY && 194 status != CPL_ERR_TCAM_MISS && 195 status != CPL_ERR_TCAM_FULL && 196 status != CPL_ERR_CONN_EXIST_SYNRECV && 197 status != CPL_ERR_CONN_EXIST); 198 } 199 200 /* 201 * Convert an ACT_OPEN_RPL status to an errno. 202 */ 203 static inline int 204 act_open_rpl_status_to_errno(int status) 205 { 206 207 switch (status) { 208 case CPL_ERR_CONN_RESET: 209 return (ECONNREFUSED); 210 case CPL_ERR_ARP_MISS: 211 return (EHOSTUNREACH); 212 case CPL_ERR_CONN_TIMEDOUT: 213 return (ETIMEDOUT); 214 case CPL_ERR_TCAM_FULL: 215 return (EAGAIN); 216 case CPL_ERR_CONN_EXIST: 217 return (EAGAIN); 218 default: 219 return (EIO); 220 } 221 } 222 223 224 enum { 225 CPL_CONN_POLICY_AUTO = 0, 226 CPL_CONN_POLICY_ASK = 1, 227 CPL_CONN_POLICY_FILTER = 2, 228 CPL_CONN_POLICY_DENY = 3 229 }; 230 231 enum { 232 ULP_MODE_NONE = 0, 233 ULP_MODE_ISCSI = 2, 234 ULP_MODE_RDMA = 4, 235 ULP_MODE_TCPDDP = 5, 236 ULP_MODE_FCOE = 6, 237 ULP_MODE_TLS = 8, 238 }; 239 240 enum { 241 ULP_CRC_HEADER = 1 << 0, 242 ULP_CRC_DATA = 1 << 1 243 }; 244 245 enum { 246 CPL_PASS_OPEN_ACCEPT, 247 CPL_PASS_OPEN_REJECT, 248 CPL_PASS_OPEN_ACCEPT_TNL 249 }; 250 251 enum { 252 CPL_ABORT_SEND_RST = 0, 253 CPL_ABORT_NO_RST, 254 }; 255 256 enum { /* TX_PKT_XT checksum types */ 257 TX_CSUM_TCP = 0, 258 TX_CSUM_UDP = 1, 259 TX_CSUM_CRC16 = 4, 260 TX_CSUM_CRC32 = 5, 261 TX_CSUM_CRC32C = 6, 262 TX_CSUM_FCOE = 7, 263 TX_CSUM_TCPIP = 8, 264 TX_CSUM_UDPIP = 9, 265 TX_CSUM_TCPIP6 = 10, 266 TX_CSUM_UDPIP6 = 11, 267 TX_CSUM_IP = 12, 268 }; 269 270 enum { /* packet type in CPL_RX_PKT */ 271 PKTYPE_XACT_UCAST = 0, 272 PKTYPE_HASH_UCAST = 1, 273 PKTYPE_XACT_MCAST = 2, 274 PKTYPE_HASH_MCAST = 3, 275 PKTYPE_PROMISC = 4, 276 PKTYPE_HPROMISC = 5, 277 PKTYPE_BCAST = 6 278 }; 279 280 enum { /* DMAC type in CPL_RX_PKT */ 281 DATYPE_UCAST, 282 DATYPE_MCAST, 283 DATYPE_BCAST 284 }; 285 286 enum { /* TCP congestion control algorithms */ 287 CONG_ALG_RENO, 288 CONG_ALG_TAHOE, 289 CONG_ALG_NEWRENO, 290 CONG_ALG_HIGHSPEED 291 }; 292 293 enum { /* RSS hash type */ 294 RSS_HASH_NONE = 0, /* no hash computed */ 295 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 296 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 297 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 298 }; 299 300 enum { /* LE commands */ 301 LE_CMD_READ = 0x4, 302 LE_CMD_WRITE = 0xb 303 }; 304 305 enum { /* LE request size */ 306 LE_SZ_NONE = 0, 307 LE_SZ_33 = 1, 308 LE_SZ_66 = 2, 309 LE_SZ_132 = 3, 310 LE_SZ_264 = 4, 311 LE_SZ_528 = 5 312 }; 313 314 union opcode_tid { 315 __be32 opcode_tid; 316 __u8 opcode; 317 }; 318 319 #define S_CPL_OPCODE 24 320 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 321 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 322 #define G_TID(x) ((x) & 0xFFFFFF) 323 324 /* tid is assumed to be 24-bits */ 325 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 326 327 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 328 329 /* extract the TID from a CPL command */ 330 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 331 #define GET_OPCODE(cmd) ((cmd)->ot.opcode) 332 333 /* partitioning of TID fields that also carry a queue id */ 334 #define S_TID_TID 0 335 #define M_TID_TID 0x7ff 336 #define V_TID_TID(x) ((x) << S_TID_TID) 337 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 338 339 #define S_TID_COOKIE 11 340 #define M_TID_COOKIE 0x7 341 #define V_TID_COOKIE(x) ((x) << S_TID_COOKIE) 342 #define G_TID_COOKIE(x) (((x) >> S_TID_COOKIE) & M_TID_COOKIE) 343 344 #define S_TID_QID 14 345 #define M_TID_QID 0x3ff 346 #define V_TID_QID(x) ((x) << S_TID_QID) 347 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 348 349 union opcode_info { 350 __be64 opcode_info; 351 __u8 opcode; 352 }; 353 354 struct tcp_options { 355 __be16 mss; 356 __u8 wsf; 357 #if defined(__LITTLE_ENDIAN_BITFIELD) 358 __u8 :4; 359 __u8 unknown:1; 360 __u8 ecn:1; 361 __u8 sack:1; 362 __u8 tstamp:1; 363 #else 364 __u8 tstamp:1; 365 __u8 sack:1; 366 __u8 ecn:1; 367 __u8 unknown:1; 368 __u8 :4; 369 #endif 370 }; 371 372 struct rss_header { 373 __u8 opcode; 374 #if defined(__LITTLE_ENDIAN_BITFIELD) 375 __u8 channel:2; 376 __u8 filter_hit:1; 377 __u8 filter_tid:1; 378 __u8 hash_type:2; 379 __u8 ipv6:1; 380 __u8 send2fw:1; 381 #else 382 __u8 send2fw:1; 383 __u8 ipv6:1; 384 __u8 hash_type:2; 385 __u8 filter_tid:1; 386 __u8 filter_hit:1; 387 __u8 channel:2; 388 #endif 389 __be16 qid; 390 __be32 hash_val; 391 }; 392 393 #define S_HASHTYPE 20 394 #define M_HASHTYPE 0x3 395 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 396 397 #define S_QNUM 0 398 #define M_QNUM 0xFFFF 399 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 400 401 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW) 402 # define RSS_HDR struct rss_header rss_hdr; 403 #else 404 # define RSS_HDR 405 #endif 406 407 #ifndef CHELSIO_FW 408 struct work_request_hdr { 409 __be32 wr_hi; 410 __be32 wr_mid; 411 __be64 wr_lo; 412 }; 413 414 /* wr_mid fields */ 415 #define S_WR_LEN16 0 416 #define M_WR_LEN16 0xFF 417 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 418 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 419 420 /* wr_hi fields */ 421 #define S_WR_OP 24 422 #define M_WR_OP 0xFF 423 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 424 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 425 426 # define WR_HDR struct work_request_hdr wr 427 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 428 #else 429 # define WR_HDR 430 # define WR_HDR_SIZE 0 431 #endif 432 433 /* option 0 fields */ 434 #define S_ACCEPT_MODE 0 435 #define M_ACCEPT_MODE 0x3 436 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 437 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 438 439 #define S_TX_CHAN 2 440 #define M_TX_CHAN 0x3 441 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 442 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 443 444 #define S_NO_CONG 4 445 #define V_NO_CONG(x) ((x) << S_NO_CONG) 446 #define F_NO_CONG V_NO_CONG(1U) 447 448 #define S_DELACK 5 449 #define V_DELACK(x) ((x) << S_DELACK) 450 #define F_DELACK V_DELACK(1U) 451 452 #define S_INJECT_TIMER 6 453 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 454 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 455 456 #define S_NON_OFFLOAD 7 457 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 458 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 459 460 #define S_ULP_MODE 8 461 #define M_ULP_MODE 0xF 462 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 463 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 464 465 #define S_RCV_BUFSIZ 12 466 #define M_RCV_BUFSIZ 0x3FFU 467 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 468 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 469 470 #define S_DSCP 22 471 #define M_DSCP 0x3F 472 #define V_DSCP(x) ((x) << S_DSCP) 473 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 474 475 #define S_SMAC_SEL 28 476 #define M_SMAC_SEL 0xFF 477 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 478 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 479 480 #define S_L2T_IDX 36 481 #define M_L2T_IDX 0xFFF 482 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 483 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 484 485 #define S_TCAM_BYPASS 48 486 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 487 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 488 489 #define S_NAGLE 49 490 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 491 #define F_NAGLE V_NAGLE(1ULL) 492 493 #define S_WND_SCALE 50 494 #define M_WND_SCALE 0xF 495 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 496 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 497 498 #define S_KEEP_ALIVE 54 499 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 500 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 501 502 #define S_MAX_RT 55 503 #define M_MAX_RT 0xF 504 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 505 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 506 507 #define S_MAX_RT_OVERRIDE 59 508 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 509 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 510 511 #define S_MSS_IDX 60 512 #define M_MSS_IDX 0xF 513 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 514 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 515 516 /* option 1 fields */ 517 #define S_SYN_RSS_ENABLE 0 518 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 519 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 520 521 #define S_SYN_RSS_USE_HASH 1 522 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 523 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 524 525 #define S_SYN_RSS_QUEUE 2 526 #define M_SYN_RSS_QUEUE 0x3FF 527 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 528 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 529 530 #define S_LISTEN_INTF 12 531 #define M_LISTEN_INTF 0xFF 532 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 533 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 534 535 #define S_LISTEN_FILTER 20 536 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 537 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 538 539 #define S_SYN_DEFENSE 21 540 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 541 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 542 543 #define S_CONN_POLICY 22 544 #define M_CONN_POLICY 0x3 545 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 546 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 547 548 #define S_T5_FILT_INFO 24 549 #define M_T5_FILT_INFO 0xffffffffffULL 550 #define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO) 551 #define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO) 552 553 #define S_FILT_INFO 28 554 #define M_FILT_INFO 0xfffffffffULL 555 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 556 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 557 558 /* option 2 fields */ 559 #define S_RSS_QUEUE 0 560 #define M_RSS_QUEUE 0x3FF 561 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 562 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 563 564 #define S_RSS_QUEUE_VALID 10 565 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 566 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 567 568 #define S_RX_COALESCE_VALID 11 569 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 570 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 571 572 #define S_RX_COALESCE 12 573 #define M_RX_COALESCE 0x3 574 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 575 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 576 577 #define S_CONG_CNTRL 14 578 #define M_CONG_CNTRL 0x3 579 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 580 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 581 582 #define S_PACE 16 583 #define M_PACE 0x3 584 #define V_PACE(x) ((x) << S_PACE) 585 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 586 587 #define S_CONG_CNTRL_VALID 18 588 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 589 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 590 591 #define S_T5_ISS 18 592 #define V_T5_ISS(x) ((x) << S_T5_ISS) 593 #define F_T5_ISS V_T5_ISS(1U) 594 595 #define S_PACE_VALID 19 596 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 597 #define F_PACE_VALID V_PACE_VALID(1U) 598 599 #define S_RX_FC_DISABLE 20 600 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 601 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 602 603 #define S_RX_FC_DDP 21 604 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 605 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 606 607 #define S_RX_FC_VALID 22 608 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 609 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 610 611 #define S_TX_QUEUE 23 612 #define M_TX_QUEUE 0x7 613 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 614 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 615 616 #define S_RX_CHANNEL 26 617 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 618 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 619 620 #define S_CCTRL_ECN 27 621 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 622 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 623 624 #define S_WND_SCALE_EN 28 625 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 626 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 627 628 #define S_TSTAMPS_EN 29 629 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 630 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 631 632 #define S_SACK_EN 30 633 #define V_SACK_EN(x) ((x) << S_SACK_EN) 634 #define F_SACK_EN V_SACK_EN(1U) 635 636 #define S_T5_OPT_2_VALID 31 637 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 638 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 639 640 struct cpl_pass_open_req { 641 WR_HDR; 642 union opcode_tid ot; 643 __be16 local_port; 644 __be16 peer_port; 645 __be32 local_ip; 646 __be32 peer_ip; 647 __be64 opt0; 648 __be64 opt1; 649 }; 650 651 struct cpl_pass_open_req6 { 652 WR_HDR; 653 union opcode_tid ot; 654 __be16 local_port; 655 __be16 peer_port; 656 __be64 local_ip_hi; 657 __be64 local_ip_lo; 658 __be64 peer_ip_hi; 659 __be64 peer_ip_lo; 660 __be64 opt0; 661 __be64 opt1; 662 }; 663 664 struct cpl_pass_open_rpl { 665 RSS_HDR 666 union opcode_tid ot; 667 __u8 rsvd[3]; 668 __u8 status; 669 }; 670 671 struct cpl_pass_establish { 672 RSS_HDR 673 union opcode_tid ot; 674 __be32 rsvd; 675 __be32 tos_stid; 676 __be16 mac_idx; 677 __be16 tcp_opt; 678 __be32 snd_isn; 679 __be32 rcv_isn; 680 }; 681 682 /* cpl_pass_establish.tos_stid fields */ 683 #define S_PASS_OPEN_TID 0 684 #define M_PASS_OPEN_TID 0xFFFFFF 685 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 686 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 687 688 #define S_PASS_OPEN_TOS 24 689 #define M_PASS_OPEN_TOS 0xFF 690 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 691 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 692 693 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 694 #define S_TCPOPT_WSCALE_OK 5 695 #define M_TCPOPT_WSCALE_OK 0x1 696 #define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK) 697 #define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK) 698 699 #define S_TCPOPT_SACK 6 700 #define M_TCPOPT_SACK 0x1 701 #define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK) 702 #define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK) 703 704 #define S_TCPOPT_TSTAMP 7 705 #define M_TCPOPT_TSTAMP 0x1 706 #define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP) 707 #define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP) 708 709 #define S_TCPOPT_SND_WSCALE 8 710 #define M_TCPOPT_SND_WSCALE 0xF 711 #define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE) 712 #define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE) 713 714 #define S_TCPOPT_MSS 12 715 #define M_TCPOPT_MSS 0xF 716 #define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS) 717 #define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS) 718 719 struct cpl_pass_accept_req { 720 RSS_HDR 721 union opcode_tid ot; 722 __be16 rsvd; 723 __be16 len; 724 __be32 hdr_len; 725 __be16 vlan; 726 __be16 l2info; 727 __be32 tos_stid; 728 struct tcp_options tcpopt; 729 }; 730 731 /* cpl_pass_accept_req.hdr_len fields */ 732 #define S_SYN_RX_CHAN 0 733 #define M_SYN_RX_CHAN 0xF 734 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 735 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 736 737 #define S_TCP_HDR_LEN 10 738 #define M_TCP_HDR_LEN 0x3F 739 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 740 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 741 742 #define S_T6_TCP_HDR_LEN 8 743 #define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN) 744 #define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN) 745 746 #define S_IP_HDR_LEN 16 747 #define M_IP_HDR_LEN 0x3FF 748 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 749 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 750 751 #define S_T6_IP_HDR_LEN 14 752 #define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN) 753 #define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN) 754 755 #define S_ETH_HDR_LEN 26 756 #define M_ETH_HDR_LEN 0x3F 757 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 758 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 759 760 #define S_T6_ETH_HDR_LEN 24 761 #define M_T6_ETH_HDR_LEN 0xFF 762 #define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN) 763 #define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN) 764 765 /* cpl_pass_accept_req.l2info fields */ 766 #define S_SYN_MAC_IDX 0 767 #define M_SYN_MAC_IDX 0x1FF 768 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 769 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 770 771 #define S_SYN_XACT_MATCH 9 772 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 773 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 774 775 #define S_SYN_INTF 12 776 #define M_SYN_INTF 0xF 777 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 778 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 779 780 struct cpl_pass_accept_rpl { 781 WR_HDR; 782 union opcode_tid ot; 783 __be32 opt2; 784 __be64 opt0; 785 }; 786 787 struct cpl_t5_pass_accept_rpl { 788 WR_HDR; 789 union opcode_tid ot; 790 __be32 opt2; 791 __be64 opt0; 792 __be32 iss; 793 union { 794 __be32 rsvd; /* T5 */ 795 __be32 opt3; /* T6 */ 796 } u; 797 }; 798 799 struct cpl_act_open_req { 800 WR_HDR; 801 union opcode_tid ot; 802 __be16 local_port; 803 __be16 peer_port; 804 __be32 local_ip; 805 __be32 peer_ip; 806 __be64 opt0; 807 __be32 params; 808 __be32 opt2; 809 }; 810 811 #define S_FILTER_TUPLE 24 812 #define M_FILTER_TUPLE 0xFFFFFFFFFF 813 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 814 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 815 struct cpl_t5_act_open_req { 816 WR_HDR; 817 union opcode_tid ot; 818 __be16 local_port; 819 __be16 peer_port; 820 __be32 local_ip; 821 __be32 peer_ip; 822 __be64 opt0; 823 __be32 iss; 824 __be32 opt2; 825 __be64 params; 826 }; 827 828 struct cpl_t6_act_open_req { 829 WR_HDR; 830 union opcode_tid ot; 831 __be16 local_port; 832 __be16 peer_port; 833 __be32 local_ip; 834 __be32 peer_ip; 835 __be64 opt0; 836 __be32 iss; 837 __be32 opt2; 838 __be64 params; 839 __be32 rsvd2; 840 __be32 opt3; 841 }; 842 843 /* cpl_{t5,t6}_act_open_req.params field */ 844 #define S_AOPEN_FCOEMASK 0 845 #define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK) 846 #define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U) 847 848 struct cpl_act_open_req6 { 849 WR_HDR; 850 union opcode_tid ot; 851 __be16 local_port; 852 __be16 peer_port; 853 __be64 local_ip_hi; 854 __be64 local_ip_lo; 855 __be64 peer_ip_hi; 856 __be64 peer_ip_lo; 857 __be64 opt0; 858 __be32 params; 859 __be32 opt2; 860 }; 861 862 struct cpl_t5_act_open_req6 { 863 WR_HDR; 864 union opcode_tid ot; 865 __be16 local_port; 866 __be16 peer_port; 867 __be64 local_ip_hi; 868 __be64 local_ip_lo; 869 __be64 peer_ip_hi; 870 __be64 peer_ip_lo; 871 __be64 opt0; 872 __be32 iss; 873 __be32 opt2; 874 __be64 params; 875 }; 876 877 struct cpl_t6_act_open_req6 { 878 WR_HDR; 879 union opcode_tid ot; 880 __be16 local_port; 881 __be16 peer_port; 882 __be64 local_ip_hi; 883 __be64 local_ip_lo; 884 __be64 peer_ip_hi; 885 __be64 peer_ip_lo; 886 __be64 opt0; 887 __be32 iss; 888 __be32 opt2; 889 __be64 params; 890 __be32 rsvd2; 891 __be32 opt3; 892 }; 893 894 struct cpl_act_open_rpl { 895 RSS_HDR 896 union opcode_tid ot; 897 __be32 atid_status; 898 }; 899 900 /* cpl_act_open_rpl.atid_status fields */ 901 #define S_AOPEN_STATUS 0 902 #define M_AOPEN_STATUS 0xFF 903 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 904 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 905 906 #define S_AOPEN_ATID 8 907 #define M_AOPEN_ATID 0xFFFFFF 908 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 909 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 910 911 struct cpl_act_establish { 912 RSS_HDR 913 union opcode_tid ot; 914 __be32 rsvd; 915 __be32 tos_atid; 916 __be16 mac_idx; 917 __be16 tcp_opt; 918 __be32 snd_isn; 919 __be32 rcv_isn; 920 }; 921 922 struct cpl_get_tcb { 923 WR_HDR; 924 union opcode_tid ot; 925 __be16 reply_ctrl; 926 __u8 rsvd; 927 __u8 cookie; 928 }; 929 930 /* cpl_get_tcb.reply_ctrl fields */ 931 #define S_QUEUENO 0 932 #define M_QUEUENO 0x3FF 933 #define V_QUEUENO(x) ((x) << S_QUEUENO) 934 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 935 936 #define S_REPLY_CHAN 14 937 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 938 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 939 940 #define S_NO_REPLY 15 941 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 942 #define F_NO_REPLY V_NO_REPLY(1U) 943 944 struct cpl_get_tcb_rpl { 945 RSS_HDR 946 union opcode_tid ot; 947 __u8 cookie; 948 __u8 status; 949 __be16 len; 950 }; 951 952 struct cpl_set_tcb { 953 WR_HDR; 954 union opcode_tid ot; 955 __be16 reply_ctrl; 956 __be16 cookie; 957 }; 958 959 struct cpl_set_tcb_field { 960 WR_HDR; 961 union opcode_tid ot; 962 __be16 reply_ctrl; 963 __be16 word_cookie; 964 __be64 mask; 965 __be64 val; 966 }; 967 968 struct cpl_set_tcb_field_core { 969 union opcode_tid ot; 970 __be16 reply_ctrl; 971 __be16 word_cookie; 972 __be64 mask; 973 __be64 val; 974 }; 975 976 /* cpl_set_tcb_field.word_cookie fields */ 977 #define S_WORD 0 978 #define M_WORD 0x1F 979 #define V_WORD(x) ((x) << S_WORD) 980 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 981 982 #define S_COOKIE 5 983 #define M_COOKIE 0x7 984 #define V_COOKIE(x) ((x) << S_COOKIE) 985 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 986 987 struct cpl_set_tcb_rpl { 988 RSS_HDR 989 union opcode_tid ot; 990 __be16 rsvd; 991 __u8 cookie; 992 __u8 status; 993 __be64 oldval; 994 }; 995 996 struct cpl_close_con_req { 997 WR_HDR; 998 union opcode_tid ot; 999 __be32 rsvd; 1000 }; 1001 1002 struct cpl_close_con_rpl { 1003 RSS_HDR 1004 union opcode_tid ot; 1005 __u8 rsvd[3]; 1006 __u8 status; 1007 __be32 snd_nxt; 1008 __be32 rcv_nxt; 1009 }; 1010 1011 struct cpl_close_listsvr_req { 1012 WR_HDR; 1013 union opcode_tid ot; 1014 __be16 reply_ctrl; 1015 __be16 rsvd; 1016 }; 1017 1018 /* additional cpl_close_listsvr_req.reply_ctrl field */ 1019 #define S_LISTSVR_IPV6 14 1020 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 1021 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 1022 1023 struct cpl_close_listsvr_rpl { 1024 RSS_HDR 1025 union opcode_tid ot; 1026 __u8 rsvd[3]; 1027 __u8 status; 1028 }; 1029 1030 struct cpl_abort_req_rss { 1031 RSS_HDR 1032 union opcode_tid ot; 1033 __u8 rsvd[3]; 1034 __u8 status; 1035 }; 1036 1037 struct cpl_abort_req_rss6 { 1038 RSS_HDR 1039 union opcode_tid ot; 1040 __u32 srqidx_status; 1041 }; 1042 1043 #define S_ABORT_RSS_STATUS 0 1044 #define M_ABORT_RSS_STATUS 0xff 1045 #define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS) 1046 #define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS) 1047 1048 #define S_ABORT_RSS_SRQIDX 8 1049 #define M_ABORT_RSS_SRQIDX 0xffffff 1050 #define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX) 1051 #define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX) 1052 1053 1054 /* cpl_abort_req status command code in case of T6, 1055 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1) 1056 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ 1057 * bit[2] specifies whether to disable the mmgr (1) or not (0) 1058 */ 1059 struct cpl_abort_req { 1060 WR_HDR; 1061 union opcode_tid ot; 1062 __be32 rsvd0; 1063 __u8 rsvd1; 1064 __u8 cmd; 1065 __u8 rsvd2[6]; 1066 }; 1067 1068 struct cpl_abort_req_core { 1069 union opcode_tid ot; 1070 __be32 rsvd0; 1071 __u8 rsvd1; 1072 __u8 cmd; 1073 __u8 rsvd2[6]; 1074 }; 1075 1076 struct cpl_abort_rpl_rss { 1077 RSS_HDR 1078 union opcode_tid ot; 1079 __u8 rsvd[3]; 1080 __u8 status; 1081 }; 1082 1083 struct cpl_abort_rpl_rss6 { 1084 RSS_HDR 1085 union opcode_tid ot; 1086 __u32 srqidx_status; 1087 }; 1088 1089 struct cpl_abort_rpl { 1090 WR_HDR; 1091 union opcode_tid ot; 1092 __be32 rsvd0; 1093 __u8 rsvd1; 1094 __u8 cmd; 1095 __u8 rsvd2[6]; 1096 }; 1097 1098 struct cpl_abort_rpl_core { 1099 union opcode_tid ot; 1100 __be32 rsvd0; 1101 __u8 rsvd1; 1102 __u8 cmd; 1103 __u8 rsvd2[6]; 1104 }; 1105 1106 struct cpl_peer_close { 1107 RSS_HDR 1108 union opcode_tid ot; 1109 __be32 rcv_nxt; 1110 }; 1111 1112 struct cpl_tid_release { 1113 WR_HDR; 1114 union opcode_tid ot; 1115 __be32 rsvd; 1116 }; 1117 1118 struct tx_data_wr { 1119 __be32 wr_hi; 1120 __be32 wr_lo; 1121 __be32 len; 1122 __be32 flags; 1123 __be32 sndseq; 1124 __be32 param; 1125 }; 1126 1127 /* tx_data_wr.flags fields */ 1128 #define S_TX_ACK_PAGES 21 1129 #define M_TX_ACK_PAGES 0x7 1130 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 1131 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 1132 1133 /* tx_data_wr.param fields */ 1134 #define S_TX_PORT 0 1135 #define M_TX_PORT 0x7 1136 #define V_TX_PORT(x) ((x) << S_TX_PORT) 1137 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 1138 1139 #define S_TX_MSS 4 1140 #define M_TX_MSS 0xF 1141 #define V_TX_MSS(x) ((x) << S_TX_MSS) 1142 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 1143 1144 #define S_TX_QOS 8 1145 #define M_TX_QOS 0xFF 1146 #define V_TX_QOS(x) ((x) << S_TX_QOS) 1147 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 1148 1149 #define S_TX_SNDBUF 16 1150 #define M_TX_SNDBUF 0xFFFF 1151 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 1152 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 1153 1154 struct cpl_tx_data { 1155 union opcode_tid ot; 1156 __be32 len; 1157 __be32 rsvd; 1158 __be32 flags; 1159 }; 1160 1161 /* cpl_tx_data.flags fields */ 1162 #define S_TX_PROXY 5 1163 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 1164 #define F_TX_PROXY V_TX_PROXY(1U) 1165 1166 #define S_TX_ULP_SUBMODE 6 1167 #define M_TX_ULP_SUBMODE 0xF 1168 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 1169 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 1170 1171 #define S_TX_ULP_MODE 10 1172 #define M_TX_ULP_MODE 0x7 1173 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 1174 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 1175 1176 #define S_TX_FORCE 13 1177 #define V_TX_FORCE(x) ((x) << S_TX_FORCE) 1178 #define F_TX_FORCE V_TX_FORCE(1U) 1179 1180 #define S_TX_SHOVE 14 1181 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 1182 #define F_TX_SHOVE V_TX_SHOVE(1U) 1183 1184 #define S_TX_MORE 15 1185 #define V_TX_MORE(x) ((x) << S_TX_MORE) 1186 #define F_TX_MORE V_TX_MORE(1U) 1187 1188 #define S_TX_URG 16 1189 #define V_TX_URG(x) ((x) << S_TX_URG) 1190 #define F_TX_URG V_TX_URG(1U) 1191 1192 #define S_TX_FLUSH 17 1193 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 1194 #define F_TX_FLUSH V_TX_FLUSH(1U) 1195 1196 #define S_TX_SAVE 18 1197 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1198 #define F_TX_SAVE V_TX_SAVE(1U) 1199 1200 #define S_TX_TNL 19 1201 #define V_TX_TNL(x) ((x) << S_TX_TNL) 1202 #define F_TX_TNL V_TX_TNL(1U) 1203 1204 #define S_T6_TX_FORCE 20 1205 #define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE) 1206 #define F_T6_TX_FORCE V_T6_TX_FORCE(1U) 1207 1208 /* additional tx_data_wr.flags fields */ 1209 #define S_TX_CPU_IDX 0 1210 #define M_TX_CPU_IDX 0x3F 1211 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1212 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1213 1214 #define S_TX_CLOSE 17 1215 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1216 #define F_TX_CLOSE V_TX_CLOSE(1U) 1217 1218 #define S_TX_INIT 18 1219 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1220 #define F_TX_INIT V_TX_INIT(1U) 1221 1222 #define S_TX_IMM_ACK 19 1223 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1224 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1225 1226 #define S_TX_IMM_DMA 20 1227 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1228 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1229 1230 struct cpl_tx_data_ack { 1231 RSS_HDR 1232 union opcode_tid ot; 1233 __be32 snd_una; 1234 }; 1235 1236 struct cpl_wr_ack { /* XXX */ 1237 RSS_HDR 1238 union opcode_tid ot; 1239 __be16 credits; 1240 __be16 rsvd; 1241 __be32 snd_nxt; 1242 __be32 snd_una; 1243 }; 1244 1245 struct cpl_tx_pkt_core { 1246 __be32 ctrl0; 1247 __be16 pack; 1248 __be16 len; 1249 __be64 ctrl1; 1250 }; 1251 1252 struct cpl_tx_pkt { 1253 WR_HDR; 1254 struct cpl_tx_pkt_core c; 1255 }; 1256 1257 #define cpl_tx_pkt_xt cpl_tx_pkt 1258 1259 /* cpl_tx_pkt_core.ctrl0 fields */ 1260 #define S_TXPKT_VF 0 1261 #define M_TXPKT_VF 0xFF 1262 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1263 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1264 1265 #define S_TXPKT_PF 8 1266 #define M_TXPKT_PF 0x7 1267 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1268 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1269 1270 #define S_TXPKT_VF_VLD 11 1271 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1272 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1273 1274 #define S_TXPKT_OVLAN_IDX 12 1275 #define M_TXPKT_OVLAN_IDX 0xF 1276 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1277 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1278 1279 #define S_TXPKT_T5_OVLAN_IDX 12 1280 #define M_TXPKT_T5_OVLAN_IDX 0x7 1281 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1282 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1283 M_TXPKT_T5_OVLAN_IDX) 1284 1285 #define S_TXPKT_INTF 16 1286 #define M_TXPKT_INTF 0xF 1287 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1288 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1289 1290 #define S_TXPKT_SPECIAL_STAT 20 1291 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1292 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1293 1294 #define S_TXPKT_T5_FCS_DIS 21 1295 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1296 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1297 1298 #define S_TXPKT_INS_OVLAN 21 1299 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1300 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1301 1302 #define S_TXPKT_T5_INS_OVLAN 15 1303 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1304 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1305 1306 #define S_TXPKT_STAT_DIS 22 1307 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1308 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1309 1310 #define S_TXPKT_LOOPBACK 23 1311 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1312 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1313 1314 #define S_TXPKT_TSTAMP 23 1315 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1316 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1317 1318 #define S_TXPKT_OPCODE 24 1319 #define M_TXPKT_OPCODE 0xFF 1320 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1321 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1322 1323 /* cpl_tx_pkt_core.ctrl1 fields */ 1324 #define S_TXPKT_SA_IDX 0 1325 #define M_TXPKT_SA_IDX 0xFFF 1326 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1327 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1328 1329 #define S_TXPKT_CSUM_END 12 1330 #define M_TXPKT_CSUM_END 0xFF 1331 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1332 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1333 1334 #define S_TXPKT_CSUM_START 20 1335 #define M_TXPKT_CSUM_START 0x3FF 1336 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1337 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1338 1339 #define S_TXPKT_IPHDR_LEN 20 1340 #define M_TXPKT_IPHDR_LEN 0x3FFF 1341 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1342 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1343 1344 #define M_T6_TXPKT_IPHDR_LEN 0xFFF 1345 #define G_T6_TXPKT_IPHDR_LEN(x) \ 1346 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN) 1347 1348 #define S_TXPKT_CSUM_LOC 30 1349 #define M_TXPKT_CSUM_LOC 0x3FF 1350 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1351 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1352 1353 #define S_TXPKT_ETHHDR_LEN 34 1354 #define M_TXPKT_ETHHDR_LEN 0x3F 1355 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1356 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1357 1358 #define S_T6_TXPKT_ETHHDR_LEN 32 1359 #define M_T6_TXPKT_ETHHDR_LEN 0xFF 1360 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN) 1361 #define G_T6_TXPKT_ETHHDR_LEN(x) \ 1362 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN) 1363 1364 #define S_TXPKT_CSUM_TYPE 40 1365 #define M_TXPKT_CSUM_TYPE 0xF 1366 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1367 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1368 1369 #define S_TXPKT_VLAN 44 1370 #define M_TXPKT_VLAN 0xFFFF 1371 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1372 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1373 1374 #define S_TXPKT_VLAN_VLD 60 1375 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1376 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1377 1378 #define S_TXPKT_IPSEC 61 1379 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1380 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1381 1382 #define S_TXPKT_IPCSUM_DIS 62 1383 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1384 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1385 1386 #define S_TXPKT_L4CSUM_DIS 63 1387 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1388 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1389 1390 struct cpl_tx_pkt_lso_core { 1391 __be32 lso_ctrl; 1392 __be16 ipid_ofst; 1393 __be16 mss; 1394 __be32 seqno_offset; 1395 __be32 len; 1396 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1397 }; 1398 1399 struct cpl_tx_pkt_lso { 1400 WR_HDR; 1401 struct cpl_tx_pkt_lso_core c; 1402 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1403 }; 1404 1405 struct cpl_tx_pkt_ufo_core { 1406 __be16 ethlen; 1407 __be16 iplen; 1408 __be16 udplen; 1409 __be16 mss; 1410 __be32 len; 1411 __be32 r1; 1412 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1413 }; 1414 1415 struct cpl_tx_pkt_ufo { 1416 WR_HDR; 1417 struct cpl_tx_pkt_ufo_core c; 1418 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1419 }; 1420 1421 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1422 #define S_LSO_TCPHDR_LEN 0 1423 #define M_LSO_TCPHDR_LEN 0xF 1424 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1425 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1426 1427 #define S_LSO_IPHDR_LEN 4 1428 #define M_LSO_IPHDR_LEN 0xFFF 1429 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1430 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1431 1432 #define S_LSO_ETHHDR_LEN 16 1433 #define M_LSO_ETHHDR_LEN 0xF 1434 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1435 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1436 1437 #define S_LSO_IPV6 20 1438 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1439 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1440 1441 #define S_LSO_OFLD_ENCAP 21 1442 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1443 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1444 1445 #define S_LSO_LAST_SLICE 22 1446 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1447 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1448 1449 #define S_LSO_FIRST_SLICE 23 1450 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1451 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1452 1453 #define S_LSO_OPCODE 24 1454 #define M_LSO_OPCODE 0xFF 1455 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1456 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1457 1458 #define S_LSO_T5_XFER_SIZE 0 1459 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1460 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1461 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1462 1463 /* cpl_tx_pkt_lso_core.mss fields */ 1464 #define S_LSO_MSS 0 1465 #define M_LSO_MSS 0x3FFF 1466 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1467 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1468 1469 #define S_LSO_IPID_SPLIT 15 1470 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1471 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1472 1473 struct cpl_tx_pkt_fso { 1474 WR_HDR; 1475 __be32 fso_ctrl; 1476 __be16 seqcnt_ofst; 1477 __be16 mtu; 1478 __be32 param_offset; 1479 __be32 len; 1480 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1481 }; 1482 1483 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1484 #define S_FSO_XCHG_CLASS 21 1485 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1486 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1487 1488 #define S_FSO_INITIATOR 20 1489 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1490 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1491 1492 #define S_FSO_FCHDR_LEN 12 1493 #define M_FSO_FCHDR_LEN 0xF 1494 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1495 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1496 1497 struct cpl_iscsi_hdr_no_rss { 1498 union opcode_tid ot; 1499 __be16 pdu_len_ddp; 1500 __be16 len; 1501 __be32 seq; 1502 __be16 urg; 1503 __u8 rsvd; 1504 __u8 status; 1505 }; 1506 1507 struct cpl_tx_data_iso { 1508 __be32 op_to_scsi; 1509 __u8 reserved1; 1510 __u8 ahs_len; 1511 __be16 mpdu; 1512 __be32 burst_size; 1513 __be32 len; 1514 __be32 reserved2_seglen_offset; 1515 __be32 datasn_offset; 1516 __be32 buffer_offset; 1517 __be32 reserved3; 1518 1519 /* encapsulated CPL_TX_DATA follows here */ 1520 }; 1521 1522 /* cpl_tx_data_iso.op_to_scsi fields */ 1523 #define S_CPL_TX_DATA_ISO_OP 24 1524 #define M_CPL_TX_DATA_ISO_OP 0xff 1525 #define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP) 1526 #define G_CPL_TX_DATA_ISO_OP(x) \ 1527 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP) 1528 1529 #define S_CPL_TX_DATA_ISO_FIRST 23 1530 #define M_CPL_TX_DATA_ISO_FIRST 0x1 1531 #define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST) 1532 #define G_CPL_TX_DATA_ISO_FIRST(x) \ 1533 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST) 1534 #define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U) 1535 1536 #define S_CPL_TX_DATA_ISO_LAST 22 1537 #define M_CPL_TX_DATA_ISO_LAST 0x1 1538 #define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST) 1539 #define G_CPL_TX_DATA_ISO_LAST(x) \ 1540 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST) 1541 #define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U) 1542 1543 #define S_CPL_TX_DATA_ISO_CPLHDRLEN 21 1544 #define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1 1545 #define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN) 1546 #define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \ 1547 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN) 1548 #define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U) 1549 1550 #define S_CPL_TX_DATA_ISO_HDRCRC 20 1551 #define M_CPL_TX_DATA_ISO_HDRCRC 0x1 1552 #define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC) 1553 #define G_CPL_TX_DATA_ISO_HDRCRC(x) \ 1554 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC) 1555 #define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U) 1556 1557 #define S_CPL_TX_DATA_ISO_PLDCRC 19 1558 #define M_CPL_TX_DATA_ISO_PLDCRC 0x1 1559 #define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC) 1560 #define G_CPL_TX_DATA_ISO_PLDCRC(x) \ 1561 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC) 1562 #define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U) 1563 1564 #define S_CPL_TX_DATA_ISO_IMMEDIATE 18 1565 #define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1 1566 #define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE) 1567 #define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \ 1568 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE) 1569 #define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U) 1570 1571 #define S_CPL_TX_DATA_ISO_SCSI 16 1572 #define M_CPL_TX_DATA_ISO_SCSI 0x3 1573 #define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI) 1574 #define G_CPL_TX_DATA_ISO_SCSI(x) \ 1575 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI) 1576 1577 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1578 #define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0 1579 #define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff 1580 #define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1581 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1582 #define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1583 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \ 1584 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1585 1586 struct cpl_iscsi_hdr { 1587 RSS_HDR 1588 union opcode_tid ot; 1589 __be16 pdu_len_ddp; 1590 __be16 len; 1591 __be32 seq; 1592 __be16 urg; 1593 __u8 rsvd; 1594 __u8 status; 1595 }; 1596 1597 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1598 #define S_ISCSI_PDU_LEN 0 1599 #define M_ISCSI_PDU_LEN 0x7FFF 1600 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1601 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1602 1603 #define S_ISCSI_DDP 15 1604 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1605 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1606 1607 struct cpl_iscsi_data { 1608 RSS_HDR 1609 union opcode_tid ot; 1610 __u8 rsvd0[2]; 1611 __be16 len; 1612 __be32 seq; 1613 __be16 urg; 1614 __u8 rsvd1; 1615 __u8 status; 1616 }; 1617 1618 struct cpl_rx_data { 1619 RSS_HDR 1620 union opcode_tid ot; 1621 __be16 rsvd; 1622 __be16 len; 1623 __be32 seq; 1624 __be16 urg; 1625 #if defined(__LITTLE_ENDIAN_BITFIELD) 1626 __u8 dack_mode:2; 1627 __u8 psh:1; 1628 __u8 heartbeat:1; 1629 __u8 ddp_off:1; 1630 __u8 :3; 1631 #else 1632 __u8 :3; 1633 __u8 ddp_off:1; 1634 __u8 heartbeat:1; 1635 __u8 psh:1; 1636 __u8 dack_mode:2; 1637 #endif 1638 __u8 status; 1639 }; 1640 1641 struct cpl_fcoe_hdr { 1642 RSS_HDR 1643 union opcode_tid ot; 1644 __be16 oxid; 1645 __be16 len; 1646 __be32 rctl_fctl; 1647 __u8 cs_ctl; 1648 __u8 df_ctl; 1649 __u8 sof; 1650 __u8 eof; 1651 __be16 seq_cnt; 1652 __u8 seq_id; 1653 __u8 type; 1654 __be32 param; 1655 }; 1656 1657 /* cpl_fcoe_hdr.rctl_fctl fields */ 1658 #define S_FCOE_FCHDR_RCTL 24 1659 #define M_FCOE_FCHDR_RCTL 0xff 1660 #define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL) 1661 #define G_FCOE_FCHDR_RCTL(x) \ 1662 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL) 1663 1664 #define S_FCOE_FCHDR_FCTL 0 1665 #define M_FCOE_FCHDR_FCTL 0xffffff 1666 #define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL) 1667 #define G_FCOE_FCHDR_FCTL(x) \ 1668 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL) 1669 1670 struct cpl_fcoe_data { 1671 RSS_HDR 1672 union opcode_tid ot; 1673 __u8 rsvd0[2]; 1674 __be16 len; 1675 __be32 seq; 1676 __u8 rsvd1[3]; 1677 __u8 status; 1678 }; 1679 1680 struct cpl_rx_urg_notify { 1681 RSS_HDR 1682 union opcode_tid ot; 1683 __be32 seq; 1684 }; 1685 1686 struct cpl_rx_urg_pkt { 1687 RSS_HDR 1688 union opcode_tid ot; 1689 __be16 rsvd; 1690 __be16 len; 1691 }; 1692 1693 struct cpl_rx_data_ack { 1694 WR_HDR; 1695 union opcode_tid ot; 1696 __be32 credit_dack; 1697 }; 1698 1699 struct cpl_rx_data_ack_core { 1700 union opcode_tid ot; 1701 __be32 credit_dack; 1702 }; 1703 1704 /* cpl_rx_data_ack.ack_seq fields */ 1705 #define S_RX_CREDITS 0 1706 #define M_RX_CREDITS 0x3FFFFFF 1707 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1708 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1709 1710 #define S_RX_MODULATE_TX 26 1711 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1712 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1713 1714 #define S_RX_MODULATE_RX 27 1715 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1716 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1717 1718 #define S_RX_FORCE_ACK 28 1719 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1720 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1721 1722 #define S_RX_DACK_MODE 29 1723 #define M_RX_DACK_MODE 0x3 1724 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1725 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1726 1727 #define S_RX_DACK_CHANGE 31 1728 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1729 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1730 1731 struct cpl_rx_ddp_complete { 1732 RSS_HDR 1733 union opcode_tid ot; 1734 __be32 ddp_report; 1735 __be32 rcv_nxt; 1736 __be32 rsvd; 1737 }; 1738 1739 struct cpl_rx_data_ddp { 1740 RSS_HDR 1741 union opcode_tid ot; 1742 __be16 urg; 1743 __be16 len; 1744 __be32 seq; 1745 union { 1746 __be32 nxt_seq; 1747 __be32 ddp_report; 1748 } u; 1749 __be32 ulp_crc; 1750 __be32 ddpvld; 1751 }; 1752 1753 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1754 1755 struct cpl_rx_fcoe_ddp { 1756 RSS_HDR 1757 union opcode_tid ot; 1758 __be16 rsvd; 1759 __be16 len; 1760 __be32 seq; 1761 __be32 ddp_report; 1762 __be32 ulp_crc; 1763 __be32 ddpvld; 1764 }; 1765 1766 struct cpl_rx_data_dif { 1767 RSS_HDR 1768 union opcode_tid ot; 1769 __be16 ddp_len; 1770 __be16 msg_len; 1771 __be32 seq; 1772 union { 1773 __be32 nxt_seq; 1774 __be32 ddp_report; 1775 } u; 1776 __be32 err_vec; 1777 __be32 ddpvld; 1778 }; 1779 1780 struct cpl_rx_iscsi_dif { 1781 RSS_HDR 1782 union opcode_tid ot; 1783 __be16 ddp_len; 1784 __be16 msg_len; 1785 __be32 seq; 1786 union { 1787 __be32 nxt_seq; 1788 __be32 ddp_report; 1789 } u; 1790 __be32 ulp_crc; 1791 __be32 ddpvld; 1792 __u8 rsvd0[8]; 1793 __be32 err_vec; 1794 __u8 rsvd1[4]; 1795 }; 1796 1797 struct cpl_rx_iscsi_cmp { 1798 RSS_HDR 1799 union opcode_tid ot; 1800 __be16 pdu_len_ddp; 1801 __be16 len; 1802 __be32 seq; 1803 __be16 urg; 1804 __u8 rsvd; 1805 __u8 status; 1806 __be32 ulp_crc; 1807 __be32 ddpvld; 1808 }; 1809 1810 struct cpl_rx_fcoe_dif { 1811 RSS_HDR 1812 union opcode_tid ot; 1813 __be16 ddp_len; 1814 __be16 msg_len; 1815 __be32 seq; 1816 __be32 ddp_report; 1817 __be32 err_vec; 1818 __be32 ddpvld; 1819 }; 1820 1821 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1822 #define S_DDP_VALID 15 1823 #define M_DDP_VALID 0x1FFFF 1824 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1825 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1826 1827 #define S_DDP_PPOD_MISMATCH 15 1828 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1829 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1830 1831 #define S_DDP_PDU 16 1832 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1833 #define F_DDP_PDU V_DDP_PDU(1U) 1834 1835 #define S_DDP_LLIMIT_ERR 17 1836 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1837 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1838 1839 #define S_DDP_PPOD_PARITY_ERR 18 1840 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1841 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1842 1843 #define S_DDP_PADDING_ERR 19 1844 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1845 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1846 1847 #define S_DDP_HDRCRC_ERR 20 1848 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1849 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1850 1851 #define S_DDP_DATACRC_ERR 21 1852 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1853 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1854 1855 #define S_DDP_INVALID_TAG 22 1856 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1857 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1858 1859 #define S_DDP_ULIMIT_ERR 23 1860 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1861 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1862 1863 #define S_DDP_OFFSET_ERR 24 1864 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1865 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1866 1867 #define S_DDP_COLOR_ERR 25 1868 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1869 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1870 1871 #define S_DDP_TID_MISMATCH 26 1872 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1873 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1874 1875 #define S_DDP_INVALID_PPOD 27 1876 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1877 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1878 1879 #define S_DDP_ULP_MODE 28 1880 #define M_DDP_ULP_MODE 0xF 1881 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1882 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1883 1884 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1885 #define S_DDP_OFFSET 0 1886 #define M_DDP_OFFSET 0xFFFFFF 1887 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1888 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1889 1890 #define S_DDP_DACK_MODE 24 1891 #define M_DDP_DACK_MODE 0x3 1892 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1893 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1894 1895 #define S_DDP_BUF_IDX 26 1896 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1897 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1898 1899 #define S_DDP_URG 27 1900 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1901 #define F_DDP_URG V_DDP_URG(1U) 1902 1903 #define S_DDP_PSH 28 1904 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1905 #define F_DDP_PSH V_DDP_PSH(1U) 1906 1907 #define S_DDP_BUF_COMPLETE 29 1908 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1909 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1910 1911 #define S_DDP_BUF_TIMED_OUT 30 1912 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1913 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1914 1915 #define S_DDP_INV 31 1916 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1917 #define F_DDP_INV V_DDP_INV(1U) 1918 1919 struct cpl_rx_pkt { 1920 RSS_HDR 1921 __u8 opcode; 1922 #if defined(__LITTLE_ENDIAN_BITFIELD) 1923 __u8 iff:4; 1924 __u8 csum_calc:1; 1925 __u8 ipmi_pkt:1; 1926 __u8 vlan_ex:1; 1927 __u8 ip_frag:1; 1928 #else 1929 __u8 ip_frag:1; 1930 __u8 vlan_ex:1; 1931 __u8 ipmi_pkt:1; 1932 __u8 csum_calc:1; 1933 __u8 iff:4; 1934 #endif 1935 __be16 csum; 1936 __be16 vlan; 1937 __be16 len; 1938 __be32 l2info; 1939 __be16 hdr_len; 1940 __be16 err_vec; 1941 }; 1942 1943 /* rx_pkt.l2info fields */ 1944 #define S_RX_ETHHDR_LEN 0 1945 #define M_RX_ETHHDR_LEN 0x1F 1946 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1947 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1948 1949 #define S_RX_T5_ETHHDR_LEN 0 1950 #define M_RX_T5_ETHHDR_LEN 0x3F 1951 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1952 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1953 1954 #define M_RX_T6_ETHHDR_LEN 0xFF 1955 #define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN) 1956 1957 #define S_RX_PKTYPE 5 1958 #define M_RX_PKTYPE 0x7 1959 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1960 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1961 1962 #define S_RX_T5_DATYPE 6 1963 #define M_RX_T5_DATYPE 0x3 1964 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1965 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1966 1967 #define S_RX_MACIDX 8 1968 #define M_RX_MACIDX 0x1FF 1969 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1970 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1971 1972 #define S_RX_T5_PKTYPE 17 1973 #define M_RX_T5_PKTYPE 0x7 1974 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1975 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1976 1977 #define S_RX_DATYPE 18 1978 #define M_RX_DATYPE 0x3 1979 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1980 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1981 1982 #define S_RXF_PSH 20 1983 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1984 #define F_RXF_PSH V_RXF_PSH(1U) 1985 1986 #define S_RXF_SYN 21 1987 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1988 #define F_RXF_SYN V_RXF_SYN(1U) 1989 1990 #define S_RXF_UDP 22 1991 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1992 #define F_RXF_UDP V_RXF_UDP(1U) 1993 1994 #define S_RXF_TCP 23 1995 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1996 #define F_RXF_TCP V_RXF_TCP(1U) 1997 1998 #define S_RXF_IP 24 1999 #define V_RXF_IP(x) ((x) << S_RXF_IP) 2000 #define F_RXF_IP V_RXF_IP(1U) 2001 2002 #define S_RXF_IP6 25 2003 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 2004 #define F_RXF_IP6 V_RXF_IP6(1U) 2005 2006 #define S_RXF_SYN_COOKIE 26 2007 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 2008 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 2009 2010 #define S_RXF_FCOE 26 2011 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 2012 #define F_RXF_FCOE V_RXF_FCOE(1U) 2013 2014 #define S_RXF_LRO 27 2015 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 2016 #define F_RXF_LRO V_RXF_LRO(1U) 2017 2018 #define S_RX_CHAN 28 2019 #define M_RX_CHAN 0xF 2020 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 2021 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 2022 2023 /* rx_pkt.hdr_len fields */ 2024 #define S_RX_TCPHDR_LEN 0 2025 #define M_RX_TCPHDR_LEN 0x3F 2026 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 2027 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 2028 2029 #define S_RX_IPHDR_LEN 6 2030 #define M_RX_IPHDR_LEN 0x3FF 2031 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 2032 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 2033 2034 /* rx_pkt.err_vec fields */ 2035 #define S_RXERR_OR 0 2036 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 2037 #define F_RXERR_OR V_RXERR_OR(1U) 2038 2039 #define S_RXERR_MAC 1 2040 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 2041 #define F_RXERR_MAC V_RXERR_MAC(1U) 2042 2043 #define S_RXERR_IPVERS 2 2044 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 2045 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 2046 2047 #define S_RXERR_FRAG 3 2048 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 2049 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 2050 2051 #define S_RXERR_ATTACK 4 2052 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 2053 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 2054 2055 #define S_RXERR_ETHHDR_LEN 5 2056 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 2057 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 2058 2059 #define S_RXERR_IPHDR_LEN 6 2060 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 2061 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 2062 2063 #define S_RXERR_TCPHDR_LEN 7 2064 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 2065 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 2066 2067 #define S_RXERR_PKT_LEN 8 2068 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 2069 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 2070 2071 #define S_RXERR_TCP_OPT 9 2072 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 2073 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 2074 2075 #define S_RXERR_IPCSUM 12 2076 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 2077 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 2078 2079 #define S_RXERR_CSUM 13 2080 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 2081 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 2082 2083 #define S_RXERR_PING 14 2084 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 2085 #define F_RXERR_PING V_RXERR_PING(1U) 2086 2087 /* In T6, rx_pkt.err_vec indicates 2088 * RxError Error vector (16b) or 2089 * Encapsulating header length (8b), 2090 * Outer encapsulation type (2b) and 2091 * compressed error vector (6b) if CRxPktEnc is 2092 * enabled in TP_OUT_CONFIG 2093 */ 2094 2095 #define S_T6_COMPR_RXERR_VEC 0 2096 #define M_T6_COMPR_RXERR_VEC 0x3F 2097 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC) 2098 #define G_T6_COMPR_RXERR_VEC(x) \ 2099 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC) 2100 2101 #define S_T6_COMPR_RXERR_MAC 0 2102 #define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC) 2103 #define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U) 2104 2105 /* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN 2106 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN 2107 */ 2108 #define S_T6_COMPR_RXERR_LEN 1 2109 #define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN) 2110 #define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U) 2111 2112 #define S_T6_COMPR_RXERR_TCP_OPT 2 2113 #define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT) 2114 #define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U) 2115 2116 #define S_T6_COMPR_RXERR_IPV6_EXT 3 2117 #define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT) 2118 #define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U) 2119 2120 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 2121 #define S_T6_COMPR_RXERR_SUM 4 2122 #define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM) 2123 #define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U) 2124 2125 /* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP, 2126 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION 2127 */ 2128 #define S_T6_COMPR_RXERR_MISC 5 2129 #define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC) 2130 #define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U) 2131 2132 #define S_T6_RX_TNL_TYPE 6 2133 #define M_T6_RX_TNL_TYPE 0x3 2134 #define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE) 2135 #define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE) 2136 2137 #define RX_PKT_TNL_TYPE_NVGRE 1 2138 #define RX_PKT_TNL_TYPE_VXLAN 2 2139 #define RX_PKT_TNL_TYPE_GENEVE 3 2140 2141 #define S_T6_RX_TNLHDR_LEN 8 2142 #define M_T6_RX_TNLHDR_LEN 0xFF 2143 #define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN) 2144 #define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN) 2145 2146 struct cpl_trace_pkt { 2147 RSS_HDR 2148 __u8 opcode; 2149 __u8 intf; 2150 #if defined(__LITTLE_ENDIAN_BITFIELD) 2151 __u8 runt:4; 2152 __u8 filter_hit:4; 2153 __u8 :6; 2154 __u8 err:1; 2155 __u8 trunc:1; 2156 #else 2157 __u8 filter_hit:4; 2158 __u8 runt:4; 2159 __u8 trunc:1; 2160 __u8 err:1; 2161 __u8 :6; 2162 #endif 2163 __be16 rsvd; 2164 __be16 len; 2165 __be64 tstamp; 2166 }; 2167 2168 struct cpl_t5_trace_pkt { 2169 RSS_HDR 2170 __u8 opcode; 2171 __u8 intf; 2172 #if defined(__LITTLE_ENDIAN_BITFIELD) 2173 __u8 runt:4; 2174 __u8 filter_hit:4; 2175 __u8 :6; 2176 __u8 err:1; 2177 __u8 trunc:1; 2178 #else 2179 __u8 filter_hit:4; 2180 __u8 runt:4; 2181 __u8 trunc:1; 2182 __u8 err:1; 2183 __u8 :6; 2184 #endif 2185 __be16 rsvd; 2186 __be16 len; 2187 __be64 tstamp; 2188 __be64 rsvd1; 2189 }; 2190 2191 struct cpl_rte_delete_req { 2192 WR_HDR; 2193 union opcode_tid ot; 2194 __be32 params; 2195 }; 2196 2197 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 2198 #define S_RTE_REQ_LUT_IX 8 2199 #define M_RTE_REQ_LUT_IX 0x7FF 2200 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 2201 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 2202 2203 #define S_RTE_REQ_LUT_BASE 19 2204 #define M_RTE_REQ_LUT_BASE 0x7FF 2205 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 2206 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 2207 2208 #define S_RTE_READ_REQ_SELECT 31 2209 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 2210 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 2211 2212 struct cpl_rte_delete_rpl { 2213 RSS_HDR 2214 union opcode_tid ot; 2215 __u8 status; 2216 __u8 rsvd[3]; 2217 }; 2218 2219 struct cpl_rte_write_req { 2220 WR_HDR; 2221 union opcode_tid ot; 2222 __u32 write_sel; 2223 __be32 lut_params; 2224 __be32 l2t_idx; 2225 __be32 netmask; 2226 __be32 faddr; 2227 }; 2228 2229 /* cpl_rte_write_req.write_sel fields */ 2230 #define S_RTE_WR_L2TIDX 31 2231 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 2232 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 2233 2234 #define S_RTE_WR_FADDR 30 2235 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 2236 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 2237 2238 /* cpl_rte_write_req.lut_params fields */ 2239 #define S_RTE_WR_LUT_IX 10 2240 #define M_RTE_WR_LUT_IX 0x7FF 2241 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 2242 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 2243 2244 #define S_RTE_WR_LUT_BASE 21 2245 #define M_RTE_WR_LUT_BASE 0x7FF 2246 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 2247 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 2248 2249 struct cpl_rte_write_rpl { 2250 RSS_HDR 2251 union opcode_tid ot; 2252 __u8 status; 2253 __u8 rsvd[3]; 2254 }; 2255 2256 struct cpl_rte_read_req { 2257 WR_HDR; 2258 union opcode_tid ot; 2259 __be32 params; 2260 }; 2261 2262 struct cpl_rte_read_rpl { 2263 RSS_HDR 2264 union opcode_tid ot; 2265 __u8 status; 2266 __u8 rsvd; 2267 __be16 l2t_idx; 2268 #if defined(__LITTLE_ENDIAN_BITFIELD) 2269 __u32 :30; 2270 __u32 select:1; 2271 #else 2272 __u32 select:1; 2273 __u32 :30; 2274 #endif 2275 __be32 addr; 2276 }; 2277 2278 struct cpl_l2t_write_req { 2279 WR_HDR; 2280 union opcode_tid ot; 2281 __be16 params; 2282 __be16 l2t_idx; 2283 __be16 vlan; 2284 __u8 dst_mac[6]; 2285 }; 2286 2287 /* cpl_l2t_write_req.params fields */ 2288 #define S_L2T_W_INFO 2 2289 #define M_L2T_W_INFO 0x3F 2290 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 2291 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 2292 2293 #define S_L2T_W_PORT 8 2294 #define M_L2T_W_PORT 0x3 2295 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 2296 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 2297 2298 #define S_L2T_W_LPBK 10 2299 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 2300 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 2301 2302 #define S_L2T_W_ARPMISS 11 2303 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 2304 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 2305 2306 #define S_L2T_W_NOREPLY 15 2307 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 2308 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 2309 2310 #define CPL_L2T_VLAN_NONE 0xfff 2311 2312 struct cpl_l2t_write_rpl { 2313 RSS_HDR 2314 union opcode_tid ot; 2315 __u8 status; 2316 __u8 rsvd[3]; 2317 }; 2318 2319 struct cpl_l2t_read_req { 2320 WR_HDR; 2321 union opcode_tid ot; 2322 __be32 l2t_idx; 2323 }; 2324 2325 struct cpl_l2t_read_rpl { 2326 RSS_HDR 2327 union opcode_tid ot; 2328 __u8 status; 2329 #if defined(__LITTLE_ENDIAN_BITFIELD) 2330 __u8 :4; 2331 __u8 iff:4; 2332 #else 2333 __u8 iff:4; 2334 __u8 :4; 2335 #endif 2336 __be16 vlan; 2337 __be16 info; 2338 __u8 dst_mac[6]; 2339 }; 2340 2341 struct cpl_srq_table_req { 2342 WR_HDR; 2343 union opcode_tid ot; 2344 __u8 status; 2345 __u8 rsvd[2]; 2346 __u8 idx; 2347 __be64 rsvd_pdid; 2348 __be32 qlen_qbase; 2349 __be16 cur_msn; 2350 __be16 max_msn; 2351 }; 2352 2353 struct cpl_srq_table_rpl { 2354 RSS_HDR 2355 union opcode_tid ot; 2356 __u8 status; 2357 __u8 rsvd[2]; 2358 __u8 idx; 2359 __be64 rsvd_pdid; 2360 __be32 qlen_qbase; 2361 __be16 cur_msn; 2362 __be16 max_msn; 2363 }; 2364 2365 /* cpl_srq_table_{req,rpl}.params fields */ 2366 #define S_SRQT_QLEN 28 2367 #define M_SRQT_QLEN 0xF 2368 #define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN) 2369 #define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN) 2370 2371 #define S_SRQT_QBASE 0 2372 #define M_SRQT_QBASE 0x3FFFFFF 2373 #define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE) 2374 #define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE) 2375 2376 #define S_SRQT_PDID 0 2377 #define M_SRQT_PDID 0xFF 2378 #define V_SRQT_PDID(x) ((x) << S_SRQT_PDID) 2379 #define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID) 2380 2381 #define S_SRQT_IDX 0 2382 #define M_SRQT_IDX 0xF 2383 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX) 2384 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX) 2385 2386 struct cpl_smt_write_req { 2387 WR_HDR; 2388 union opcode_tid ot; 2389 __be32 params; 2390 __be16 pfvf1; 2391 __u8 src_mac1[6]; 2392 __be16 pfvf0; 2393 __u8 src_mac0[6]; 2394 }; 2395 2396 struct cpl_t6_smt_write_req { 2397 WR_HDR; 2398 union opcode_tid ot; 2399 __be32 params; 2400 __be64 tag; 2401 __be16 pfvf0; 2402 __u8 src_mac0[6]; 2403 __be32 local_ip; 2404 __be32 rsvd; 2405 }; 2406 2407 struct cpl_smt_write_rpl { 2408 RSS_HDR 2409 union opcode_tid ot; 2410 __u8 status; 2411 __u8 rsvd[3]; 2412 }; 2413 2414 struct cpl_smt_read_req { 2415 WR_HDR; 2416 union opcode_tid ot; 2417 __be32 params; 2418 }; 2419 2420 struct cpl_smt_read_rpl { 2421 RSS_HDR 2422 union opcode_tid ot; 2423 __u8 status; 2424 __u8 ovlan_idx; 2425 __be16 rsvd; 2426 __be16 pfvf1; 2427 __u8 src_mac1[6]; 2428 __be16 pfvf0; 2429 __u8 src_mac0[6]; 2430 }; 2431 2432 /* cpl_smt_{read,write}_req.params fields */ 2433 #define S_SMTW_OVLAN_IDX 16 2434 #define M_SMTW_OVLAN_IDX 0xF 2435 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2436 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2437 2438 #define S_SMTW_IDX 20 2439 #define M_SMTW_IDX 0x7F 2440 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2441 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2442 2443 #define M_T6_SMTW_IDX 0xFF 2444 #define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX) 2445 2446 #define S_SMTW_NORPL 31 2447 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2448 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 2449 2450 /* cpl_smt_{read,write}_req.pfvf? fields */ 2451 #define S_SMTW_VF 0 2452 #define M_SMTW_VF 0xFF 2453 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2454 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2455 2456 #define S_SMTW_PF 8 2457 #define M_SMTW_PF 0x7 2458 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2459 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2460 2461 #define S_SMTW_VF_VLD 11 2462 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2463 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2464 2465 struct cpl_tag_write_req { 2466 WR_HDR; 2467 union opcode_tid ot; 2468 __be32 params; 2469 __be64 tag_val; 2470 }; 2471 2472 struct cpl_tag_write_rpl { 2473 RSS_HDR 2474 union opcode_tid ot; 2475 __u8 status; 2476 __u8 rsvd[2]; 2477 __u8 idx; 2478 }; 2479 2480 struct cpl_tag_read_req { 2481 WR_HDR; 2482 union opcode_tid ot; 2483 __be32 params; 2484 }; 2485 2486 struct cpl_tag_read_rpl { 2487 RSS_HDR 2488 union opcode_tid ot; 2489 __u8 status; 2490 #if defined(__LITTLE_ENDIAN_BITFIELD) 2491 __u8 :4; 2492 __u8 tag_len:1; 2493 __u8 :2; 2494 __u8 ins_enable:1; 2495 #else 2496 __u8 ins_enable:1; 2497 __u8 :2; 2498 __u8 tag_len:1; 2499 __u8 :4; 2500 #endif 2501 __u8 rsvd; 2502 __u8 tag_idx; 2503 __be64 tag_val; 2504 }; 2505 2506 /* cpl_tag{read,write}_req.params fields */ 2507 #define S_TAGW_IDX 0 2508 #define M_TAGW_IDX 0x7F 2509 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2510 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2511 2512 #define S_TAGW_LEN 20 2513 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2514 #define F_TAGW_LEN V_TAGW_LEN(1U) 2515 2516 #define S_TAGW_INS_ENABLE 23 2517 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2518 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2519 2520 #define S_TAGW_NORPL 31 2521 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2522 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2523 2524 struct cpl_barrier { 2525 WR_HDR; 2526 __u8 opcode; 2527 __u8 chan_map; 2528 __be16 rsvd0; 2529 __be32 rsvd1; 2530 }; 2531 2532 /* cpl_barrier.chan_map fields */ 2533 #define S_CHAN_MAP 4 2534 #define M_CHAN_MAP 0xF 2535 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2536 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2537 2538 struct cpl_error { 2539 RSS_HDR 2540 union opcode_tid ot; 2541 __be32 error; 2542 }; 2543 2544 struct cpl_hit_notify { 2545 RSS_HDR 2546 union opcode_tid ot; 2547 __be32 rsvd; 2548 __be32 info; 2549 __be32 reason; 2550 }; 2551 2552 struct cpl_pkt_notify { 2553 RSS_HDR 2554 union opcode_tid ot; 2555 __be16 rsvd; 2556 __be16 len; 2557 __be32 info; 2558 __be32 reason; 2559 }; 2560 2561 /* cpl_{hit,pkt}_notify.info fields */ 2562 #define S_NTFY_MAC_IDX 0 2563 #define M_NTFY_MAC_IDX 0x1FF 2564 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2565 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2566 2567 #define S_NTFY_INTF 10 2568 #define M_NTFY_INTF 0xF 2569 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2570 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2571 2572 #define S_NTFY_TCPHDR_LEN 14 2573 #define M_NTFY_TCPHDR_LEN 0xF 2574 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2575 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2576 2577 #define S_NTFY_IPHDR_LEN 18 2578 #define M_NTFY_IPHDR_LEN 0x1FF 2579 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2580 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2581 2582 #define S_NTFY_ETHHDR_LEN 27 2583 #define M_NTFY_ETHHDR_LEN 0x1F 2584 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2585 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2586 2587 #define S_NTFY_T5_IPHDR_LEN 18 2588 #define M_NTFY_T5_IPHDR_LEN 0xFF 2589 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2590 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2591 2592 #define S_NTFY_T5_ETHHDR_LEN 26 2593 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2594 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2595 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2596 2597 struct cpl_rdma_terminate { 2598 RSS_HDR 2599 union opcode_tid ot; 2600 __be16 rsvd; 2601 __be16 len; 2602 }; 2603 2604 struct cpl_set_le_req { 2605 WR_HDR; 2606 union opcode_tid ot; 2607 __be16 reply_ctrl; 2608 __be16 params; 2609 __be64 mask_hi; 2610 __be64 mask_lo; 2611 __be64 val_hi; 2612 __be64 val_lo; 2613 }; 2614 2615 /* cpl_set_le_req.reply_ctrl additional fields */ 2616 #define S_LE_REQ_IP6 13 2617 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2618 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2619 2620 /* cpl_set_le_req.params fields */ 2621 #define S_LE_CHAN 0 2622 #define M_LE_CHAN 0x3 2623 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2624 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2625 2626 #define S_LE_OFFSET 5 2627 #define M_LE_OFFSET 0x7 2628 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2629 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2630 2631 #define S_LE_MORE 8 2632 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2633 #define F_LE_MORE V_LE_MORE(1U) 2634 2635 #define S_LE_REQSIZE 9 2636 #define M_LE_REQSIZE 0x7 2637 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2638 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2639 2640 #define S_LE_REQCMD 12 2641 #define M_LE_REQCMD 0xF 2642 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2643 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2644 2645 struct cpl_set_le_rpl { 2646 RSS_HDR 2647 union opcode_tid ot; 2648 __u8 chan; 2649 __u8 info; 2650 __be16 len; 2651 }; 2652 2653 /* cpl_set_le_rpl.info fields */ 2654 #define S_LE_RSPCMD 0 2655 #define M_LE_RSPCMD 0xF 2656 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2657 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2658 2659 #define S_LE_RSPSIZE 4 2660 #define M_LE_RSPSIZE 0x7 2661 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2662 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2663 2664 #define S_LE_RSPTYPE 7 2665 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2666 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2667 2668 struct cpl_sge_egr_update { 2669 RSS_HDR 2670 __be32 opcode_qid; 2671 __be16 cidx; 2672 __be16 pidx; 2673 }; 2674 2675 /* cpl_sge_egr_update.ot fields */ 2676 #define S_AUTOEQU 22 2677 #define M_AUTOEQU 0x1 2678 #define V_AUTOEQU(x) ((x) << S_AUTOEQU) 2679 #define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU) 2680 2681 #define S_EGR_QID 0 2682 #define M_EGR_QID 0x1FFFF 2683 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2684 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2685 2686 /* cpl_fw*.type values */ 2687 enum { 2688 FW_TYPE_CMD_RPL = 0, 2689 FW_TYPE_WR_RPL = 1, 2690 FW_TYPE_CQE = 2, 2691 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2692 FW_TYPE_RSSCPL = 4, 2693 FW_TYPE_WRERR_RPL = 5, 2694 FW_TYPE_PI_ERR = 6, 2695 FW_TYPE_TLS_KEY = 7, 2696 }; 2697 2698 struct cpl_fw2_pld { 2699 RSS_HDR 2700 u8 opcode; 2701 u8 rsvd[5]; 2702 __be16 len; 2703 }; 2704 2705 struct cpl_fw4_pld { 2706 RSS_HDR 2707 u8 opcode; 2708 u8 rsvd0[3]; 2709 u8 type; 2710 u8 rsvd1; 2711 __be16 len; 2712 __be64 data; 2713 __be64 rsvd2; 2714 }; 2715 2716 struct cpl_fw6_pld { 2717 RSS_HDR 2718 u8 opcode; 2719 u8 rsvd[5]; 2720 __be16 len; 2721 __be64 data[4]; 2722 }; 2723 2724 struct cpl_fw2_msg { 2725 RSS_HDR 2726 union opcode_info oi; 2727 }; 2728 2729 struct cpl_fw4_msg { 2730 RSS_HDR 2731 u8 opcode; 2732 u8 type; 2733 __be16 rsvd0; 2734 __be32 rsvd1; 2735 __be64 data[2]; 2736 }; 2737 2738 struct cpl_fw4_ack { 2739 RSS_HDR 2740 union opcode_tid ot; 2741 u8 credits; 2742 u8 rsvd0[2]; 2743 u8 flags; 2744 __be32 snd_nxt; 2745 __be32 snd_una; 2746 __be64 rsvd1; 2747 }; 2748 2749 enum { 2750 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2751 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2752 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2753 }; 2754 2755 #define S_CPL_FW4_ACK_OPCODE 24 2756 #define M_CPL_FW4_ACK_OPCODE 0xff 2757 #define V_CPL_FW4_ACK_OPCODE(x) ((x) << S_CPL_FW4_ACK_OPCODE) 2758 #define G_CPL_FW4_ACK_OPCODE(x) \ 2759 (((x) >> S_CPL_FW4_ACK_OPCODE) & M_CPL_FW4_ACK_OPCODE) 2760 2761 #define S_CPL_FW4_ACK_FLOWID 0 2762 #define M_CPL_FW4_ACK_FLOWID 0xffffff 2763 #define V_CPL_FW4_ACK_FLOWID(x) ((x) << S_CPL_FW4_ACK_FLOWID) 2764 #define G_CPL_FW4_ACK_FLOWID(x) \ 2765 (((x) >> S_CPL_FW4_ACK_FLOWID) & M_CPL_FW4_ACK_FLOWID) 2766 2767 #define S_CPL_FW4_ACK_CR 24 2768 #define M_CPL_FW4_ACK_CR 0xff 2769 #define V_CPL_FW4_ACK_CR(x) ((x) << S_CPL_FW4_ACK_CR) 2770 #define G_CPL_FW4_ACK_CR(x) (((x) >> S_CPL_FW4_ACK_CR) & M_CPL_FW4_ACK_CR) 2771 2772 #define S_CPL_FW4_ACK_SEQVAL 0 2773 #define M_CPL_FW4_ACK_SEQVAL 0x1 2774 #define V_CPL_FW4_ACK_SEQVAL(x) ((x) << S_CPL_FW4_ACK_SEQVAL) 2775 #define G_CPL_FW4_ACK_SEQVAL(x) \ 2776 (((x) >> S_CPL_FW4_ACK_SEQVAL) & M_CPL_FW4_ACK_SEQVAL) 2777 #define F_CPL_FW4_ACK_SEQVAL V_CPL_FW4_ACK_SEQVAL(1U) 2778 2779 struct cpl_fw6_msg { 2780 RSS_HDR 2781 u8 opcode; 2782 u8 type; 2783 __be16 rsvd0; 2784 __be32 rsvd1; 2785 __be64 data[4]; 2786 }; 2787 2788 /* cpl_fw6_msg.type values */ 2789 enum { 2790 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2791 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2792 FW6_TYPE_CQE = FW_TYPE_CQE, 2793 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2794 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2795 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL, 2796 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR, 2797 NUM_FW6_TYPES 2798 }; 2799 2800 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2801 __u64 cookie; 2802 __be32 tid; /* or atid in case of active failure */ 2803 __u8 t_state; 2804 __u8 retval; 2805 __u8 rsvd[2]; 2806 }; 2807 2808 /* ULP_TX opcodes */ 2809 enum { 2810 ULP_TX_MEM_READ = 2, 2811 ULP_TX_MEM_WRITE = 3, 2812 ULP_TX_PKT = 4 2813 }; 2814 2815 enum { 2816 ULP_TX_SC_NOOP = 0x80, 2817 ULP_TX_SC_IMM = 0x81, 2818 ULP_TX_SC_DSGL = 0x82, 2819 ULP_TX_SC_ISGL = 0x83, 2820 ULP_TX_SC_PICTRL = 0x84, 2821 ULP_TX_SC_MEMRD = 0x86 2822 }; 2823 2824 #define S_ULPTX_CMD 24 2825 #define M_ULPTX_CMD 0xFF 2826 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2827 2828 #define S_ULPTX_LEN16 0 2829 #define M_ULPTX_LEN16 0xFF 2830 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2831 2832 #define S_ULP_TX_SC_MORE 23 2833 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2834 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2835 2836 struct ulptx_sge_pair { 2837 __be32 len[2]; 2838 __be64 addr[2]; 2839 }; 2840 2841 struct ulptx_sgl { 2842 __be32 cmd_nsge; 2843 __be32 len0; 2844 __be64 addr0; 2845 #if !(defined C99_NOT_SUPPORTED) 2846 struct ulptx_sge_pair sge[0]; 2847 #endif 2848 }; 2849 2850 struct ulptx_isge { 2851 __be32 stag; 2852 __be32 len; 2853 __be64 target_ofst; 2854 }; 2855 2856 struct ulptx_isgl { 2857 __be32 cmd_nisge; 2858 __be32 rsvd; 2859 #if !(defined C99_NOT_SUPPORTED) 2860 struct ulptx_isge sge[0]; 2861 #endif 2862 }; 2863 2864 struct ulptx_idata { 2865 __be32 cmd_more; 2866 __be32 len; 2867 }; 2868 2869 #define S_ULPTX_NSGE 0 2870 #define M_ULPTX_NSGE 0xFFFF 2871 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2872 #define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE) 2873 2874 struct ulptx_sc_memrd { 2875 __be32 cmd_to_len; 2876 __be32 addr; 2877 }; 2878 2879 struct ulp_mem_io { 2880 WR_HDR; 2881 __be32 cmd; 2882 __be32 len16; /* command length */ 2883 __be32 dlen; /* data length in 32-byte units */ 2884 __be32 lock_addr; 2885 }; 2886 2887 /* additional ulp_mem_io.cmd fields */ 2888 #define S_ULP_MEMIO_ORDER 23 2889 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2890 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2891 2892 #define S_T5_ULP_MEMIO_IMM 23 2893 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2894 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2895 2896 #define S_T5_ULP_MEMIO_ORDER 22 2897 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2898 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2899 2900 #define S_T5_ULP_MEMIO_FID 4 2901 #define M_T5_ULP_MEMIO_FID 0x7ff 2902 #define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID) 2903 2904 /* ulp_mem_io.lock_addr fields */ 2905 #define S_ULP_MEMIO_ADDR 0 2906 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2907 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2908 2909 #define S_ULP_MEMIO_LOCK 31 2910 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2911 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2912 2913 /* ulp_mem_io.dlen fields */ 2914 #define S_ULP_MEMIO_DATA_LEN 0 2915 #define M_ULP_MEMIO_DATA_LEN 0x1F 2916 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2917 2918 /* ULP_TXPKT field values */ 2919 enum { 2920 ULP_TXPKT_DEST_TP = 0, 2921 ULP_TXPKT_DEST_SGE, 2922 ULP_TXPKT_DEST_UP, 2923 ULP_TXPKT_DEST_DEVNULL, 2924 }; 2925 2926 struct ulp_txpkt { 2927 __be32 cmd_dest; 2928 __be32 len; 2929 }; 2930 2931 /* ulp_txpkt.cmd_dest fields */ 2932 #define S_ULP_TXPKT_DATAMODIFY 23 2933 #define M_ULP_TXPKT_DATAMODIFY 0x1 2934 #define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY) 2935 #define G_ULP_TXPKT_DATAMODIFY(x) \ 2936 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_) 2937 #define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U) 2938 2939 #define S_ULP_TXPKT_CHANNELID 22 2940 #define M_ULP_TXPKT_CHANNELID 0x1 2941 #define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID) 2942 #define G_ULP_TXPKT_CHANNELID(x) \ 2943 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID) 2944 #define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U) 2945 2946 /* ulp_txpkt.cmd_dest fields */ 2947 #define S_ULP_TXPKT_DEST 16 2948 #define M_ULP_TXPKT_DEST 0x3 2949 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2950 2951 #define S_ULP_TXPKT_FID 4 2952 #define M_ULP_TXPKT_FID 0x7ff 2953 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2954 2955 #define S_ULP_TXPKT_RO 3 2956 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2957 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2958 2959 enum cpl_tx_tnl_lso_type { 2960 TX_TNL_TYPE_OPAQUE, 2961 TX_TNL_TYPE_NVGRE, 2962 TX_TNL_TYPE_VXLAN, 2963 TX_TNL_TYPE_GENEVE, 2964 }; 2965 2966 struct cpl_tx_tnl_lso { 2967 __be32 op_to_IpIdSplitOut; 2968 __be16 IpIdOffsetOut; 2969 __be16 UdpLenSetOut_to_TnlHdrLen; 2970 __be64 r1; 2971 __be32 Flow_to_TcpHdrLen; 2972 __be16 IpIdOffset; 2973 __be16 IpIdSplit_to_Mss; 2974 __be32 TCPSeqOffset; 2975 __be32 EthLenOffset_Size; 2976 /* encapsulated CPL (TX_PKT_XT) follows here */ 2977 }; 2978 2979 #define S_CPL_TX_TNL_LSO_OPCODE 24 2980 #define M_CPL_TX_TNL_LSO_OPCODE 0xff 2981 #define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE) 2982 #define G_CPL_TX_TNL_LSO_OPCODE(x) \ 2983 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE) 2984 2985 #define S_CPL_TX_TNL_LSO_FIRST 23 2986 #define M_CPL_TX_TNL_LSO_FIRST 0x1 2987 #define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST) 2988 #define G_CPL_TX_TNL_LSO_FIRST(x) \ 2989 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST) 2990 #define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U) 2991 2992 #define S_CPL_TX_TNL_LSO_LAST 22 2993 #define M_CPL_TX_TNL_LSO_LAST 0x1 2994 #define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST) 2995 #define G_CPL_TX_TNL_LSO_LAST(x) \ 2996 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST) 2997 #define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U) 2998 2999 #define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21 3000 #define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1 3001 #define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 3002 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 3003 #define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 3004 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 3005 #define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U) 3006 3007 #define S_CPL_TX_TNL_LSO_IPV6OUT 20 3008 #define M_CPL_TX_TNL_LSO_IPV6OUT 0x1 3009 #define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT) 3010 #define G_CPL_TX_TNL_LSO_IPV6OUT(x) \ 3011 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT) 3012 #define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U) 3013 3014 #define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16 3015 #define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf 3016 #define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 3017 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT) 3018 #define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 3019 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT) 3020 3021 #define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4 3022 #define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff 3023 #define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT) 3024 #define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \ 3025 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT) 3026 3027 #define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3 3028 #define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1 3029 #define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT) 3030 #define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \ 3031 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT) 3032 #define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U) 3033 3034 #define S_CPL_TX_TNL_LSO_IPLENSETOUT 2 3035 #define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1 3036 #define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT) 3037 #define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \ 3038 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT) 3039 #define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U) 3040 3041 #define S_CPL_TX_TNL_LSO_IPIDINCOUT 1 3042 #define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1 3043 #define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT) 3044 #define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \ 3045 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT) 3046 #define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U) 3047 3048 #define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0 3049 #define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1 3050 #define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 3051 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT) 3052 #define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 3053 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT) 3054 #define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U) 3055 3056 #define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15 3057 #define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1 3058 #define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 3059 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT) 3060 #define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 3061 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT) 3062 #define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U) 3063 3064 #define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14 3065 #define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1 3066 #define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 3067 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3068 #define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 3069 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3070 #define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U) 3071 3072 #define S_CPL_TX_TNL_LSO_TNLTYPE 12 3073 #define M_CPL_TX_TNL_LSO_TNLTYPE 0x3 3074 #define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE) 3075 #define G_CPL_TX_TNL_LSO_TNLTYPE(x) \ 3076 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE) 3077 3078 #define S_CPL_TX_TNL_LSO_TNLHDRLEN 0 3079 #define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff 3080 #define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN) 3081 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \ 3082 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN) 3083 3084 #define S_CPL_TX_TNL_LSO_FLOW 21 3085 #define M_CPL_TX_TNL_LSO_FLOW 0x1 3086 #define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW) 3087 #define G_CPL_TX_TNL_LSO_FLOW(x) \ 3088 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW) 3089 #define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U) 3090 3091 #define S_CPL_TX_TNL_LSO_IPV6 20 3092 #define M_CPL_TX_TNL_LSO_IPV6 0x1 3093 #define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6) 3094 #define G_CPL_TX_TNL_LSO_IPV6(x) \ 3095 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6) 3096 #define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U) 3097 3098 #define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 3099 #define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 3100 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 3101 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 3102 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 3103 3104 #define S_CPL_TX_TNL_LSO_IPHDRLEN 4 3105 #define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff 3106 #define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN) 3107 #define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \ 3108 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN) 3109 3110 #define S_CPL_TX_TNL_LSO_TCPHDRLEN 0 3111 #define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf 3112 #define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN) 3113 #define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \ 3114 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN) 3115 3116 #define S_CPL_TX_TNL_LSO_IPIDSPLIT 15 3117 #define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1 3118 #define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT) 3119 #define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \ 3120 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT) 3121 #define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U) 3122 3123 #define S_CPL_TX_TNL_LSO_ETHHDRLENX 14 3124 #define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1 3125 #define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX) 3126 #define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \ 3127 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX) 3128 #define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U) 3129 3130 #define S_CPL_TX_TNL_LSO_MSS 0 3131 #define M_CPL_TX_TNL_LSO_MSS 0x3fff 3132 #define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS) 3133 #define G_CPL_TX_TNL_LSO_MSS(x) \ 3134 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS) 3135 3136 #define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28 3137 #define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf 3138 #define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3139 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET) 3140 #define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3141 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET) 3142 3143 #define S_CPL_TX_TNL_LSO_SIZE 0 3144 #define M_CPL_TX_TNL_LSO_SIZE 0xfffffff 3145 #define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE) 3146 #define G_CPL_TX_TNL_LSO_SIZE(x) \ 3147 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE) 3148 3149 struct cpl_rx_mps_pkt { 3150 __be32 op_to_r1_hi; 3151 __be32 r1_lo_length; 3152 }; 3153 3154 #define S_CPL_RX_MPS_PKT_OP 24 3155 #define M_CPL_RX_MPS_PKT_OP 0xff 3156 #define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP) 3157 #define G_CPL_RX_MPS_PKT_OP(x) \ 3158 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP) 3159 3160 #define S_CPL_RX_MPS_PKT_TYPE 20 3161 #define M_CPL_RX_MPS_PKT_TYPE 0xf 3162 #define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE) 3163 #define G_CPL_RX_MPS_PKT_TYPE(x) \ 3164 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE) 3165 3166 /* 3167 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field. 3168 */ 3169 #define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0) 3170 #define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1) 3171 #define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2) 3172 #define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3) 3173 3174 struct cpl_tx_tls_sfo { 3175 __be32 op_to_seg_len; 3176 __be32 pld_len; 3177 __be32 type_protover; 3178 __be32 r1_lo; 3179 __be32 seqno_numivs; 3180 __be32 ivgen_hdrlen; 3181 __be64 scmd1; 3182 }; 3183 3184 /* cpl_tx_tls_sfo macros */ 3185 #define S_CPL_TX_TLS_SFO_OPCODE 24 3186 #define M_CPL_TX_TLS_SFO_OPCODE 0xff 3187 #define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE) 3188 #define G_CPL_TX_TLS_SFO_OPCODE(x) \ 3189 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE) 3190 3191 #define S_CPL_TX_TLS_SFO_DATA_TYPE 20 3192 #define M_CPL_TX_TLS_SFO_DATA_TYPE 0xf 3193 #define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE) 3194 #define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \ 3195 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE) 3196 3197 #define S_CPL_TX_TLS_SFO_CPL_LEN 16 3198 #define M_CPL_TX_TLS_SFO_CPL_LEN 0xf 3199 #define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN) 3200 #define G_CPL_TX_TLS_SFO_CPL_LEN(x) \ 3201 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN) 3202 3203 #define S_CPL_TX_TLS_SFO_SEG_LEN 0 3204 #define M_CPL_TX_TLS_SFO_SEG_LEN 0xffff 3205 #define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN) 3206 #define G_CPL_TX_TLS_SFO_SEG_LEN(x) \ 3207 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN) 3208 3209 #define S_CPL_TX_TLS_SFO_TYPE 24 3210 #define M_CPL_TX_TLS_SFO_TYPE 0xff 3211 #define V_CPL_TX_TLS_SFO_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_TYPE) 3212 #define G_CPL_TX_TLS_SFO_TYPE(x) \ 3213 (((x) >> S_CPL_TX_TLS_SFO_TYPE) & M_CPL_TX_TLS_SFO_TYPE) 3214 3215 #define S_CPL_TX_TLS_SFO_PROTOVER 8 3216 #define M_CPL_TX_TLS_SFO_PROTOVER 0xffff 3217 #define V_CPL_TX_TLS_SFO_PROTOVER(x) ((x) << S_CPL_TX_TLS_SFO_PROTOVER) 3218 #define G_CPL_TX_TLS_SFO_PROTOVER(x) \ 3219 (((x) >> S_CPL_TX_TLS_SFO_PROTOVER) & M_CPL_TX_TLS_SFO_PROTOVER) 3220 3221 struct cpl_tls_data { 3222 RSS_HDR 3223 union opcode_tid ot; 3224 __be32 length_pkd; 3225 __be32 seq; 3226 __be32 r1; 3227 }; 3228 3229 #define S_CPL_TLS_DATA_OPCODE 24 3230 #define M_CPL_TLS_DATA_OPCODE 0xff 3231 #define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE) 3232 #define G_CPL_TLS_DATA_OPCODE(x) \ 3233 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE) 3234 3235 #define S_CPL_TLS_DATA_TID 0 3236 #define M_CPL_TLS_DATA_TID 0xffffff 3237 #define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID) 3238 #define G_CPL_TLS_DATA_TID(x) \ 3239 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID) 3240 3241 #define S_CPL_TLS_DATA_LENGTH 0 3242 #define M_CPL_TLS_DATA_LENGTH 0xffff 3243 #define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH) 3244 #define G_CPL_TLS_DATA_LENGTH(x) \ 3245 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH) 3246 3247 struct cpl_rx_tls_cmp { 3248 RSS_HDR 3249 union opcode_tid ot; 3250 __be32 pdulength_length; 3251 __be32 seq; 3252 __be32 ddp_report; 3253 __be32 r; 3254 __be32 ddp_valid; 3255 }; 3256 3257 #define S_CPL_RX_TLS_CMP_OPCODE 24 3258 #define M_CPL_RX_TLS_CMP_OPCODE 0xff 3259 #define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE) 3260 #define G_CPL_RX_TLS_CMP_OPCODE(x) \ 3261 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE) 3262 3263 #define S_CPL_RX_TLS_CMP_TID 0 3264 #define M_CPL_RX_TLS_CMP_TID 0xffffff 3265 #define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID) 3266 #define G_CPL_RX_TLS_CMP_TID(x) \ 3267 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID) 3268 3269 #define S_CPL_RX_TLS_CMP_PDULENGTH 16 3270 #define M_CPL_RX_TLS_CMP_PDULENGTH 0xffff 3271 #define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH) 3272 #define G_CPL_RX_TLS_CMP_PDULENGTH(x) \ 3273 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH) 3274 3275 #define S_CPL_RX_TLS_CMP_LENGTH 0 3276 #define M_CPL_RX_TLS_CMP_LENGTH 0xffff 3277 #define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH) 3278 #define G_CPL_RX_TLS_CMP_LENGTH(x) \ 3279 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH) 3280 3281 #define S_SCMD_SEQ_NO_CTRL 29 3282 #define M_SCMD_SEQ_NO_CTRL 0x3 3283 #define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL) 3284 #define G_SCMD_SEQ_NO_CTRL(x) \ 3285 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL) 3286 3287 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 3288 #define S_SCMD_STATUS_PRESENT 28 3289 #define M_SCMD_STATUS_PRESENT 0x1 3290 #define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT) 3291 #define G_SCMD_STATUS_PRESENT(x) \ 3292 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT) 3293 #define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U) 3294 3295 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 3296 * 3-15: Reserved. */ 3297 #define S_SCMD_PROTO_VERSION 24 3298 #define M_SCMD_PROTO_VERSION 0xf 3299 #define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION) 3300 #define G_SCMD_PROTO_VERSION(x) \ 3301 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION) 3302 3303 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 3304 #define S_SCMD_ENC_DEC_CTRL 23 3305 #define M_SCMD_ENC_DEC_CTRL 0x1 3306 #define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL) 3307 #define G_SCMD_ENC_DEC_CTRL(x) \ 3308 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL) 3309 #define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U) 3310 3311 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 3312 #define S_SCMD_CIPH_AUTH_SEQ_CTRL 22 3313 #define M_SCMD_CIPH_AUTH_SEQ_CTRL 0x1 3314 #define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3315 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL) 3316 #define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3317 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL) 3318 #define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U) 3319 3320 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 3321 * 4:Generic-AES, 5-15: Reserved. */ 3322 #define S_SCMD_CIPH_MODE 18 3323 #define M_SCMD_CIPH_MODE 0xf 3324 #define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE) 3325 #define G_SCMD_CIPH_MODE(x) \ 3326 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE) 3327 3328 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 3329 * 4-15: Reserved */ 3330 #define S_SCMD_AUTH_MODE 14 3331 #define M_SCMD_AUTH_MODE 0xf 3332 #define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE) 3333 #define G_SCMD_AUTH_MODE(x) \ 3334 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE) 3335 3336 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 3337 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 3338 */ 3339 #define S_SCMD_HMAC_CTRL 11 3340 #define M_SCMD_HMAC_CTRL 0x7 3341 #define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL) 3342 #define G_SCMD_HMAC_CTRL(x) \ 3343 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL) 3344 3345 /* IvSize - IV size in units of 2 bytes */ 3346 #define S_SCMD_IV_SIZE 7 3347 #define M_SCMD_IV_SIZE 0xf 3348 #define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE) 3349 #define G_SCMD_IV_SIZE(x) \ 3350 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE) 3351 3352 /* NumIVs - Number of IVs */ 3353 #define S_SCMD_NUM_IVS 0 3354 #define M_SCMD_NUM_IVS 0x7f 3355 #define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS) 3356 #define G_SCMD_NUM_IVS(x) \ 3357 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS) 3358 3359 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 3360 * (below) are used as Cid (connection id for debug status), these 3361 * bits are padded to zero for forming the 64 bit 3362 * sequence number for TLS 3363 */ 3364 #define S_SCMD_ENB_DBGID 31 3365 #define M_SCMD_ENB_DBGID 0x1 3366 #define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID) 3367 #define G_SCMD_ENB_DBGID(x) \ 3368 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID) 3369 3370 /* IV generation in SW. */ 3371 #define S_SCMD_IV_GEN_CTRL 30 3372 #define M_SCMD_IV_GEN_CTRL 0x1 3373 #define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL) 3374 #define G_SCMD_IV_GEN_CTRL(x) \ 3375 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL) 3376 #define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U) 3377 3378 /* More frags */ 3379 #define S_SCMD_MORE_FRAGS 20 3380 #define M_SCMD_MORE_FRAGS 0x1 3381 #define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS) 3382 #define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS) 3383 3384 /*last frag */ 3385 #define S_SCMD_LAST_FRAG 19 3386 #define M_SCMD_LAST_FRAG 0x1 3387 #define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG) 3388 #define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG) 3389 3390 /* TlsCompPdu */ 3391 #define S_SCMD_TLS_COMPPDU 18 3392 #define M_SCMD_TLS_COMPPDU 0x1 3393 #define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU) 3394 #define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU) 3395 3396 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 3397 #define S_SCMD_KEY_CTX_INLINE 17 3398 #define M_SCMD_KEY_CTX_INLINE 0x1 3399 #define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE) 3400 #define G_SCMD_KEY_CTX_INLINE(x) \ 3401 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE) 3402 #define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U) 3403 3404 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 3405 #define S_SCMD_TLS_FRAG_ENABLE 16 3406 #define M_SCMD_TLS_FRAG_ENABLE 0x1 3407 #define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE) 3408 #define G_SCMD_TLS_FRAG_ENABLE(x) \ 3409 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE) 3410 #define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U) 3411 3412 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 3413 * modes, in this case TLS_TX will drop the PDU and only 3414 * send back the MAC bytes. */ 3415 #define S_SCMD_MAC_ONLY 15 3416 #define M_SCMD_MAC_ONLY 0x1 3417 #define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY) 3418 #define G_SCMD_MAC_ONLY(x) \ 3419 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY) 3420 #define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U) 3421 3422 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 3423 * which have complex AAD and IV formations Eg:AES-CCM 3424 */ 3425 #define S_SCMD_AADIVDROP 14 3426 #define M_SCMD_AADIVDROP 0x1 3427 #define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP) 3428 #define G_SCMD_AADIVDROP(x) \ 3429 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP) 3430 #define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U) 3431 3432 /* HdrLength - Length of all headers excluding TLS header 3433 * present before start of crypto PDU/payload. */ 3434 #define S_SCMD_HDR_LEN 0 3435 #define M_SCMD_HDR_LEN 0x3fff 3436 #define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN) 3437 #define G_SCMD_HDR_LEN(x) \ 3438 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN) 3439 3440 struct cpl_tx_sec_pdu { 3441 __be32 op_ivinsrtofst; 3442 __be32 pldlen; 3443 __be32 aadstart_cipherstop_hi; 3444 __be32 cipherstop_lo_authinsert; 3445 __be32 seqno_numivs; 3446 __be32 ivgen_hdrlen; 3447 __be64 scmd1; 3448 }; 3449 3450 #define S_CPL_TX_SEC_PDU_OPCODE 24 3451 #define M_CPL_TX_SEC_PDU_OPCODE 0xff 3452 #define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE) 3453 #define G_CPL_TX_SEC_PDU_OPCODE(x) \ 3454 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE) 3455 3456 /* RX Channel Id */ 3457 #define S_CPL_TX_SEC_PDU_RXCHID 22 3458 #define M_CPL_TX_SEC_PDU_RXCHID 0x1 3459 #define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID) 3460 #define G_CPL_TX_SEC_PDU_RXCHID(x) \ 3461 (((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID) 3462 #define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U) 3463 3464 /* Ack Follows */ 3465 #define S_CPL_TX_SEC_PDU_ACKFOLLOWS 21 3466 #define M_CPL_TX_SEC_PDU_ACKFOLLOWS 0x1 3467 #define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS) 3468 #define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \ 3469 (((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS) 3470 #define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U) 3471 3472 /* Loopback bit in cpl_tx_sec_pdu */ 3473 #define S_CPL_TX_SEC_PDU_ULPTXLPBK 20 3474 #define M_CPL_TX_SEC_PDU_ULPTXLPBK 0x1 3475 #define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK) 3476 #define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \ 3477 (((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK) 3478 #define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U) 3479 3480 /* Length of cpl header encapsulated */ 3481 #define S_CPL_TX_SEC_PDU_CPLLEN 16 3482 #define M_CPL_TX_SEC_PDU_CPLLEN 0xf 3483 #define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN) 3484 #define G_CPL_TX_SEC_PDU_CPLLEN(x) \ 3485 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN) 3486 3487 /* PlaceHolder */ 3488 #define S_CPL_TX_SEC_PDU_PLACEHOLDER 10 3489 #define M_CPL_TX_SEC_PDU_PLACEHOLDER 0x1 3490 #define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER) 3491 #define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \ 3492 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \ 3493 M_CPL_TX_SEC_PDU_PLACEHOLDER) 3494 3495 /* IvInsrtOffset: Insertion location for IV */ 3496 #define S_CPL_TX_SEC_PDU_IVINSRTOFST 0 3497 #define M_CPL_TX_SEC_PDU_IVINSRTOFST 0x3ff 3498 #define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST) 3499 #define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \ 3500 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \ 3501 M_CPL_TX_SEC_PDU_IVINSRTOFST) 3502 3503 /* AadStartOffset: Offset in bytes for AAD start from 3504 * the first byte following 3505 * the pkt headers (0-255 3506 * bytes) */ 3507 #define S_CPL_TX_SEC_PDU_AADSTART 24 3508 #define M_CPL_TX_SEC_PDU_AADSTART 0xff 3509 #define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART) 3510 #define G_CPL_TX_SEC_PDU_AADSTART(x) \ 3511 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \ 3512 M_CPL_TX_SEC_PDU_AADSTART) 3513 3514 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 3515 * the pkt headers (0-511 bytes) */ 3516 #define S_CPL_TX_SEC_PDU_AADSTOP 15 3517 #define M_CPL_TX_SEC_PDU_AADSTOP 0x1ff 3518 #define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP) 3519 #define G_CPL_TX_SEC_PDU_AADSTOP(x) \ 3520 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP) 3521 3522 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 3523 * first byte following the pkt headers (0-1023 3524 * bytes) */ 3525 #define S_CPL_TX_SEC_PDU_CIPHERSTART 5 3526 #define M_CPL_TX_SEC_PDU_CIPHERSTART 0x3ff 3527 #define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART) 3528 #define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \ 3529 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \ 3530 M_CPL_TX_SEC_PDU_CIPHERSTART) 3531 3532 /* CipherStopOffset: offset in bytes for encryption/decryption end 3533 * from end of the payload of this command (0-511 bytes) */ 3534 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0 3535 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0x1f 3536 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3537 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3538 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3539 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \ 3540 M_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3541 3542 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_LO 28 3543 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_LO 0xf 3544 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3545 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3546 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3547 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \ 3548 M_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3549 3550 /* AuthStartOffset: offset in bytes for authentication start from 3551 * the first byte following the pkt headers (0-1023) 3552 * */ 3553 #define S_CPL_TX_SEC_PDU_AUTHSTART 18 3554 #define M_CPL_TX_SEC_PDU_AUTHSTART 0x3ff 3555 #define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART) 3556 #define G_CPL_TX_SEC_PDU_AUTHSTART(x) \ 3557 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \ 3558 M_CPL_TX_SEC_PDU_AUTHSTART) 3559 3560 /* AuthStopOffset: offset in bytes for authentication 3561 * end from end of the payload of this command (0-511 Bytes) */ 3562 #define S_CPL_TX_SEC_PDU_AUTHSTOP 9 3563 #define M_CPL_TX_SEC_PDU_AUTHSTOP 0x1ff 3564 #define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP) 3565 #define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \ 3566 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \ 3567 M_CPL_TX_SEC_PDU_AUTHSTOP) 3568 3569 /* AuthInsrtOffset: offset in bytes for authentication insertion 3570 * from end of the payload of this command (0-511 bytes) */ 3571 #define S_CPL_TX_SEC_PDU_AUTHINSERT 0 3572 #define M_CPL_TX_SEC_PDU_AUTHINSERT 0x1ff 3573 #define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT) 3574 #define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \ 3575 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \ 3576 M_CPL_TX_SEC_PDU_AUTHINSERT) 3577 3578 struct cpl_rx_phys_dsgl { 3579 __be32 op_to_tid; 3580 __be32 pcirlxorder_to_noofsgentr; 3581 struct rss_header rss_hdr_int; 3582 }; 3583 3584 #define S_CPL_RX_PHYS_DSGL_OPCODE 24 3585 #define M_CPL_RX_PHYS_DSGL_OPCODE 0xff 3586 #define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE) 3587 #define G_CPL_RX_PHYS_DSGL_OPCODE(x) \ 3588 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE) 3589 3590 #define S_CPL_RX_PHYS_DSGL_ISRDMA 23 3591 #define M_CPL_RX_PHYS_DSGL_ISRDMA 0x1 3592 #define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA) 3593 #define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \ 3594 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA) 3595 #define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U) 3596 3597 #define S_CPL_RX_PHYS_DSGL_RSVD1 20 3598 #define M_CPL_RX_PHYS_DSGL_RSVD1 0x7 3599 #define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1) 3600 #define G_CPL_RX_PHYS_DSGL_RSVD1(x) \ 3601 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1) 3602 3603 #define S_CPL_RX_PHYS_DSGL_PCIRLXORDER 31 3604 #define M_CPL_RX_PHYS_DSGL_PCIRLXORDER 0x1 3605 #define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3606 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3607 #define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3608 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \ 3609 M_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3610 #define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U) 3611 3612 #define S_CPL_RX_PHYS_DSGL_PCINOSNOOP 30 3613 #define M_CPL_RX_PHYS_DSGL_PCINOSNOOP 0x1 3614 #define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3615 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3616 #define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3617 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \ 3618 M_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3619 #define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U) 3620 3621 #define S_CPL_RX_PHYS_DSGL_PCITPHNTENB 29 3622 #define M_CPL_RX_PHYS_DSGL_PCITPHNTENB 0x1 3623 #define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3624 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3625 #define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3626 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \ 3627 M_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3628 #define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U) 3629 3630 #define S_CPL_RX_PHYS_DSGL_PCITPHNT 27 3631 #define M_CPL_RX_PHYS_DSGL_PCITPHNT 0x3 3632 #define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT) 3633 #define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \ 3634 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \ 3635 M_CPL_RX_PHYS_DSGL_PCITPHNT) 3636 3637 #define S_CPL_RX_PHYS_DSGL_DCAID 16 3638 #define M_CPL_RX_PHYS_DSGL_DCAID 0x7ff 3639 #define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID) 3640 #define G_CPL_RX_PHYS_DSGL_DCAID(x) \ 3641 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \ 3642 M_CPL_RX_PHYS_DSGL_DCAID) 3643 3644 #define S_CPL_RX_PHYS_DSGL_NOOFSGENTR 0 3645 #define M_CPL_RX_PHYS_DSGL_NOOFSGENTR 0xffff 3646 #define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3647 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3648 #define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3649 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \ 3650 M_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3651 3652 /* CPL_TX_TLS_ACK */ 3653 struct cpl_tx_tls_ack { 3654 __be32 op_to_Rsvd2; 3655 __be32 PldLen; 3656 __be64 Rsvd3; 3657 }; 3658 3659 #define S_CPL_TX_TLS_ACK_OPCODE 24 3660 #define M_CPL_TX_TLS_ACK_OPCODE 0xff 3661 #define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE) 3662 #define G_CPL_TX_TLS_ACK_OPCODE(x) \ 3663 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE) 3664 3665 #define S_CPL_TX_TLS_ACK_RSVD1 23 3666 #define M_CPL_TX_TLS_ACK_RSVD1 0x1 3667 #define V_CPL_TX_TLS_ACK_RSVD1(x) ((x) << S_CPL_TX_TLS_ACK_RSVD1) 3668 #define G_CPL_TX_TLS_ACK_RSVD1(x) \ 3669 (((x) >> S_CPL_TX_TLS_ACK_RSVD1) & M_CPL_TX_TLS_ACK_RSVD1) 3670 #define F_CPL_TX_TLS_ACK_RSVD1 V_CPL_TX_TLS_ACK_RSVD1(1U) 3671 3672 #define S_CPL_TX_TLS_ACK_RXCHID 22 3673 #define M_CPL_TX_TLS_ACK_RXCHID 0x1 3674 #define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID) 3675 #define G_CPL_TX_TLS_ACK_RXCHID(x) \ 3676 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID) 3677 #define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U) 3678 3679 #define S_CPL_TX_TLS_ACK_FWMSG 21 3680 #define M_CPL_TX_TLS_ACK_FWMSG 0x1 3681 #define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG) 3682 #define G_CPL_TX_TLS_ACK_FWMSG(x) \ 3683 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG) 3684 #define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U) 3685 3686 #define S_CPL_TX_TLS_ACK_ULPTXLPBK 20 3687 #define M_CPL_TX_TLS_ACK_ULPTXLPBK 0x1 3688 #define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK) 3689 #define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \ 3690 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK) 3691 #define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U) 3692 3693 #define S_CPL_TX_TLS_ACK_CPLLEN 16 3694 #define M_CPL_TX_TLS_ACK_CPLLEN 0xf 3695 #define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN) 3696 #define G_CPL_TX_TLS_ACK_CPLLEN(x) \ 3697 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN) 3698 3699 #define S_CPL_TX_TLS_ACK_COMPLONERR 15 3700 #define M_CPL_TX_TLS_ACK_COMPLONERR 0x1 3701 #define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR) 3702 #define G_CPL_TX_TLS_ACK_COMPLONERR(x) \ 3703 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR) 3704 #define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U) 3705 3706 #define S_CPL_TX_TLS_ACK_LCB 14 3707 #define M_CPL_TX_TLS_ACK_LCB 0x1 3708 #define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB) 3709 #define G_CPL_TX_TLS_ACK_LCB(x) \ 3710 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB) 3711 #define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U) 3712 3713 #define S_CPL_TX_TLS_ACK_PHASH 13 3714 #define M_CPL_TX_TLS_ACK_PHASH 0x1 3715 #define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH) 3716 #define G_CPL_TX_TLS_ACK_PHASH(x) \ 3717 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH) 3718 #define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U) 3719 3720 #define S_CPL_TX_TLS_ACK_RSVD2 0 3721 #define M_CPL_TX_TLS_ACK_RSVD2 0x1fff 3722 #define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2) 3723 #define G_CPL_TX_TLS_ACK_RSVD2(x) \ 3724 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2) 3725 3726 #endif /* T4_MSG_H */ 3727