1 /*- 2 * Copyright (c) 2012-2017 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed successfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 FW_SCSI_IO_BLOCK = 143, /* IO is going to be blocked due to resource failure */ 77 }; 78 79 /****************************************************************************** 80 * M E M O R Y T Y P E s 81 ******************************/ 82 83 enum fw_memtype { 84 FW_MEMTYPE_EDC0 = 0x0, 85 FW_MEMTYPE_EDC1 = 0x1, 86 FW_MEMTYPE_EXTMEM = 0x2, 87 FW_MEMTYPE_FLASH = 0x4, 88 FW_MEMTYPE_INTERNAL = 0x5, 89 FW_MEMTYPE_EXTMEM1 = 0x6, 90 FW_MEMTYPE_HMA = 0x7, 91 }; 92 93 /****************************************************************************** 94 * W O R K R E Q U E S T s 95 ********************************/ 96 97 enum fw_wr_opcodes { 98 FW_FRAG_WR = 0x1d, 99 FW_FILTER_WR = 0x02, 100 FW_ULPTX_WR = 0x04, 101 FW_TP_WR = 0x05, 102 FW_ETH_TX_PKT_WR = 0x08, 103 FW_ETH_TX_PKT2_WR = 0x44, 104 FW_ETH_TX_PKTS_WR = 0x09, 105 FW_ETH_TX_PKTS2_WR = 0x78, 106 FW_ETH_TX_EO_WR = 0x1c, 107 FW_EQ_FLUSH_WR = 0x1b, 108 FW_OFLD_CONNECTION_WR = 0x2f, 109 FW_FLOWC_WR = 0x0a, 110 FW_OFLD_TX_DATA_WR = 0x0b, 111 FW_CMD_WR = 0x10, 112 FW_ETH_TX_PKT_VM_WR = 0x11, 113 FW_ETH_TX_PKTS_VM_WR = 0x12, 114 FW_RI_RES_WR = 0x0c, 115 FW_RI_RDMA_WRITE_WR = 0x14, 116 FW_RI_SEND_WR = 0x15, 117 FW_RI_RDMA_READ_WR = 0x16, 118 FW_RI_RECV_WR = 0x17, 119 FW_RI_BIND_MW_WR = 0x18, 120 FW_RI_FR_NSMR_WR = 0x19, 121 FW_RI_FR_NSMR_TPTE_WR = 0x20, 122 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 123 FW_RI_INV_LSTAG_WR = 0x1a, 124 FW_RI_SEND_IMMEDIATE_WR = 0x15, 125 FW_RI_ATOMIC_WR = 0x16, 126 FW_RI_WR = 0x0d, 127 FW_CHNET_IFCONF_WR = 0x6b, 128 FW_RDEV_WR = 0x38, 129 FW_FOISCSI_NODE_WR = 0x60, 130 FW_FOISCSI_CTRL_WR = 0x6a, 131 FW_FOISCSI_CHAP_WR = 0x6c, 132 FW_FCOE_ELS_CT_WR = 0x30, 133 FW_SCSI_WRITE_WR = 0x31, 134 FW_SCSI_READ_WR = 0x32, 135 FW_SCSI_CMD_WR = 0x33, 136 FW_SCSI_ABRT_CLS_WR = 0x34, 137 FW_SCSI_TGT_ACC_WR = 0x35, 138 FW_SCSI_TGT_XMIT_WR = 0x36, 139 FW_SCSI_TGT_RSP_WR = 0x37, 140 FW_POFCOE_TCB_WR = 0x42, 141 FW_POFCOE_ULPTX_WR = 0x43, 142 FW_ISCSI_TX_DATA_WR = 0x45, 143 FW_PTP_TX_PKT_WR = 0x46, 144 FW_TLSTX_DATA_WR = 0x68, 145 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 146 FW_COISCSI_TGT_WR = 0x70, 147 FW_COISCSI_TGT_CONN_WR = 0x71, 148 FW_COISCSI_TGT_XMIT_WR = 0x72, 149 FW_COISCSI_STATS_WR = 0x73, 150 FW_ISNS_WR = 0x75, 151 FW_ISNS_XMIT_WR = 0x76, 152 FW_FILTER2_WR = 0x77, 153 FW_LASTC2E_WR = 0x80 154 }; 155 156 /* 157 * Generic work request header flit0 158 */ 159 struct fw_wr_hdr { 160 __be32 hi; 161 __be32 lo; 162 }; 163 164 /* work request opcode (hi) 165 */ 166 #define S_FW_WR_OP 24 167 #define M_FW_WR_OP 0xff 168 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 169 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 170 171 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 172 */ 173 #define S_FW_WR_ATOMIC 23 174 #define M_FW_WR_ATOMIC 0x1 175 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 176 #define G_FW_WR_ATOMIC(x) \ 177 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 178 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 179 180 /* flush flag (hi) - firmware flushes flushable work request buffered 181 * in the flow context. 182 */ 183 #define S_FW_WR_FLUSH 22 184 #define M_FW_WR_FLUSH 0x1 185 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 186 #define G_FW_WR_FLUSH(x) \ 187 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 188 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 189 190 /* completion flag (hi) - firmware generates a cpl_fw6_ack 191 */ 192 #define S_FW_WR_COMPL 21 193 #define M_FW_WR_COMPL 0x1 194 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 195 #define G_FW_WR_COMPL(x) \ 196 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 197 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 198 199 200 /* work request immediate data lengh (hi) 201 */ 202 #define S_FW_WR_IMMDLEN 0 203 #define M_FW_WR_IMMDLEN 0xff 204 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 205 #define G_FW_WR_IMMDLEN(x) \ 206 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 207 208 /* egress queue status update to associated ingress queue entry (lo) 209 */ 210 #define S_FW_WR_EQUIQ 31 211 #define M_FW_WR_EQUIQ 0x1 212 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 213 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 214 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 215 216 /* egress queue status update to egress queue status entry (lo) 217 */ 218 #define S_FW_WR_EQUEQ 30 219 #define M_FW_WR_EQUEQ 0x1 220 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 221 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 222 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 223 224 /* flow context identifier (lo) 225 */ 226 #define S_FW_WR_FLOWID 8 227 #define M_FW_WR_FLOWID 0xfffff 228 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 229 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 230 231 /* length in units of 16-bytes (lo) 232 */ 233 #define S_FW_WR_LEN16 0 234 #define M_FW_WR_LEN16 0xff 235 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 236 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 237 238 struct fw_frag_wr { 239 __be32 op_to_fragoff16; 240 __be32 flowid_len16; 241 __be64 r4; 242 }; 243 244 #define S_FW_FRAG_WR_EOF 15 245 #define M_FW_FRAG_WR_EOF 0x1 246 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 247 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 248 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 249 250 #define S_FW_FRAG_WR_FRAGOFF16 8 251 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 252 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 253 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 254 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 255 256 /* valid filter configurations for compressed tuple 257 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 258 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 259 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 260 * OV - Outer VLAN/VNIC_ID, 261 */ 262 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 263 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 264 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 265 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 266 #define HW_TPL_FR_MT_E_PR_T 0x370 267 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 268 #define HW_TPL_FR_MT_E_T_P_FC 0X353 269 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 270 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 271 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 272 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 273 #define HW_TPL_FR_M_E_PR_FC 0X2E1 274 #define HW_TPL_FR_M_E_T_FC 0X2D1 275 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 276 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 277 #define HW_TPL_FR_M_T_IV_FC 0X299 278 #define HW_TPL_FR_M_T_OV_FC 0X295 279 #define HW_TPL_FR_E_PR_T_P 0X272 280 #define HW_TPL_FR_E_PR_T_FC 0X271 281 #define HW_TPL_FR_E_IV_FC 0X249 282 #define HW_TPL_FR_E_OV_FC 0X245 283 #define HW_TPL_FR_PR_T_IV_FC 0X239 284 #define HW_TPL_FR_PR_T_OV_FC 0X235 285 #define HW_TPL_FR_IV_OV_FC 0X20D 286 #define HW_TPL_MT_M_E_PR 0X1E0 287 #define HW_TPL_MT_M_E_T 0X1D0 288 #define HW_TPL_MT_E_PR_T_FC 0X171 289 #define HW_TPL_MT_E_IV 0X148 290 #define HW_TPL_MT_E_OV 0X144 291 #define HW_TPL_MT_PR_T_IV 0X138 292 #define HW_TPL_MT_PR_T_OV 0X134 293 #define HW_TPL_M_E_PR_P 0X0E2 294 #define HW_TPL_M_E_T_P 0X0D2 295 #define HW_TPL_E_PR_T_P_FC 0X073 296 #define HW_TPL_E_IV_P 0X04A 297 #define HW_TPL_E_OV_P 0X046 298 #define HW_TPL_PR_T_IV_P 0X03A 299 #define HW_TPL_PR_T_OV_P 0X036 300 301 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 302 enum fw_filter_wr_cookie { 303 FW_FILTER_WR_SUCCESS, 304 FW_FILTER_WR_FLT_ADDED, 305 FW_FILTER_WR_FLT_DELETED, 306 FW_FILTER_WR_SMT_TBL_FULL, 307 FW_FILTER_WR_EINVAL, 308 }; 309 310 enum fw_filter_wr_nat_mode { 311 FW_FILTER_WR_NATMODE_NONE = 0, 312 FW_FILTER_WR_NATMODE_DIP , 313 FW_FILTER_WR_NATMODE_DIPDP, 314 FW_FILTER_WR_NATMODE_DIPDPSIP, 315 FW_FILTER_WR_NATMODE_DIPDPSP, 316 FW_FILTER_WR_NATMODE_SIPSP, 317 FW_FILTER_WR_NATMODE_DIPSIPSP, 318 FW_FILTER_WR_NATMODE_FOURTUPLE, 319 }; 320 321 struct fw_filter_wr { 322 __be32 op_pkd; 323 __be32 len16_pkd; 324 __be64 r3; 325 __be32 tid_to_iq; 326 __be32 del_filter_to_l2tix; 327 __be16 ethtype; 328 __be16 ethtypem; 329 __u8 frag_to_ovlan_vldm; 330 __u8 smac_sel; 331 __be16 rx_chan_rx_rpl_iq; 332 __be32 maci_to_matchtypem; 333 __u8 ptcl; 334 __u8 ptclm; 335 __u8 ttyp; 336 __u8 ttypm; 337 __be16 ivlan; 338 __be16 ivlanm; 339 __be16 ovlan; 340 __be16 ovlanm; 341 __u8 lip[16]; 342 __u8 lipm[16]; 343 __u8 fip[16]; 344 __u8 fipm[16]; 345 __be16 lp; 346 __be16 lpm; 347 __be16 fp; 348 __be16 fpm; 349 __be16 r7; 350 __u8 sma[6]; 351 }; 352 353 struct fw_filter2_wr { 354 __be32 op_pkd; 355 __be32 len16_pkd; 356 __be64 r3; 357 __be32 tid_to_iq; 358 __be32 del_filter_to_l2tix; 359 __be16 ethtype; 360 __be16 ethtypem; 361 __u8 frag_to_ovlan_vldm; 362 __u8 smac_sel; 363 __be16 rx_chan_rx_rpl_iq; 364 __be32 maci_to_matchtypem; 365 __u8 ptcl; 366 __u8 ptclm; 367 __u8 ttyp; 368 __u8 ttypm; 369 __be16 ivlan; 370 __be16 ivlanm; 371 __be16 ovlan; 372 __be16 ovlanm; 373 __u8 lip[16]; 374 __u8 lipm[16]; 375 __u8 fip[16]; 376 __u8 fipm[16]; 377 __be16 lp; 378 __be16 lpm; 379 __be16 fp; 380 __be16 fpm; 381 __be16 r7; 382 __u8 sma[6]; 383 __be16 r8; 384 __u8 filter_type_swapmac; 385 __u8 natmode_to_ulp_type; 386 __be16 newlport; 387 __be16 newfport; 388 __u8 newlip[16]; 389 __u8 newfip[16]; 390 __be32 natseqcheck; 391 __be32 r9; 392 __be64 r10; 393 __be64 r11; 394 __be64 r12; 395 __be64 r13; 396 }; 397 398 #define S_FW_FILTER_WR_TID 12 399 #define M_FW_FILTER_WR_TID 0xfffff 400 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 401 #define G_FW_FILTER_WR_TID(x) \ 402 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 403 404 #define S_FW_FILTER_WR_RQTYPE 11 405 #define M_FW_FILTER_WR_RQTYPE 0x1 406 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 407 #define G_FW_FILTER_WR_RQTYPE(x) \ 408 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 409 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 410 411 #define S_FW_FILTER_WR_NOREPLY 10 412 #define M_FW_FILTER_WR_NOREPLY 0x1 413 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 414 #define G_FW_FILTER_WR_NOREPLY(x) \ 415 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 416 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 417 418 #define S_FW_FILTER_WR_IQ 0 419 #define M_FW_FILTER_WR_IQ 0x3ff 420 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 421 #define G_FW_FILTER_WR_IQ(x) \ 422 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 423 424 #define S_FW_FILTER_WR_DEL_FILTER 31 425 #define M_FW_FILTER_WR_DEL_FILTER 0x1 426 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 427 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 428 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 429 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 430 431 #define S_FW_FILTER2_WR_DROP_ENCAP 30 432 #define M_FW_FILTER2_WR_DROP_ENCAP 0x1 433 #define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP) 434 #define G_FW_FILTER2_WR_DROP_ENCAP(x) \ 435 (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP) 436 #define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U) 437 438 #define S_FW_FILTER2_WR_TX_LOOP 29 439 #define M_FW_FILTER2_WR_TX_LOOP 0x1 440 #define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP) 441 #define G_FW_FILTER2_WR_TX_LOOP(x) \ 442 (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP) 443 #define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U) 444 445 #define S_FW_FILTER_WR_RPTTID 25 446 #define M_FW_FILTER_WR_RPTTID 0x1 447 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 448 #define G_FW_FILTER_WR_RPTTID(x) \ 449 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 450 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 451 452 #define S_FW_FILTER_WR_DROP 24 453 #define M_FW_FILTER_WR_DROP 0x1 454 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 455 #define G_FW_FILTER_WR_DROP(x) \ 456 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 457 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 458 459 #define S_FW_FILTER_WR_DIRSTEER 23 460 #define M_FW_FILTER_WR_DIRSTEER 0x1 461 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 462 #define G_FW_FILTER_WR_DIRSTEER(x) \ 463 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 464 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 465 466 #define S_FW_FILTER_WR_MASKHASH 22 467 #define M_FW_FILTER_WR_MASKHASH 0x1 468 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 469 #define G_FW_FILTER_WR_MASKHASH(x) \ 470 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 471 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 472 473 #define S_FW_FILTER_WR_DIRSTEERHASH 21 474 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 475 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 476 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 477 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 478 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 479 480 #define S_FW_FILTER_WR_LPBK 20 481 #define M_FW_FILTER_WR_LPBK 0x1 482 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 483 #define G_FW_FILTER_WR_LPBK(x) \ 484 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 485 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 486 487 #define S_FW_FILTER_WR_DMAC 19 488 #define M_FW_FILTER_WR_DMAC 0x1 489 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 490 #define G_FW_FILTER_WR_DMAC(x) \ 491 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 492 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 493 494 #define S_FW_FILTER_WR_SMAC 18 495 #define M_FW_FILTER_WR_SMAC 0x1 496 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 497 #define G_FW_FILTER_WR_SMAC(x) \ 498 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 499 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 500 501 #define S_FW_FILTER_WR_INSVLAN 17 502 #define M_FW_FILTER_WR_INSVLAN 0x1 503 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 504 #define G_FW_FILTER_WR_INSVLAN(x) \ 505 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 506 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 507 508 #define S_FW_FILTER_WR_RMVLAN 16 509 #define M_FW_FILTER_WR_RMVLAN 0x1 510 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 511 #define G_FW_FILTER_WR_RMVLAN(x) \ 512 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 513 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 514 515 #define S_FW_FILTER_WR_HITCNTS 15 516 #define M_FW_FILTER_WR_HITCNTS 0x1 517 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 518 #define G_FW_FILTER_WR_HITCNTS(x) \ 519 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 520 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 521 522 #define S_FW_FILTER_WR_TXCHAN 13 523 #define M_FW_FILTER_WR_TXCHAN 0x3 524 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 525 #define G_FW_FILTER_WR_TXCHAN(x) \ 526 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 527 528 #define S_FW_FILTER_WR_PRIO 12 529 #define M_FW_FILTER_WR_PRIO 0x1 530 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 531 #define G_FW_FILTER_WR_PRIO(x) \ 532 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 533 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 534 535 #define S_FW_FILTER_WR_L2TIX 0 536 #define M_FW_FILTER_WR_L2TIX 0xfff 537 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 538 #define G_FW_FILTER_WR_L2TIX(x) \ 539 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 540 541 #define S_FW_FILTER_WR_FRAG 7 542 #define M_FW_FILTER_WR_FRAG 0x1 543 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 544 #define G_FW_FILTER_WR_FRAG(x) \ 545 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 546 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 547 548 #define S_FW_FILTER_WR_FRAGM 6 549 #define M_FW_FILTER_WR_FRAGM 0x1 550 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 551 #define G_FW_FILTER_WR_FRAGM(x) \ 552 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 553 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 554 555 #define S_FW_FILTER_WR_IVLAN_VLD 5 556 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 557 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 558 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 559 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 560 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 561 562 #define S_FW_FILTER_WR_OVLAN_VLD 4 563 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 564 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 565 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 566 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 567 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 568 569 #define S_FW_FILTER_WR_IVLAN_VLDM 3 570 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 571 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 572 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 573 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 574 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 575 576 #define S_FW_FILTER_WR_OVLAN_VLDM 2 577 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 578 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 579 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 580 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 581 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 582 583 #define S_FW_FILTER_WR_RX_CHAN 15 584 #define M_FW_FILTER_WR_RX_CHAN 0x1 585 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 586 #define G_FW_FILTER_WR_RX_CHAN(x) \ 587 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 588 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 589 590 #define S_FW_FILTER_WR_RX_RPL_IQ 0 591 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 592 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 593 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 594 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 595 596 #define S_FW_FILTER2_WR_FILTER_TYPE 1 597 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 598 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 599 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 600 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 601 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 602 603 #define S_FW_FILTER2_WR_SWAPMAC 0 604 #define M_FW_FILTER2_WR_SWAPMAC 0x1 605 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 606 #define G_FW_FILTER2_WR_SWAPMAC(x) \ 607 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 608 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 609 610 #define S_FW_FILTER2_WR_NATMODE 5 611 #define M_FW_FILTER2_WR_NATMODE 0x7 612 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 613 #define G_FW_FILTER2_WR_NATMODE(x) \ 614 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 615 616 #define S_FW_FILTER2_WR_NATFLAGCHECK 4 617 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 618 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 619 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 620 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 621 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 622 623 #define S_FW_FILTER2_WR_ULP_TYPE 0 624 #define M_FW_FILTER2_WR_ULP_TYPE 0xf 625 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 626 #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 627 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 628 629 #define S_FW_FILTER_WR_MACI 23 630 #define M_FW_FILTER_WR_MACI 0x1ff 631 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 632 #define G_FW_FILTER_WR_MACI(x) \ 633 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 634 635 #define S_FW_FILTER_WR_MACIM 14 636 #define M_FW_FILTER_WR_MACIM 0x1ff 637 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 638 #define G_FW_FILTER_WR_MACIM(x) \ 639 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 640 641 #define S_FW_FILTER_WR_FCOE 13 642 #define M_FW_FILTER_WR_FCOE 0x1 643 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 644 #define G_FW_FILTER_WR_FCOE(x) \ 645 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 646 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 647 648 #define S_FW_FILTER_WR_FCOEM 12 649 #define M_FW_FILTER_WR_FCOEM 0x1 650 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 651 #define G_FW_FILTER_WR_FCOEM(x) \ 652 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 653 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 654 655 #define S_FW_FILTER_WR_PORT 9 656 #define M_FW_FILTER_WR_PORT 0x7 657 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 658 #define G_FW_FILTER_WR_PORT(x) \ 659 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 660 661 #define S_FW_FILTER_WR_PORTM 6 662 #define M_FW_FILTER_WR_PORTM 0x7 663 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 664 #define G_FW_FILTER_WR_PORTM(x) \ 665 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 666 667 #define S_FW_FILTER_WR_MATCHTYPE 3 668 #define M_FW_FILTER_WR_MATCHTYPE 0x7 669 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 670 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 671 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 672 673 #define S_FW_FILTER_WR_MATCHTYPEM 0 674 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 675 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 676 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 677 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 678 679 struct fw_ulptx_wr { 680 __be32 op_to_compl; 681 __be32 flowid_len16; 682 __u64 cookie; 683 }; 684 685 /* flag for packet type - control packet (0), data packet (1) 686 */ 687 #define S_FW_ULPTX_WR_DATA 28 688 #define M_FW_ULPTX_WR_DATA 0x1 689 #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA) 690 #define G_FW_ULPTX_WR_DATA(x) \ 691 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA) 692 #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U) 693 694 struct fw_tp_wr { 695 __be32 op_to_immdlen; 696 __be32 flowid_len16; 697 __u64 cookie; 698 }; 699 700 struct fw_eth_tx_pkt_wr { 701 __be32 op_immdlen; 702 __be32 equiq_to_len16; 703 __be64 r3; 704 }; 705 706 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 707 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 708 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 709 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 710 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 711 712 struct fw_eth_tx_pkt2_wr { 713 __be32 op_immdlen; 714 __be32 equiq_to_len16; 715 __be32 r3; 716 __be32 L4ChkDisable_to_IpHdrLen; 717 }; 718 719 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 720 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 721 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 722 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 723 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 724 725 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 726 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 727 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 728 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 729 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 730 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 731 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 732 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 733 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 734 735 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 736 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 737 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 738 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 739 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 740 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 741 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 742 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 743 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 744 745 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 746 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 747 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 748 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 749 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 750 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 751 752 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 753 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 754 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 755 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 756 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 757 758 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 759 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 760 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 761 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 762 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 763 764 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 765 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 766 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 767 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 768 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 769 770 struct fw_eth_tx_pkts_wr { 771 __be32 op_pkd; 772 __be32 equiq_to_len16; 773 __be32 r3; 774 __be16 plen; 775 __u8 npkt; 776 __u8 type; 777 }; 778 779 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 780 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 781 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 782 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 783 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 784 785 struct fw_eth_tx_pkt_ptp_wr { 786 __be32 op_immdlen; 787 __be32 equiq_to_len16; 788 __be64 r3; 789 }; 790 791 enum fw_eth_tx_eo_type { 792 FW_ETH_TX_EO_TYPE_UDPSEG, 793 FW_ETH_TX_EO_TYPE_TCPSEG, 794 FW_ETH_TX_EO_TYPE_NVGRESEG, 795 FW_ETH_TX_EO_TYPE_VXLANSEG, 796 FW_ETH_TX_EO_TYPE_GENEVESEG, 797 }; 798 799 struct fw_eth_tx_eo_wr { 800 __be32 op_immdlen; 801 __be32 equiq_to_len16; 802 __be64 r3; 803 union fw_eth_tx_eo { 804 struct fw_eth_tx_eo_udpseg { 805 __u8 type; 806 __u8 ethlen; 807 __be16 iplen; 808 __u8 udplen; 809 __u8 rtplen; 810 __be16 r4; 811 __be16 mss; 812 __be16 schedpktsize; 813 __be32 plen; 814 } udpseg; 815 struct fw_eth_tx_eo_tcpseg { 816 __u8 type; 817 __u8 ethlen; 818 __be16 iplen; 819 __u8 tcplen; 820 __u8 tsclk_tsoff; 821 __be16 r4; 822 __be16 mss; 823 __be16 r5; 824 __be32 plen; 825 } tcpseg; 826 struct fw_eth_tx_eo_nvgreseg { 827 __u8 type; 828 __u8 iphdroffout; 829 __be16 grehdroff; 830 __be16 iphdroffin; 831 __be16 tcphdroffin; 832 __be16 mss; 833 __be16 r4; 834 __be32 plen; 835 } nvgreseg; 836 struct fw_eth_tx_eo_vxlanseg { 837 __u8 type; 838 __u8 iphdroffout; 839 __be16 vxlanhdroff; 840 __be16 iphdroffin; 841 __be16 tcphdroffin; 842 __be16 mss; 843 __be16 r4; 844 __be32 plen; 845 846 } vxlanseg; 847 struct fw_eth_tx_eo_geneveseg { 848 __u8 type; 849 __u8 iphdroffout; 850 __be16 genevehdroff; 851 __be16 iphdroffin; 852 __be16 tcphdroffin; 853 __be16 mss; 854 __be16 r4; 855 __be32 plen; 856 } geneveseg; 857 } u; 858 }; 859 860 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 861 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 862 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 863 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 864 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 865 866 #define S_FW_ETH_TX_EO_WR_TSCLK 6 867 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 868 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 869 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 870 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 871 872 #define S_FW_ETH_TX_EO_WR_TSOFF 0 873 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 874 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 875 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 876 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 877 878 struct fw_eq_flush_wr { 879 __u8 opcode; 880 __u8 r1[3]; 881 __be32 equiq_to_len16; 882 __be64 r3; 883 }; 884 885 struct fw_ofld_connection_wr { 886 __be32 op_compl; 887 __be32 len16_pkd; 888 __u64 cookie; 889 __be64 r2; 890 __be64 r3; 891 struct fw_ofld_connection_le { 892 __be32 version_cpl; 893 __be32 filter; 894 __be32 r1; 895 __be16 lport; 896 __be16 pport; 897 union fw_ofld_connection_leip { 898 struct fw_ofld_connection_le_ipv4 { 899 __be32 pip; 900 __be32 lip; 901 __be64 r0; 902 __be64 r1; 903 __be64 r2; 904 } ipv4; 905 struct fw_ofld_connection_le_ipv6 { 906 __be64 pip_hi; 907 __be64 pip_lo; 908 __be64 lip_hi; 909 __be64 lip_lo; 910 } ipv6; 911 } u; 912 } le; 913 struct fw_ofld_connection_tcb { 914 __be32 t_state_to_astid; 915 __be16 cplrxdataack_cplpassacceptrpl; 916 __be16 rcv_adv; 917 __be32 rcv_nxt; 918 __be32 tx_max; 919 __be64 opt0; 920 __be32 opt2; 921 __be32 r1; 922 __be64 r2; 923 __be64 r3; 924 } tcb; 925 }; 926 927 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 928 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 929 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 930 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 931 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 932 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 933 M_FW_OFLD_CONNECTION_WR_VERSION) 934 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 935 936 #define S_FW_OFLD_CONNECTION_WR_CPL 30 937 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 938 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 939 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 940 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 941 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 942 943 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 944 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 945 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 946 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 947 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 948 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 949 M_FW_OFLD_CONNECTION_WR_T_STATE) 950 951 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 952 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 953 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 954 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 955 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 956 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 957 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 958 959 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 960 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 961 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 962 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 963 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 964 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 965 966 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 967 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 968 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 969 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 970 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 971 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 972 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 973 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 974 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 975 976 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 977 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 978 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 979 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 980 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 981 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 982 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 983 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 984 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 985 986 enum fw_flowc_mnem_tcpstate { 987 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 988 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 989 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 990 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 991 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 992 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 993 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 994 * will resend FIN - equiv ESTAB 995 */ 996 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 997 * will resend FIN but have 998 * received FIN 999 */ 1000 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 1001 * will resend FIN but have 1002 * received FIN 1003 */ 1004 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 1005 * waiting for FIN 1006 */ 1007 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 1008 }; 1009 1010 enum fw_flowc_mnem_eostate { 1011 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 1012 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 1013 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 1014 * outstanding payload 1015 */ 1016 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 1017 * discarding outstanding payload 1018 */ 1019 }; 1020 1021 enum fw_flowc_mnem { 1022 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1023 FW_FLOWC_MNEM_CH = 1, 1024 FW_FLOWC_MNEM_PORT = 2, 1025 FW_FLOWC_MNEM_IQID = 3, 1026 FW_FLOWC_MNEM_SNDNXT = 4, 1027 FW_FLOWC_MNEM_RCVNXT = 5, 1028 FW_FLOWC_MNEM_SNDBUF = 6, 1029 FW_FLOWC_MNEM_MSS = 7, 1030 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1031 FW_FLOWC_MNEM_TCPSTATE = 9, 1032 FW_FLOWC_MNEM_EOSTATE = 10, 1033 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1034 FW_FLOWC_MNEM_DCBPRIO = 12, 1035 FW_FLOWC_MNEM_SND_SCALE = 13, 1036 FW_FLOWC_MNEM_RCV_SCALE = 14, 1037 FW_FLOWC_MNEM_ULP_MODE = 15, 1038 FW_FLOWC_MNEM_MAX = 16, 1039 }; 1040 1041 struct fw_flowc_mnemval { 1042 __u8 mnemonic; 1043 __u8 r4[3]; 1044 __be32 val; 1045 }; 1046 1047 struct fw_flowc_wr { 1048 __be32 op_to_nparams; 1049 __be32 flowid_len16; 1050 #ifndef C99_NOT_SUPPORTED 1051 struct fw_flowc_mnemval mnemval[0]; 1052 #endif 1053 }; 1054 1055 #define S_FW_FLOWC_WR_NPARAMS 0 1056 #define M_FW_FLOWC_WR_NPARAMS 0xff 1057 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1058 #define G_FW_FLOWC_WR_NPARAMS(x) \ 1059 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1060 1061 struct fw_ofld_tx_data_wr { 1062 __be32 op_to_immdlen; 1063 __be32 flowid_len16; 1064 __be32 plen; 1065 __be32 lsodisable_to_flags; 1066 }; 1067 1068 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1069 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1070 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1071 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1072 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1073 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1074 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1075 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1076 1077 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1078 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1079 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1080 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1081 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1082 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1083 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1084 1085 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1086 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1087 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1088 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1089 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1090 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1091 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1092 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1093 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1094 1095 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1096 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1097 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1098 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1099 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1100 1101 1102 /* Use fw_ofld_tx_data_wr structure */ 1103 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1104 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1105 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1106 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1107 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1108 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1109 1110 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1111 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1112 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1113 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1114 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1115 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1116 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1117 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1118 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1119 1120 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1121 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1122 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1123 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1124 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1125 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1126 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1127 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1128 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1129 1130 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1131 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1132 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1133 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1134 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1135 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1136 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1137 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1138 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1139 1140 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1141 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1142 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1143 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1144 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1145 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1146 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1147 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1148 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1149 1150 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1151 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1152 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1153 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1154 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1155 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1156 1157 struct fw_cmd_wr { 1158 __be32 op_dma; 1159 __be32 len16_pkd; 1160 __be64 cookie_daddr; 1161 }; 1162 1163 #define S_FW_CMD_WR_DMA 17 1164 #define M_FW_CMD_WR_DMA 0x1 1165 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1166 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1167 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1168 1169 struct fw_eth_tx_pkt_vm_wr { 1170 __be32 op_immdlen; 1171 __be32 equiq_to_len16; 1172 __be32 r3[2]; 1173 __u8 ethmacdst[6]; 1174 __u8 ethmacsrc[6]; 1175 __be16 ethtype; 1176 __be16 vlantci; 1177 }; 1178 1179 struct fw_eth_tx_pkts_vm_wr { 1180 __be32 op_pkd; 1181 __be32 equiq_to_len16; 1182 __be32 r3; 1183 __be16 plen; 1184 __u8 npkt; 1185 __u8 r4; 1186 __u8 ethmacdst[6]; 1187 __u8 ethmacsrc[6]; 1188 __be16 ethtype; 1189 __be16 vlantci; 1190 }; 1191 1192 /****************************************************************************** 1193 * R I W O R K R E Q U E S T s 1194 **************************************/ 1195 1196 enum fw_ri_wr_opcode { 1197 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1198 FW_RI_READ_REQ = 0x1, 1199 FW_RI_READ_RESP = 0x2, 1200 FW_RI_SEND = 0x3, 1201 FW_RI_SEND_WITH_INV = 0x4, 1202 FW_RI_SEND_WITH_SE = 0x5, 1203 FW_RI_SEND_WITH_SE_INV = 0x6, 1204 FW_RI_TERMINATE = 0x7, 1205 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1206 FW_RI_BIND_MW = 0x9, 1207 FW_RI_FAST_REGISTER = 0xa, 1208 FW_RI_LOCAL_INV = 0xb, 1209 FW_RI_QP_MODIFY = 0xc, 1210 FW_RI_BYPASS = 0xd, 1211 FW_RI_RECEIVE = 0xe, 1212 #if 0 1213 FW_RI_SEND_IMMEDIATE = 0x8, 1214 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1215 FW_RI_ATOMIC_REQUEST = 0xa, 1216 FW_RI_ATOMIC_RESPONSE = 0xb, 1217 1218 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1219 FW_RI_FAST_REGISTER = 0xd, 1220 FW_RI_LOCAL_INV = 0xe, 1221 #endif 1222 FW_RI_SGE_EC_CR_RETURN = 0xf, 1223 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 1224 }; 1225 1226 enum fw_ri_wr_flags { 1227 FW_RI_COMPLETION_FLAG = 0x01, 1228 FW_RI_NOTIFICATION_FLAG = 0x02, 1229 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1230 FW_RI_READ_FENCE_FLAG = 0x08, 1231 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1232 FW_RI_RDMA_READ_INVALIDATE = 0x20, 1233 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40 1234 }; 1235 1236 enum fw_ri_mpa_attrs { 1237 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1238 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1239 FW_RI_MPA_CRC_ENABLE = 0x04, 1240 FW_RI_MPA_IETF_ENABLE = 0x08 1241 }; 1242 1243 enum fw_ri_qp_caps { 1244 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1245 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1246 FW_RI_QP_BIND_ENABLE = 0x04, 1247 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1248 FW_RI_QP_STAG0_ENABLE = 0x10, 1249 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1250 }; 1251 1252 enum fw_ri_addr_type { 1253 FW_RI_ZERO_BASED_TO = 0x00, 1254 FW_RI_VA_BASED_TO = 0x01 1255 }; 1256 1257 enum fw_ri_mem_perms { 1258 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1259 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1260 FW_RI_MEM_ACCESS_REM = 0x03, 1261 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1262 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1263 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1264 }; 1265 1266 enum fw_ri_stag_type { 1267 FW_RI_STAG_NSMR = 0x00, 1268 FW_RI_STAG_SMR = 0x01, 1269 FW_RI_STAG_MW = 0x02, 1270 FW_RI_STAG_MW_RELAXED = 0x03 1271 }; 1272 1273 enum fw_ri_data_op { 1274 FW_RI_DATA_IMMD = 0x81, 1275 FW_RI_DATA_DSGL = 0x82, 1276 FW_RI_DATA_ISGL = 0x83 1277 }; 1278 1279 enum fw_ri_sgl_depth { 1280 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1281 FW_RI_SGL_DEPTH_MAX_RQ = 4 1282 }; 1283 1284 enum fw_ri_cqe_err { 1285 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1286 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1287 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1288 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1289 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1290 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1291 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1292 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1293 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1294 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1295 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1296 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1297 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1298 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1299 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1300 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1301 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1302 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1303 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1304 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1305 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1306 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1307 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1308 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1309 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1310 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1311 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1312 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1313 1314 }; 1315 1316 struct fw_ri_dsge_pair { 1317 __be32 len[2]; 1318 __be64 addr[2]; 1319 }; 1320 1321 struct fw_ri_dsgl { 1322 __u8 op; 1323 __u8 r1; 1324 __be16 nsge; 1325 __be32 len0; 1326 __be64 addr0; 1327 #ifndef C99_NOT_SUPPORTED 1328 struct fw_ri_dsge_pair sge[0]; 1329 #endif 1330 }; 1331 1332 struct fw_ri_sge { 1333 __be32 stag; 1334 __be32 len; 1335 __be64 to; 1336 }; 1337 1338 struct fw_ri_isgl { 1339 __u8 op; 1340 __u8 r1; 1341 __be16 nsge; 1342 __be32 r2; 1343 #ifndef C99_NOT_SUPPORTED 1344 struct fw_ri_sge sge[0]; 1345 #endif 1346 }; 1347 1348 struct fw_ri_immd { 1349 __u8 op; 1350 __u8 r1; 1351 __be16 r2; 1352 __be32 immdlen; 1353 #ifndef C99_NOT_SUPPORTED 1354 __u8 data[0]; 1355 #endif 1356 }; 1357 1358 struct fw_ri_tpte { 1359 __be32 valid_to_pdid; 1360 __be32 locread_to_qpid; 1361 __be32 nosnoop_pbladdr; 1362 __be32 len_lo; 1363 __be32 va_hi; 1364 __be32 va_lo_fbo; 1365 __be32 dca_mwbcnt_pstag; 1366 __be32 len_hi; 1367 }; 1368 1369 #define S_FW_RI_TPTE_VALID 31 1370 #define M_FW_RI_TPTE_VALID 0x1 1371 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1372 #define G_FW_RI_TPTE_VALID(x) \ 1373 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1374 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1375 1376 #define S_FW_RI_TPTE_STAGKEY 23 1377 #define M_FW_RI_TPTE_STAGKEY 0xff 1378 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1379 #define G_FW_RI_TPTE_STAGKEY(x) \ 1380 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1381 1382 #define S_FW_RI_TPTE_STAGSTATE 22 1383 #define M_FW_RI_TPTE_STAGSTATE 0x1 1384 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1385 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1386 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1387 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1388 1389 #define S_FW_RI_TPTE_STAGTYPE 20 1390 #define M_FW_RI_TPTE_STAGTYPE 0x3 1391 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1392 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1393 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1394 1395 #define S_FW_RI_TPTE_PDID 0 1396 #define M_FW_RI_TPTE_PDID 0xfffff 1397 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1398 #define G_FW_RI_TPTE_PDID(x) \ 1399 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1400 1401 #define S_FW_RI_TPTE_PERM 28 1402 #define M_FW_RI_TPTE_PERM 0xf 1403 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1404 #define G_FW_RI_TPTE_PERM(x) \ 1405 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1406 1407 #define S_FW_RI_TPTE_REMINVDIS 27 1408 #define M_FW_RI_TPTE_REMINVDIS 0x1 1409 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1410 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1411 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1412 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1413 1414 #define S_FW_RI_TPTE_ADDRTYPE 26 1415 #define M_FW_RI_TPTE_ADDRTYPE 1 1416 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1417 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1418 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1419 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1420 1421 #define S_FW_RI_TPTE_MWBINDEN 25 1422 #define M_FW_RI_TPTE_MWBINDEN 0x1 1423 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1424 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1425 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1426 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1427 1428 #define S_FW_RI_TPTE_PS 20 1429 #define M_FW_RI_TPTE_PS 0x1f 1430 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1431 #define G_FW_RI_TPTE_PS(x) \ 1432 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1433 1434 #define S_FW_RI_TPTE_QPID 0 1435 #define M_FW_RI_TPTE_QPID 0xfffff 1436 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1437 #define G_FW_RI_TPTE_QPID(x) \ 1438 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1439 1440 #define S_FW_RI_TPTE_NOSNOOP 31 1441 #define M_FW_RI_TPTE_NOSNOOP 0x1 1442 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1443 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1444 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1445 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1446 1447 #define S_FW_RI_TPTE_PBLADDR 0 1448 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1449 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1450 #define G_FW_RI_TPTE_PBLADDR(x) \ 1451 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1452 1453 #define S_FW_RI_TPTE_DCA 24 1454 #define M_FW_RI_TPTE_DCA 0x1f 1455 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1456 #define G_FW_RI_TPTE_DCA(x) \ 1457 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1458 1459 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1460 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1461 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1462 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1463 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1464 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1465 1466 enum fw_ri_cqe_rxtx { 1467 FW_RI_CQE_RXTX_RX = 0x0, 1468 FW_RI_CQE_RXTX_TX = 0x1, 1469 }; 1470 1471 struct fw_ri_cqe { 1472 union fw_ri_rxtx { 1473 struct fw_ri_scqe { 1474 __be32 qpid_n_stat_rxtx_type; 1475 __be32 plen; 1476 __be32 stag; 1477 __be32 wrid; 1478 } scqe; 1479 struct fw_ri_rcqe { 1480 __be32 qpid_n_stat_rxtx_type; 1481 __be32 plen; 1482 __be32 stag; 1483 __be32 msn; 1484 } rcqe; 1485 struct fw_ri_rcqe_imm { 1486 __be32 qpid_n_stat_rxtx_type; 1487 __be32 plen; 1488 __be32 mo; 1489 __be32 msn; 1490 __u64 imm_data; 1491 } imm_data_rcqe; 1492 } u; 1493 }; 1494 1495 #define S_FW_RI_CQE_QPID 12 1496 #define M_FW_RI_CQE_QPID 0xfffff 1497 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1498 #define G_FW_RI_CQE_QPID(x) \ 1499 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1500 1501 #define S_FW_RI_CQE_NOTIFY 10 1502 #define M_FW_RI_CQE_NOTIFY 0x1 1503 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1504 #define G_FW_RI_CQE_NOTIFY(x) \ 1505 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1506 1507 #define S_FW_RI_CQE_STATUS 5 1508 #define M_FW_RI_CQE_STATUS 0x1f 1509 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1510 #define G_FW_RI_CQE_STATUS(x) \ 1511 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1512 1513 1514 #define S_FW_RI_CQE_RXTX 4 1515 #define M_FW_RI_CQE_RXTX 0x1 1516 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1517 #define G_FW_RI_CQE_RXTX(x) \ 1518 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1519 1520 #define S_FW_RI_CQE_TYPE 0 1521 #define M_FW_RI_CQE_TYPE 0xf 1522 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1523 #define G_FW_RI_CQE_TYPE(x) \ 1524 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1525 1526 enum fw_ri_res_type { 1527 FW_RI_RES_TYPE_SQ, 1528 FW_RI_RES_TYPE_RQ, 1529 FW_RI_RES_TYPE_CQ, 1530 FW_RI_RES_TYPE_SRQ, 1531 }; 1532 1533 enum fw_ri_res_op { 1534 FW_RI_RES_OP_WRITE, 1535 FW_RI_RES_OP_RESET, 1536 }; 1537 1538 struct fw_ri_res { 1539 union fw_ri_restype { 1540 struct fw_ri_res_sqrq { 1541 __u8 restype; 1542 __u8 op; 1543 __be16 r3; 1544 __be32 eqid; 1545 __be32 r4[2]; 1546 __be32 fetchszm_to_iqid; 1547 __be32 dcaen_to_eqsize; 1548 __be64 eqaddr; 1549 } sqrq; 1550 struct fw_ri_res_cq { 1551 __u8 restype; 1552 __u8 op; 1553 __be16 r3; 1554 __be32 iqid; 1555 __be32 r4[2]; 1556 __be32 iqandst_to_iqandstindex; 1557 __be16 iqdroprss_to_iqesize; 1558 __be16 iqsize; 1559 __be64 iqaddr; 1560 __be32 iqns_iqro; 1561 __be32 r6_lo; 1562 __be64 r7; 1563 } cq; 1564 struct fw_ri_res_srq { 1565 __u8 restype; 1566 __u8 op; 1567 __be16 r3; 1568 __be32 eqid; 1569 __be32 r4[2]; 1570 __be32 fetchszm_to_iqid; 1571 __be32 dcaen_to_eqsize; 1572 __be64 eqaddr; 1573 __be32 srqid; 1574 __be32 pdid; 1575 __be32 hwsrqsize; 1576 __be32 hwsrqaddr; 1577 } srq; 1578 } u; 1579 }; 1580 1581 struct fw_ri_res_wr { 1582 __be32 op_nres; 1583 __be32 len16_pkd; 1584 __u64 cookie; 1585 #ifndef C99_NOT_SUPPORTED 1586 struct fw_ri_res res[0]; 1587 #endif 1588 }; 1589 1590 #define S_FW_RI_RES_WR_VFN 8 1591 #define M_FW_RI_RES_WR_VFN 0xff 1592 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1593 #define G_FW_RI_RES_WR_VFN(x) \ 1594 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1595 1596 #define S_FW_RI_RES_WR_NRES 0 1597 #define M_FW_RI_RES_WR_NRES 0xff 1598 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1599 #define G_FW_RI_RES_WR_NRES(x) \ 1600 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1601 1602 #define S_FW_RI_RES_WR_FETCHSZM 26 1603 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1604 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1605 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1606 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1607 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1608 1609 #define S_FW_RI_RES_WR_STATUSPGNS 25 1610 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1611 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1612 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1613 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1614 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1615 1616 #define S_FW_RI_RES_WR_STATUSPGRO 24 1617 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1618 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1619 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1620 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1621 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1622 1623 #define S_FW_RI_RES_WR_FETCHNS 23 1624 #define M_FW_RI_RES_WR_FETCHNS 0x1 1625 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1626 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1627 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1628 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1629 1630 #define S_FW_RI_RES_WR_FETCHRO 22 1631 #define M_FW_RI_RES_WR_FETCHRO 0x1 1632 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1633 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1634 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1635 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1636 1637 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1638 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1639 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1640 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1641 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1642 1643 #define S_FW_RI_RES_WR_CPRIO 19 1644 #define M_FW_RI_RES_WR_CPRIO 0x1 1645 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1646 #define G_FW_RI_RES_WR_CPRIO(x) \ 1647 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1648 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1649 1650 #define S_FW_RI_RES_WR_ONCHIP 18 1651 #define M_FW_RI_RES_WR_ONCHIP 0x1 1652 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1653 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1654 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1655 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1656 1657 #define S_FW_RI_RES_WR_PCIECHN 16 1658 #define M_FW_RI_RES_WR_PCIECHN 0x3 1659 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1660 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1661 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1662 1663 #define S_FW_RI_RES_WR_IQID 0 1664 #define M_FW_RI_RES_WR_IQID 0xffff 1665 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1666 #define G_FW_RI_RES_WR_IQID(x) \ 1667 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1668 1669 #define S_FW_RI_RES_WR_DCAEN 31 1670 #define M_FW_RI_RES_WR_DCAEN 0x1 1671 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1672 #define G_FW_RI_RES_WR_DCAEN(x) \ 1673 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1674 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1675 1676 #define S_FW_RI_RES_WR_DCACPU 26 1677 #define M_FW_RI_RES_WR_DCACPU 0x1f 1678 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1679 #define G_FW_RI_RES_WR_DCACPU(x) \ 1680 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1681 1682 #define S_FW_RI_RES_WR_FBMIN 23 1683 #define M_FW_RI_RES_WR_FBMIN 0x7 1684 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1685 #define G_FW_RI_RES_WR_FBMIN(x) \ 1686 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1687 1688 #define S_FW_RI_RES_WR_FBMAX 20 1689 #define M_FW_RI_RES_WR_FBMAX 0x7 1690 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1691 #define G_FW_RI_RES_WR_FBMAX(x) \ 1692 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1693 1694 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1695 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1696 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1697 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1698 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1699 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1700 1701 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1702 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1703 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1704 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1705 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1706 1707 #define S_FW_RI_RES_WR_EQSIZE 0 1708 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1709 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1710 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1711 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1712 1713 #define S_FW_RI_RES_WR_IQANDST 15 1714 #define M_FW_RI_RES_WR_IQANDST 0x1 1715 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1716 #define G_FW_RI_RES_WR_IQANDST(x) \ 1717 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1718 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1719 1720 #define S_FW_RI_RES_WR_IQANUS 14 1721 #define M_FW_RI_RES_WR_IQANUS 0x1 1722 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1723 #define G_FW_RI_RES_WR_IQANUS(x) \ 1724 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1725 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1726 1727 #define S_FW_RI_RES_WR_IQANUD 12 1728 #define M_FW_RI_RES_WR_IQANUD 0x3 1729 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1730 #define G_FW_RI_RES_WR_IQANUD(x) \ 1731 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1732 1733 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1734 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1735 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1736 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1737 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1738 1739 #define S_FW_RI_RES_WR_IQDROPRSS 15 1740 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1741 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1742 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1743 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1744 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1745 1746 #define S_FW_RI_RES_WR_IQGTSMODE 14 1747 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1748 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1749 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1750 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1751 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1752 1753 #define S_FW_RI_RES_WR_IQPCIECH 12 1754 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1755 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1756 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1757 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1758 1759 #define S_FW_RI_RES_WR_IQDCAEN 11 1760 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1761 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1762 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1763 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1764 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1765 1766 #define S_FW_RI_RES_WR_IQDCACPU 6 1767 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1768 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1769 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1770 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1771 1772 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1773 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1774 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1775 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1776 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1777 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1778 1779 #define S_FW_RI_RES_WR_IQO 3 1780 #define M_FW_RI_RES_WR_IQO 0x1 1781 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1782 #define G_FW_RI_RES_WR_IQO(x) \ 1783 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1784 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1785 1786 #define S_FW_RI_RES_WR_IQCPRIO 2 1787 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1788 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1789 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1790 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1791 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1792 1793 #define S_FW_RI_RES_WR_IQESIZE 0 1794 #define M_FW_RI_RES_WR_IQESIZE 0x3 1795 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1796 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1797 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1798 1799 #define S_FW_RI_RES_WR_IQNS 31 1800 #define M_FW_RI_RES_WR_IQNS 0x1 1801 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1802 #define G_FW_RI_RES_WR_IQNS(x) \ 1803 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1804 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1805 1806 #define S_FW_RI_RES_WR_IQRO 30 1807 #define M_FW_RI_RES_WR_IQRO 0x1 1808 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1809 #define G_FW_RI_RES_WR_IQRO(x) \ 1810 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1811 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1812 1813 struct fw_ri_rdma_write_wr { 1814 __u8 opcode; 1815 __u8 flags; 1816 __u16 wrid; 1817 __u8 r1[3]; 1818 __u8 len16; 1819 __u64 immd_data; 1820 __be32 plen; 1821 __be32 stag_sink; 1822 __be64 to_sink; 1823 #ifndef C99_NOT_SUPPORTED 1824 union { 1825 struct fw_ri_immd immd_src[0]; 1826 struct fw_ri_isgl isgl_src[0]; 1827 } u; 1828 #endif 1829 }; 1830 1831 struct fw_ri_send_wr { 1832 __u8 opcode; 1833 __u8 flags; 1834 __u16 wrid; 1835 __u8 r1[3]; 1836 __u8 len16; 1837 __be32 sendop_pkd; 1838 __be32 stag_inv; 1839 __be32 plen; 1840 __be32 r3; 1841 __be64 r4; 1842 #ifndef C99_NOT_SUPPORTED 1843 union { 1844 struct fw_ri_immd immd_src[0]; 1845 struct fw_ri_isgl isgl_src[0]; 1846 } u; 1847 #endif 1848 }; 1849 1850 #define S_FW_RI_SEND_WR_SENDOP 0 1851 #define M_FW_RI_SEND_WR_SENDOP 0xf 1852 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1853 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1854 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1855 1856 struct fw_ri_rdma_write_cmpl_wr { 1857 __u8 opcode; 1858 __u8 flags; 1859 __u16 wrid; 1860 __u8 r1[3]; 1861 __u8 len16; 1862 __u8 r2; 1863 __u8 flags_send; 1864 __u16 wrid_send; 1865 __be32 stag_inv; 1866 __be32 plen; 1867 __be32 stag_sink; 1868 __be64 to_sink; 1869 union fw_ri_cmpl { 1870 struct fw_ri_immd_cmpl { 1871 __u8 op; 1872 __u8 r1[6]; 1873 __u8 immdlen; 1874 __u8 data[16]; 1875 } immd_src; 1876 struct fw_ri_isgl isgl_src; 1877 } u_cmpl; 1878 __be64 r3; 1879 #ifndef C99_NOT_SUPPORTED 1880 union fw_ri_write { 1881 struct fw_ri_immd immd_src[0]; 1882 struct fw_ri_isgl isgl_src[0]; 1883 } u; 1884 #endif 1885 }; 1886 1887 struct fw_ri_rdma_read_wr { 1888 __u8 opcode; 1889 __u8 flags; 1890 __u16 wrid; 1891 __u8 r1[3]; 1892 __u8 len16; 1893 __be64 r2; 1894 __be32 stag_sink; 1895 __be32 to_sink_hi; 1896 __be32 to_sink_lo; 1897 __be32 plen; 1898 __be32 stag_src; 1899 __be32 to_src_hi; 1900 __be32 to_src_lo; 1901 __be32 r5; 1902 }; 1903 1904 struct fw_ri_recv_wr { 1905 __u8 opcode; 1906 __u8 r1; 1907 __u16 wrid; 1908 __u8 r2[3]; 1909 __u8 len16; 1910 struct fw_ri_isgl isgl; 1911 }; 1912 1913 struct fw_ri_bind_mw_wr { 1914 __u8 opcode; 1915 __u8 flags; 1916 __u16 wrid; 1917 __u8 r1[3]; 1918 __u8 len16; 1919 __u8 qpbinde_to_dcacpu; 1920 __u8 pgsz_shift; 1921 __u8 addr_type; 1922 __u8 mem_perms; 1923 __be32 stag_mr; 1924 __be32 stag_mw; 1925 __be32 r3; 1926 __be64 len_mw; 1927 __be64 va_fbo; 1928 __be64 r4; 1929 }; 1930 1931 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1932 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1933 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1934 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1935 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1936 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1937 1938 #define S_FW_RI_BIND_MW_WR_NS 5 1939 #define M_FW_RI_BIND_MW_WR_NS 0x1 1940 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1941 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1942 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1943 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1944 1945 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1946 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1947 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1948 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1949 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1950 1951 struct fw_ri_fr_nsmr_wr { 1952 __u8 opcode; 1953 __u8 flags; 1954 __u16 wrid; 1955 __u8 r1[3]; 1956 __u8 len16; 1957 __u8 qpbinde_to_dcacpu; 1958 __u8 pgsz_shift; 1959 __u8 addr_type; 1960 __u8 mem_perms; 1961 __be32 stag; 1962 __be32 len_hi; 1963 __be32 len_lo; 1964 __be32 va_hi; 1965 __be32 va_lo_fbo; 1966 }; 1967 1968 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1969 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1970 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1971 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1972 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1973 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1974 1975 #define S_FW_RI_FR_NSMR_WR_NS 5 1976 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1977 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1978 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1979 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1980 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1981 1982 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1983 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1984 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1985 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1986 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1987 1988 struct fw_ri_fr_nsmr_tpte_wr { 1989 __u8 opcode; 1990 __u8 flags; 1991 __u16 wrid; 1992 __u8 r1[3]; 1993 __u8 len16; 1994 __be32 r2; 1995 __be32 stag; 1996 struct fw_ri_tpte tpte; 1997 __be64 pbl[2]; 1998 }; 1999 2000 struct fw_ri_inv_lstag_wr { 2001 __u8 opcode; 2002 __u8 flags; 2003 __u16 wrid; 2004 __u8 r1[3]; 2005 __u8 len16; 2006 __be32 r2; 2007 __be32 stag_inv; 2008 }; 2009 2010 struct fw_ri_send_immediate_wr { 2011 __u8 opcode; 2012 __u8 flags; 2013 __u16 wrid; 2014 __u8 r1[3]; 2015 __u8 len16; 2016 __be32 sendimmop_pkd; 2017 __be32 r3; 2018 __be32 plen; 2019 __be32 r4; 2020 __be64 r5; 2021 #ifndef C99_NOT_SUPPORTED 2022 struct fw_ri_immd immd_src[0]; 2023 #endif 2024 }; 2025 2026 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 2027 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 2028 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2029 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2030 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2031 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 2032 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2033 2034 enum fw_ri_atomic_op { 2035 FW_RI_ATOMIC_OP_FETCHADD, 2036 FW_RI_ATOMIC_OP_SWAP, 2037 FW_RI_ATOMIC_OP_CMDSWAP, 2038 }; 2039 2040 struct fw_ri_atomic_wr { 2041 __u8 opcode; 2042 __u8 flags; 2043 __u16 wrid; 2044 __u8 r1[3]; 2045 __u8 len16; 2046 __be32 atomicop_pkd; 2047 __be64 r3; 2048 __be32 aopcode_pkd; 2049 __be32 reqid; 2050 __be32 stag; 2051 __be32 to_hi; 2052 __be32 to_lo; 2053 __be32 addswap_data_hi; 2054 __be32 addswap_data_lo; 2055 __be32 addswap_mask_hi; 2056 __be32 addswap_mask_lo; 2057 __be32 compare_data_hi; 2058 __be32 compare_data_lo; 2059 __be32 compare_mask_hi; 2060 __be32 compare_mask_lo; 2061 __be32 r5; 2062 }; 2063 2064 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 2065 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 2066 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 2067 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 2068 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2069 2070 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 2071 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2072 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2073 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2074 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2075 2076 enum fw_ri_type { 2077 FW_RI_TYPE_INIT, 2078 FW_RI_TYPE_FINI, 2079 FW_RI_TYPE_TERMINATE 2080 }; 2081 2082 enum fw_ri_init_p2ptype { 2083 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2084 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2085 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2086 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2087 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2088 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2089 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2090 }; 2091 2092 enum fw_ri_init_rqeqid_srq { 2093 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 2094 }; 2095 2096 struct fw_ri_wr { 2097 __be32 op_compl; 2098 __be32 flowid_len16; 2099 __u64 cookie; 2100 union fw_ri { 2101 struct fw_ri_init { 2102 __u8 type; 2103 __u8 mpareqbit_p2ptype; 2104 __u8 r4[2]; 2105 __u8 mpa_attrs; 2106 __u8 qp_caps; 2107 __be16 nrqe; 2108 __be32 pdid; 2109 __be32 qpid; 2110 __be32 sq_eqid; 2111 __be32 rq_eqid; 2112 __be32 scqid; 2113 __be32 rcqid; 2114 __be32 ord_max; 2115 __be32 ird_max; 2116 __be32 iss; 2117 __be32 irs; 2118 __be32 hwrqsize; 2119 __be32 hwrqaddr; 2120 __be64 r5; 2121 union fw_ri_init_p2p { 2122 struct fw_ri_rdma_write_wr write; 2123 struct fw_ri_rdma_read_wr read; 2124 struct fw_ri_send_wr send; 2125 } u; 2126 } init; 2127 struct fw_ri_fini { 2128 __u8 type; 2129 __u8 r3[7]; 2130 __be64 r4; 2131 } fini; 2132 struct fw_ri_terminate { 2133 __u8 type; 2134 __u8 r3[3]; 2135 __be32 immdlen; 2136 __u8 termmsg[40]; 2137 } terminate; 2138 } u; 2139 }; 2140 2141 #define S_FW_RI_WR_MPAREQBIT 7 2142 #define M_FW_RI_WR_MPAREQBIT 0x1 2143 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2144 #define G_FW_RI_WR_MPAREQBIT(x) \ 2145 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2146 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2147 2148 #define S_FW_RI_WR_0BRRBIT 6 2149 #define M_FW_RI_WR_0BRRBIT 0x1 2150 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2151 #define G_FW_RI_WR_0BRRBIT(x) \ 2152 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2153 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2154 2155 #define S_FW_RI_WR_P2PTYPE 0 2156 #define M_FW_RI_WR_P2PTYPE 0xf 2157 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2158 #define G_FW_RI_WR_P2PTYPE(x) \ 2159 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2160 2161 /****************************************************************************** 2162 * F O i S C S I W O R K R E Q U E S T s 2163 *********************************************/ 2164 2165 #define FW_FOISCSI_NAME_MAX_LEN 224 2166 #define FW_FOISCSI_ALIAS_MAX_LEN 224 2167 #define FW_FOISCSI_KEY_MAX_LEN 64 2168 #define FW_FOISCSI_VAL_MAX_LEN 256 2169 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 2170 #define FW_FOISCSI_INIT_NODE_MAX 8 2171 2172 enum fw_chnet_ifconf_wr_subop { 2173 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 2174 2175 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 2176 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 2177 2178 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 2179 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 2180 2181 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 2182 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 2183 2184 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 2185 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 2186 2187 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 2188 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 2189 2190 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 2191 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 2192 2193 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2194 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2195 2196 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2197 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2198 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2199 2200 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4, 2201 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6, 2202 2203 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2204 }; 2205 2206 struct fw_chnet_ifconf_wr { 2207 __be32 op_compl; 2208 __be32 flowid_len16; 2209 __u64 cookie; 2210 __be32 if_flowid; 2211 __u8 idx; 2212 __u8 subop; 2213 __u8 retval; 2214 __u8 r2; 2215 union { 2216 __be64 r3; 2217 struct fw_chnet_ifconf_ping { 2218 __be16 ping_time; 2219 __u8 ping_rsptype; 2220 __u8 ping_param_rspcode_to_fin_bit; 2221 __u8 ping_pktsize; 2222 __u8 ping_ttl; 2223 __be16 ping_seq; 2224 } ping; 2225 struct fw_chnet_ifconf_mac { 2226 __u8 peer_mac[6]; 2227 __u8 smac_idx; 2228 } mac; 2229 } u; 2230 struct fw_chnet_ifconf_params { 2231 __be32 r0; 2232 __be16 vlanid; 2233 __be16 mtu; 2234 union fw_chnet_ifconf_addr_type { 2235 struct fw_chnet_ifconf_ipv4 { 2236 __be32 addr; 2237 __be32 mask; 2238 __be32 router; 2239 __be32 r0; 2240 __be64 r1; 2241 } ipv4; 2242 struct fw_chnet_ifconf_ipv6 { 2243 __u8 prefix_len; 2244 __u8 r0; 2245 __be16 r1; 2246 __be32 r2; 2247 __be64 addr_hi; 2248 __be64 addr_lo; 2249 __be64 router_hi; 2250 __be64 router_lo; 2251 } ipv6; 2252 } in_attr; 2253 } param; 2254 }; 2255 2256 #define S_FW_CHNET_IFCONF_WR_PING_MACBIT 1 2257 #define M_FW_CHNET_IFCONF_WR_PING_MACBIT 0x1 2258 #define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 2259 ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT) 2260 #define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 2261 (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \ 2262 M_FW_CHNET_IFCONF_WR_PING_MACBIT) 2263 #define F_FW_CHNET_IFCONF_WR_PING_MACBIT \ 2264 V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U) 2265 2266 #define S_FW_CHNET_IFCONF_WR_FIN_BIT 0 2267 #define M_FW_CHNET_IFCONF_WR_FIN_BIT 0x1 2268 #define V_FW_CHNET_IFCONF_WR_FIN_BIT(x) ((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT) 2269 #define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \ 2270 (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT) 2271 #define F_FW_CHNET_IFCONF_WR_FIN_BIT V_FW_CHNET_IFCONF_WR_FIN_BIT(1U) 2272 2273 enum fw_foiscsi_node_type { 2274 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2275 FW_FOISCSI_NODE_TYPE_TARGET, 2276 }; 2277 2278 enum fw_foiscsi_session_type { 2279 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2280 FW_FOISCSI_SESSION_TYPE_NORMAL, 2281 }; 2282 2283 enum fw_foiscsi_auth_policy { 2284 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2285 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2286 }; 2287 2288 enum fw_foiscsi_auth_method { 2289 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2290 FW_FOISCSI_AUTH_METHOD_CHAP, 2291 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2292 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2293 }; 2294 2295 enum fw_foiscsi_digest_type { 2296 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2297 FW_FOISCSI_DIGEST_TYPE_CRC32, 2298 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2299 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2300 }; 2301 2302 enum fw_foiscsi_wr_subop { 2303 FW_FOISCSI_WR_SUBOP_ADD = 1, 2304 FW_FOISCSI_WR_SUBOP_DEL = 2, 2305 FW_FOISCSI_WR_SUBOP_MOD = 4, 2306 }; 2307 2308 enum fw_coiscsi_stats_wr_subop { 2309 FW_COISCSI_WR_SUBOP_TOT = 1, 2310 FW_COISCSI_WR_SUBOP_MAX = 2, 2311 FW_COISCSI_WR_SUBOP_CUR = 3, 2312 FW_COISCSI_WR_SUBOP_CLR = 4, 2313 }; 2314 2315 enum fw_foiscsi_ctrl_state { 2316 FW_FOISCSI_CTRL_STATE_FREE = 0, 2317 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2318 FW_FOISCSI_CTRL_STATE_FAILED, 2319 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2320 FW_FOISCSI_CTRL_STATE_REDIRECT, 2321 }; 2322 2323 struct fw_rdev_wr { 2324 __be32 op_to_immdlen; 2325 __be32 alloc_to_len16; 2326 __be64 cookie; 2327 __u8 protocol; 2328 __u8 event_cause; 2329 __u8 cur_state; 2330 __u8 prev_state; 2331 __be32 flags_to_assoc_flowid; 2332 union rdev_entry { 2333 struct fcoe_rdev_entry { 2334 __be32 flowid; 2335 __u8 protocol; 2336 __u8 event_cause; 2337 __u8 flags; 2338 __u8 rjt_reason; 2339 __u8 cur_login_st; 2340 __u8 prev_login_st; 2341 __be16 rcv_fr_sz; 2342 __u8 rd_xfer_rdy_to_rport_type; 2343 __u8 vft_to_qos; 2344 __u8 org_proc_assoc_to_acc_rsp_code; 2345 __u8 enh_disc_to_tgt; 2346 __u8 wwnn[8]; 2347 __u8 wwpn[8]; 2348 __be16 iqid; 2349 __u8 fc_oui[3]; 2350 __u8 r_id[3]; 2351 } fcoe_rdev; 2352 struct iscsi_rdev_entry { 2353 __be32 flowid; 2354 __u8 protocol; 2355 __u8 event_cause; 2356 __u8 flags; 2357 __u8 r3; 2358 __be16 iscsi_opts; 2359 __be16 tcp_opts; 2360 __be16 ip_opts; 2361 __be16 max_rcv_len; 2362 __be16 max_snd_len; 2363 __be16 first_brst_len; 2364 __be16 max_brst_len; 2365 __be16 r4; 2366 __be16 def_time2wait; 2367 __be16 def_time2ret; 2368 __be16 nop_out_intrvl; 2369 __be16 non_scsi_to; 2370 __be16 isid; 2371 __be16 tsid; 2372 __be16 port; 2373 __be16 tpgt; 2374 __u8 r5[6]; 2375 __be16 iqid; 2376 } iscsi_rdev; 2377 } u; 2378 }; 2379 2380 #define S_FW_RDEV_WR_IMMDLEN 0 2381 #define M_FW_RDEV_WR_IMMDLEN 0xff 2382 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2383 #define G_FW_RDEV_WR_IMMDLEN(x) \ 2384 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2385 2386 #define S_FW_RDEV_WR_ALLOC 31 2387 #define M_FW_RDEV_WR_ALLOC 0x1 2388 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2389 #define G_FW_RDEV_WR_ALLOC(x) \ 2390 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2391 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2392 2393 #define S_FW_RDEV_WR_FREE 30 2394 #define M_FW_RDEV_WR_FREE 0x1 2395 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2396 #define G_FW_RDEV_WR_FREE(x) \ 2397 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2398 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2399 2400 #define S_FW_RDEV_WR_MODIFY 29 2401 #define M_FW_RDEV_WR_MODIFY 0x1 2402 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2403 #define G_FW_RDEV_WR_MODIFY(x) \ 2404 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2405 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2406 2407 #define S_FW_RDEV_WR_FLOWID 8 2408 #define M_FW_RDEV_WR_FLOWID 0xfffff 2409 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2410 #define G_FW_RDEV_WR_FLOWID(x) \ 2411 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2412 2413 #define S_FW_RDEV_WR_LEN16 0 2414 #define M_FW_RDEV_WR_LEN16 0xff 2415 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2416 #define G_FW_RDEV_WR_LEN16(x) \ 2417 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2418 2419 #define S_FW_RDEV_WR_FLAGS 24 2420 #define M_FW_RDEV_WR_FLAGS 0xff 2421 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2422 #define G_FW_RDEV_WR_FLAGS(x) \ 2423 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2424 2425 #define S_FW_RDEV_WR_GET_NEXT 20 2426 #define M_FW_RDEV_WR_GET_NEXT 0xf 2427 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2428 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2429 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2430 2431 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2432 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2433 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2434 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2435 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2436 2437 #define S_FW_RDEV_WR_RJT 7 2438 #define M_FW_RDEV_WR_RJT 0x1 2439 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2440 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2441 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2442 2443 #define S_FW_RDEV_WR_REASON 0 2444 #define M_FW_RDEV_WR_REASON 0x7f 2445 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2446 #define G_FW_RDEV_WR_REASON(x) \ 2447 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2448 2449 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2450 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2451 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2452 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2453 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2454 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2455 2456 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2457 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2458 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2459 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2460 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2461 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2462 2463 #define S_FW_RDEV_WR_FC_SP 5 2464 #define M_FW_RDEV_WR_FC_SP 0x1 2465 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2466 #define G_FW_RDEV_WR_FC_SP(x) \ 2467 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2468 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2469 2470 #define S_FW_RDEV_WR_RPORT_TYPE 0 2471 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2472 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2473 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2474 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2475 2476 #define S_FW_RDEV_WR_VFT 7 2477 #define M_FW_RDEV_WR_VFT 0x1 2478 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2479 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2480 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2481 2482 #define S_FW_RDEV_WR_NPIV 6 2483 #define M_FW_RDEV_WR_NPIV 0x1 2484 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2485 #define G_FW_RDEV_WR_NPIV(x) \ 2486 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2487 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2488 2489 #define S_FW_RDEV_WR_CLASS 4 2490 #define M_FW_RDEV_WR_CLASS 0x3 2491 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2492 #define G_FW_RDEV_WR_CLASS(x) \ 2493 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2494 2495 #define S_FW_RDEV_WR_SEQ_DEL 3 2496 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2497 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2498 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2499 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2500 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2501 2502 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2503 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2504 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2505 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2506 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2507 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2508 2509 #define S_FW_RDEV_WR_PREF 1 2510 #define M_FW_RDEV_WR_PREF 0x1 2511 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2512 #define G_FW_RDEV_WR_PREF(x) \ 2513 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2514 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2515 2516 #define S_FW_RDEV_WR_QOS 0 2517 #define M_FW_RDEV_WR_QOS 0x1 2518 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2519 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2520 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2521 2522 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2523 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2524 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2525 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2526 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2527 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2528 2529 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2530 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2531 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2532 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2533 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2534 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2535 2536 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2537 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2538 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2539 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2540 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2541 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2542 2543 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2544 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2545 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2546 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2547 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2548 2549 #define S_FW_RDEV_WR_ENH_DISC 7 2550 #define M_FW_RDEV_WR_ENH_DISC 0x1 2551 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2552 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2553 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2554 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2555 2556 #define S_FW_RDEV_WR_REC 6 2557 #define M_FW_RDEV_WR_REC 0x1 2558 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2559 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2560 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2561 2562 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2563 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2564 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2565 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2566 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2567 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2568 2569 #define S_FW_RDEV_WR_RETRY 4 2570 #define M_FW_RDEV_WR_RETRY 0x1 2571 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2572 #define G_FW_RDEV_WR_RETRY(x) \ 2573 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2574 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2575 2576 #define S_FW_RDEV_WR_CONF_CMPL 3 2577 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2578 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2579 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2580 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2581 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2582 2583 #define S_FW_RDEV_WR_DATA_OVLY 2 2584 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2585 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2586 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2587 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2588 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2589 2590 #define S_FW_RDEV_WR_INI 1 2591 #define M_FW_RDEV_WR_INI 0x1 2592 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2593 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2594 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2595 2596 #define S_FW_RDEV_WR_TGT 0 2597 #define M_FW_RDEV_WR_TGT 0x1 2598 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2599 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2600 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2601 2602 struct fw_foiscsi_node_wr { 2603 __be32 op_to_immdlen; 2604 __be32 no_sess_recv_to_len16; 2605 __u64 cookie; 2606 __u8 subop; 2607 __u8 status; 2608 __u8 alias_len; 2609 __u8 iqn_len; 2610 __be32 node_flowid; 2611 __be16 nodeid; 2612 __be16 login_retry; 2613 __be16 retry_timeout; 2614 __be16 r3; 2615 __u8 iqn[224]; 2616 __u8 alias[224]; 2617 __be32 isid_tval_to_isid_cval; 2618 }; 2619 2620 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2621 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2622 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2623 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2624 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2625 2626 #define S_FW_FOISCSI_NODE_WR_NO_SESS_RECV 28 2627 #define M_FW_FOISCSI_NODE_WR_NO_SESS_RECV 0x1 2628 #define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 2629 ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 2630 #define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 2631 (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \ 2632 M_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 2633 #define F_FW_FOISCSI_NODE_WR_NO_SESS_RECV \ 2634 V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U) 2635 2636 #define S_FW_FOISCSI_NODE_WR_ISID_TVAL 30 2637 #define M_FW_FOISCSI_NODE_WR_ISID_TVAL 0x3 2638 #define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 2639 ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL) 2640 #define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 2641 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL) 2642 2643 #define S_FW_FOISCSI_NODE_WR_ISID_AVAL 24 2644 #define M_FW_FOISCSI_NODE_WR_ISID_AVAL 0x3f 2645 #define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 2646 ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL) 2647 #define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 2648 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL) 2649 2650 #define S_FW_FOISCSI_NODE_WR_ISID_BVAL 8 2651 #define M_FW_FOISCSI_NODE_WR_ISID_BVAL 0xffff 2652 #define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 2653 ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL) 2654 #define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 2655 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL) 2656 2657 #define S_FW_FOISCSI_NODE_WR_ISID_CVAL 0 2658 #define M_FW_FOISCSI_NODE_WR_ISID_CVAL 0xff 2659 #define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 2660 ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL) 2661 #define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 2662 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL) 2663 2664 struct fw_foiscsi_ctrl_wr { 2665 __be32 op_to_no_fin; 2666 __be32 flowid_len16; 2667 __u64 cookie; 2668 __u8 subop; 2669 __u8 status; 2670 __u8 ctrl_state; 2671 __u8 io_state; 2672 __be32 node_id; 2673 __be32 ctrl_id; 2674 __be32 io_id; 2675 struct fw_foiscsi_sess_attr { 2676 __be32 sess_type_to_erl; 2677 __be16 max_conn; 2678 __be16 max_r2t; 2679 __be16 time2wait; 2680 __be16 time2retain; 2681 __be32 max_burst; 2682 __be32 first_burst; 2683 __be32 r1; 2684 } sess_attr; 2685 struct fw_foiscsi_conn_attr { 2686 __be32 hdigest_to_tcp_ws_en; 2687 __be32 max_rcv_dsl; 2688 __be32 ping_tmo; 2689 __be16 dst_port; 2690 __be16 src_port; 2691 union fw_foiscsi_conn_attr_addr { 2692 struct fw_foiscsi_conn_attr_ipv6 { 2693 __be64 dst_addr[2]; 2694 __be64 src_addr[2]; 2695 } ipv6_addr; 2696 struct fw_foiscsi_conn_attr_ipv4 { 2697 __be32 dst_addr; 2698 __be32 src_addr; 2699 } ipv4_addr; 2700 } u; 2701 } conn_attr; 2702 __u8 tgt_name_len; 2703 __u8 r3[7]; 2704 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2705 }; 2706 2707 #define S_FW_FOISCSI_CTRL_WR_PORTID 1 2708 #define M_FW_FOISCSI_CTRL_WR_PORTID 0x7 2709 #define V_FW_FOISCSI_CTRL_WR_PORTID(x) ((x) << S_FW_FOISCSI_CTRL_WR_PORTID) 2710 #define G_FW_FOISCSI_CTRL_WR_PORTID(x) \ 2711 (((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID) 2712 2713 #define S_FW_FOISCSI_CTRL_WR_NO_FIN 0 2714 #define M_FW_FOISCSI_CTRL_WR_NO_FIN 0x1 2715 #define V_FW_FOISCSI_CTRL_WR_NO_FIN(x) ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN) 2716 #define G_FW_FOISCSI_CTRL_WR_NO_FIN(x) \ 2717 (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN) 2718 #define F_FW_FOISCSI_CTRL_WR_NO_FIN V_FW_FOISCSI_CTRL_WR_NO_FIN(1U) 2719 2720 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2721 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2722 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2723 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2724 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2725 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2726 2727 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2728 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2729 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2730 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2731 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2732 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2733 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2734 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2735 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2736 2737 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2738 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2739 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2740 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2741 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2742 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2743 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2744 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2745 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2746 2747 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2748 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2749 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2750 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2751 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2752 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2753 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2754 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2755 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2756 2757 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2758 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2759 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2760 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2761 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2762 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2763 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2764 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2765 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2766 2767 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2768 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2769 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2770 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2771 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2772 2773 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2774 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2775 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2776 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2777 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2778 2779 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2780 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2781 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2782 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2783 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2784 2785 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2786 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2787 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2788 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2789 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2790 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2791 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2792 2793 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2794 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2795 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2796 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2797 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2798 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2799 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2800 2801 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2802 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2803 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2804 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2805 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2806 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2807 2808 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 2809 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2810 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2811 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2812 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2813 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2814 2815 #define S_FW_FOISCSI_CTRL_WR_DDP_PGIDX 16 2816 #define M_FW_FOISCSI_CTRL_WR_DDP_PGIDX 0xf 2817 #define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 2818 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 2819 #define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 2820 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 2821 2822 #define S_FW_FOISCSI_CTRL_WR_TCP_WS 12 2823 #define M_FW_FOISCSI_CTRL_WR_TCP_WS 0xf 2824 #define V_FW_FOISCSI_CTRL_WR_TCP_WS(x) ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS) 2825 #define G_FW_FOISCSI_CTRL_WR_TCP_WS(x) \ 2826 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS) 2827 2828 #define S_FW_FOISCSI_CTRL_WR_TCP_WS_EN 11 2829 #define M_FW_FOISCSI_CTRL_WR_TCP_WS_EN 0x1 2830 #define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 2831 ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 2832 #define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 2833 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 2834 #define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U) 2835 2836 struct fw_foiscsi_chap_wr { 2837 __be32 op_to_kv_flag; 2838 __be32 flowid_len16; 2839 __u64 cookie; 2840 __u8 status; 2841 union fw_foiscsi_len { 2842 struct fw_foiscsi_chap_lens { 2843 __u8 id_len; 2844 __u8 sec_len; 2845 } chapl; 2846 struct fw_foiscsi_vend_kv_lens { 2847 __u8 key_len; 2848 __u8 val_len; 2849 } vend_kvl; 2850 } lenu; 2851 __u8 node_type; 2852 __be16 node_id; 2853 __u8 r3[2]; 2854 union fw_foiscsi_chap_vend { 2855 struct fw_foiscsi_chap { 2856 __u8 chap_id[224]; 2857 __u8 chap_sec[128]; 2858 } chap; 2859 struct fw_foiscsi_vend_kv { 2860 __u8 vend_key[64]; 2861 __u8 vend_val[256]; 2862 } vend_kv; 2863 } u; 2864 }; 2865 2866 #define S_FW_FOISCSI_CHAP_WR_KV_FLAG 20 2867 #define M_FW_FOISCSI_CHAP_WR_KV_FLAG 0x1 2868 #define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x) ((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG) 2869 #define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \ 2870 (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG) 2871 #define F_FW_FOISCSI_CHAP_WR_KV_FLAG V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U) 2872 2873 /****************************************************************************** 2874 * C O i S C S I W O R K R E Q U E S T S 2875 ********************************************/ 2876 2877 enum fw_chnet_addr_type { 2878 FW_CHNET_ADDD_TYPE_NONE = 0, 2879 FW_CHNET_ADDR_TYPE_IPV4, 2880 FW_CHNET_ADDR_TYPE_IPV6, 2881 }; 2882 2883 enum fw_msg_wr_type { 2884 FW_MSG_WR_TYPE_RPL = 0, 2885 FW_MSG_WR_TYPE_ERR, 2886 FW_MSG_WR_TYPE_PLD, 2887 }; 2888 2889 struct fw_coiscsi_tgt_wr { 2890 __be32 op_compl; 2891 __be32 flowid_len16; 2892 __u64 cookie; 2893 __u8 subop; 2894 __u8 status; 2895 __be16 r4; 2896 __be32 flags; 2897 struct fw_coiscsi_tgt_conn_attr { 2898 __be32 in_tid; 2899 __be16 in_port; 2900 __u8 in_type; 2901 __u8 r6; 2902 union fw_coiscsi_tgt_conn_attr_addr { 2903 struct fw_coiscsi_tgt_conn_attr_in_addr { 2904 __be32 addr; 2905 __be32 r7; 2906 __be32 r8[2]; 2907 } in_addr; 2908 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2909 __be64 addr[2]; 2910 } in_addr6; 2911 } u; 2912 } conn_attr; 2913 }; 2914 2915 #define S_FW_COISCSI_TGT_WR_PORTID 0 2916 #define M_FW_COISCSI_TGT_WR_PORTID 0x7 2917 #define V_FW_COISCSI_TGT_WR_PORTID(x) ((x) << S_FW_COISCSI_TGT_WR_PORTID) 2918 #define G_FW_COISCSI_TGT_WR_PORTID(x) \ 2919 (((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID) 2920 2921 struct fw_coiscsi_tgt_conn_wr { 2922 __be32 op_compl; 2923 __be32 flowid_len16; 2924 __u64 cookie; 2925 __u8 subop; 2926 __u8 status; 2927 __be16 iq_id; 2928 __be32 in_stid; 2929 __be32 io_id; 2930 __be32 flags_fin; 2931 union { 2932 struct fw_coiscsi_tgt_conn_tcp { 2933 __be16 in_sport; 2934 __be16 in_dport; 2935 __u8 wscale_wsen; 2936 __u8 r4[3]; 2937 union fw_coiscsi_tgt_conn_tcp_addr { 2938 struct fw_coiscsi_tgt_conn_tcp_in_addr { 2939 __be32 saddr; 2940 __be32 daddr; 2941 } in_addr; 2942 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 2943 __be64 saddr[2]; 2944 __be64 daddr[2]; 2945 } in_addr6; 2946 } u; 2947 } conn_tcp; 2948 struct fw_coiscsi_tgt_conn_stats { 2949 __be32 ddp_reqs; 2950 __be32 ddp_cmpls; 2951 __be16 ddp_aborts; 2952 __be16 ddp_bps; 2953 } stats; 2954 } u; 2955 struct fw_coiscsi_tgt_conn_iscsi { 2956 __be32 hdigest_to_ddp_pgsz; 2957 __be32 tgt_id; 2958 __be16 max_r2t; 2959 __be16 r5; 2960 __be32 max_burst; 2961 __be32 max_rdsl; 2962 __be32 max_tdsl; 2963 __be32 cur_sn; 2964 __be32 r6; 2965 } conn_iscsi; 2966 }; 2967 2968 #define S_FW_COISCSI_TGT_CONN_WR_PORTID 0 2969 #define M_FW_COISCSI_TGT_CONN_WR_PORTID 0x7 2970 #define V_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 2971 ((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID) 2972 #define G_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 2973 (((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \ 2974 M_FW_COISCSI_TGT_CONN_WR_PORTID) 2975 2976 #define S_FW_COISCSI_TGT_CONN_WR_FIN 0 2977 #define M_FW_COISCSI_TGT_CONN_WR_FIN 0x1 2978 #define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN) 2979 #define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \ 2980 (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN) 2981 #define F_FW_COISCSI_TGT_CONN_WR_FIN V_FW_COISCSI_TGT_CONN_WR_FIN(1U) 2982 2983 #define S_FW_COISCSI_TGT_CONN_WR_WSCALE 1 2984 #define M_FW_COISCSI_TGT_CONN_WR_WSCALE 0xf 2985 #define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 2986 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE) 2987 #define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 2988 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \ 2989 M_FW_COISCSI_TGT_CONN_WR_WSCALE) 2990 2991 #define S_FW_COISCSI_TGT_CONN_WR_WSEN 0 2992 #define M_FW_COISCSI_TGT_CONN_WR_WSEN 0x1 2993 #define V_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 2994 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN) 2995 #define G_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 2996 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN) 2997 #define F_FW_COISCSI_TGT_CONN_WR_WSEN V_FW_COISCSI_TGT_CONN_WR_WSEN(1U) 2998 2999 struct fw_coiscsi_tgt_xmit_wr { 3000 __be32 op_to_immdlen; 3001 union { 3002 struct cmpl_stat { 3003 __be32 cmpl_status_pkd; 3004 } cs; 3005 struct flowid_len { 3006 __be32 flowid_len16; 3007 } fllen; 3008 } u; 3009 __u64 cookie; 3010 __be16 iq_id; 3011 __be16 r3; 3012 __be32 pz_off; 3013 __be32 t_xfer_len; 3014 union { 3015 __be32 tag; 3016 __be32 datasn; 3017 __be32 ddp_status; 3018 } cu; 3019 }; 3020 3021 #define S_FW_COISCSI_TGT_XMIT_WR_DDGST 23 3022 #define M_FW_COISCSI_TGT_XMIT_WR_DDGST 0x1 3023 #define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 3024 ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST) 3025 #define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 3026 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST) 3027 #define F_FW_COISCSI_TGT_XMIT_WR_DDGST V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U) 3028 3029 #define S_FW_COISCSI_TGT_XMIT_WR_HDGST 22 3030 #define M_FW_COISCSI_TGT_XMIT_WR_HDGST 0x1 3031 #define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3032 ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST) 3033 #define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3034 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST) 3035 #define F_FW_COISCSI_TGT_XMIT_WR_HDGST V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U) 3036 3037 #define S_FW_COISCSI_TGT_XMIT_WR_DDP 20 3038 #define M_FW_COISCSI_TGT_XMIT_WR_DDP 0x1 3039 #define V_FW_COISCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP) 3040 #define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \ 3041 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP) 3042 #define F_FW_COISCSI_TGT_XMIT_WR_DDP V_FW_COISCSI_TGT_XMIT_WR_DDP(1U) 3043 3044 #define S_FW_COISCSI_TGT_XMIT_WR_ABORT 19 3045 #define M_FW_COISCSI_TGT_XMIT_WR_ABORT 0x1 3046 #define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3047 ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT) 3048 #define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3049 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT) 3050 #define F_FW_COISCSI_TGT_XMIT_WR_ABORT V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U) 3051 3052 #define S_FW_COISCSI_TGT_XMIT_WR_FINAL 18 3053 #define M_FW_COISCSI_TGT_XMIT_WR_FINAL 0x1 3054 #define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3055 ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL) 3056 #define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3057 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL) 3058 #define F_FW_COISCSI_TGT_XMIT_WR_FINAL V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U) 3059 3060 #define S_FW_COISCSI_TGT_XMIT_WR_PADLEN 16 3061 #define M_FW_COISCSI_TGT_XMIT_WR_PADLEN 0x3 3062 #define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3063 ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3064 #define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3065 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \ 3066 M_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3067 3068 #define S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 15 3069 #define M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 0x1 3070 #define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3071 ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3072 #define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3073 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \ 3074 M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3075 #define F_FW_COISCSI_TGT_XMIT_WR_INCSTATSN \ 3076 V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U) 3077 3078 #define S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0 3079 #define M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0xff 3080 #define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3081 ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 3082 #define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3083 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \ 3084 M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 3085 3086 #define S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 8 3087 #define M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 0xff 3088 #define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3089 ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3090 #define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3091 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \ 3092 M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3093 3094 struct fw_coiscsi_stats_wr { 3095 __be32 op_compl; 3096 __be32 flowid_len16; 3097 __u64 cookie; 3098 __u8 subop; 3099 __u8 status; 3100 union fw_coiscsi_stats { 3101 struct fw_coiscsi_resource { 3102 __u8 num_ipv4_tgt; 3103 __u8 num_ipv6_tgt; 3104 __be16 num_l2t_entries; 3105 __be16 num_csocks; 3106 __be16 num_tasks; 3107 __be16 num_ppods_zone[11]; 3108 __be32 num_bufll64; 3109 __u8 r2[12]; 3110 } rsrc; 3111 } u; 3112 }; 3113 3114 #define S_FW_COISCSI_STATS_WR_PORTID 0 3115 #define M_FW_COISCSI_STATS_WR_PORTID 0x7 3116 #define V_FW_COISCSI_STATS_WR_PORTID(x) ((x) << S_FW_COISCSI_STATS_WR_PORTID) 3117 #define G_FW_COISCSI_STATS_WR_PORTID(x) \ 3118 (((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID) 3119 3120 struct fw_isns_wr { 3121 __be32 op_compl; 3122 __be32 flowid_len16; 3123 __u64 cookie; 3124 __u8 subop; 3125 __u8 status; 3126 __be16 iq_id; 3127 __be16 vlanid; 3128 __be16 r4; 3129 struct fw_tcp_conn_attr { 3130 __be32 in_tid; 3131 __be16 in_port; 3132 __u8 in_type; 3133 __u8 r6; 3134 union fw_tcp_conn_attr_addr { 3135 struct fw_tcp_conn_attr_in_addr { 3136 __be32 addr; 3137 __be32 r7; 3138 __be32 r8[2]; 3139 } in_addr; 3140 struct fw_tcp_conn_attr_in_addr6 { 3141 __be64 addr[2]; 3142 } in_addr6; 3143 } u; 3144 } conn_attr; 3145 }; 3146 3147 #define S_FW_ISNS_WR_PORTID 0 3148 #define M_FW_ISNS_WR_PORTID 0x7 3149 #define V_FW_ISNS_WR_PORTID(x) ((x) << S_FW_ISNS_WR_PORTID) 3150 #define G_FW_ISNS_WR_PORTID(x) \ 3151 (((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID) 3152 3153 struct fw_isns_xmit_wr { 3154 __be32 op_to_immdlen; 3155 __be32 flowid_len16; 3156 __u64 cookie; 3157 __be16 iq_id; 3158 __be16 r4; 3159 __be32 xfer_len; 3160 __be64 r5; 3161 }; 3162 3163 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 3164 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 3165 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 3166 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 3167 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 3168 3169 /****************************************************************************** 3170 * F O F C O E W O R K R E Q U E S T s 3171 *******************************************/ 3172 3173 struct fw_fcoe_els_ct_wr { 3174 __be32 op_immdlen; 3175 __be32 flowid_len16; 3176 __be64 cookie; 3177 __be16 iqid; 3178 __u8 tmo_val; 3179 __u8 els_ct_type; 3180 __u8 ctl_pri; 3181 __u8 cp_en_class; 3182 __be16 xfer_cnt; 3183 __u8 fl_to_sp; 3184 __u8 l_id[3]; 3185 __u8 r5; 3186 __u8 r_id[3]; 3187 __be64 rsp_dmaaddr; 3188 __be32 rsp_dmalen; 3189 __be32 r6; 3190 }; 3191 3192 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 3193 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 3194 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 3195 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 3196 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 3197 3198 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 3199 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 3200 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 3201 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 3202 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 3203 3204 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 3205 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 3206 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 3207 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 3208 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 3209 3210 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 3211 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 3212 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 3213 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 3214 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 3215 3216 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 3217 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 3218 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 3219 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 3220 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 3221 3222 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 3223 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 3224 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 3225 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 3226 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 3227 3228 #define S_FW_FCOE_ELS_CT_WR_FL 2 3229 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 3230 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 3231 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 3232 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 3233 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 3234 3235 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 3236 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 3237 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 3238 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 3239 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 3240 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 3241 3242 #define S_FW_FCOE_ELS_CT_WR_SP 0 3243 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 3244 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 3245 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 3246 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 3247 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 3248 3249 /****************************************************************************** 3250 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 3251 *****************************************************************************/ 3252 3253 struct fw_scsi_write_wr { 3254 __be32 op_immdlen; 3255 __be32 flowid_len16; 3256 __be64 cookie; 3257 __be16 iqid; 3258 __u8 tmo_val; 3259 __u8 use_xfer_cnt; 3260 union fw_scsi_write_priv { 3261 struct fcoe_write_priv { 3262 __u8 ctl_pri; 3263 __u8 cp_en_class; 3264 __u8 r3_lo[2]; 3265 } fcoe; 3266 struct iscsi_write_priv { 3267 __u8 r3[4]; 3268 } iscsi; 3269 } u; 3270 __be32 xfer_cnt; 3271 __be32 ini_xfer_cnt; 3272 __be64 rsp_dmaaddr; 3273 __be32 rsp_dmalen; 3274 __be32 r4; 3275 }; 3276 3277 #define S_FW_SCSI_WRITE_WR_OPCODE 24 3278 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 3279 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 3280 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 3281 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 3282 3283 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 3284 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 3285 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 3286 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 3287 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 3288 3289 #define S_FW_SCSI_WRITE_WR_FLOWID 8 3290 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 3291 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 3292 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 3293 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 3294 3295 #define S_FW_SCSI_WRITE_WR_LEN16 0 3296 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 3297 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 3298 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 3299 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 3300 3301 #define S_FW_SCSI_WRITE_WR_CP_EN 6 3302 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 3303 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 3304 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 3305 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 3306 3307 #define S_FW_SCSI_WRITE_WR_CLASS 4 3308 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 3309 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 3310 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 3311 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 3312 3313 struct fw_scsi_read_wr { 3314 __be32 op_immdlen; 3315 __be32 flowid_len16; 3316 __be64 cookie; 3317 __be16 iqid; 3318 __u8 tmo_val; 3319 __u8 use_xfer_cnt; 3320 union fw_scsi_read_priv { 3321 struct fcoe_read_priv { 3322 __u8 ctl_pri; 3323 __u8 cp_en_class; 3324 __u8 r3_lo[2]; 3325 } fcoe; 3326 struct iscsi_read_priv { 3327 __u8 r3[4]; 3328 } iscsi; 3329 } u; 3330 __be32 xfer_cnt; 3331 __be32 ini_xfer_cnt; 3332 __be64 rsp_dmaaddr; 3333 __be32 rsp_dmalen; 3334 __be32 r4; 3335 }; 3336 3337 #define S_FW_SCSI_READ_WR_OPCODE 24 3338 #define M_FW_SCSI_READ_WR_OPCODE 0xff 3339 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 3340 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 3341 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 3342 3343 #define S_FW_SCSI_READ_WR_IMMDLEN 0 3344 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 3345 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 3346 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 3347 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 3348 3349 #define S_FW_SCSI_READ_WR_FLOWID 8 3350 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 3351 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 3352 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 3353 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 3354 3355 #define S_FW_SCSI_READ_WR_LEN16 0 3356 #define M_FW_SCSI_READ_WR_LEN16 0xff 3357 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 3358 #define G_FW_SCSI_READ_WR_LEN16(x) \ 3359 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 3360 3361 #define S_FW_SCSI_READ_WR_CP_EN 6 3362 #define M_FW_SCSI_READ_WR_CP_EN 0x3 3363 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 3364 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 3365 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 3366 3367 #define S_FW_SCSI_READ_WR_CLASS 4 3368 #define M_FW_SCSI_READ_WR_CLASS 0x3 3369 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 3370 #define G_FW_SCSI_READ_WR_CLASS(x) \ 3371 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 3372 3373 struct fw_scsi_cmd_wr { 3374 __be32 op_immdlen; 3375 __be32 flowid_len16; 3376 __be64 cookie; 3377 __be16 iqid; 3378 __u8 tmo_val; 3379 __u8 r3; 3380 union fw_scsi_cmd_priv { 3381 struct fcoe_cmd_priv { 3382 __u8 ctl_pri; 3383 __u8 cp_en_class; 3384 __u8 r4_lo[2]; 3385 } fcoe; 3386 struct iscsi_cmd_priv { 3387 __u8 r4[4]; 3388 } iscsi; 3389 } u; 3390 __u8 r5[8]; 3391 __be64 rsp_dmaaddr; 3392 __be32 rsp_dmalen; 3393 __be32 r6; 3394 }; 3395 3396 #define S_FW_SCSI_CMD_WR_OPCODE 24 3397 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 3398 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 3399 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 3400 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 3401 3402 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 3403 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 3404 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 3405 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 3406 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 3407 3408 #define S_FW_SCSI_CMD_WR_FLOWID 8 3409 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 3410 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 3411 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 3412 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 3413 3414 #define S_FW_SCSI_CMD_WR_LEN16 0 3415 #define M_FW_SCSI_CMD_WR_LEN16 0xff 3416 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 3417 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 3418 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 3419 3420 #define S_FW_SCSI_CMD_WR_CP_EN 6 3421 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 3422 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 3423 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 3424 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 3425 3426 #define S_FW_SCSI_CMD_WR_CLASS 4 3427 #define M_FW_SCSI_CMD_WR_CLASS 0x3 3428 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 3429 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 3430 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 3431 3432 struct fw_scsi_abrt_cls_wr { 3433 __be32 op_immdlen; 3434 __be32 flowid_len16; 3435 __be64 cookie; 3436 __be16 iqid; 3437 __u8 tmo_val; 3438 __u8 sub_opcode_to_chk_all_io; 3439 __u8 r3[4]; 3440 __be64 t_cookie; 3441 }; 3442 3443 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 3444 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 3445 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 3446 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 3447 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 3448 3449 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 3450 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 3451 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3452 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3453 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3454 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3455 3456 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 3457 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 3458 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 3459 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 3460 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 3461 3462 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 3463 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 3464 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 3465 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 3466 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 3467 3468 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 3469 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 3470 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3471 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3472 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3473 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3474 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3475 3476 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3477 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3478 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3479 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3480 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3481 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3482 3483 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3484 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3485 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3486 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3487 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3488 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3489 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3490 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 3491 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 3492 3493 struct fw_scsi_tgt_acc_wr { 3494 __be32 op_immdlen; 3495 __be32 flowid_len16; 3496 __be64 cookie; 3497 __be16 iqid; 3498 __u8 r3; 3499 __u8 use_burst_len; 3500 union fw_scsi_tgt_acc_priv { 3501 struct fcoe_tgt_acc_priv { 3502 __u8 ctl_pri; 3503 __u8 cp_en_class; 3504 __u8 r4_lo[2]; 3505 } fcoe; 3506 struct iscsi_tgt_acc_priv { 3507 __u8 r4[4]; 3508 } iscsi; 3509 } u; 3510 __be32 burst_len; 3511 __be32 rel_off; 3512 __be64 r5; 3513 __be32 r6; 3514 __be32 tot_xfer_len; 3515 }; 3516 3517 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3518 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3519 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3520 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3521 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3522 3523 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3524 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3525 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3526 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3527 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3528 3529 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3530 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3531 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3532 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3533 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3534 3535 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3536 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3537 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3538 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3539 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3540 3541 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3542 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3543 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3544 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3545 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3546 3547 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3548 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3549 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3550 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3551 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 3552 3553 struct fw_scsi_tgt_xmit_wr { 3554 __be32 op_immdlen; 3555 __be32 flowid_len16; 3556 __be64 cookie; 3557 __be16 iqid; 3558 __u8 auto_rsp; 3559 __u8 use_xfer_cnt; 3560 union fw_scsi_tgt_xmit_priv { 3561 struct fcoe_tgt_xmit_priv { 3562 __u8 ctl_pri; 3563 __u8 cp_en_class; 3564 __u8 r3_lo[2]; 3565 } fcoe; 3566 struct iscsi_tgt_xmit_priv { 3567 __u8 r3[4]; 3568 } iscsi; 3569 } u; 3570 __be32 xfer_cnt; 3571 __be32 r4; 3572 __be64 r5; 3573 __be32 r6; 3574 __be32 tot_xfer_len; 3575 }; 3576 3577 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3578 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3579 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3580 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3581 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3582 3583 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3584 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3585 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3586 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3587 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3588 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3589 3590 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3591 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3592 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3593 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3594 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3595 3596 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3597 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3598 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3599 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3600 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3601 3602 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3603 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3604 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3605 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3606 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3607 3608 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3609 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3610 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3611 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3612 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 3613 3614 struct fw_scsi_tgt_rsp_wr { 3615 __be32 op_immdlen; 3616 __be32 flowid_len16; 3617 __be64 cookie; 3618 __be16 iqid; 3619 __u8 r3[2]; 3620 union fw_scsi_tgt_rsp_priv { 3621 struct fcoe_tgt_rsp_priv { 3622 __u8 ctl_pri; 3623 __u8 cp_en_class; 3624 __u8 r4_lo[2]; 3625 } fcoe; 3626 struct iscsi_tgt_rsp_priv { 3627 __u8 r4[4]; 3628 } iscsi; 3629 } u; 3630 __u8 r5[8]; 3631 }; 3632 3633 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3634 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3635 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3636 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3637 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3638 3639 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3640 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3641 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3642 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3643 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3644 3645 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3646 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3647 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3648 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3649 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3650 3651 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3652 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3653 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3654 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3655 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3656 3657 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3658 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3659 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3660 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3661 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3662 3663 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3664 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3665 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3666 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3667 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3668 3669 struct fw_pofcoe_tcb_wr { 3670 __be32 op_compl; 3671 __be32 equiq_to_len16; 3672 __be32 r4; 3673 __be32 xfer_len; 3674 __be32 tid_to_port; 3675 __be16 x_id; 3676 __be16 vlan_id; 3677 __be64 cookie; 3678 __be32 s_id; 3679 __be32 d_id; 3680 __be32 tag; 3681 __be16 r6; 3682 __be16 iqid; 3683 }; 3684 3685 #define S_FW_POFCOE_TCB_WR_TID 12 3686 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 3687 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3688 #define G_FW_POFCOE_TCB_WR_TID(x) \ 3689 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3690 3691 #define S_FW_POFCOE_TCB_WR_ALLOC 4 3692 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3693 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3694 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3695 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3696 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3697 3698 #define S_FW_POFCOE_TCB_WR_FREE 3 3699 #define M_FW_POFCOE_TCB_WR_FREE 0x1 3700 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3701 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 3702 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3703 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3704 3705 #define S_FW_POFCOE_TCB_WR_PORT 0 3706 #define M_FW_POFCOE_TCB_WR_PORT 0x7 3707 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3708 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 3709 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3710 3711 struct fw_pofcoe_ulptx_wr { 3712 __be32 op_pkd; 3713 __be32 equiq_to_len16; 3714 __u64 cookie; 3715 }; 3716 3717 /******************************************************************* 3718 * T10 DIF related definition 3719 *******************************************************************/ 3720 struct fw_tx_pi_header { 3721 __be16 op_to_inline; 3722 __u8 pi_interval_tag_type; 3723 __u8 num_pi; 3724 __be32 pi_start4_pi_end4; 3725 __u8 tag_gen_enabled_pkd; 3726 __u8 num_pi_dsg; 3727 __be16 app_tag; 3728 __be32 ref_tag; 3729 }; 3730 3731 #define S_FW_TX_PI_HEADER_OP 8 3732 #define M_FW_TX_PI_HEADER_OP 0xff 3733 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3734 #define G_FW_TX_PI_HEADER_OP(x) \ 3735 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3736 3737 #define S_FW_TX_PI_HEADER_ULPTXMORE 7 3738 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3739 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3740 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3741 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3742 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3743 3744 #define S_FW_TX_PI_HEADER_PI_CONTROL 4 3745 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3746 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3747 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3748 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3749 3750 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3751 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3752 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3753 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3754 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3755 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3756 3757 #define S_FW_TX_PI_HEADER_VALIDATE 1 3758 #define M_FW_TX_PI_HEADER_VALIDATE 0x1 3759 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3760 #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3761 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3762 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3763 3764 #define S_FW_TX_PI_HEADER_INLINE 0 3765 #define M_FW_TX_PI_HEADER_INLINE 0x1 3766 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3767 #define G_FW_TX_PI_HEADER_INLINE(x) \ 3768 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3769 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3770 3771 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3772 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3773 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3774 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3775 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3776 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3777 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3778 3779 #define S_FW_TX_PI_HEADER_TAG_TYPE 5 3780 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3781 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3782 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3783 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3784 3785 #define S_FW_TX_PI_HEADER_PI_START4 22 3786 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3787 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3788 #define G_FW_TX_PI_HEADER_PI_START4(x) \ 3789 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3790 3791 #define S_FW_TX_PI_HEADER_PI_END4 0 3792 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3793 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3794 #define G_FW_TX_PI_HEADER_PI_END4(x) \ 3795 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3796 3797 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3798 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3799 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3800 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3801 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3802 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3803 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3804 3805 enum fw_pi_error_type { 3806 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3807 }; 3808 3809 struct fw_pi_error { 3810 __be32 err_type_pkd; 3811 __be32 flowid_len16; 3812 __be16 r2; 3813 __be16 app_tag; 3814 __be32 ref_tag; 3815 __be32 pisc[4]; 3816 }; 3817 3818 #define S_FW_PI_ERROR_ERR_TYPE 24 3819 #define M_FW_PI_ERROR_ERR_TYPE 0xff 3820 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3821 #define G_FW_PI_ERROR_ERR_TYPE(x) \ 3822 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3823 3824 struct fw_tlstx_data_wr { 3825 __be32 op_to_immdlen; 3826 __be32 flowid_len16; 3827 __be32 plen; 3828 __be32 lsodisable_to_flags; 3829 __be32 r5; 3830 __be32 ctxloc_to_exp; 3831 __be16 mfs; 3832 __be16 adjustedplen_pkd; 3833 __be16 expinplenmax_pkd; 3834 __u8 pdusinplenmax_pkd; 3835 __u8 r10; 3836 }; 3837 3838 #define S_FW_TLSTX_DATA_WR_OPCODE 24 3839 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff 3840 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 3841 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 3842 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 3843 3844 #define S_FW_TLSTX_DATA_WR_COMPL 21 3845 #define M_FW_TLSTX_DATA_WR_COMPL 0x1 3846 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 3847 #define G_FW_TLSTX_DATA_WR_COMPL(x) \ 3848 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 3849 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 3850 3851 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0 3852 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 3853 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 3854 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 3855 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 3856 3857 #define S_FW_TLSTX_DATA_WR_FLOWID 8 3858 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 3859 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 3860 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 3861 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 3862 3863 #define S_FW_TLSTX_DATA_WR_LEN16 0 3864 #define M_FW_TLSTX_DATA_WR_LEN16 0xff 3865 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 3866 #define G_FW_TLSTX_DATA_WR_LEN16(x) \ 3867 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 3868 3869 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31 3870 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 3871 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3872 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 3873 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3874 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 3875 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 3876 3877 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 3878 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 3879 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 3880 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 3881 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 3882 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 3883 3884 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 3885 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 3886 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3887 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3888 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3889 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 3890 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3891 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 3892 3893 #define S_FW_TLSTX_DATA_WR_FLAGS 0 3894 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 3895 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 3896 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 3897 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 3898 3899 #define S_FW_TLSTX_DATA_WR_CTXLOC 30 3900 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 3901 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 3902 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 3903 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 3904 3905 #define S_FW_TLSTX_DATA_WR_IVDSGL 29 3906 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 3907 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 3908 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 3909 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 3910 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 3911 3912 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24 3913 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 3914 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 3915 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 3916 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 3917 3918 #define S_FW_TLSTX_DATA_WR_NUMIVS 14 3919 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 3920 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 3921 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 3922 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 3923 3924 #define S_FW_TLSTX_DATA_WR_EXP 0 3925 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff 3926 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 3927 #define G_FW_TLSTX_DATA_WR_EXP(x) \ 3928 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 3929 3930 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 3931 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 3932 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3933 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3934 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3935 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 3936 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3937 3938 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 3939 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 3940 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3941 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3942 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3943 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 3944 M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3945 3946 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 3947 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 3948 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3949 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3950 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3951 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 3952 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3953 3954 struct fw_crypto_lookaside_wr { 3955 __be32 op_to_cctx_size; 3956 __be32 len16_pkd; 3957 __be32 session_id; 3958 __be32 rx_chid_to_rx_q_id; 3959 __be32 key_addr; 3960 __be32 pld_size_hash_size; 3961 __be64 cookie; 3962 }; 3963 3964 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 3965 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 3966 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3967 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3968 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3969 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 3970 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3971 3972 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 3973 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 3974 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3975 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3976 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3977 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 3978 M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3979 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 3980 3981 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 3982 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 3983 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3984 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3985 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3986 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 3987 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3988 3989 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 3990 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 3991 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3992 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3993 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3994 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 3995 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3996 3997 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 3998 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 3999 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4000 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4001 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4002 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 4003 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4004 4005 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 4006 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 4007 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4008 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4009 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4010 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 4011 M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4012 4013 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 4014 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 4015 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4016 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4017 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4018 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 4019 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4020 4021 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 4022 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 4023 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4024 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 4025 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4026 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 4027 4028 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 4029 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 4030 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4031 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4032 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4033 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 4034 M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4035 4036 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 4037 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 4038 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4039 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 4040 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4041 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 4042 4043 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 4044 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 4045 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4046 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4047 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4048 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 4049 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4050 4051 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 4052 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 4053 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4054 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4055 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4056 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 4057 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4058 4059 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 4060 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 4061 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4062 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4063 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4064 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 4065 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4066 4067 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 4068 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 4069 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4070 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4071 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4072 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 4073 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4074 4075 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 4076 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 4077 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4078 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4079 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4080 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 4081 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4082 4083 /****************************************************************************** 4084 * C O M M A N D s 4085 *********************/ 4086 4087 /* 4088 * The maximum length of time, in miliseconds, that we expect any firmware 4089 * command to take to execute and return a reply to the host. The RESET 4090 * and INITIALIZE commands can take a fair amount of time to execute but 4091 * most execute in far less time than this maximum. This constant is used 4092 * by host software to determine how long to wait for a firmware command 4093 * reply before declaring the firmware as dead/unreachable ... 4094 */ 4095 #define FW_CMD_MAX_TIMEOUT 10000 4096 4097 /* 4098 * If a host driver does a HELLO and discovers that there's already a MASTER 4099 * selected, we may have to wait for that MASTER to finish issuing RESET, 4100 * configuration and INITIALIZE commands. Also, there's a possibility that 4101 * our own HELLO may get lost if it happens right as the MASTER is issuign a 4102 * RESET command, so we need to be willing to make a few retries of our HELLO. 4103 */ 4104 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 4105 #define FW_CMD_HELLO_RETRIES 3 4106 4107 enum fw_cmd_opcodes { 4108 FW_LDST_CMD = 0x01, 4109 FW_RESET_CMD = 0x03, 4110 FW_HELLO_CMD = 0x04, 4111 FW_BYE_CMD = 0x05, 4112 FW_INITIALIZE_CMD = 0x06, 4113 FW_CAPS_CONFIG_CMD = 0x07, 4114 FW_PARAMS_CMD = 0x08, 4115 FW_PFVF_CMD = 0x09, 4116 FW_IQ_CMD = 0x10, 4117 FW_EQ_MNGT_CMD = 0x11, 4118 FW_EQ_ETH_CMD = 0x12, 4119 FW_EQ_CTRL_CMD = 0x13, 4120 FW_EQ_OFLD_CMD = 0x21, 4121 FW_VI_CMD = 0x14, 4122 FW_VI_MAC_CMD = 0x15, 4123 FW_VI_RXMODE_CMD = 0x16, 4124 FW_VI_ENABLE_CMD = 0x17, 4125 FW_VI_STATS_CMD = 0x1a, 4126 FW_ACL_MAC_CMD = 0x18, 4127 FW_ACL_VLAN_CMD = 0x19, 4128 FW_PORT_CMD = 0x1b, 4129 FW_PORT_STATS_CMD = 0x1c, 4130 FW_PORT_LB_STATS_CMD = 0x1d, 4131 FW_PORT_TRACE_CMD = 0x1e, 4132 FW_PORT_TRACE_MMAP_CMD = 0x1f, 4133 FW_RSS_IND_TBL_CMD = 0x20, 4134 FW_RSS_GLB_CONFIG_CMD = 0x22, 4135 FW_RSS_VI_CONFIG_CMD = 0x23, 4136 FW_SCHED_CMD = 0x24, 4137 FW_DEVLOG_CMD = 0x25, 4138 FW_WATCHDOG_CMD = 0x27, 4139 FW_CLIP_CMD = 0x28, 4140 FW_CHNET_IFACE_CMD = 0x26, 4141 FW_FCOE_RES_INFO_CMD = 0x31, 4142 FW_FCOE_LINK_CMD = 0x32, 4143 FW_FCOE_VNP_CMD = 0x33, 4144 FW_FCOE_SPARAMS_CMD = 0x35, 4145 FW_FCOE_STATS_CMD = 0x37, 4146 FW_FCOE_FCF_CMD = 0x38, 4147 FW_DCB_IEEE_CMD = 0x3a, 4148 FW_DIAG_CMD = 0x3d, 4149 FW_PTP_CMD = 0x3e, 4150 FW_HMA_CMD = 0x3f, 4151 FW_LASTC2E_CMD = 0x40, 4152 FW_ERROR_CMD = 0x80, 4153 FW_DEBUG_CMD = 0x81, 4154 }; 4155 4156 enum fw_cmd_cap { 4157 FW_CMD_CAP_PF = 0x01, 4158 FW_CMD_CAP_DMAQ = 0x02, 4159 FW_CMD_CAP_PORT = 0x04, 4160 FW_CMD_CAP_PORTPROMISC = 0x08, 4161 FW_CMD_CAP_PORTSTATS = 0x10, 4162 FW_CMD_CAP_VF = 0x80, 4163 }; 4164 4165 /* 4166 * Generic command header flit0 4167 */ 4168 struct fw_cmd_hdr { 4169 __be32 hi; 4170 __be32 lo; 4171 }; 4172 4173 #define S_FW_CMD_OP 24 4174 #define M_FW_CMD_OP 0xff 4175 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 4176 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 4177 4178 #define S_FW_CMD_REQUEST 23 4179 #define M_FW_CMD_REQUEST 0x1 4180 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 4181 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 4182 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 4183 4184 #define S_FW_CMD_READ 22 4185 #define M_FW_CMD_READ 0x1 4186 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 4187 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 4188 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 4189 4190 #define S_FW_CMD_WRITE 21 4191 #define M_FW_CMD_WRITE 0x1 4192 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 4193 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 4194 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 4195 4196 #define S_FW_CMD_EXEC 20 4197 #define M_FW_CMD_EXEC 0x1 4198 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 4199 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 4200 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 4201 4202 #define S_FW_CMD_RAMASK 20 4203 #define M_FW_CMD_RAMASK 0xf 4204 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 4205 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 4206 4207 #define S_FW_CMD_RETVAL 8 4208 #define M_FW_CMD_RETVAL 0xff 4209 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 4210 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 4211 4212 #define S_FW_CMD_LEN16 0 4213 #define M_FW_CMD_LEN16 0xff 4214 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 4215 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 4216 4217 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 4218 4219 /* 4220 * address spaces 4221 */ 4222 enum fw_ldst_addrspc { 4223 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 4224 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 4225 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 4226 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 4227 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 4228 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 4229 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 4230 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 4231 FW_LDST_ADDRSPC_MDIO = 0x0018, 4232 FW_LDST_ADDRSPC_MPS = 0x0020, 4233 FW_LDST_ADDRSPC_FUNC = 0x0028, 4234 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 4235 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 4236 FW_LDST_ADDRSPC_LE = 0x0030, 4237 FW_LDST_ADDRSPC_I2C = 0x0038, 4238 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 4239 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 4240 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 4241 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 4242 }; 4243 4244 /* 4245 * MDIO VSC8634 register access control field 4246 */ 4247 enum fw_ldst_mdio_vsc8634_aid { 4248 FW_LDST_MDIO_VS_STANDARD, 4249 FW_LDST_MDIO_VS_EXTENDED, 4250 FW_LDST_MDIO_VS_GPIO 4251 }; 4252 4253 enum fw_ldst_mps_fid { 4254 FW_LDST_MPS_ATRB, 4255 FW_LDST_MPS_RPLC 4256 }; 4257 4258 enum fw_ldst_func_access_ctl { 4259 FW_LDST_FUNC_ACC_CTL_VIID, 4260 FW_LDST_FUNC_ACC_CTL_FID 4261 }; 4262 4263 enum fw_ldst_func_mod_index { 4264 FW_LDST_FUNC_MPS 4265 }; 4266 4267 struct fw_ldst_cmd { 4268 __be32 op_to_addrspace; 4269 __be32 cycles_to_len16; 4270 union fw_ldst { 4271 struct fw_ldst_addrval { 4272 __be32 addr; 4273 __be32 val; 4274 } addrval; 4275 struct fw_ldst_idctxt { 4276 __be32 physid; 4277 __be32 msg_ctxtflush; 4278 __be32 ctxt_data7; 4279 __be32 ctxt_data6; 4280 __be32 ctxt_data5; 4281 __be32 ctxt_data4; 4282 __be32 ctxt_data3; 4283 __be32 ctxt_data2; 4284 __be32 ctxt_data1; 4285 __be32 ctxt_data0; 4286 } idctxt; 4287 struct fw_ldst_mdio { 4288 __be16 paddr_mmd; 4289 __be16 raddr; 4290 __be16 vctl; 4291 __be16 rval; 4292 } mdio; 4293 struct fw_ldst_cim_rq { 4294 __u8 req_first64[8]; 4295 __u8 req_second64[8]; 4296 __u8 resp_first64[8]; 4297 __u8 resp_second64[8]; 4298 __be32 r3[2]; 4299 } cim_rq; 4300 union fw_ldst_mps { 4301 struct fw_ldst_mps_rplc { 4302 __be16 fid_idx; 4303 __be16 rplcpf_pkd; 4304 __be32 rplc255_224; 4305 __be32 rplc223_192; 4306 __be32 rplc191_160; 4307 __be32 rplc159_128; 4308 __be32 rplc127_96; 4309 __be32 rplc95_64; 4310 __be32 rplc63_32; 4311 __be32 rplc31_0; 4312 } rplc; 4313 struct fw_ldst_mps_atrb { 4314 __be16 fid_mpsid; 4315 __be16 r2[3]; 4316 __be32 r3[2]; 4317 __be32 r4; 4318 __be32 atrb; 4319 __be16 vlan[16]; 4320 } atrb; 4321 } mps; 4322 struct fw_ldst_func { 4323 __u8 access_ctl; 4324 __u8 mod_index; 4325 __be16 ctl_id; 4326 __be32 offset; 4327 __be64 data0; 4328 __be64 data1; 4329 } func; 4330 struct fw_ldst_pcie { 4331 __u8 ctrl_to_fn; 4332 __u8 bnum; 4333 __u8 r; 4334 __u8 ext_r; 4335 __u8 select_naccess; 4336 __u8 pcie_fn; 4337 __be16 nset_pkd; 4338 __be32 data[12]; 4339 } pcie; 4340 struct fw_ldst_i2c_deprecated { 4341 __u8 pid_pkd; 4342 __u8 base; 4343 __u8 boffset; 4344 __u8 data; 4345 __be32 r9; 4346 } i2c_deprecated; 4347 struct fw_ldst_i2c { 4348 __u8 pid; 4349 __u8 did; 4350 __u8 boffset; 4351 __u8 blen; 4352 __be32 r9; 4353 __u8 data[48]; 4354 } i2c; 4355 struct fw_ldst_le { 4356 __be32 index; 4357 __be32 r9; 4358 __u8 val[33]; 4359 __u8 r11[7]; 4360 } le; 4361 } u; 4362 }; 4363 4364 #define S_FW_LDST_CMD_ADDRSPACE 0 4365 #define M_FW_LDST_CMD_ADDRSPACE 0xff 4366 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 4367 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 4368 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 4369 4370 #define S_FW_LDST_CMD_CYCLES 16 4371 #define M_FW_LDST_CMD_CYCLES 0xffff 4372 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 4373 #define G_FW_LDST_CMD_CYCLES(x) \ 4374 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 4375 4376 #define S_FW_LDST_CMD_MSG 31 4377 #define M_FW_LDST_CMD_MSG 0x1 4378 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 4379 #define G_FW_LDST_CMD_MSG(x) \ 4380 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 4381 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 4382 4383 #define S_FW_LDST_CMD_CTXTFLUSH 30 4384 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 4385 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 4386 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 4387 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 4388 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 4389 4390 #define S_FW_LDST_CMD_PADDR 8 4391 #define M_FW_LDST_CMD_PADDR 0x1f 4392 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 4393 #define G_FW_LDST_CMD_PADDR(x) \ 4394 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 4395 4396 #define S_FW_LDST_CMD_MMD 0 4397 #define M_FW_LDST_CMD_MMD 0x1f 4398 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 4399 #define G_FW_LDST_CMD_MMD(x) \ 4400 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 4401 4402 #define S_FW_LDST_CMD_FID 15 4403 #define M_FW_LDST_CMD_FID 0x1 4404 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 4405 #define G_FW_LDST_CMD_FID(x) \ 4406 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 4407 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 4408 4409 #define S_FW_LDST_CMD_IDX 0 4410 #define M_FW_LDST_CMD_IDX 0x7fff 4411 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 4412 #define G_FW_LDST_CMD_IDX(x) \ 4413 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 4414 4415 #define S_FW_LDST_CMD_RPLCPF 0 4416 #define M_FW_LDST_CMD_RPLCPF 0xff 4417 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 4418 #define G_FW_LDST_CMD_RPLCPF(x) \ 4419 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 4420 4421 #define S_FW_LDST_CMD_MPSID 0 4422 #define M_FW_LDST_CMD_MPSID 0x7fff 4423 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 4424 #define G_FW_LDST_CMD_MPSID(x) \ 4425 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 4426 4427 #define S_FW_LDST_CMD_CTRL 7 4428 #define M_FW_LDST_CMD_CTRL 0x1 4429 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 4430 #define G_FW_LDST_CMD_CTRL(x) \ 4431 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 4432 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 4433 4434 #define S_FW_LDST_CMD_LC 4 4435 #define M_FW_LDST_CMD_LC 0x1 4436 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 4437 #define G_FW_LDST_CMD_LC(x) \ 4438 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 4439 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 4440 4441 #define S_FW_LDST_CMD_AI 3 4442 #define M_FW_LDST_CMD_AI 0x1 4443 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 4444 #define G_FW_LDST_CMD_AI(x) \ 4445 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 4446 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 4447 4448 #define S_FW_LDST_CMD_FN 0 4449 #define M_FW_LDST_CMD_FN 0x7 4450 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 4451 #define G_FW_LDST_CMD_FN(x) \ 4452 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 4453 4454 #define S_FW_LDST_CMD_SELECT 4 4455 #define M_FW_LDST_CMD_SELECT 0xf 4456 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 4457 #define G_FW_LDST_CMD_SELECT(x) \ 4458 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 4459 4460 #define S_FW_LDST_CMD_NACCESS 0 4461 #define M_FW_LDST_CMD_NACCESS 0xf 4462 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 4463 #define G_FW_LDST_CMD_NACCESS(x) \ 4464 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 4465 4466 #define S_FW_LDST_CMD_NSET 14 4467 #define M_FW_LDST_CMD_NSET 0x3 4468 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 4469 #define G_FW_LDST_CMD_NSET(x) \ 4470 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 4471 4472 #define S_FW_LDST_CMD_PID 6 4473 #define M_FW_LDST_CMD_PID 0x3 4474 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 4475 #define G_FW_LDST_CMD_PID(x) \ 4476 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 4477 4478 struct fw_reset_cmd { 4479 __be32 op_to_write; 4480 __be32 retval_len16; 4481 __be32 val; 4482 __be32 halt_pkd; 4483 }; 4484 4485 #define S_FW_RESET_CMD_HALT 31 4486 #define M_FW_RESET_CMD_HALT 0x1 4487 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 4488 #define G_FW_RESET_CMD_HALT(x) \ 4489 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 4490 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 4491 4492 enum { 4493 FW_HELLO_CMD_STAGE_OS = 0, 4494 FW_HELLO_CMD_STAGE_PREOS0 = 1, 4495 FW_HELLO_CMD_STAGE_PREOS1 = 2, 4496 FW_HELLO_CMD_STAGE_POSTOS = 3, 4497 }; 4498 4499 struct fw_hello_cmd { 4500 __be32 op_to_write; 4501 __be32 retval_len16; 4502 __be32 err_to_clearinit; 4503 __be32 fwrev; 4504 }; 4505 4506 #define S_FW_HELLO_CMD_ERR 31 4507 #define M_FW_HELLO_CMD_ERR 0x1 4508 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 4509 #define G_FW_HELLO_CMD_ERR(x) \ 4510 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 4511 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 4512 4513 #define S_FW_HELLO_CMD_INIT 30 4514 #define M_FW_HELLO_CMD_INIT 0x1 4515 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 4516 #define G_FW_HELLO_CMD_INIT(x) \ 4517 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 4518 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 4519 4520 #define S_FW_HELLO_CMD_MASTERDIS 29 4521 #define M_FW_HELLO_CMD_MASTERDIS 0x1 4522 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 4523 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 4524 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 4525 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 4526 4527 #define S_FW_HELLO_CMD_MASTERFORCE 28 4528 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 4529 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 4530 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 4531 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 4532 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 4533 4534 #define S_FW_HELLO_CMD_MBMASTER 24 4535 #define M_FW_HELLO_CMD_MBMASTER 0xf 4536 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 4537 #define G_FW_HELLO_CMD_MBMASTER(x) \ 4538 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 4539 4540 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 4541 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 4542 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 4543 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 4544 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 4545 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 4546 4547 #define S_FW_HELLO_CMD_MBASYNCNOT 20 4548 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 4549 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 4550 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 4551 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 4552 4553 #define S_FW_HELLO_CMD_STAGE 17 4554 #define M_FW_HELLO_CMD_STAGE 0x7 4555 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 4556 #define G_FW_HELLO_CMD_STAGE(x) \ 4557 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 4558 4559 #define S_FW_HELLO_CMD_CLEARINIT 16 4560 #define M_FW_HELLO_CMD_CLEARINIT 0x1 4561 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 4562 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 4563 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 4564 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 4565 4566 struct fw_bye_cmd { 4567 __be32 op_to_write; 4568 __be32 retval_len16; 4569 __be64 r3; 4570 }; 4571 4572 struct fw_initialize_cmd { 4573 __be32 op_to_write; 4574 __be32 retval_len16; 4575 __be64 r3; 4576 }; 4577 4578 enum fw_caps_config_hm { 4579 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 4580 FW_CAPS_CONFIG_HM_PL = 0x00000002, 4581 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 4582 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 4583 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 4584 FW_CAPS_CONFIG_HM_TP = 0x00000020, 4585 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 4586 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 4587 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 4588 FW_CAPS_CONFIG_HM_MC = 0x00000200, 4589 FW_CAPS_CONFIG_HM_LE = 0x00000400, 4590 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 4591 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 4592 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 4593 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 4594 FW_CAPS_CONFIG_HM_MI = 0x00008000, 4595 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 4596 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 4597 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 4598 FW_CAPS_CONFIG_HM_MA = 0x00080000, 4599 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 4600 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 4601 FW_CAPS_CONFIG_HM_UART = 0x00400000, 4602 FW_CAPS_CONFIG_HM_SF = 0x00800000, 4603 }; 4604 4605 /* 4606 * The VF Register Map. 4607 * 4608 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 4609 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 4610 * the Slice to Module Map Table (see below) in the Physical Function Register 4611 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 4612 * and Offset registers in the PF Register Map. The MBDATA base address is 4613 * quite constrained as it determines the Mailbox Data addresses for both PFs 4614 * and VFs, and therefore must fit in both the VF and PF Register Maps without 4615 * overlapping other registers. 4616 */ 4617 #define FW_T4VF_SGE_BASE_ADDR 0x0000 4618 #define FW_T4VF_MPS_BASE_ADDR 0x0100 4619 #define FW_T4VF_PL_BASE_ADDR 0x0200 4620 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4621 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4622 #define FW_T4VF_CIM_BASE_ADDR 0x0300 4623 4624 #define FW_T4VF_REGMAP_START 0x0000 4625 #define FW_T4VF_REGMAP_SIZE 0x0400 4626 4627 enum fw_caps_config_nbm { 4628 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 4629 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 4630 }; 4631 4632 enum fw_caps_config_link { 4633 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 4634 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 4635 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 4636 }; 4637 4638 enum fw_caps_config_switch { 4639 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 4640 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 4641 }; 4642 4643 enum fw_caps_config_nic { 4644 FW_CAPS_CONFIG_NIC = 0x00000001, 4645 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 4646 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 4647 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 4648 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4649 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4650 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 4651 }; 4652 4653 enum fw_caps_config_toe { 4654 FW_CAPS_CONFIG_TOE = 0x00000001, 4655 }; 4656 4657 enum fw_caps_config_rdma { 4658 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 4659 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 4660 }; 4661 4662 enum fw_caps_config_iscsi { 4663 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 4664 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 4665 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 4666 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 4667 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 4668 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4669 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4670 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4671 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4672 }; 4673 4674 enum fw_caps_config_crypto { 4675 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 4676 FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 4677 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004, 4678 }; 4679 4680 enum fw_caps_config_fcoe { 4681 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 4682 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 4683 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4684 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4685 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 4686 }; 4687 4688 enum fw_memtype_cf { 4689 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4690 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4691 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4692 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4693 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4694 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 4695 }; 4696 4697 struct fw_caps_config_cmd { 4698 __be32 op_to_write; 4699 __be32 cfvalid_to_len16; 4700 __be32 r2; 4701 __be32 hwmbitmap; 4702 __be16 nbmcaps; 4703 __be16 linkcaps; 4704 __be16 switchcaps; 4705 __be16 r3; 4706 __be16 niccaps; 4707 __be16 toecaps; 4708 __be16 rdmacaps; 4709 __be16 cryptocaps; 4710 __be16 iscsicaps; 4711 __be16 fcoecaps; 4712 __be32 cfcsum; 4713 __be32 finiver; 4714 __be32 finicsum; 4715 }; 4716 4717 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4718 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4719 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4720 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4721 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4722 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4723 4724 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4725 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4726 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4727 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4728 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4729 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4730 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4731 4732 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4733 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4734 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4735 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4736 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4737 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4738 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4739 4740 /* 4741 * params command mnemonics 4742 */ 4743 enum fw_params_mnem { 4744 FW_PARAMS_MNEM_DEV = 1, /* device params */ 4745 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 4746 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 4747 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4748 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 4749 FW_PARAMS_MNEM_LAST 4750 }; 4751 4752 /* 4753 * device parameters 4754 */ 4755 enum fw_params_param_dev { 4756 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 4757 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4758 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4759 * allocated by the device's 4760 * Lookup Engine 4761 */ 4762 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 4763 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 4764 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 4765 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 4766 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 4767 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 4768 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 4769 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4770 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4771 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4772 FW_PARAMS_PARAM_DEV_CF = 0x0D, 4773 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4774 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4775 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4776 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4777 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4778 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4779 */ 4780 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4781 */ 4782 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4783 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4784 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4785 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4786 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4787 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 4788 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 4789 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 4790 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 4791 4792 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 4793 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 4794 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 4795 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 4796 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22, 4797 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 4798 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 4799 FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25, 4800 FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26, 4801 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 4802 }; 4803 4804 /* 4805 * dev bypass parameters; actions and modes 4806 */ 4807 enum fw_params_param_dev_bypass { 4808 4809 /* actions 4810 */ 4811 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4812 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4813 4814 /* modes 4815 */ 4816 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4817 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4818 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4819 }; 4820 4821 enum fw_params_param_dev_phyfw { 4822 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4823 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4824 }; 4825 4826 enum fw_params_param_dev_diag { 4827 FW_PARAM_DEV_DIAG_TMP = 0x00, 4828 FW_PARAM_DEV_DIAG_VDD = 0x01, 4829 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 4830 }; 4831 4832 enum fw_params_param_dev_fwcache { 4833 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4834 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 4835 }; 4836 4837 /* 4838 * physical and virtual function parameters 4839 */ 4840 enum fw_params_param_pfvf { 4841 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 4842 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 4843 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 4844 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 4845 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 4846 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 4847 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 4848 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 4849 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 4850 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 4851 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 4852 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 4853 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 4854 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 4855 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 4856 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 4857 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 4858 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 4859 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 4860 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 4861 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 4862 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 4863 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 4864 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 4865 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4866 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4867 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 4868 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 4869 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 4870 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 4871 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 4872 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 4873 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 4874 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 4875 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 4876 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 4877 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 4878 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 4879 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 4880 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4881 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4882 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4883 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4884 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4885 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4886 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4887 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4888 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4889 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 4890 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 4891 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 4892 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 4893 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 4894 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, 4895 }; 4896 4897 /* 4898 * dma queue parameters 4899 */ 4900 enum fw_params_param_dmaq { 4901 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 4902 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4903 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4904 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 4905 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 4906 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 4907 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4908 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4909 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4910 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4911 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 4912 }; 4913 4914 /* 4915 * chnet parameters 4916 */ 4917 enum fw_params_param_chnet { 4918 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4919 }; 4920 4921 enum fw_params_param_chnet_flags { 4922 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4923 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4924 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4925 }; 4926 4927 #define S_FW_PARAMS_MNEM 24 4928 #define M_FW_PARAMS_MNEM 0xff 4929 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 4930 #define G_FW_PARAMS_MNEM(x) \ 4931 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 4932 4933 #define S_FW_PARAMS_PARAM_X 16 4934 #define M_FW_PARAMS_PARAM_X 0xff 4935 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 4936 #define G_FW_PARAMS_PARAM_X(x) \ 4937 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 4938 4939 #define S_FW_PARAMS_PARAM_Y 8 4940 #define M_FW_PARAMS_PARAM_Y 0xff 4941 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 4942 #define G_FW_PARAMS_PARAM_Y(x) \ 4943 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 4944 4945 #define S_FW_PARAMS_PARAM_Z 0 4946 #define M_FW_PARAMS_PARAM_Z 0xff 4947 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 4948 #define G_FW_PARAMS_PARAM_Z(x) \ 4949 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 4950 4951 #define S_FW_PARAMS_PARAM_XYZ 0 4952 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 4953 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 4954 #define G_FW_PARAMS_PARAM_XYZ(x) \ 4955 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 4956 4957 #define S_FW_PARAMS_PARAM_YZ 0 4958 #define M_FW_PARAMS_PARAM_YZ 0xffff 4959 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 4960 #define G_FW_PARAMS_PARAM_YZ(x) \ 4961 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 4962 4963 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 4964 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 4965 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4966 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4967 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4968 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 4969 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4970 4971 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 4972 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 4973 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4974 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4975 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4976 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 4977 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4978 4979 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 4980 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 4981 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4982 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4983 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4984 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4985 4986 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 4987 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 4988 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4989 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4990 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4991 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 4992 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4993 4994 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 4995 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 4996 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4997 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 4998 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4999 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 5000 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 5001 5002 struct fw_params_cmd { 5003 __be32 op_to_vfn; 5004 __be32 retval_len16; 5005 struct fw_params_param { 5006 __be32 mnem; 5007 __be32 val; 5008 } param[7]; 5009 }; 5010 5011 #define S_FW_PARAMS_CMD_PFN 8 5012 #define M_FW_PARAMS_CMD_PFN 0x7 5013 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 5014 #define G_FW_PARAMS_CMD_PFN(x) \ 5015 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 5016 5017 #define S_FW_PARAMS_CMD_VFN 0 5018 #define M_FW_PARAMS_CMD_VFN 0xff 5019 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 5020 #define G_FW_PARAMS_CMD_VFN(x) \ 5021 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 5022 5023 struct fw_pfvf_cmd { 5024 __be32 op_to_vfn; 5025 __be32 retval_len16; 5026 __be32 niqflint_niq; 5027 __be32 type_to_neq; 5028 __be32 tc_to_nexactf; 5029 __be32 r_caps_to_nethctrl; 5030 __be16 nricq; 5031 __be16 nriqp; 5032 __be32 r4; 5033 }; 5034 5035 #define S_FW_PFVF_CMD_PFN 8 5036 #define M_FW_PFVF_CMD_PFN 0x7 5037 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 5038 #define G_FW_PFVF_CMD_PFN(x) \ 5039 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 5040 5041 #define S_FW_PFVF_CMD_VFN 0 5042 #define M_FW_PFVF_CMD_VFN 0xff 5043 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 5044 #define G_FW_PFVF_CMD_VFN(x) \ 5045 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 5046 5047 #define S_FW_PFVF_CMD_NIQFLINT 20 5048 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 5049 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 5050 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 5051 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 5052 5053 #define S_FW_PFVF_CMD_NIQ 0 5054 #define M_FW_PFVF_CMD_NIQ 0xfffff 5055 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 5056 #define G_FW_PFVF_CMD_NIQ(x) \ 5057 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 5058 5059 #define S_FW_PFVF_CMD_TYPE 31 5060 #define M_FW_PFVF_CMD_TYPE 0x1 5061 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 5062 #define G_FW_PFVF_CMD_TYPE(x) \ 5063 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 5064 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 5065 5066 #define S_FW_PFVF_CMD_CMASK 24 5067 #define M_FW_PFVF_CMD_CMASK 0xf 5068 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 5069 #define G_FW_PFVF_CMD_CMASK(x) \ 5070 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 5071 5072 #define S_FW_PFVF_CMD_PMASK 20 5073 #define M_FW_PFVF_CMD_PMASK 0xf 5074 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 5075 #define G_FW_PFVF_CMD_PMASK(x) \ 5076 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 5077 5078 #define S_FW_PFVF_CMD_NEQ 0 5079 #define M_FW_PFVF_CMD_NEQ 0xfffff 5080 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 5081 #define G_FW_PFVF_CMD_NEQ(x) \ 5082 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 5083 5084 #define S_FW_PFVF_CMD_TC 24 5085 #define M_FW_PFVF_CMD_TC 0xff 5086 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 5087 #define G_FW_PFVF_CMD_TC(x) \ 5088 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 5089 5090 #define S_FW_PFVF_CMD_NVI 16 5091 #define M_FW_PFVF_CMD_NVI 0xff 5092 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 5093 #define G_FW_PFVF_CMD_NVI(x) \ 5094 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 5095 5096 #define S_FW_PFVF_CMD_NEXACTF 0 5097 #define M_FW_PFVF_CMD_NEXACTF 0xffff 5098 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 5099 #define G_FW_PFVF_CMD_NEXACTF(x) \ 5100 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 5101 5102 #define S_FW_PFVF_CMD_R_CAPS 24 5103 #define M_FW_PFVF_CMD_R_CAPS 0xff 5104 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 5105 #define G_FW_PFVF_CMD_R_CAPS(x) \ 5106 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 5107 5108 #define S_FW_PFVF_CMD_WX_CAPS 16 5109 #define M_FW_PFVF_CMD_WX_CAPS 0xff 5110 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 5111 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 5112 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 5113 5114 #define S_FW_PFVF_CMD_NETHCTRL 0 5115 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 5116 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 5117 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 5118 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 5119 5120 /* 5121 * ingress queue type; the first 1K ingress queues can have associated 0, 5122 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 5123 * capabilities 5124 */ 5125 enum fw_iq_type { 5126 FW_IQ_TYPE_FL_INT_CAP, 5127 FW_IQ_TYPE_NO_FL_INT_CAP, 5128 FW_IQ_TYPE_VF_CQ 5129 }; 5130 5131 enum fw_iq_iqtype { 5132 FW_IQ_IQTYPE_OTHER, 5133 FW_IQ_IQTYPE_NIC, 5134 FW_IQ_IQTYPE_OFLD, 5135 }; 5136 5137 struct fw_iq_cmd { 5138 __be32 op_to_vfn; 5139 __be32 alloc_to_len16; 5140 __be16 physiqid; 5141 __be16 iqid; 5142 __be16 fl0id; 5143 __be16 fl1id; 5144 __be32 type_to_iqandstindex; 5145 __be16 iqdroprss_to_iqesize; 5146 __be16 iqsize; 5147 __be64 iqaddr; 5148 __be32 iqns_to_fl0congen; 5149 __be16 fl0dcaen_to_fl0cidxfthresh; 5150 __be16 fl0size; 5151 __be64 fl0addr; 5152 __be32 fl1cngchmap_to_fl1congen; 5153 __be16 fl1dcaen_to_fl1cidxfthresh; 5154 __be16 fl1size; 5155 __be64 fl1addr; 5156 }; 5157 5158 #define S_FW_IQ_CMD_PFN 8 5159 #define M_FW_IQ_CMD_PFN 0x7 5160 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 5161 #define G_FW_IQ_CMD_PFN(x) \ 5162 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 5163 5164 #define S_FW_IQ_CMD_VFN 0 5165 #define M_FW_IQ_CMD_VFN 0xff 5166 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 5167 #define G_FW_IQ_CMD_VFN(x) \ 5168 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 5169 5170 #define S_FW_IQ_CMD_ALLOC 31 5171 #define M_FW_IQ_CMD_ALLOC 0x1 5172 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 5173 #define G_FW_IQ_CMD_ALLOC(x) \ 5174 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 5175 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 5176 5177 #define S_FW_IQ_CMD_FREE 30 5178 #define M_FW_IQ_CMD_FREE 0x1 5179 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 5180 #define G_FW_IQ_CMD_FREE(x) \ 5181 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 5182 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 5183 5184 #define S_FW_IQ_CMD_MODIFY 29 5185 #define M_FW_IQ_CMD_MODIFY 0x1 5186 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 5187 #define G_FW_IQ_CMD_MODIFY(x) \ 5188 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 5189 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 5190 5191 #define S_FW_IQ_CMD_IQSTART 28 5192 #define M_FW_IQ_CMD_IQSTART 0x1 5193 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 5194 #define G_FW_IQ_CMD_IQSTART(x) \ 5195 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 5196 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 5197 5198 #define S_FW_IQ_CMD_IQSTOP 27 5199 #define M_FW_IQ_CMD_IQSTOP 0x1 5200 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 5201 #define G_FW_IQ_CMD_IQSTOP(x) \ 5202 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 5203 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 5204 5205 #define S_FW_IQ_CMD_TYPE 29 5206 #define M_FW_IQ_CMD_TYPE 0x7 5207 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 5208 #define G_FW_IQ_CMD_TYPE(x) \ 5209 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 5210 5211 #define S_FW_IQ_CMD_IQASYNCH 28 5212 #define M_FW_IQ_CMD_IQASYNCH 0x1 5213 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 5214 #define G_FW_IQ_CMD_IQASYNCH(x) \ 5215 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 5216 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 5217 5218 #define S_FW_IQ_CMD_VIID 16 5219 #define M_FW_IQ_CMD_VIID 0xfff 5220 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 5221 #define G_FW_IQ_CMD_VIID(x) \ 5222 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 5223 5224 #define S_FW_IQ_CMD_IQANDST 15 5225 #define M_FW_IQ_CMD_IQANDST 0x1 5226 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 5227 #define G_FW_IQ_CMD_IQANDST(x) \ 5228 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 5229 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 5230 5231 #define S_FW_IQ_CMD_IQANUS 14 5232 #define M_FW_IQ_CMD_IQANUS 0x1 5233 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 5234 #define G_FW_IQ_CMD_IQANUS(x) \ 5235 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 5236 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 5237 5238 #define S_FW_IQ_CMD_IQANUD 12 5239 #define M_FW_IQ_CMD_IQANUD 0x3 5240 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 5241 #define G_FW_IQ_CMD_IQANUD(x) \ 5242 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 5243 5244 #define S_FW_IQ_CMD_IQANDSTINDEX 0 5245 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 5246 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 5247 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 5248 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 5249 5250 #define S_FW_IQ_CMD_IQDROPRSS 15 5251 #define M_FW_IQ_CMD_IQDROPRSS 0x1 5252 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 5253 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 5254 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 5255 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 5256 5257 #define S_FW_IQ_CMD_IQGTSMODE 14 5258 #define M_FW_IQ_CMD_IQGTSMODE 0x1 5259 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 5260 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 5261 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 5262 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 5263 5264 #define S_FW_IQ_CMD_IQPCIECH 12 5265 #define M_FW_IQ_CMD_IQPCIECH 0x3 5266 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 5267 #define G_FW_IQ_CMD_IQPCIECH(x) \ 5268 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 5269 5270 #define S_FW_IQ_CMD_IQDCAEN 11 5271 #define M_FW_IQ_CMD_IQDCAEN 0x1 5272 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 5273 #define G_FW_IQ_CMD_IQDCAEN(x) \ 5274 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 5275 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 5276 5277 #define S_FW_IQ_CMD_IQDCACPU 6 5278 #define M_FW_IQ_CMD_IQDCACPU 0x1f 5279 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 5280 #define G_FW_IQ_CMD_IQDCACPU(x) \ 5281 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 5282 5283 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 5284 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 5285 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 5286 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 5287 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 5288 5289 #define S_FW_IQ_CMD_IQO 3 5290 #define M_FW_IQ_CMD_IQO 0x1 5291 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 5292 #define G_FW_IQ_CMD_IQO(x) \ 5293 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 5294 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 5295 5296 #define S_FW_IQ_CMD_IQCPRIO 2 5297 #define M_FW_IQ_CMD_IQCPRIO 0x1 5298 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 5299 #define G_FW_IQ_CMD_IQCPRIO(x) \ 5300 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 5301 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 5302 5303 #define S_FW_IQ_CMD_IQESIZE 0 5304 #define M_FW_IQ_CMD_IQESIZE 0x3 5305 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 5306 #define G_FW_IQ_CMD_IQESIZE(x) \ 5307 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 5308 5309 #define S_FW_IQ_CMD_IQNS 31 5310 #define M_FW_IQ_CMD_IQNS 0x1 5311 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 5312 #define G_FW_IQ_CMD_IQNS(x) \ 5313 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 5314 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 5315 5316 #define S_FW_IQ_CMD_IQRO 30 5317 #define M_FW_IQ_CMD_IQRO 0x1 5318 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 5319 #define G_FW_IQ_CMD_IQRO(x) \ 5320 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 5321 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 5322 5323 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 5324 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 5325 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 5326 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 5327 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 5328 5329 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 5330 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 5331 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 5332 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 5333 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 5334 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 5335 5336 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 5337 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 5338 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 5339 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 5340 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 5341 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 5342 5343 #define S_FW_IQ_CMD_IQTYPE 24 5344 #define M_FW_IQ_CMD_IQTYPE 0x3 5345 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 5346 #define G_FW_IQ_CMD_IQTYPE(x) \ 5347 (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE) 5348 5349 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 5350 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 5351 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 5352 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 5353 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 5354 5355 #define S_FW_IQ_CMD_FL0CONGDROP 16 5356 #define M_FW_IQ_CMD_FL0CONGDROP 0x1 5357 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 5358 #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 5359 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 5360 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 5361 5362 #define S_FW_IQ_CMD_FL0CACHELOCK 15 5363 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 5364 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 5365 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 5366 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 5367 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 5368 5369 #define S_FW_IQ_CMD_FL0DBP 14 5370 #define M_FW_IQ_CMD_FL0DBP 0x1 5371 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 5372 #define G_FW_IQ_CMD_FL0DBP(x) \ 5373 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 5374 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 5375 5376 #define S_FW_IQ_CMD_FL0DATANS 13 5377 #define M_FW_IQ_CMD_FL0DATANS 0x1 5378 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 5379 #define G_FW_IQ_CMD_FL0DATANS(x) \ 5380 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 5381 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 5382 5383 #define S_FW_IQ_CMD_FL0DATARO 12 5384 #define M_FW_IQ_CMD_FL0DATARO 0x1 5385 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 5386 #define G_FW_IQ_CMD_FL0DATARO(x) \ 5387 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 5388 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 5389 5390 #define S_FW_IQ_CMD_FL0CONGCIF 11 5391 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 5392 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 5393 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 5394 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 5395 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 5396 5397 #define S_FW_IQ_CMD_FL0ONCHIP 10 5398 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 5399 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 5400 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 5401 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 5402 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 5403 5404 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 5405 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 5406 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 5407 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 5408 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 5409 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 5410 5411 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 5412 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 5413 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 5414 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 5415 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 5416 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 5417 5418 #define S_FW_IQ_CMD_FL0FETCHNS 7 5419 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 5420 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 5421 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 5422 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 5423 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 5424 5425 #define S_FW_IQ_CMD_FL0FETCHRO 6 5426 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 5427 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 5428 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 5429 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 5430 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 5431 5432 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 5433 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 5434 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 5435 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 5436 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 5437 5438 #define S_FW_IQ_CMD_FL0CPRIO 3 5439 #define M_FW_IQ_CMD_FL0CPRIO 0x1 5440 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 5441 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 5442 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 5443 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 5444 5445 #define S_FW_IQ_CMD_FL0PADEN 2 5446 #define M_FW_IQ_CMD_FL0PADEN 0x1 5447 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 5448 #define G_FW_IQ_CMD_FL0PADEN(x) \ 5449 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 5450 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 5451 5452 #define S_FW_IQ_CMD_FL0PACKEN 1 5453 #define M_FW_IQ_CMD_FL0PACKEN 0x1 5454 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 5455 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 5456 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 5457 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 5458 5459 #define S_FW_IQ_CMD_FL0CONGEN 0 5460 #define M_FW_IQ_CMD_FL0CONGEN 0x1 5461 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 5462 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 5463 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 5464 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 5465 5466 #define S_FW_IQ_CMD_FL0DCAEN 15 5467 #define M_FW_IQ_CMD_FL0DCAEN 0x1 5468 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 5469 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 5470 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 5471 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 5472 5473 #define S_FW_IQ_CMD_FL0DCACPU 10 5474 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 5475 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 5476 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 5477 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 5478 5479 #define S_FW_IQ_CMD_FL0FBMIN 7 5480 #define M_FW_IQ_CMD_FL0FBMIN 0x7 5481 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 5482 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 5483 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 5484 5485 #define S_FW_IQ_CMD_FL0FBMAX 4 5486 #define M_FW_IQ_CMD_FL0FBMAX 0x7 5487 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 5488 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 5489 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 5490 5491 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 5492 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 5493 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 5494 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 5495 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 5496 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 5497 5498 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 5499 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 5500 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 5501 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 5502 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 5503 5504 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 5505 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 5506 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 5507 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 5508 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 5509 5510 #define S_FW_IQ_CMD_FL1CONGDROP 16 5511 #define M_FW_IQ_CMD_FL1CONGDROP 0x1 5512 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 5513 #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 5514 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 5515 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 5516 5517 #define S_FW_IQ_CMD_FL1CACHELOCK 15 5518 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 5519 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 5520 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 5521 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 5522 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 5523 5524 #define S_FW_IQ_CMD_FL1DBP 14 5525 #define M_FW_IQ_CMD_FL1DBP 0x1 5526 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 5527 #define G_FW_IQ_CMD_FL1DBP(x) \ 5528 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 5529 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 5530 5531 #define S_FW_IQ_CMD_FL1DATANS 13 5532 #define M_FW_IQ_CMD_FL1DATANS 0x1 5533 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 5534 #define G_FW_IQ_CMD_FL1DATANS(x) \ 5535 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 5536 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 5537 5538 #define S_FW_IQ_CMD_FL1DATARO 12 5539 #define M_FW_IQ_CMD_FL1DATARO 0x1 5540 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 5541 #define G_FW_IQ_CMD_FL1DATARO(x) \ 5542 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 5543 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 5544 5545 #define S_FW_IQ_CMD_FL1CONGCIF 11 5546 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 5547 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 5548 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 5549 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 5550 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 5551 5552 #define S_FW_IQ_CMD_FL1ONCHIP 10 5553 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 5554 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 5555 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 5556 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 5557 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 5558 5559 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 5560 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 5561 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 5562 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 5563 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 5564 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 5565 5566 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 5567 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 5568 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 5569 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 5570 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 5571 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 5572 5573 #define S_FW_IQ_CMD_FL1FETCHNS 7 5574 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 5575 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 5576 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 5577 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 5578 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 5579 5580 #define S_FW_IQ_CMD_FL1FETCHRO 6 5581 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 5582 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 5583 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 5584 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 5585 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 5586 5587 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 5588 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 5589 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 5590 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 5591 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 5592 5593 #define S_FW_IQ_CMD_FL1CPRIO 3 5594 #define M_FW_IQ_CMD_FL1CPRIO 0x1 5595 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 5596 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 5597 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 5598 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 5599 5600 #define S_FW_IQ_CMD_FL1PADEN 2 5601 #define M_FW_IQ_CMD_FL1PADEN 0x1 5602 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 5603 #define G_FW_IQ_CMD_FL1PADEN(x) \ 5604 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 5605 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 5606 5607 #define S_FW_IQ_CMD_FL1PACKEN 1 5608 #define M_FW_IQ_CMD_FL1PACKEN 0x1 5609 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 5610 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 5611 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 5612 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 5613 5614 #define S_FW_IQ_CMD_FL1CONGEN 0 5615 #define M_FW_IQ_CMD_FL1CONGEN 0x1 5616 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 5617 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 5618 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 5619 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 5620 5621 #define S_FW_IQ_CMD_FL1DCAEN 15 5622 #define M_FW_IQ_CMD_FL1DCAEN 0x1 5623 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 5624 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 5625 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 5626 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 5627 5628 #define S_FW_IQ_CMD_FL1DCACPU 10 5629 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 5630 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 5631 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 5632 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 5633 5634 #define S_FW_IQ_CMD_FL1FBMIN 7 5635 #define M_FW_IQ_CMD_FL1FBMIN 0x7 5636 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 5637 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 5638 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 5639 5640 #define S_FW_IQ_CMD_FL1FBMAX 4 5641 #define M_FW_IQ_CMD_FL1FBMAX 0x7 5642 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 5643 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 5644 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 5645 5646 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 5647 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 5648 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 5649 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 5650 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 5651 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 5652 5653 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 5654 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 5655 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 5656 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 5657 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 5658 5659 struct fw_eq_mngt_cmd { 5660 __be32 op_to_vfn; 5661 __be32 alloc_to_len16; 5662 __be32 cmpliqid_eqid; 5663 __be32 physeqid_pkd; 5664 __be32 fetchszm_to_iqid; 5665 __be32 dcaen_to_eqsize; 5666 __be64 eqaddr; 5667 }; 5668 5669 #define S_FW_EQ_MNGT_CMD_PFN 8 5670 #define M_FW_EQ_MNGT_CMD_PFN 0x7 5671 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5672 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 5673 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5674 5675 #define S_FW_EQ_MNGT_CMD_VFN 0 5676 #define M_FW_EQ_MNGT_CMD_VFN 0xff 5677 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5678 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 5679 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5680 5681 #define S_FW_EQ_MNGT_CMD_ALLOC 31 5682 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5683 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5684 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5685 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5686 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5687 5688 #define S_FW_EQ_MNGT_CMD_FREE 30 5689 #define M_FW_EQ_MNGT_CMD_FREE 0x1 5690 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5691 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 5692 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5693 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5694 5695 #define S_FW_EQ_MNGT_CMD_MODIFY 29 5696 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5697 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5698 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5699 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5700 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5701 5702 #define S_FW_EQ_MNGT_CMD_EQSTART 28 5703 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5704 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5705 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5706 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5707 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5708 5709 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 5710 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5711 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5712 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5713 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5714 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5715 5716 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5717 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5718 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5719 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5720 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5721 5722 #define S_FW_EQ_MNGT_CMD_EQID 0 5723 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5724 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5725 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 5726 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5727 5728 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5729 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5730 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5731 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5732 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5733 5734 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5735 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5736 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5737 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5738 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5739 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5740 5741 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5742 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5743 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5744 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5745 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5746 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5747 5748 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5749 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5750 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5751 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5752 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5753 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5754 5755 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 5756 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5757 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5758 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5759 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5760 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5761 5762 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 5763 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5764 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5765 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5766 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5767 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5768 5769 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5770 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5771 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5772 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5773 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5774 5775 #define S_FW_EQ_MNGT_CMD_CPRIO 19 5776 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5777 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5778 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5779 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5780 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5781 5782 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 5783 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5784 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5785 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5786 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5787 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5788 5789 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 5790 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5791 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5792 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5793 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5794 5795 #define S_FW_EQ_MNGT_CMD_IQID 0 5796 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 5797 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5798 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 5799 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5800 5801 #define S_FW_EQ_MNGT_CMD_DCAEN 31 5802 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5803 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5804 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5805 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5806 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5807 5808 #define S_FW_EQ_MNGT_CMD_DCACPU 26 5809 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5810 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5811 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5812 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5813 5814 #define S_FW_EQ_MNGT_CMD_FBMIN 23 5815 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5816 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5817 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5818 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5819 5820 #define S_FW_EQ_MNGT_CMD_FBMAX 20 5821 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5822 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5823 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5824 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5825 5826 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5827 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5828 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5829 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5830 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5831 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5832 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5833 5834 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5835 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5836 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5837 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5838 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5839 5840 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 5841 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5842 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5843 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5844 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 5845 5846 struct fw_eq_eth_cmd { 5847 __be32 op_to_vfn; 5848 __be32 alloc_to_len16; 5849 __be32 eqid_pkd; 5850 __be32 physeqid_pkd; 5851 __be32 fetchszm_to_iqid; 5852 __be32 dcaen_to_eqsize; 5853 __be64 eqaddr; 5854 __be32 autoequiqe_to_viid; 5855 __be32 r8_lo; 5856 __be64 r9; 5857 }; 5858 5859 #define S_FW_EQ_ETH_CMD_PFN 8 5860 #define M_FW_EQ_ETH_CMD_PFN 0x7 5861 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5862 #define G_FW_EQ_ETH_CMD_PFN(x) \ 5863 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5864 5865 #define S_FW_EQ_ETH_CMD_VFN 0 5866 #define M_FW_EQ_ETH_CMD_VFN 0xff 5867 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5868 #define G_FW_EQ_ETH_CMD_VFN(x) \ 5869 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5870 5871 #define S_FW_EQ_ETH_CMD_ALLOC 31 5872 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 5873 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5874 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5875 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5876 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5877 5878 #define S_FW_EQ_ETH_CMD_FREE 30 5879 #define M_FW_EQ_ETH_CMD_FREE 0x1 5880 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5881 #define G_FW_EQ_ETH_CMD_FREE(x) \ 5882 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5883 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5884 5885 #define S_FW_EQ_ETH_CMD_MODIFY 29 5886 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 5887 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5888 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5889 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5890 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5891 5892 #define S_FW_EQ_ETH_CMD_EQSTART 28 5893 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 5894 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5895 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5896 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5897 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5898 5899 #define S_FW_EQ_ETH_CMD_EQSTOP 27 5900 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5901 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5902 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5903 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5904 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5905 5906 #define S_FW_EQ_ETH_CMD_EQID 0 5907 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 5908 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5909 #define G_FW_EQ_ETH_CMD_EQID(x) \ 5910 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5911 5912 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 5913 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5914 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5915 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5916 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5917 5918 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 5919 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5920 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5921 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5922 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5923 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5924 5925 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5926 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5927 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5928 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5929 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 5930 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 5931 5932 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 5933 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 5934 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 5935 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 5936 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 5937 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 5938 5939 #define S_FW_EQ_ETH_CMD_FETCHNS 23 5940 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 5941 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 5942 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 5943 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 5944 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 5945 5946 #define S_FW_EQ_ETH_CMD_FETCHRO 22 5947 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 5948 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 5949 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 5950 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 5951 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 5952 5953 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 5954 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 5955 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 5956 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 5957 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 5958 5959 #define S_FW_EQ_ETH_CMD_CPRIO 19 5960 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 5961 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 5962 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 5963 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 5964 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 5965 5966 #define S_FW_EQ_ETH_CMD_ONCHIP 18 5967 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 5968 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 5969 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 5970 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 5971 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 5972 5973 #define S_FW_EQ_ETH_CMD_PCIECHN 16 5974 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 5975 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 5976 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 5977 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 5978 5979 #define S_FW_EQ_ETH_CMD_IQID 0 5980 #define M_FW_EQ_ETH_CMD_IQID 0xffff 5981 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 5982 #define G_FW_EQ_ETH_CMD_IQID(x) \ 5983 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 5984 5985 #define S_FW_EQ_ETH_CMD_DCAEN 31 5986 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 5987 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 5988 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 5989 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 5990 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 5991 5992 #define S_FW_EQ_ETH_CMD_DCACPU 26 5993 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 5994 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 5995 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 5996 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 5997 5998 #define S_FW_EQ_ETH_CMD_FBMIN 23 5999 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 6000 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 6001 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 6002 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 6003 6004 #define S_FW_EQ_ETH_CMD_FBMAX 20 6005 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 6006 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 6007 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 6008 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 6009 6010 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 6011 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 6012 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 6013 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 6014 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 6015 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 6016 6017 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 6018 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 6019 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 6020 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 6021 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 6022 6023 #define S_FW_EQ_ETH_CMD_EQSIZE 0 6024 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 6025 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 6026 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 6027 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 6028 6029 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 6030 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 6031 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 6032 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 6033 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 6034 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 6035 6036 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 6037 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 6038 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 6039 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 6040 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 6041 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 6042 6043 #define S_FW_EQ_ETH_CMD_VIID 16 6044 #define M_FW_EQ_ETH_CMD_VIID 0xfff 6045 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 6046 #define G_FW_EQ_ETH_CMD_VIID(x) \ 6047 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 6048 6049 struct fw_eq_ctrl_cmd { 6050 __be32 op_to_vfn; 6051 __be32 alloc_to_len16; 6052 __be32 cmpliqid_eqid; 6053 __be32 physeqid_pkd; 6054 __be32 fetchszm_to_iqid; 6055 __be32 dcaen_to_eqsize; 6056 __be64 eqaddr; 6057 }; 6058 6059 #define S_FW_EQ_CTRL_CMD_PFN 8 6060 #define M_FW_EQ_CTRL_CMD_PFN 0x7 6061 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 6062 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 6063 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 6064 6065 #define S_FW_EQ_CTRL_CMD_VFN 0 6066 #define M_FW_EQ_CTRL_CMD_VFN 0xff 6067 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 6068 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 6069 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 6070 6071 #define S_FW_EQ_CTRL_CMD_ALLOC 31 6072 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 6073 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 6074 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 6075 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 6076 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 6077 6078 #define S_FW_EQ_CTRL_CMD_FREE 30 6079 #define M_FW_EQ_CTRL_CMD_FREE 0x1 6080 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 6081 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 6082 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 6083 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 6084 6085 #define S_FW_EQ_CTRL_CMD_MODIFY 29 6086 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 6087 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 6088 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 6089 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 6090 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 6091 6092 #define S_FW_EQ_CTRL_CMD_EQSTART 28 6093 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 6094 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 6095 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 6096 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 6097 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 6098 6099 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 6100 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 6101 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 6102 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 6103 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 6104 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 6105 6106 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 6107 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 6108 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 6109 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 6110 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 6111 6112 #define S_FW_EQ_CTRL_CMD_EQID 0 6113 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 6114 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 6115 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 6116 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 6117 6118 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 6119 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 6120 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 6121 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 6122 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 6123 6124 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 6125 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 6126 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 6127 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 6128 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 6129 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 6130 6131 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 6132 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 6133 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 6134 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 6135 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 6136 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 6137 6138 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 6139 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 6140 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 6141 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 6142 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 6143 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 6144 6145 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 6146 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 6147 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 6148 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 6149 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 6150 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 6151 6152 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 6153 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 6154 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 6155 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 6156 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 6157 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 6158 6159 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 6160 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 6161 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 6162 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 6163 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 6164 6165 #define S_FW_EQ_CTRL_CMD_CPRIO 19 6166 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 6167 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 6168 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 6169 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 6170 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 6171 6172 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 6173 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 6174 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 6175 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 6176 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 6177 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 6178 6179 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 6180 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 6181 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 6182 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 6183 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 6184 6185 #define S_FW_EQ_CTRL_CMD_IQID 0 6186 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 6187 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 6188 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 6189 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 6190 6191 #define S_FW_EQ_CTRL_CMD_DCAEN 31 6192 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 6193 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 6194 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 6195 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 6196 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 6197 6198 #define S_FW_EQ_CTRL_CMD_DCACPU 26 6199 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 6200 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 6201 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 6202 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 6203 6204 #define S_FW_EQ_CTRL_CMD_FBMIN 23 6205 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 6206 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 6207 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 6208 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 6209 6210 #define S_FW_EQ_CTRL_CMD_FBMAX 20 6211 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 6212 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 6213 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 6214 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 6215 6216 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 6217 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 6218 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6219 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6220 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6221 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6222 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 6223 6224 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 6225 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 6226 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6227 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 6228 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6229 6230 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 6231 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 6232 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 6233 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 6234 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 6235 6236 struct fw_eq_ofld_cmd { 6237 __be32 op_to_vfn; 6238 __be32 alloc_to_len16; 6239 __be32 eqid_pkd; 6240 __be32 physeqid_pkd; 6241 __be32 fetchszm_to_iqid; 6242 __be32 dcaen_to_eqsize; 6243 __be64 eqaddr; 6244 }; 6245 6246 #define S_FW_EQ_OFLD_CMD_PFN 8 6247 #define M_FW_EQ_OFLD_CMD_PFN 0x7 6248 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 6249 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 6250 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 6251 6252 #define S_FW_EQ_OFLD_CMD_VFN 0 6253 #define M_FW_EQ_OFLD_CMD_VFN 0xff 6254 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 6255 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 6256 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 6257 6258 #define S_FW_EQ_OFLD_CMD_ALLOC 31 6259 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 6260 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 6261 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 6262 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 6263 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 6264 6265 #define S_FW_EQ_OFLD_CMD_FREE 30 6266 #define M_FW_EQ_OFLD_CMD_FREE 0x1 6267 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 6268 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 6269 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 6270 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 6271 6272 #define S_FW_EQ_OFLD_CMD_MODIFY 29 6273 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 6274 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 6275 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 6276 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 6277 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 6278 6279 #define S_FW_EQ_OFLD_CMD_EQSTART 28 6280 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 6281 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 6282 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 6283 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 6284 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 6285 6286 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 6287 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 6288 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 6289 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 6290 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 6291 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 6292 6293 #define S_FW_EQ_OFLD_CMD_EQID 0 6294 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 6295 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 6296 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 6297 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 6298 6299 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 6300 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 6301 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 6302 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 6303 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 6304 6305 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 6306 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 6307 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 6308 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 6309 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 6310 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 6311 6312 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 6313 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 6314 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 6315 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 6316 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 6317 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 6318 6319 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 6320 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 6321 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 6322 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 6323 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 6324 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 6325 6326 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 6327 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 6328 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 6329 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 6330 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 6331 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 6332 6333 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 6334 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 6335 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 6336 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 6337 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 6338 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 6339 6340 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 6341 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 6342 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 6343 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 6344 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 6345 6346 #define S_FW_EQ_OFLD_CMD_CPRIO 19 6347 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 6348 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 6349 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 6350 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 6351 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 6352 6353 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 6354 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 6355 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 6356 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 6357 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 6358 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 6359 6360 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 6361 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 6362 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 6363 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 6364 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 6365 6366 #define S_FW_EQ_OFLD_CMD_IQID 0 6367 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 6368 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 6369 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 6370 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 6371 6372 #define S_FW_EQ_OFLD_CMD_DCAEN 31 6373 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 6374 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 6375 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 6376 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 6377 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 6378 6379 #define S_FW_EQ_OFLD_CMD_DCACPU 26 6380 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 6381 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 6382 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 6383 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 6384 6385 #define S_FW_EQ_OFLD_CMD_FBMIN 23 6386 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 6387 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 6388 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 6389 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 6390 6391 #define S_FW_EQ_OFLD_CMD_FBMAX 20 6392 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 6393 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 6394 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 6395 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 6396 6397 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 6398 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 6399 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6400 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6401 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6402 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6403 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 6404 6405 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 6406 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 6407 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6408 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 6409 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6410 6411 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 6412 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 6413 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 6414 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 6415 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 6416 6417 /* Macros for VIID parsing: 6418 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 6419 #define S_FW_VIID_PFN 8 6420 #define M_FW_VIID_PFN 0x7 6421 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 6422 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 6423 6424 #define S_FW_VIID_VIVLD 7 6425 #define M_FW_VIID_VIVLD 0x1 6426 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 6427 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 6428 6429 #define S_FW_VIID_VIN 0 6430 #define M_FW_VIID_VIN 0x7F 6431 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 6432 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 6433 6434 /* Macros for VIID parsing: 6435 VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */ 6436 #define S_FW_256VIID_PFN 9 6437 #define M_FW_256VIID_PFN 0x7 6438 #define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN) 6439 #define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN) 6440 6441 #define S_FW_256VIID_VIVLD 8 6442 #define M_FW_256VIID_VIVLD 0x1 6443 #define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD) 6444 #define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD) 6445 6446 #define S_FW_256VIID_VIN 0 6447 #define M_FW_256VIID_VIN 0xFF 6448 #define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN) 6449 #define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN) 6450 6451 enum fw_vi_func { 6452 FW_VI_FUNC_ETH, 6453 FW_VI_FUNC_OFLD, 6454 FW_VI_FUNC_IWARP, 6455 FW_VI_FUNC_OPENISCSI, 6456 FW_VI_FUNC_OPENFCOE, 6457 FW_VI_FUNC_FOISCSI, 6458 FW_VI_FUNC_FOFCOE, 6459 FW_VI_FUNC_FW, 6460 }; 6461 6462 struct fw_vi_cmd { 6463 __be32 op_to_vfn; 6464 __be32 alloc_to_len16; 6465 __be16 type_to_viid; 6466 __u8 mac[6]; 6467 __u8 portid_pkd; 6468 __u8 nmac; 6469 __u8 nmac0[6]; 6470 __be16 norss_rsssize; 6471 __u8 nmac1[6]; 6472 __be16 idsiiq_pkd; 6473 __u8 nmac2[6]; 6474 __be16 idseiq_pkd; 6475 __u8 nmac3[6]; 6476 __be64 r9; 6477 __be64 r10; 6478 }; 6479 6480 #define S_FW_VI_CMD_PFN 8 6481 #define M_FW_VI_CMD_PFN 0x7 6482 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 6483 #define G_FW_VI_CMD_PFN(x) \ 6484 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 6485 6486 #define S_FW_VI_CMD_VFN 0 6487 #define M_FW_VI_CMD_VFN 0xff 6488 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 6489 #define G_FW_VI_CMD_VFN(x) \ 6490 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 6491 6492 #define S_FW_VI_CMD_ALLOC 31 6493 #define M_FW_VI_CMD_ALLOC 0x1 6494 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 6495 #define G_FW_VI_CMD_ALLOC(x) \ 6496 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 6497 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 6498 6499 #define S_FW_VI_CMD_FREE 30 6500 #define M_FW_VI_CMD_FREE 0x1 6501 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 6502 #define G_FW_VI_CMD_FREE(x) \ 6503 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 6504 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 6505 6506 #define S_FW_VI_CMD_VFVLD 24 6507 #define M_FW_VI_CMD_VFVLD 0x1 6508 #define V_FW_VI_CMD_VFVLD(x) ((x) << S_FW_VI_CMD_VFVLD) 6509 #define G_FW_VI_CMD_VFVLD(x) \ 6510 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD) 6511 #define F_FW_VI_CMD_VFVLD V_FW_VI_CMD_VFVLD(1U) 6512 6513 #define S_FW_VI_CMD_VIN 16 6514 #define M_FW_VI_CMD_VIN 0xff 6515 #define V_FW_VI_CMD_VIN(x) ((x) << S_FW_VI_CMD_VIN) 6516 #define G_FW_VI_CMD_VIN(x) \ 6517 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN) 6518 6519 #define S_FW_VI_CMD_TYPE 15 6520 #define M_FW_VI_CMD_TYPE 0x1 6521 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 6522 #define G_FW_VI_CMD_TYPE(x) \ 6523 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 6524 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 6525 6526 #define S_FW_VI_CMD_FUNC 12 6527 #define M_FW_VI_CMD_FUNC 0x7 6528 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 6529 #define G_FW_VI_CMD_FUNC(x) \ 6530 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 6531 6532 #define S_FW_VI_CMD_VIID 0 6533 #define M_FW_VI_CMD_VIID 0xfff 6534 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 6535 #define G_FW_VI_CMD_VIID(x) \ 6536 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 6537 6538 #define S_FW_VI_CMD_PORTID 4 6539 #define M_FW_VI_CMD_PORTID 0xf 6540 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 6541 #define G_FW_VI_CMD_PORTID(x) \ 6542 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 6543 6544 #define S_FW_VI_CMD_NORSS 11 6545 #define M_FW_VI_CMD_NORSS 0x1 6546 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 6547 #define G_FW_VI_CMD_NORSS(x) \ 6548 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 6549 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 6550 6551 #define S_FW_VI_CMD_RSSSIZE 0 6552 #define M_FW_VI_CMD_RSSSIZE 0x7ff 6553 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 6554 #define G_FW_VI_CMD_RSSSIZE(x) \ 6555 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 6556 6557 #define S_FW_VI_CMD_IDSIIQ 0 6558 #define M_FW_VI_CMD_IDSIIQ 0x3ff 6559 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 6560 #define G_FW_VI_CMD_IDSIIQ(x) \ 6561 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 6562 6563 #define S_FW_VI_CMD_IDSEIQ 0 6564 #define M_FW_VI_CMD_IDSEIQ 0x3ff 6565 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 6566 #define G_FW_VI_CMD_IDSEIQ(x) \ 6567 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 6568 6569 /* Special VI_MAC command index ids */ 6570 #define FW_VI_MAC_ADD_MAC 0x3FF 6571 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 6572 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 6573 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 6574 6575 enum fw_vi_mac_smac { 6576 FW_VI_MAC_MPS_TCAM_ENTRY, 6577 FW_VI_MAC_MPS_TCAM_ONLY, 6578 FW_VI_MAC_SMT_ONLY, 6579 FW_VI_MAC_SMT_AND_MPSTCAM 6580 }; 6581 6582 enum fw_vi_mac_result { 6583 FW_VI_MAC_R_SUCCESS, 6584 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 6585 FW_VI_MAC_R_SMAC_FAIL, 6586 FW_VI_MAC_R_F_ACL_CHECK 6587 }; 6588 6589 enum fw_vi_mac_entry_types { 6590 FW_VI_MAC_TYPE_EXACTMAC, 6591 FW_VI_MAC_TYPE_HASHVEC, 6592 FW_VI_MAC_TYPE_RAW, 6593 FW_VI_MAC_TYPE_EXACTMAC_VNI, 6594 }; 6595 6596 struct fw_vi_mac_cmd { 6597 __be32 op_to_viid; 6598 __be32 freemacs_to_len16; 6599 union fw_vi_mac { 6600 struct fw_vi_mac_exact { 6601 __be16 valid_to_idx; 6602 __u8 macaddr[6]; 6603 } exact[7]; 6604 struct fw_vi_mac_hash { 6605 __be64 hashvec; 6606 } hash; 6607 struct fw_vi_mac_raw { 6608 __be32 raw_idx_pkd; 6609 __be32 data0_pkd; 6610 __be32 data1[2]; 6611 __be64 data0m_pkd; 6612 __be32 data1m[2]; 6613 } raw; 6614 struct fw_vi_mac_vni { 6615 __be16 valid_to_idx; 6616 __u8 macaddr[6]; 6617 __be16 r7; 6618 __u8 macaddr_mask[6]; 6619 __be32 lookup_type_to_vni; 6620 __be32 vni_mask_pkd; 6621 } exact_vni[2]; 6622 } u; 6623 }; 6624 6625 #define S_FW_VI_MAC_CMD_SMTID 12 6626 #define M_FW_VI_MAC_CMD_SMTID 0xff 6627 #define V_FW_VI_MAC_CMD_SMTID(x) ((x) << S_FW_VI_MAC_CMD_SMTID) 6628 #define G_FW_VI_MAC_CMD_SMTID(x) \ 6629 (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID) 6630 6631 #define S_FW_VI_MAC_CMD_VIID 0 6632 #define M_FW_VI_MAC_CMD_VIID 0xfff 6633 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 6634 #define G_FW_VI_MAC_CMD_VIID(x) \ 6635 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 6636 6637 #define S_FW_VI_MAC_CMD_FREEMACS 31 6638 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 6639 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 6640 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 6641 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 6642 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 6643 6644 #define S_FW_VI_MAC_CMD_IS_SMAC 30 6645 #define M_FW_VI_MAC_CMD_IS_SMAC 0x1 6646 #define V_FW_VI_MAC_CMD_IS_SMAC(x) ((x) << S_FW_VI_MAC_CMD_IS_SMAC) 6647 #define G_FW_VI_MAC_CMD_IS_SMAC(x) \ 6648 (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC) 6649 #define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U) 6650 6651 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 6652 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 6653 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 6654 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 6655 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 6656 6657 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 6658 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 6659 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 6660 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 6661 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 6662 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 6663 6664 #define S_FW_VI_MAC_CMD_VALID 15 6665 #define M_FW_VI_MAC_CMD_VALID 0x1 6666 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 6667 #define G_FW_VI_MAC_CMD_VALID(x) \ 6668 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 6669 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 6670 6671 #define S_FW_VI_MAC_CMD_PRIO 12 6672 #define M_FW_VI_MAC_CMD_PRIO 0x7 6673 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 6674 #define G_FW_VI_MAC_CMD_PRIO(x) \ 6675 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 6676 6677 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 6678 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 6679 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 6680 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 6681 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 6682 6683 #define S_FW_VI_MAC_CMD_IDX 0 6684 #define M_FW_VI_MAC_CMD_IDX 0x3ff 6685 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 6686 #define G_FW_VI_MAC_CMD_IDX(x) \ 6687 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 6688 6689 #define S_FW_VI_MAC_CMD_RAW_IDX 16 6690 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 6691 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 6692 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 6693 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 6694 6695 #define S_FW_VI_MAC_CMD_DATA0 0 6696 #define M_FW_VI_MAC_CMD_DATA0 0xffff 6697 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 6698 #define G_FW_VI_MAC_CMD_DATA0(x) \ 6699 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 6700 6701 #define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31 6702 #define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1 6703 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE) 6704 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \ 6705 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE) 6706 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U) 6707 6708 #define S_FW_VI_MAC_CMD_DIP_HIT 30 6709 #define M_FW_VI_MAC_CMD_DIP_HIT 0x1 6710 #define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT) 6711 #define G_FW_VI_MAC_CMD_DIP_HIT(x) \ 6712 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT) 6713 #define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U) 6714 6715 #define S_FW_VI_MAC_CMD_VNI 0 6716 #define M_FW_VI_MAC_CMD_VNI 0xffffff 6717 #define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI) 6718 #define G_FW_VI_MAC_CMD_VNI(x) \ 6719 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI) 6720 6721 /* Extracting loopback port number passed from driver. 6722 * as a part of fw_vi_mac_vni For non loopback entries 6723 * ignore the field and update port number from flowc. 6724 * Fw will ignore if physical port number received. 6725 * expected range (4-7). 6726 */ 6727 6728 #define S_FW_VI_MAC_CMD_PORT 24 6729 #define M_FW_VI_MAC_CMD_PORT 0x7 6730 #define V_FW_VI_MAC_CMD_PORT(x) ((x) << S_FW_VI_MAC_CMD_PORT) 6731 #define G_FW_VI_MAC_CMD_PORT(x) \ 6732 (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT) 6733 6734 #define S_FW_VI_MAC_CMD_VNI_MASK 0 6735 #define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff 6736 #define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK) 6737 #define G_FW_VI_MAC_CMD_VNI_MASK(x) \ 6738 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK) 6739 6740 /* T4 max MTU supported */ 6741 #define T4_MAX_MTU_SUPPORTED 9600 6742 #define FW_RXMODE_MTU_NO_CHG 65535 6743 6744 struct fw_vi_rxmode_cmd { 6745 __be32 op_to_viid; 6746 __be32 retval_len16; 6747 __be32 mtu_to_vlanexen; 6748 __be32 r4_lo; 6749 }; 6750 6751 #define S_FW_VI_RXMODE_CMD_VIID 0 6752 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 6753 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 6754 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 6755 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6756 6757 #define S_FW_VI_RXMODE_CMD_MTU 16 6758 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 6759 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6760 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 6761 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6762 6763 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6764 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6765 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6766 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6767 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6768 6769 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6770 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6771 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6772 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6773 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6774 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6775 6776 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6777 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6778 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6779 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6780 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6781 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6782 6783 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6784 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6785 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6786 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6787 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 6788 6789 struct fw_vi_enable_cmd { 6790 __be32 op_to_viid; 6791 __be32 ien_to_len16; 6792 __be16 blinkdur; 6793 __be16 r3; 6794 __be32 r4; 6795 }; 6796 6797 #define S_FW_VI_ENABLE_CMD_VIID 0 6798 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 6799 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6800 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 6801 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6802 6803 #define S_FW_VI_ENABLE_CMD_IEN 31 6804 #define M_FW_VI_ENABLE_CMD_IEN 0x1 6805 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6806 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 6807 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6808 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6809 6810 #define S_FW_VI_ENABLE_CMD_EEN 30 6811 #define M_FW_VI_ENABLE_CMD_EEN 0x1 6812 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6813 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 6814 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6815 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6816 6817 #define S_FW_VI_ENABLE_CMD_LED 29 6818 #define M_FW_VI_ENABLE_CMD_LED 0x1 6819 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6820 #define G_FW_VI_ENABLE_CMD_LED(x) \ 6821 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6822 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 6823 6824 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6825 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6826 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6827 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6828 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6829 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6830 6831 /* VI VF stats offset definitions */ 6832 #define VI_VF_NUM_STATS 16 6833 enum fw_vi_stats_vf_index { 6834 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 6835 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 6836 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 6837 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 6838 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 6839 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 6840 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 6841 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 6842 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 6843 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 6844 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 6845 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 6846 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 6847 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 6848 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 6849 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 6850 }; 6851 6852 /* VI PF stats offset definitions */ 6853 #define VI_PF_NUM_STATS 17 6854 enum fw_vi_stats_pf_index { 6855 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 6856 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 6857 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 6858 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 6859 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 6860 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 6861 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 6862 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 6863 FW_VI_PF_STAT_RX_BYTES_IX, 6864 FW_VI_PF_STAT_RX_FRAMES_IX, 6865 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 6866 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 6867 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 6868 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 6869 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 6870 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 6871 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 6872 }; 6873 6874 struct fw_vi_stats_cmd { 6875 __be32 op_to_viid; 6876 __be32 retval_len16; 6877 union fw_vi_stats { 6878 struct fw_vi_stats_ctl { 6879 __be16 nstats_ix; 6880 __be16 r6; 6881 __be32 r7; 6882 __be64 stat0; 6883 __be64 stat1; 6884 __be64 stat2; 6885 __be64 stat3; 6886 __be64 stat4; 6887 __be64 stat5; 6888 } ctl; 6889 struct fw_vi_stats_pf { 6890 __be64 tx_bcast_bytes; 6891 __be64 tx_bcast_frames; 6892 __be64 tx_mcast_bytes; 6893 __be64 tx_mcast_frames; 6894 __be64 tx_ucast_bytes; 6895 __be64 tx_ucast_frames; 6896 __be64 tx_offload_bytes; 6897 __be64 tx_offload_frames; 6898 __be64 rx_pf_bytes; 6899 __be64 rx_pf_frames; 6900 __be64 rx_bcast_bytes; 6901 __be64 rx_bcast_frames; 6902 __be64 rx_mcast_bytes; 6903 __be64 rx_mcast_frames; 6904 __be64 rx_ucast_bytes; 6905 __be64 rx_ucast_frames; 6906 __be64 rx_err_frames; 6907 } pf; 6908 struct fw_vi_stats_vf { 6909 __be64 tx_bcast_bytes; 6910 __be64 tx_bcast_frames; 6911 __be64 tx_mcast_bytes; 6912 __be64 tx_mcast_frames; 6913 __be64 tx_ucast_bytes; 6914 __be64 tx_ucast_frames; 6915 __be64 tx_drop_frames; 6916 __be64 tx_offload_bytes; 6917 __be64 tx_offload_frames; 6918 __be64 rx_bcast_bytes; 6919 __be64 rx_bcast_frames; 6920 __be64 rx_mcast_bytes; 6921 __be64 rx_mcast_frames; 6922 __be64 rx_ucast_bytes; 6923 __be64 rx_ucast_frames; 6924 __be64 rx_err_frames; 6925 } vf; 6926 } u; 6927 }; 6928 6929 #define S_FW_VI_STATS_CMD_VIID 0 6930 #define M_FW_VI_STATS_CMD_VIID 0xfff 6931 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 6932 #define G_FW_VI_STATS_CMD_VIID(x) \ 6933 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 6934 6935 #define S_FW_VI_STATS_CMD_NSTATS 12 6936 #define M_FW_VI_STATS_CMD_NSTATS 0x7 6937 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 6938 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 6939 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 6940 6941 #define S_FW_VI_STATS_CMD_IX 0 6942 #define M_FW_VI_STATS_CMD_IX 0x1f 6943 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 6944 #define G_FW_VI_STATS_CMD_IX(x) \ 6945 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 6946 6947 struct fw_acl_mac_cmd { 6948 __be32 op_to_vfn; 6949 __be32 en_to_len16; 6950 __u8 nmac; 6951 __u8 r3[7]; 6952 __be16 r4; 6953 __u8 macaddr0[6]; 6954 __be16 r5; 6955 __u8 macaddr1[6]; 6956 __be16 r6; 6957 __u8 macaddr2[6]; 6958 __be16 r7; 6959 __u8 macaddr3[6]; 6960 }; 6961 6962 #define S_FW_ACL_MAC_CMD_PFN 8 6963 #define M_FW_ACL_MAC_CMD_PFN 0x7 6964 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 6965 #define G_FW_ACL_MAC_CMD_PFN(x) \ 6966 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 6967 6968 #define S_FW_ACL_MAC_CMD_VFN 0 6969 #define M_FW_ACL_MAC_CMD_VFN 0xff 6970 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 6971 #define G_FW_ACL_MAC_CMD_VFN(x) \ 6972 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 6973 6974 #define S_FW_ACL_MAC_CMD_EN 31 6975 #define M_FW_ACL_MAC_CMD_EN 0x1 6976 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 6977 #define G_FW_ACL_MAC_CMD_EN(x) \ 6978 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 6979 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 6980 6981 struct fw_acl_vlan_cmd { 6982 __be32 op_to_vfn; 6983 __be32 en_to_len16; 6984 __u8 nvlan; 6985 __u8 dropnovlan_fm; 6986 __u8 r3_lo[6]; 6987 __be16 vlanid[16]; 6988 }; 6989 6990 #define S_FW_ACL_VLAN_CMD_PFN 8 6991 #define M_FW_ACL_VLAN_CMD_PFN 0x7 6992 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 6993 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 6994 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 6995 6996 #define S_FW_ACL_VLAN_CMD_VFN 0 6997 #define M_FW_ACL_VLAN_CMD_VFN 0xff 6998 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 6999 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 7000 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 7001 7002 #define S_FW_ACL_VLAN_CMD_EN 31 7003 #define M_FW_ACL_VLAN_CMD_EN 0x1 7004 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 7005 #define G_FW_ACL_VLAN_CMD_EN(x) \ 7006 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 7007 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 7008 7009 #define S_FW_ACL_VLAN_CMD_TRANSPARENT 30 7010 #define M_FW_ACL_VLAN_CMD_TRANSPARENT 0x1 7011 #define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 7012 ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT) 7013 #define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 7014 (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT) 7015 #define F_FW_ACL_VLAN_CMD_TRANSPARENT V_FW_ACL_VLAN_CMD_TRANSPARENT(1U) 7016 7017 #define S_FW_ACL_VLAN_CMD_PMASK 16 7018 #define M_FW_ACL_VLAN_CMD_PMASK 0xf 7019 #define V_FW_ACL_VLAN_CMD_PMASK(x) ((x) << S_FW_ACL_VLAN_CMD_PMASK) 7020 #define G_FW_ACL_VLAN_CMD_PMASK(x) \ 7021 (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK) 7022 7023 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 7024 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 7025 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 7026 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 7027 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 7028 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 7029 7030 #define S_FW_ACL_VLAN_CMD_FM 6 7031 #define M_FW_ACL_VLAN_CMD_FM 0x1 7032 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 7033 #define G_FW_ACL_VLAN_CMD_FM(x) \ 7034 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 7035 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 7036 7037 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 7038 enum fw_port_cap { 7039 FW_PORT_CAP_SPEED_100M = 0x0001, 7040 FW_PORT_CAP_SPEED_1G = 0x0002, 7041 FW_PORT_CAP_SPEED_25G = 0x0004, 7042 FW_PORT_CAP_SPEED_10G = 0x0008, 7043 FW_PORT_CAP_SPEED_40G = 0x0010, 7044 FW_PORT_CAP_SPEED_100G = 0x0020, 7045 FW_PORT_CAP_FC_RX = 0x0040, 7046 FW_PORT_CAP_FC_TX = 0x0080, 7047 FW_PORT_CAP_ANEG = 0x0100, 7048 FW_PORT_CAP_MDIAUTO = 0x0200, 7049 FW_PORT_CAP_MDISTRAIGHT = 0x0400, 7050 FW_PORT_CAP_FEC_RS = 0x0800, 7051 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 7052 FW_PORT_CAP_FORCE_PAUSE = 0x2000, 7053 FW_PORT_CAP_802_3_PAUSE = 0x4000, 7054 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 7055 }; 7056 7057 #define S_FW_PORT_CAP_SPEED 0 7058 #define M_FW_PORT_CAP_SPEED 0x3f 7059 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 7060 #define G_FW_PORT_CAP_SPEED(x) \ 7061 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 7062 7063 #define S_FW_PORT_CAP_FC 6 7064 #define M_FW_PORT_CAP_FC 0x3 7065 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 7066 #define G_FW_PORT_CAP_FC(x) \ 7067 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 7068 7069 #define S_FW_PORT_CAP_ANEG 8 7070 #define M_FW_PORT_CAP_ANEG 0x1 7071 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 7072 #define G_FW_PORT_CAP_ANEG(x) \ 7073 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 7074 7075 #define S_FW_PORT_CAP_FEC 11 7076 #define M_FW_PORT_CAP_FEC 0x3 7077 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 7078 #define G_FW_PORT_CAP_FEC(x) \ 7079 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 7080 7081 #define S_FW_PORT_CAP_FORCE_PAUSE 13 7082 #define M_FW_PORT_CAP_FORCE_PAUSE 0x1 7083 #define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE) 7084 #define G_FW_PORT_CAP_FORCE_PAUSE(x) \ 7085 (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE) 7086 7087 #define S_FW_PORT_CAP_802_3 14 7088 #define M_FW_PORT_CAP_802_3 0x3 7089 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 7090 #define G_FW_PORT_CAP_802_3(x) \ 7091 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 7092 7093 enum fw_port_mdi { 7094 FW_PORT_CAP_MDI_UNCHANGED, 7095 FW_PORT_CAP_MDI_AUTO, 7096 FW_PORT_CAP_MDI_F_STRAIGHT, 7097 FW_PORT_CAP_MDI_F_CROSSOVER 7098 }; 7099 7100 #define S_FW_PORT_CAP_MDI 9 7101 #define M_FW_PORT_CAP_MDI 3 7102 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 7103 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 7104 7105 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 7106 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 7107 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 7108 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 7109 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 7110 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 7111 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 7112 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 7113 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 7114 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 7115 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 7116 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 7117 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 7118 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 7119 #define FW_PORT_CAP32_FC_RX 0x00010000UL 7120 #define FW_PORT_CAP32_FC_TX 0x00020000UL 7121 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 7122 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 7123 #define FW_PORT_CAP32_ANEG 0x00100000UL 7124 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL 7125 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 7126 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 7127 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 7128 #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 7129 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 7130 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 7131 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 7132 #define FW_PORT_CAP32_RESERVED2 0xe0000000UL 7133 7134 #define S_FW_PORT_CAP32_SPEED 0 7135 #define M_FW_PORT_CAP32_SPEED 0xfff 7136 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 7137 #define G_FW_PORT_CAP32_SPEED(x) \ 7138 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 7139 7140 #define S_FW_PORT_CAP32_FC 16 7141 #define M_FW_PORT_CAP32_FC 0x3 7142 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) 7143 #define G_FW_PORT_CAP32_FC(x) \ 7144 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC) 7145 7146 #define S_FW_PORT_CAP32_802_3 18 7147 #define M_FW_PORT_CAP32_802_3 0x3 7148 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) 7149 #define G_FW_PORT_CAP32_802_3(x) \ 7150 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3) 7151 7152 #define S_FW_PORT_CAP32_ANEG 20 7153 #define M_FW_PORT_CAP32_ANEG 0x1 7154 #define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG) 7155 #define G_FW_PORT_CAP32_ANEG(x) \ 7156 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG) 7157 7158 #define S_FW_PORT_CAP32_FORCE_PAUSE 28 7159 #define M_FW_PORT_CAP32_FORCE_PAUSE 0x1 7160 #define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE) 7161 #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \ 7162 (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE) 7163 7164 enum fw_port_mdi32 { 7165 FW_PORT_CAP32_MDI_UNCHANGED, 7166 FW_PORT_CAP32_MDI_AUTO, 7167 FW_PORT_CAP32_MDI_F_STRAIGHT, 7168 FW_PORT_CAP32_MDI_F_CROSSOVER 7169 }; 7170 7171 #define S_FW_PORT_CAP32_MDI 21 7172 #define M_FW_PORT_CAP32_MDI 3 7173 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 7174 #define G_FW_PORT_CAP32_MDI(x) \ 7175 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 7176 7177 #define S_FW_PORT_CAP32_FEC 23 7178 #define M_FW_PORT_CAP32_FEC 0x1f 7179 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) 7180 #define G_FW_PORT_CAP32_FEC(x) \ 7181 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC) 7182 7183 /* macros to isolate various 32-bit Port Capabilities sub-fields */ 7184 #define CAP32_SPEED(__cap32) \ 7185 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32) 7186 7187 #define CAP32_FEC(__cap32) \ 7188 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32) 7189 7190 #define CAP32_FC(__cap32) \ 7191 (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32) 7192 7193 enum fw_port_action { 7194 FW_PORT_ACTION_L1_CFG = 0x0001, 7195 FW_PORT_ACTION_L2_CFG = 0x0002, 7196 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 7197 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 7198 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 7199 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 7200 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 7201 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 7202 FW_PORT_ACTION_L1_CFG32 = 0x0009, 7203 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 7204 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 7205 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 7206 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 7207 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 7208 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 7209 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 7210 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 7211 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 7212 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 7213 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 7214 FW_PORT_ACTION_PHY_RESET = 0x0040, 7215 FW_PORT_ACTION_PMA_RESET = 0x0041, 7216 FW_PORT_ACTION_PCS_RESET = 0x0042, 7217 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 7218 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 7219 FW_PORT_ACTION_AN_RESET = 0x0045, 7220 }; 7221 7222 enum fw_port_l2cfg_ctlbf { 7223 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 7224 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 7225 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 7226 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 7227 FW_PORT_L2_CTLBF_IVLAN = 0x10, 7228 FW_PORT_L2_CTLBF_TXIPG = 0x20, 7229 FW_PORT_L2_CTLBF_MTU = 0x40 7230 }; 7231 7232 enum fw_dcb_app_tlv_sf { 7233 FW_DCB_APP_SF_ETHERTYPE, 7234 FW_DCB_APP_SF_SOCKET_TCP, 7235 FW_DCB_APP_SF_SOCKET_UDP, 7236 FW_DCB_APP_SF_SOCKET_ALL, 7237 }; 7238 7239 enum fw_port_dcb_versions { 7240 FW_PORT_DCB_VER_UNKNOWN, 7241 FW_PORT_DCB_VER_CEE1D0, 7242 FW_PORT_DCB_VER_CEE1D01, 7243 FW_PORT_DCB_VER_IEEE, 7244 FW_PORT_DCB_VER_AUTO=7 7245 }; 7246 7247 enum fw_port_dcb_cfg { 7248 FW_PORT_DCB_CFG_PG = 0x01, 7249 FW_PORT_DCB_CFG_PFC = 0x02, 7250 FW_PORT_DCB_CFG_APPL = 0x04 7251 }; 7252 7253 enum fw_port_dcb_cfg_rc { 7254 FW_PORT_DCB_CFG_SUCCESS = 0x0, 7255 FW_PORT_DCB_CFG_ERROR = 0x1 7256 }; 7257 7258 enum fw_port_dcb_type { 7259 FW_PORT_DCB_TYPE_PGID = 0x00, 7260 FW_PORT_DCB_TYPE_PGRATE = 0x01, 7261 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 7262 FW_PORT_DCB_TYPE_PFC = 0x03, 7263 FW_PORT_DCB_TYPE_APP_ID = 0x04, 7264 FW_PORT_DCB_TYPE_CONTROL = 0x05, 7265 }; 7266 7267 enum fw_port_dcb_feature_state { 7268 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 7269 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 7270 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 7271 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 7272 }; 7273 7274 enum fw_port_diag_ops { 7275 FW_PORT_DIAGS_TEMP = 0x00, 7276 FW_PORT_DIAGS_TX_POWER = 0x01, 7277 FW_PORT_DIAGS_RX_POWER = 0x02, 7278 FW_PORT_DIAGS_TX_DIS = 0x03, 7279 }; 7280 7281 struct fw_port_cmd { 7282 __be32 op_to_portid; 7283 __be32 action_to_len16; 7284 union fw_port { 7285 struct fw_port_l1cfg { 7286 __be32 rcap; 7287 __be32 r; 7288 } l1cfg; 7289 struct fw_port_l2cfg { 7290 __u8 ctlbf; 7291 __u8 ovlan3_to_ivlan0; 7292 __be16 ivlantype; 7293 __be16 txipg_force_pinfo; 7294 __be16 mtu; 7295 __be16 ovlan0mask; 7296 __be16 ovlan0type; 7297 __be16 ovlan1mask; 7298 __be16 ovlan1type; 7299 __be16 ovlan2mask; 7300 __be16 ovlan2type; 7301 __be16 ovlan3mask; 7302 __be16 ovlan3type; 7303 } l2cfg; 7304 struct fw_port_info { 7305 __be32 lstatus_to_modtype; 7306 __be16 pcap; 7307 __be16 acap; 7308 __be16 mtu; 7309 __u8 cbllen; 7310 __u8 auxlinfo; 7311 __u8 dcbxdis_pkd; 7312 __u8 r8_lo; 7313 __be16 lpacap; 7314 __be64 r9; 7315 } info; 7316 struct fw_port_diags { 7317 __u8 diagop; 7318 __u8 r[3]; 7319 __be32 diagval; 7320 } diags; 7321 union fw_port_dcb { 7322 struct fw_port_dcb_pgid { 7323 __u8 type; 7324 __u8 apply_pkd; 7325 __u8 r10_lo[2]; 7326 __be32 pgid; 7327 __be64 r11; 7328 } pgid; 7329 struct fw_port_dcb_pgrate { 7330 __u8 type; 7331 __u8 apply_pkd; 7332 __u8 r10_lo[5]; 7333 __u8 num_tcs_supported; 7334 __u8 pgrate[8]; 7335 __u8 tsa[8]; 7336 } pgrate; 7337 struct fw_port_dcb_priorate { 7338 __u8 type; 7339 __u8 apply_pkd; 7340 __u8 r10_lo[6]; 7341 __u8 strict_priorate[8]; 7342 } priorate; 7343 struct fw_port_dcb_pfc { 7344 __u8 type; 7345 __u8 pfcen; 7346 __u8 apply_pkd; 7347 __u8 r10_lo[4]; 7348 __u8 max_pfc_tcs; 7349 __be64 r11; 7350 } pfc; 7351 struct fw_port_app_priority { 7352 __u8 type; 7353 __u8 apply_pkd; 7354 __u8 r10_lo; 7355 __u8 idx; 7356 __u8 user_prio_map; 7357 __u8 sel_field; 7358 __be16 protocolid; 7359 __be64 r12; 7360 } app_priority; 7361 struct fw_port_dcb_control { 7362 __u8 type; 7363 __u8 all_syncd_pkd; 7364 __be16 dcb_version_to_app_state; 7365 __be32 r11; 7366 __be64 r12; 7367 } control; 7368 } dcb; 7369 struct fw_port_l1cfg32 { 7370 __be32 rcap32; 7371 __be32 r; 7372 } l1cfg32; 7373 struct fw_port_info32 { 7374 __be32 lstatus32_to_cbllen32; 7375 __be32 auxlinfo32_mtu32; 7376 __be32 linkattr32; 7377 __be32 pcaps32; 7378 __be32 acaps32; 7379 __be32 lpacaps32; 7380 } info32; 7381 } u; 7382 }; 7383 7384 #define S_FW_PORT_CMD_READ 22 7385 #define M_FW_PORT_CMD_READ 0x1 7386 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 7387 #define G_FW_PORT_CMD_READ(x) \ 7388 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 7389 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 7390 7391 #define S_FW_PORT_CMD_PORTID 0 7392 #define M_FW_PORT_CMD_PORTID 0xf 7393 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 7394 #define G_FW_PORT_CMD_PORTID(x) \ 7395 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 7396 7397 #define S_FW_PORT_CMD_ACTION 16 7398 #define M_FW_PORT_CMD_ACTION 0xffff 7399 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 7400 #define G_FW_PORT_CMD_ACTION(x) \ 7401 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 7402 7403 #define S_FW_PORT_CMD_OVLAN3 7 7404 #define M_FW_PORT_CMD_OVLAN3 0x1 7405 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 7406 #define G_FW_PORT_CMD_OVLAN3(x) \ 7407 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 7408 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 7409 7410 #define S_FW_PORT_CMD_OVLAN2 6 7411 #define M_FW_PORT_CMD_OVLAN2 0x1 7412 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 7413 #define G_FW_PORT_CMD_OVLAN2(x) \ 7414 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 7415 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 7416 7417 #define S_FW_PORT_CMD_OVLAN1 5 7418 #define M_FW_PORT_CMD_OVLAN1 0x1 7419 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 7420 #define G_FW_PORT_CMD_OVLAN1(x) \ 7421 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 7422 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 7423 7424 #define S_FW_PORT_CMD_OVLAN0 4 7425 #define M_FW_PORT_CMD_OVLAN0 0x1 7426 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 7427 #define G_FW_PORT_CMD_OVLAN0(x) \ 7428 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 7429 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 7430 7431 #define S_FW_PORT_CMD_IVLAN0 3 7432 #define M_FW_PORT_CMD_IVLAN0 0x1 7433 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 7434 #define G_FW_PORT_CMD_IVLAN0(x) \ 7435 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 7436 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 7437 7438 #define S_FW_PORT_CMD_TXIPG 3 7439 #define M_FW_PORT_CMD_TXIPG 0x1fff 7440 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 7441 #define G_FW_PORT_CMD_TXIPG(x) \ 7442 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 7443 7444 #define S_FW_PORT_CMD_FORCE_PINFO 0 7445 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 7446 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 7447 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 7448 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 7449 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 7450 7451 #define S_FW_PORT_CMD_LSTATUS 31 7452 #define M_FW_PORT_CMD_LSTATUS 0x1 7453 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 7454 #define G_FW_PORT_CMD_LSTATUS(x) \ 7455 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 7456 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 7457 7458 #define S_FW_PORT_CMD_LSPEED 24 7459 #define M_FW_PORT_CMD_LSPEED 0x3f 7460 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 7461 #define G_FW_PORT_CMD_LSPEED(x) \ 7462 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 7463 7464 #define S_FW_PORT_CMD_TXPAUSE 23 7465 #define M_FW_PORT_CMD_TXPAUSE 0x1 7466 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 7467 #define G_FW_PORT_CMD_TXPAUSE(x) \ 7468 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 7469 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 7470 7471 #define S_FW_PORT_CMD_RXPAUSE 22 7472 #define M_FW_PORT_CMD_RXPAUSE 0x1 7473 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 7474 #define G_FW_PORT_CMD_RXPAUSE(x) \ 7475 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 7476 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 7477 7478 #define S_FW_PORT_CMD_MDIOCAP 21 7479 #define M_FW_PORT_CMD_MDIOCAP 0x1 7480 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 7481 #define G_FW_PORT_CMD_MDIOCAP(x) \ 7482 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 7483 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 7484 7485 #define S_FW_PORT_CMD_MDIOADDR 16 7486 #define M_FW_PORT_CMD_MDIOADDR 0x1f 7487 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 7488 #define G_FW_PORT_CMD_MDIOADDR(x) \ 7489 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 7490 7491 #define S_FW_PORT_CMD_LPTXPAUSE 15 7492 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 7493 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 7494 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 7495 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 7496 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 7497 7498 #define S_FW_PORT_CMD_LPRXPAUSE 14 7499 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 7500 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 7501 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 7502 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 7503 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 7504 7505 #define S_FW_PORT_CMD_PTYPE 8 7506 #define M_FW_PORT_CMD_PTYPE 0x1f 7507 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 7508 #define G_FW_PORT_CMD_PTYPE(x) \ 7509 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 7510 7511 #define S_FW_PORT_CMD_LINKDNRC 5 7512 #define M_FW_PORT_CMD_LINKDNRC 0x7 7513 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 7514 #define G_FW_PORT_CMD_LINKDNRC(x) \ 7515 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 7516 7517 #define S_FW_PORT_CMD_MODTYPE 0 7518 #define M_FW_PORT_CMD_MODTYPE 0x1f 7519 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 7520 #define G_FW_PORT_CMD_MODTYPE(x) \ 7521 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 7522 7523 #define S_FW_PORT_AUXLINFO_KX4 2 7524 #define M_FW_PORT_AUXLINFO_KX4 0x1 7525 #define V_FW_PORT_AUXLINFO_KX4(x) \ 7526 ((x) << S_FW_PORT_AUXLINFO_KX4) 7527 #define G_FW_PORT_AUXLINFO_KX4(x) \ 7528 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 7529 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 7530 7531 #define S_FW_PORT_AUXLINFO_KR 1 7532 #define M_FW_PORT_AUXLINFO_KR 0x1 7533 #define V_FW_PORT_AUXLINFO_KR(x) \ 7534 ((x) << S_FW_PORT_AUXLINFO_KR) 7535 #define G_FW_PORT_AUXLINFO_KR(x) \ 7536 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 7537 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 7538 7539 #define S_FW_PORT_CMD_DCBXDIS 7 7540 #define M_FW_PORT_CMD_DCBXDIS 0x1 7541 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 7542 #define G_FW_PORT_CMD_DCBXDIS(x) \ 7543 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 7544 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 7545 7546 #define S_FW_PORT_CMD_APPLY 7 7547 #define M_FW_PORT_CMD_APPLY 0x1 7548 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 7549 #define G_FW_PORT_CMD_APPLY(x) \ 7550 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 7551 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 7552 7553 #define S_FW_PORT_CMD_ALL_SYNCD 7 7554 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 7555 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 7556 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 7557 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 7558 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 7559 7560 #define S_FW_PORT_CMD_DCB_VERSION 12 7561 #define M_FW_PORT_CMD_DCB_VERSION 0x7 7562 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 7563 #define G_FW_PORT_CMD_DCB_VERSION(x) \ 7564 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 7565 7566 #define S_FW_PORT_CMD_PFC_STATE 8 7567 #define M_FW_PORT_CMD_PFC_STATE 0xf 7568 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 7569 #define G_FW_PORT_CMD_PFC_STATE(x) \ 7570 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 7571 7572 #define S_FW_PORT_CMD_ETS_STATE 4 7573 #define M_FW_PORT_CMD_ETS_STATE 0xf 7574 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 7575 #define G_FW_PORT_CMD_ETS_STATE(x) \ 7576 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 7577 7578 #define S_FW_PORT_CMD_APP_STATE 0 7579 #define M_FW_PORT_CMD_APP_STATE 0xf 7580 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 7581 #define G_FW_PORT_CMD_APP_STATE(x) \ 7582 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 7583 7584 #define S_FW_PORT_CMD_LSTATUS32 31 7585 #define M_FW_PORT_CMD_LSTATUS32 0x1 7586 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 7587 #define G_FW_PORT_CMD_LSTATUS32(x) \ 7588 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32) 7589 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 7590 7591 #define S_FW_PORT_CMD_LINKDNRC32 28 7592 #define M_FW_PORT_CMD_LINKDNRC32 0x7 7593 #define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32) 7594 #define G_FW_PORT_CMD_LINKDNRC32(x) \ 7595 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 7596 7597 #define S_FW_PORT_CMD_DCBXDIS32 27 7598 #define M_FW_PORT_CMD_DCBXDIS32 0x1 7599 #define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32) 7600 #define G_FW_PORT_CMD_DCBXDIS32(x) \ 7601 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32) 7602 #define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U) 7603 7604 #define S_FW_PORT_CMD_MDIOCAP32 26 7605 #define M_FW_PORT_CMD_MDIOCAP32 0x1 7606 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 7607 #define G_FW_PORT_CMD_MDIOCAP32(x) \ 7608 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32) 7609 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 7610 7611 #define S_FW_PORT_CMD_MDIOADDR32 21 7612 #define M_FW_PORT_CMD_MDIOADDR32 0x1f 7613 #define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32) 7614 #define G_FW_PORT_CMD_MDIOADDR32(x) \ 7615 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 7616 7617 #define S_FW_PORT_CMD_PORTTYPE32 13 7618 #define M_FW_PORT_CMD_PORTTYPE32 0xff 7619 #define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32) 7620 #define G_FW_PORT_CMD_PORTTYPE32(x) \ 7621 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 7622 7623 #define S_FW_PORT_CMD_MODTYPE32 8 7624 #define M_FW_PORT_CMD_MODTYPE32 0x1f 7625 #define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32) 7626 #define G_FW_PORT_CMD_MODTYPE32(x) \ 7627 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 7628 7629 #define S_FW_PORT_CMD_CBLLEN32 0 7630 #define M_FW_PORT_CMD_CBLLEN32 0xff 7631 #define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32) 7632 #define G_FW_PORT_CMD_CBLLEN32(x) \ 7633 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32) 7634 7635 #define S_FW_PORT_CMD_AUXLINFO32 24 7636 #define M_FW_PORT_CMD_AUXLINFO32 0xff 7637 #define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32) 7638 #define G_FW_PORT_CMD_AUXLINFO32(x) \ 7639 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32) 7640 7641 #define S_FW_PORT_AUXLINFO32_KX4 2 7642 #define M_FW_PORT_AUXLINFO32_KX4 0x1 7643 #define V_FW_PORT_AUXLINFO32_KX4(x) \ 7644 ((x) << S_FW_PORT_AUXLINFO32_KX4) 7645 #define G_FW_PORT_AUXLINFO32_KX4(x) \ 7646 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4) 7647 #define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U) 7648 7649 #define S_FW_PORT_AUXLINFO32_KR 1 7650 #define M_FW_PORT_AUXLINFO32_KR 0x1 7651 #define V_FW_PORT_AUXLINFO32_KR(x) \ 7652 ((x) << S_FW_PORT_AUXLINFO32_KR) 7653 #define G_FW_PORT_AUXLINFO32_KR(x) \ 7654 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR) 7655 #define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U) 7656 7657 #define S_FW_PORT_CMD_MTU32 0 7658 #define M_FW_PORT_CMD_MTU32 0xffff 7659 #define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32) 7660 #define G_FW_PORT_CMD_MTU32(x) \ 7661 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32) 7662 7663 /* 7664 * These are configured into the VPD and hence tools that generate 7665 * VPD may use this enumeration. 7666 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 7667 * 7668 * REMEMBER: 7669 * Update the Common Code t4_hw.c:t4_get_port_type_description() 7670 * with any new Firmware Port Technology Types! 7671 */ 7672 enum fw_port_type { 7673 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 7674 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 7675 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 7676 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 7677 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 7678 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 7679 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 7680 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 7681 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 7682 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 7683 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 7684 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 7685 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 7686 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 7687 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 7688 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 7689 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 7690 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 7691 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 7692 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 7693 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 7694 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 7695 FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/ 7696 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 7697 }; 7698 7699 /* These are read from module's EEPROM and determined once the 7700 module is inserted. */ 7701 enum fw_port_module_type { 7702 FW_PORT_MOD_TYPE_NA = 0x0, 7703 FW_PORT_MOD_TYPE_LR = 0x1, 7704 FW_PORT_MOD_TYPE_SR = 0x2, 7705 FW_PORT_MOD_TYPE_ER = 0x3, 7706 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 7707 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 7708 FW_PORT_MOD_TYPE_LRM = 0x6, 7709 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 7710 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 7711 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 7712 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 7713 }; 7714 7715 /* used by FW and tools may use this to generate VPD */ 7716 enum fw_port_mod_sub_type { 7717 FW_PORT_MOD_SUB_TYPE_NA, 7718 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 7719 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 7720 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 7721 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 7722 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 7723 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 7724 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 7725 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 7726 7727 /* 7728 * The following will never been in the VPD. They are TWINAX cable 7729 * lengths decoded from SFP+ module i2c PROMs. These should almost 7730 * certainly go somewhere else ... 7731 */ 7732 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 7733 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 7734 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 7735 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 7736 }; 7737 7738 /* link down reason codes (3b) */ 7739 enum fw_port_link_dn_rc { 7740 FW_PORT_LINK_DN_RC_NONE, 7741 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 7742 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 7743 FW_PORT_LINK_DN_RESERVED3, 7744 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 7745 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 7746 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 7747 FW_PORT_LINK_DN_RESERVED7 7748 }; 7749 enum fw_port_stats_tx_index { 7750 FW_STAT_TX_PORT_BYTES_IX = 0, 7751 FW_STAT_TX_PORT_FRAMES_IX, 7752 FW_STAT_TX_PORT_BCAST_IX, 7753 FW_STAT_TX_PORT_MCAST_IX, 7754 FW_STAT_TX_PORT_UCAST_IX, 7755 FW_STAT_TX_PORT_ERROR_IX, 7756 FW_STAT_TX_PORT_64B_IX, 7757 FW_STAT_TX_PORT_65B_127B_IX, 7758 FW_STAT_TX_PORT_128B_255B_IX, 7759 FW_STAT_TX_PORT_256B_511B_IX, 7760 FW_STAT_TX_PORT_512B_1023B_IX, 7761 FW_STAT_TX_PORT_1024B_1518B_IX, 7762 FW_STAT_TX_PORT_1519B_MAX_IX, 7763 FW_STAT_TX_PORT_DROP_IX, 7764 FW_STAT_TX_PORT_PAUSE_IX, 7765 FW_STAT_TX_PORT_PPP0_IX, 7766 FW_STAT_TX_PORT_PPP1_IX, 7767 FW_STAT_TX_PORT_PPP2_IX, 7768 FW_STAT_TX_PORT_PPP3_IX, 7769 FW_STAT_TX_PORT_PPP4_IX, 7770 FW_STAT_TX_PORT_PPP5_IX, 7771 FW_STAT_TX_PORT_PPP6_IX, 7772 FW_STAT_TX_PORT_PPP7_IX, 7773 FW_NUM_PORT_TX_STATS 7774 }; 7775 7776 enum fw_port_stat_rx_index { 7777 FW_STAT_RX_PORT_BYTES_IX = 0, 7778 FW_STAT_RX_PORT_FRAMES_IX, 7779 FW_STAT_RX_PORT_BCAST_IX, 7780 FW_STAT_RX_PORT_MCAST_IX, 7781 FW_STAT_RX_PORT_UCAST_IX, 7782 FW_STAT_RX_PORT_MTU_ERROR_IX, 7783 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 7784 FW_STAT_RX_PORT_CRC_ERROR_IX, 7785 FW_STAT_RX_PORT_LEN_ERROR_IX, 7786 FW_STAT_RX_PORT_SYM_ERROR_IX, 7787 FW_STAT_RX_PORT_64B_IX, 7788 FW_STAT_RX_PORT_65B_127B_IX, 7789 FW_STAT_RX_PORT_128B_255B_IX, 7790 FW_STAT_RX_PORT_256B_511B_IX, 7791 FW_STAT_RX_PORT_512B_1023B_IX, 7792 FW_STAT_RX_PORT_1024B_1518B_IX, 7793 FW_STAT_RX_PORT_1519B_MAX_IX, 7794 FW_STAT_RX_PORT_PAUSE_IX, 7795 FW_STAT_RX_PORT_PPP0_IX, 7796 FW_STAT_RX_PORT_PPP1_IX, 7797 FW_STAT_RX_PORT_PPP2_IX, 7798 FW_STAT_RX_PORT_PPP3_IX, 7799 FW_STAT_RX_PORT_PPP4_IX, 7800 FW_STAT_RX_PORT_PPP5_IX, 7801 FW_STAT_RX_PORT_PPP6_IX, 7802 FW_STAT_RX_PORT_PPP7_IX, 7803 FW_STAT_RX_PORT_LESS_64B_IX, 7804 FW_STAT_RX_PORT_MAC_ERROR_IX, 7805 FW_NUM_PORT_RX_STATS 7806 }; 7807 /* port stats */ 7808 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 7809 FW_NUM_PORT_RX_STATS) 7810 7811 7812 struct fw_port_stats_cmd { 7813 __be32 op_to_portid; 7814 __be32 retval_len16; 7815 union fw_port_stats { 7816 struct fw_port_stats_ctl { 7817 __u8 nstats_bg_bm; 7818 __u8 tx_ix; 7819 __be16 r6; 7820 __be32 r7; 7821 __be64 stat0; 7822 __be64 stat1; 7823 __be64 stat2; 7824 __be64 stat3; 7825 __be64 stat4; 7826 __be64 stat5; 7827 } ctl; 7828 struct fw_port_stats_all { 7829 __be64 tx_bytes; 7830 __be64 tx_frames; 7831 __be64 tx_bcast; 7832 __be64 tx_mcast; 7833 __be64 tx_ucast; 7834 __be64 tx_error; 7835 __be64 tx_64b; 7836 __be64 tx_65b_127b; 7837 __be64 tx_128b_255b; 7838 __be64 tx_256b_511b; 7839 __be64 tx_512b_1023b; 7840 __be64 tx_1024b_1518b; 7841 __be64 tx_1519b_max; 7842 __be64 tx_drop; 7843 __be64 tx_pause; 7844 __be64 tx_ppp0; 7845 __be64 tx_ppp1; 7846 __be64 tx_ppp2; 7847 __be64 tx_ppp3; 7848 __be64 tx_ppp4; 7849 __be64 tx_ppp5; 7850 __be64 tx_ppp6; 7851 __be64 tx_ppp7; 7852 __be64 rx_bytes; 7853 __be64 rx_frames; 7854 __be64 rx_bcast; 7855 __be64 rx_mcast; 7856 __be64 rx_ucast; 7857 __be64 rx_mtu_error; 7858 __be64 rx_mtu_crc_error; 7859 __be64 rx_crc_error; 7860 __be64 rx_len_error; 7861 __be64 rx_sym_error; 7862 __be64 rx_64b; 7863 __be64 rx_65b_127b; 7864 __be64 rx_128b_255b; 7865 __be64 rx_256b_511b; 7866 __be64 rx_512b_1023b; 7867 __be64 rx_1024b_1518b; 7868 __be64 rx_1519b_max; 7869 __be64 rx_pause; 7870 __be64 rx_ppp0; 7871 __be64 rx_ppp1; 7872 __be64 rx_ppp2; 7873 __be64 rx_ppp3; 7874 __be64 rx_ppp4; 7875 __be64 rx_ppp5; 7876 __be64 rx_ppp6; 7877 __be64 rx_ppp7; 7878 __be64 rx_less_64b; 7879 __be64 rx_bg_drop; 7880 __be64 rx_bg_trunc; 7881 } all; 7882 } u; 7883 }; 7884 7885 #define S_FW_PORT_STATS_CMD_NSTATS 4 7886 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 7887 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 7888 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 7889 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 7890 7891 #define S_FW_PORT_STATS_CMD_BG_BM 0 7892 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 7893 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 7894 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 7895 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 7896 7897 #define S_FW_PORT_STATS_CMD_TX 7 7898 #define M_FW_PORT_STATS_CMD_TX 0x1 7899 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 7900 #define G_FW_PORT_STATS_CMD_TX(x) \ 7901 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 7902 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 7903 7904 #define S_FW_PORT_STATS_CMD_IX 0 7905 #define M_FW_PORT_STATS_CMD_IX 0x3f 7906 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 7907 #define G_FW_PORT_STATS_CMD_IX(x) \ 7908 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 7909 7910 /* port loopback stats */ 7911 #define FW_NUM_LB_STATS 14 7912 enum fw_port_lb_stats_index { 7913 FW_STAT_LB_PORT_BYTES_IX, 7914 FW_STAT_LB_PORT_FRAMES_IX, 7915 FW_STAT_LB_PORT_BCAST_IX, 7916 FW_STAT_LB_PORT_MCAST_IX, 7917 FW_STAT_LB_PORT_UCAST_IX, 7918 FW_STAT_LB_PORT_ERROR_IX, 7919 FW_STAT_LB_PORT_64B_IX, 7920 FW_STAT_LB_PORT_65B_127B_IX, 7921 FW_STAT_LB_PORT_128B_255B_IX, 7922 FW_STAT_LB_PORT_256B_511B_IX, 7923 FW_STAT_LB_PORT_512B_1023B_IX, 7924 FW_STAT_LB_PORT_1024B_1518B_IX, 7925 FW_STAT_LB_PORT_1519B_MAX_IX, 7926 FW_STAT_LB_PORT_DROP_FRAMES_IX 7927 }; 7928 7929 struct fw_port_lb_stats_cmd { 7930 __be32 op_to_lbport; 7931 __be32 retval_len16; 7932 union fw_port_lb_stats { 7933 struct fw_port_lb_stats_ctl { 7934 __u8 nstats_bg_bm; 7935 __u8 ix_pkd; 7936 __be16 r6; 7937 __be32 r7; 7938 __be64 stat0; 7939 __be64 stat1; 7940 __be64 stat2; 7941 __be64 stat3; 7942 __be64 stat4; 7943 __be64 stat5; 7944 } ctl; 7945 struct fw_port_lb_stats_all { 7946 __be64 tx_bytes; 7947 __be64 tx_frames; 7948 __be64 tx_bcast; 7949 __be64 tx_mcast; 7950 __be64 tx_ucast; 7951 __be64 tx_error; 7952 __be64 tx_64b; 7953 __be64 tx_65b_127b; 7954 __be64 tx_128b_255b; 7955 __be64 tx_256b_511b; 7956 __be64 tx_512b_1023b; 7957 __be64 tx_1024b_1518b; 7958 __be64 tx_1519b_max; 7959 __be64 rx_lb_drop; 7960 __be64 rx_lb_trunc; 7961 } all; 7962 } u; 7963 }; 7964 7965 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 7966 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 7967 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7968 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 7969 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7970 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 7971 7972 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 7973 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 7974 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7975 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 7976 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7977 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 7978 7979 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 7980 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 7981 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 7982 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 7983 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 7984 7985 #define S_FW_PORT_LB_STATS_CMD_IX 0 7986 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 7987 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 7988 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 7989 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 7990 7991 /* Trace related defines */ 7992 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 7993 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 7994 7995 struct fw_port_trace_cmd { 7996 __be32 op_to_portid; 7997 __be32 retval_len16; 7998 __be16 traceen_to_pciech; 7999 __be16 qnum; 8000 __be32 r5; 8001 }; 8002 8003 #define S_FW_PORT_TRACE_CMD_PORTID 0 8004 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 8005 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 8006 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 8007 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 8008 8009 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 8010 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 8011 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 8012 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 8013 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 8014 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 8015 8016 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 8017 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 8018 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 8019 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 8020 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 8021 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 8022 8023 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 8024 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 8025 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 8026 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 8027 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 8028 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 8029 8030 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 8031 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 8032 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 8033 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 8034 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 8035 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 8036 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 8037 8038 #define S_FW_PORT_TRACE_CMD_PCIECH 6 8039 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 8040 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 8041 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 8042 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 8043 8044 struct fw_port_trace_mmap_cmd { 8045 __be32 op_to_portid; 8046 __be32 retval_len16; 8047 __be32 fid_to_skipoffset; 8048 __be32 minpktsize_capturemax; 8049 __u8 map[224]; 8050 }; 8051 8052 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 8053 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 8054 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 8055 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 8056 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 8057 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 8058 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 8059 8060 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 8061 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 8062 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 8063 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 8064 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 8065 8066 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 8067 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 8068 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 8069 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 8070 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 8071 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 8072 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 8073 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 8074 8075 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 8076 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 8077 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 8078 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 8079 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 8080 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 8081 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 8082 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 8083 8084 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 8085 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 8086 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 8087 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 8088 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 8089 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 8090 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 8091 8092 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 8093 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 8094 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 8095 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 8096 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 8097 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 8098 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 8099 8100 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 8101 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 8102 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 8103 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 8104 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 8105 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 8106 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 8107 8108 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 8109 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 8110 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 8111 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 8112 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 8113 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 8114 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 8115 8116 enum fw_ptp_subop { 8117 8118 /* none */ 8119 FW_PTP_SC_INIT_TIMER = 0x00, 8120 FW_PTP_SC_TX_TYPE = 0x01, 8121 8122 /* init */ 8123 FW_PTP_SC_RXTIME_STAMP = 0x08, 8124 FW_PTP_SC_RDRX_TYPE = 0x09, 8125 8126 /* ts */ 8127 FW_PTP_SC_ADJ_FREQ = 0x10, 8128 FW_PTP_SC_ADJ_TIME = 0x11, 8129 FW_PTP_SC_ADJ_FTIME = 0x12, 8130 FW_PTP_SC_WALL_CLOCK = 0x13, 8131 FW_PTP_SC_GET_TIME = 0x14, 8132 FW_PTP_SC_SET_TIME = 0x15, 8133 }; 8134 8135 struct fw_ptp_cmd { 8136 __be32 op_to_portid; 8137 __be32 retval_len16; 8138 union fw_ptp { 8139 struct fw_ptp_sc { 8140 __u8 sc; 8141 __u8 r3[7]; 8142 } scmd; 8143 struct fw_ptp_init { 8144 __u8 sc; 8145 __u8 txchan; 8146 __be16 absid; 8147 __be16 mode; 8148 __be16 r3; 8149 } init; 8150 struct fw_ptp_ts { 8151 __u8 sc; 8152 __u8 sign; 8153 __be16 r3; 8154 __be32 ppb; 8155 __be64 tm; 8156 } ts; 8157 } u; 8158 __be64 r3; 8159 }; 8160 8161 #define S_FW_PTP_CMD_PORTID 0 8162 #define M_FW_PTP_CMD_PORTID 0xf 8163 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 8164 #define G_FW_PTP_CMD_PORTID(x) \ 8165 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 8166 8167 struct fw_rss_ind_tbl_cmd { 8168 __be32 op_to_viid; 8169 __be32 retval_len16; 8170 __be16 niqid; 8171 __be16 startidx; 8172 __be32 r3; 8173 __be32 iq0_to_iq2; 8174 __be32 iq3_to_iq5; 8175 __be32 iq6_to_iq8; 8176 __be32 iq9_to_iq11; 8177 __be32 iq12_to_iq14; 8178 __be32 iq15_to_iq17; 8179 __be32 iq18_to_iq20; 8180 __be32 iq21_to_iq23; 8181 __be32 iq24_to_iq26; 8182 __be32 iq27_to_iq29; 8183 __be32 iq30_iq31; 8184 __be32 r15_lo; 8185 }; 8186 8187 #define S_FW_RSS_IND_TBL_CMD_VIID 0 8188 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 8189 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 8190 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 8191 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 8192 8193 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 8194 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 8195 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 8196 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 8197 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 8198 8199 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 8200 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 8201 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 8202 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 8203 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 8204 8205 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 8206 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 8207 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 8208 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 8209 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 8210 8211 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 8212 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 8213 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 8214 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 8215 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 8216 8217 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 8218 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 8219 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 8220 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 8221 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 8222 8223 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 8224 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 8225 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 8226 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 8227 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 8228 8229 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 8230 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 8231 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 8232 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 8233 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 8234 8235 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 8236 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 8237 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 8238 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 8239 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 8240 8241 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 8242 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 8243 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 8244 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 8245 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 8246 8247 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 8248 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 8249 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 8250 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 8251 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 8252 8253 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 8254 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 8255 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 8256 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 8257 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 8258 8259 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 8260 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 8261 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 8262 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 8263 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 8264 8265 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 8266 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 8267 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 8268 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 8269 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 8270 8271 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 8272 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 8273 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 8274 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 8275 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 8276 8277 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 8278 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 8279 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 8280 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 8281 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 8282 8283 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 8284 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 8285 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 8286 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 8287 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 8288 8289 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 8290 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 8291 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 8292 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 8293 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 8294 8295 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 8296 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 8297 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 8298 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 8299 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 8300 8301 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 8302 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 8303 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 8304 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 8305 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 8306 8307 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 8308 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 8309 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 8310 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 8311 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 8312 8313 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 8314 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 8315 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 8316 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 8317 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 8318 8319 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 8320 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 8321 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 8322 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 8323 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 8324 8325 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 8326 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 8327 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 8328 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 8329 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 8330 8331 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 8332 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 8333 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 8334 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 8335 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 8336 8337 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 8338 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 8339 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 8340 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 8341 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 8342 8343 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 8344 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 8345 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 8346 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 8347 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 8348 8349 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 8350 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 8351 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 8352 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 8353 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 8354 8355 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 8356 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 8357 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 8358 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 8359 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 8360 8361 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 8362 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 8363 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 8364 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 8365 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 8366 8367 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 8368 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 8369 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 8370 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 8371 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 8372 8373 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 8374 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 8375 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 8376 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 8377 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 8378 8379 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 8380 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 8381 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 8382 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 8383 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 8384 8385 struct fw_rss_glb_config_cmd { 8386 __be32 op_to_write; 8387 __be32 retval_len16; 8388 union fw_rss_glb_config { 8389 struct fw_rss_glb_config_manual { 8390 __be32 mode_pkd; 8391 __be32 r3; 8392 __be64 r4; 8393 __be64 r5; 8394 } manual; 8395 struct fw_rss_glb_config_basicvirtual { 8396 __be32 mode_keymode; 8397 __be32 synmapen_to_hashtoeplitz; 8398 __be64 r8; 8399 __be64 r9; 8400 } basicvirtual; 8401 } u; 8402 }; 8403 8404 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 8405 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 8406 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 8407 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 8408 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 8409 8410 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 8411 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 8412 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 8413 8414 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 8415 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 8416 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8417 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8418 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8419 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 8420 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8421 8422 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 8423 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 8424 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 8425 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 8426 8427 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 8428 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 8429 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8430 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8431 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8432 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 8433 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8434 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 8435 8436 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 8437 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 8438 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8439 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8440 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8441 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 8442 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8443 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 8444 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 8445 8446 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 8447 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 8448 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8449 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8450 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8451 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 8452 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8453 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 8454 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 8455 8456 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 8457 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 8458 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8459 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8460 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8461 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 8462 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8463 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 8464 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 8465 8466 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 8467 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 8468 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8469 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8470 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8471 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 8472 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8473 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 8474 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 8475 8476 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 8477 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 8478 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8479 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8480 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8481 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 8482 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8483 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 8484 8485 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 8486 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 8487 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8488 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8489 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8490 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 8491 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8492 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 8493 8494 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 8495 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 8496 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8497 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8498 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8499 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 8500 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8501 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 8502 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 8503 8504 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 8505 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 8506 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8507 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8508 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8509 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 8510 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8511 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 8512 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 8513 8514 struct fw_rss_vi_config_cmd { 8515 __be32 op_to_viid; 8516 __be32 retval_len16; 8517 union fw_rss_vi_config { 8518 struct fw_rss_vi_config_manual { 8519 __be64 r3; 8520 __be64 r4; 8521 __be64 r5; 8522 } manual; 8523 struct fw_rss_vi_config_basicvirtual { 8524 __be32 r6; 8525 __be32 defaultq_to_udpen; 8526 __be32 secretkeyidx_pkd; 8527 __be32 secretkeyxor; 8528 __be64 r10; 8529 } basicvirtual; 8530 } u; 8531 }; 8532 8533 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 8534 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 8535 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 8536 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 8537 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 8538 8539 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 8540 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 8541 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8542 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8543 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8544 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 8545 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8546 8547 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 8548 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 8549 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8550 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8551 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8552 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 8553 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8554 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 8555 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 8556 8557 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 8558 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 8559 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8560 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8561 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8562 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 8563 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8564 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 8565 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 8566 8567 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 8568 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 8569 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8570 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8571 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8572 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 8573 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8574 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 8575 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 8576 8577 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 8578 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 8579 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8580 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8581 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8582 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 8583 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8584 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 8585 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 8586 8587 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 8588 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 8589 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 8590 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 8591 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 8592 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 8593 8594 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 8595 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 8596 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8597 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8598 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8599 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 8600 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8601 8602 enum fw_sched_sc { 8603 FW_SCHED_SC_CONFIG = 0, 8604 FW_SCHED_SC_PARAMS = 1, 8605 }; 8606 8607 enum fw_sched_type { 8608 FW_SCHED_TYPE_PKTSCHED = 0, 8609 FW_SCHED_TYPE_STREAMSCHED = 1, 8610 }; 8611 8612 enum fw_sched_params_level { 8613 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 8614 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 8615 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 8616 }; 8617 8618 enum fw_sched_params_mode { 8619 FW_SCHED_PARAMS_MODE_CLASS = 0, 8620 FW_SCHED_PARAMS_MODE_FLOW = 1, 8621 }; 8622 8623 enum fw_sched_params_unit { 8624 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 8625 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 8626 }; 8627 8628 enum fw_sched_params_rate { 8629 FW_SCHED_PARAMS_RATE_REL = 0, 8630 FW_SCHED_PARAMS_RATE_ABS = 1, 8631 }; 8632 8633 struct fw_sched_cmd { 8634 __be32 op_to_write; 8635 __be32 retval_len16; 8636 union fw_sched { 8637 struct fw_sched_config { 8638 __u8 sc; 8639 __u8 type; 8640 __u8 minmaxen; 8641 __u8 r3[5]; 8642 __u8 nclasses[4]; 8643 __be32 r4; 8644 } config; 8645 struct fw_sched_params { 8646 __u8 sc; 8647 __u8 type; 8648 __u8 level; 8649 __u8 mode; 8650 __u8 unit; 8651 __u8 rate; 8652 __u8 ch; 8653 __u8 cl; 8654 __be32 min; 8655 __be32 max; 8656 __be16 weight; 8657 __be16 pktsize; 8658 __be16 burstsize; 8659 __be16 r4; 8660 } params; 8661 } u; 8662 }; 8663 8664 /* 8665 * length of the formatting string 8666 */ 8667 #define FW_DEVLOG_FMT_LEN 192 8668 8669 /* 8670 * maximum number of the formatting string parameters 8671 */ 8672 #define FW_DEVLOG_FMT_PARAMS_NUM 8 8673 8674 /* 8675 * priority levels 8676 */ 8677 enum fw_devlog_level { 8678 FW_DEVLOG_LEVEL_EMERG = 0x0, 8679 FW_DEVLOG_LEVEL_CRIT = 0x1, 8680 FW_DEVLOG_LEVEL_ERR = 0x2, 8681 FW_DEVLOG_LEVEL_NOTICE = 0x3, 8682 FW_DEVLOG_LEVEL_INFO = 0x4, 8683 FW_DEVLOG_LEVEL_DEBUG = 0x5, 8684 FW_DEVLOG_LEVEL_MAX = 0x5, 8685 }; 8686 8687 /* 8688 * facilities that may send a log message 8689 */ 8690 enum fw_devlog_facility { 8691 FW_DEVLOG_FACILITY_CORE = 0x00, 8692 FW_DEVLOG_FACILITY_CF = 0x01, 8693 FW_DEVLOG_FACILITY_SCHED = 0x02, 8694 FW_DEVLOG_FACILITY_TIMER = 0x04, 8695 FW_DEVLOG_FACILITY_RES = 0x06, 8696 FW_DEVLOG_FACILITY_HW = 0x08, 8697 FW_DEVLOG_FACILITY_FLR = 0x10, 8698 FW_DEVLOG_FACILITY_DMAQ = 0x12, 8699 FW_DEVLOG_FACILITY_PHY = 0x14, 8700 FW_DEVLOG_FACILITY_MAC = 0x16, 8701 FW_DEVLOG_FACILITY_PORT = 0x18, 8702 FW_DEVLOG_FACILITY_VI = 0x1A, 8703 FW_DEVLOG_FACILITY_FILTER = 0x1C, 8704 FW_DEVLOG_FACILITY_ACL = 0x1E, 8705 FW_DEVLOG_FACILITY_TM = 0x20, 8706 FW_DEVLOG_FACILITY_QFC = 0x22, 8707 FW_DEVLOG_FACILITY_DCB = 0x24, 8708 FW_DEVLOG_FACILITY_ETH = 0x26, 8709 FW_DEVLOG_FACILITY_OFLD = 0x28, 8710 FW_DEVLOG_FACILITY_RI = 0x2A, 8711 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 8712 FW_DEVLOG_FACILITY_FCOE = 0x2E, 8713 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 8714 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 8715 FW_DEVLOG_FACILITY_CHNET = 0x34, 8716 FW_DEVLOG_FACILITY_COISCSI = 0x36, 8717 FW_DEVLOG_FACILITY_MAX = 0x38, 8718 }; 8719 8720 /* 8721 * log message format 8722 */ 8723 struct fw_devlog_e { 8724 __be64 timestamp; 8725 __be32 seqno; 8726 __be16 reserved1; 8727 __u8 level; 8728 __u8 facility; 8729 __u8 fmt[FW_DEVLOG_FMT_LEN]; 8730 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 8731 __be32 reserved3[4]; 8732 }; 8733 8734 struct fw_devlog_cmd { 8735 __be32 op_to_write; 8736 __be32 retval_len16; 8737 __u8 level; 8738 __u8 r2[7]; 8739 __be32 memtype_devlog_memaddr16_devlog; 8740 __be32 memsize_devlog; 8741 __be32 r3[2]; 8742 }; 8743 8744 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 8745 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 8746 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8747 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8748 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8749 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8750 8751 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 8752 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 8753 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8754 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8755 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8756 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 8757 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8758 8759 enum fw_watchdog_actions { 8760 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 8761 FW_WATCHDOG_ACTION_FLR = 1, 8762 FW_WATCHDOG_ACTION_BYPASS = 2, 8763 FW_WATCHDOG_ACTION_TMPCHK = 3, 8764 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 8765 8766 FW_WATCHDOG_ACTION_MAX = 5, 8767 }; 8768 8769 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 8770 8771 struct fw_watchdog_cmd { 8772 __be32 op_to_vfn; 8773 __be32 retval_len16; 8774 __be32 timeout; 8775 __be32 action; 8776 }; 8777 8778 #define S_FW_WATCHDOG_CMD_PFN 8 8779 #define M_FW_WATCHDOG_CMD_PFN 0x7 8780 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 8781 #define G_FW_WATCHDOG_CMD_PFN(x) \ 8782 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 8783 8784 #define S_FW_WATCHDOG_CMD_VFN 0 8785 #define M_FW_WATCHDOG_CMD_VFN 0xff 8786 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 8787 #define G_FW_WATCHDOG_CMD_VFN(x) \ 8788 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 8789 8790 struct fw_clip_cmd { 8791 __be32 op_to_write; 8792 __be32 alloc_to_len16; 8793 __be64 ip_hi; 8794 __be64 ip_lo; 8795 __be32 r4[2]; 8796 }; 8797 8798 #define S_FW_CLIP_CMD_ALLOC 31 8799 #define M_FW_CLIP_CMD_ALLOC 0x1 8800 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 8801 #define G_FW_CLIP_CMD_ALLOC(x) \ 8802 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 8803 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 8804 8805 #define S_FW_CLIP_CMD_FREE 30 8806 #define M_FW_CLIP_CMD_FREE 0x1 8807 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 8808 #define G_FW_CLIP_CMD_FREE(x) \ 8809 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 8810 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 8811 8812 #define S_FW_CLIP_CMD_INDEX 16 8813 #define M_FW_CLIP_CMD_INDEX 0x1fff 8814 #define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX) 8815 #define G_FW_CLIP_CMD_INDEX(x) \ 8816 (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX) 8817 8818 /****************************************************************************** 8819 * F O i S C S I C O M M A N D s 8820 **************************************/ 8821 8822 #define FW_CHNET_IFACE_ADDR_MAX 3 8823 8824 enum fw_chnet_iface_cmd_subop { 8825 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 8826 8827 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 8828 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 8829 8830 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 8831 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 8832 8833 FW_CHNET_IFACE_CMD_SUBOP_MAX, 8834 }; 8835 8836 struct fw_chnet_iface_cmd { 8837 __be32 op_to_portid; 8838 __be32 retval_len16; 8839 __u8 subop; 8840 __u8 r2[2]; 8841 __u8 flags; 8842 __be32 ifid_ifstate; 8843 __be16 mtu; 8844 __be16 vlanid; 8845 __be32 r3; 8846 __be16 r4; 8847 __u8 mac[6]; 8848 }; 8849 8850 #define S_FW_CHNET_IFACE_CMD_PORTID 0 8851 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 8852 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 8853 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 8854 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 8855 8856 #define S_FW_CHNET_IFACE_CMD_RSS_IQID 16 8857 #define M_FW_CHNET_IFACE_CMD_RSS_IQID 0xffff 8858 #define V_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 8859 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID) 8860 #define G_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 8861 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID) 8862 8863 #define S_FW_CHNET_IFACE_CMD_RSS_IQID_F 0 8864 #define M_FW_CHNET_IFACE_CMD_RSS_IQID_F 0x1 8865 #define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 8866 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F) 8867 #define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 8868 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) & \ 8869 M_FW_CHNET_IFACE_CMD_RSS_IQID_F) 8870 #define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U) 8871 8872 #define S_FW_CHNET_IFACE_CMD_IFID 8 8873 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 8874 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 8875 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 8876 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 8877 8878 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 8879 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 8880 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 8881 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 8882 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 8883 8884 struct fw_fcoe_res_info_cmd { 8885 __be32 op_to_read; 8886 __be32 retval_len16; 8887 __be16 e_d_tov; 8888 __be16 r_a_tov_seq; 8889 __be16 r_a_tov_els; 8890 __be16 r_r_tov; 8891 __be32 max_xchgs; 8892 __be32 max_ssns; 8893 __be32 used_xchgs; 8894 __be32 used_ssns; 8895 __be32 max_fcfs; 8896 __be32 max_vnps; 8897 __be32 used_fcfs; 8898 __be32 used_vnps; 8899 }; 8900 8901 struct fw_fcoe_link_cmd { 8902 __be32 op_to_portid; 8903 __be32 retval_len16; 8904 __be32 sub_opcode_fcfi; 8905 __u8 r3; 8906 __u8 lstatus; 8907 __be16 flags; 8908 __u8 r4; 8909 __u8 set_vlan; 8910 __be16 vlan_id; 8911 __be32 vnpi_pkd; 8912 __be16 r6; 8913 __u8 phy_mac[6]; 8914 __u8 vnport_wwnn[8]; 8915 __u8 vnport_wwpn[8]; 8916 }; 8917 8918 #define S_FW_FCOE_LINK_CMD_PORTID 0 8919 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 8920 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 8921 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 8922 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 8923 8924 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 8925 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 8926 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8927 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 8928 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8929 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 8930 8931 #define S_FW_FCOE_LINK_CMD_FCFI 0 8932 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 8933 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 8934 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 8935 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 8936 8937 #define S_FW_FCOE_LINK_CMD_VNPI 0 8938 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 8939 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 8940 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 8941 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 8942 8943 struct fw_fcoe_vnp_cmd { 8944 __be32 op_to_fcfi; 8945 __be32 alloc_to_len16; 8946 __be32 gen_wwn_to_vnpi; 8947 __be32 vf_id; 8948 __be16 iqid; 8949 __u8 vnport_mac[6]; 8950 __u8 vnport_wwnn[8]; 8951 __u8 vnport_wwpn[8]; 8952 __u8 cmn_srv_parms[16]; 8953 __u8 clsp_word_0_1[8]; 8954 }; 8955 8956 #define S_FW_FCOE_VNP_CMD_FCFI 0 8957 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 8958 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 8959 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 8960 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 8961 8962 #define S_FW_FCOE_VNP_CMD_ALLOC 31 8963 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 8964 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 8965 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 8966 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 8967 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 8968 8969 #define S_FW_FCOE_VNP_CMD_FREE 30 8970 #define M_FW_FCOE_VNP_CMD_FREE 0x1 8971 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 8972 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 8973 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 8974 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 8975 8976 #define S_FW_FCOE_VNP_CMD_MODIFY 29 8977 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 8978 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 8979 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 8980 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 8981 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 8982 8983 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 8984 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 8985 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 8986 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 8987 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 8988 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 8989 8990 #define S_FW_FCOE_VNP_CMD_PERSIST 21 8991 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 8992 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 8993 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 8994 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 8995 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 8996 8997 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 8998 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 8999 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 9000 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 9001 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 9002 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 9003 9004 #define S_FW_FCOE_VNP_CMD_VNPI 0 9005 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 9006 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 9007 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 9008 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 9009 9010 struct fw_fcoe_sparams_cmd { 9011 __be32 op_to_portid; 9012 __be32 retval_len16; 9013 __u8 r3[7]; 9014 __u8 cos; 9015 __u8 lport_wwnn[8]; 9016 __u8 lport_wwpn[8]; 9017 __u8 cmn_srv_parms[16]; 9018 __u8 cls_srv_parms[16]; 9019 }; 9020 9021 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 9022 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 9023 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 9024 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 9025 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 9026 9027 struct fw_fcoe_stats_cmd { 9028 __be32 op_to_flowid; 9029 __be32 free_to_len16; 9030 union fw_fcoe_stats { 9031 struct fw_fcoe_stats_ctl { 9032 __u8 nstats_port; 9033 __u8 port_valid_ix; 9034 __be16 r6; 9035 __be32 r7; 9036 __be64 stat0; 9037 __be64 stat1; 9038 __be64 stat2; 9039 __be64 stat3; 9040 __be64 stat4; 9041 __be64 stat5; 9042 } ctl; 9043 struct fw_fcoe_port_stats { 9044 __be64 tx_bcast_bytes; 9045 __be64 tx_bcast_frames; 9046 __be64 tx_mcast_bytes; 9047 __be64 tx_mcast_frames; 9048 __be64 tx_ucast_bytes; 9049 __be64 tx_ucast_frames; 9050 __be64 tx_drop_frames; 9051 __be64 tx_offload_bytes; 9052 __be64 tx_offload_frames; 9053 __be64 rx_bcast_bytes; 9054 __be64 rx_bcast_frames; 9055 __be64 rx_mcast_bytes; 9056 __be64 rx_mcast_frames; 9057 __be64 rx_ucast_bytes; 9058 __be64 rx_ucast_frames; 9059 __be64 rx_err_frames; 9060 } port_stats; 9061 struct fw_fcoe_fcf_stats { 9062 __be32 fip_tx_bytes; 9063 __be32 fip_tx_fr; 9064 __be64 fcf_ka; 9065 __be64 mcast_adv_rcvd; 9066 __be16 ucast_adv_rcvd; 9067 __be16 sol_sent; 9068 __be16 vlan_req; 9069 __be16 vlan_rpl; 9070 __be16 clr_vlink; 9071 __be16 link_down; 9072 __be16 link_up; 9073 __be16 logo; 9074 __be16 flogi_req; 9075 __be16 flogi_rpl; 9076 __be16 fdisc_req; 9077 __be16 fdisc_rpl; 9078 __be16 fka_prd_chg; 9079 __be16 fc_map_chg; 9080 __be16 vfid_chg; 9081 __u8 no_fka_req; 9082 __u8 no_vnp; 9083 } fcf_stats; 9084 struct fw_fcoe_pcb_stats { 9085 __be64 tx_bytes; 9086 __be64 tx_frames; 9087 __be64 rx_bytes; 9088 __be64 rx_frames; 9089 __be32 vnp_ka; 9090 __be32 unsol_els_rcvd; 9091 __be64 unsol_cmd_rcvd; 9092 __be16 implicit_logo; 9093 __be16 flogi_inv_sparm; 9094 __be16 fdisc_inv_sparm; 9095 __be16 flogi_rjt; 9096 __be16 fdisc_rjt; 9097 __be16 no_ssn; 9098 __be16 mac_flt_fail; 9099 __be16 inv_fr_rcvd; 9100 } pcb_stats; 9101 struct fw_fcoe_scb_stats { 9102 __be64 tx_bytes; 9103 __be64 tx_frames; 9104 __be64 rx_bytes; 9105 __be64 rx_frames; 9106 __be32 host_abrt_req; 9107 __be32 adap_auto_abrt; 9108 __be32 adap_abrt_rsp; 9109 __be32 host_ios_req; 9110 __be16 ssn_offl_ios; 9111 __be16 ssn_not_rdy_ios; 9112 __u8 rx_data_ddp_err; 9113 __u8 ddp_flt_set_err; 9114 __be16 rx_data_fr_err; 9115 __u8 bad_st_abrt_req; 9116 __u8 no_io_abrt_req; 9117 __u8 abort_tmo; 9118 __u8 abort_tmo_2; 9119 __be32 abort_req; 9120 __u8 no_ppod_res_tmo; 9121 __u8 bp_tmo; 9122 __u8 adap_auto_cls; 9123 __u8 no_io_cls_req; 9124 __be32 host_cls_req; 9125 __be64 unsol_cmd_rcvd; 9126 __be32 plogi_req_rcvd; 9127 __be32 prli_req_rcvd; 9128 __be16 logo_req_rcvd; 9129 __be16 prlo_req_rcvd; 9130 __be16 plogi_rjt_rcvd; 9131 __be16 prli_rjt_rcvd; 9132 __be32 adisc_req_rcvd; 9133 __be32 rscn_rcvd; 9134 __be32 rrq_req_rcvd; 9135 __be32 unsol_els_rcvd; 9136 __u8 adisc_rjt_rcvd; 9137 __u8 scr_rjt; 9138 __u8 ct_rjt; 9139 __u8 inval_bls_rcvd; 9140 __be32 ba_rjt_rcvd; 9141 } scb_stats; 9142 } u; 9143 }; 9144 9145 #define S_FW_FCOE_STATS_CMD_FLOWID 0 9146 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 9147 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 9148 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 9149 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 9150 9151 #define S_FW_FCOE_STATS_CMD_FREE 30 9152 #define M_FW_FCOE_STATS_CMD_FREE 0x1 9153 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 9154 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 9155 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 9156 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 9157 9158 #define S_FW_FCOE_STATS_CMD_NSTATS 4 9159 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 9160 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 9161 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 9162 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 9163 9164 #define S_FW_FCOE_STATS_CMD_PORT 0 9165 #define M_FW_FCOE_STATS_CMD_PORT 0x3 9166 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 9167 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 9168 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 9169 9170 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 9171 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 9172 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 9173 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 9174 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 9175 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 9176 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 9177 9178 #define S_FW_FCOE_STATS_CMD_IX 0 9179 #define M_FW_FCOE_STATS_CMD_IX 0x3f 9180 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 9181 #define G_FW_FCOE_STATS_CMD_IX(x) \ 9182 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 9183 9184 struct fw_fcoe_fcf_cmd { 9185 __be32 op_to_fcfi; 9186 __be32 retval_len16; 9187 __be16 priority_pkd; 9188 __u8 mac[6]; 9189 __u8 name_id[8]; 9190 __u8 fabric[8]; 9191 __be16 vf_id; 9192 __be16 max_fcoe_size; 9193 __u8 vlan_id; 9194 __u8 fc_map[3]; 9195 __be32 fka_adv; 9196 __be32 r6; 9197 __u8 r7_hi; 9198 __u8 fpma_to_portid; 9199 __u8 spma_mac[6]; 9200 __be64 r8; 9201 }; 9202 9203 #define S_FW_FCOE_FCF_CMD_FCFI 0 9204 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 9205 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 9206 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 9207 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 9208 9209 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 9210 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 9211 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 9212 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 9213 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 9214 9215 #define S_FW_FCOE_FCF_CMD_FPMA 6 9216 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 9217 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 9218 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 9219 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 9220 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 9221 9222 #define S_FW_FCOE_FCF_CMD_SPMA 5 9223 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 9224 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 9225 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 9226 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 9227 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 9228 9229 #define S_FW_FCOE_FCF_CMD_LOGIN 4 9230 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 9231 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 9232 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 9233 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 9234 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 9235 9236 #define S_FW_FCOE_FCF_CMD_PORTID 0 9237 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 9238 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 9239 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 9240 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 9241 9242 /****************************************************************************** 9243 * E R R O R a n d D E B U G C O M M A N D s 9244 ******************************************************/ 9245 9246 enum fw_error_type { 9247 FW_ERROR_TYPE_EXCEPTION = 0x0, 9248 FW_ERROR_TYPE_HWMODULE = 0x1, 9249 FW_ERROR_TYPE_WR = 0x2, 9250 FW_ERROR_TYPE_ACL = 0x3, 9251 }; 9252 9253 enum fw_dcb_ieee_locations { 9254 FW_IEEE_LOC_LOCAL, 9255 FW_IEEE_LOC_PEER, 9256 FW_IEEE_LOC_OPERATIONAL, 9257 }; 9258 9259 struct fw_dcb_ieee_cmd { 9260 __be32 op_to_location; 9261 __be32 changed_to_len16; 9262 union fw_dcbx_stats { 9263 struct fw_dcbx_pfc_stats_ieee { 9264 __be32 pfc_mbc_pkd; 9265 __be32 pfc_willing_to_pfc_en; 9266 } dcbx_pfc_stats; 9267 struct fw_dcbx_ets_stats_ieee { 9268 __be32 cbs_to_ets_max_tc; 9269 __be32 pg_table; 9270 __u8 pg_percent[8]; 9271 __u8 tsa[8]; 9272 } dcbx_ets_stats; 9273 struct fw_dcbx_app_stats_ieee { 9274 __be32 num_apps_pkd; 9275 __be32 r6; 9276 __be32 app[4]; 9277 } dcbx_app_stats; 9278 struct fw_dcbx_control { 9279 __be32 multi_peer_invalidated; 9280 __u8 version; 9281 __u8 r6[3]; 9282 } dcbx_control; 9283 } u; 9284 }; 9285 9286 #define S_FW_DCB_IEEE_CMD_PORT 8 9287 #define M_FW_DCB_IEEE_CMD_PORT 0x7 9288 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 9289 #define G_FW_DCB_IEEE_CMD_PORT(x) \ 9290 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 9291 9292 #define S_FW_DCB_IEEE_CMD_FEATURE 2 9293 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 9294 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 9295 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 9296 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 9297 9298 #define S_FW_DCB_IEEE_CMD_LOCATION 0 9299 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 9300 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 9301 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 9302 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 9303 9304 #define S_FW_DCB_IEEE_CMD_CHANGED 20 9305 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 9306 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 9307 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 9308 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 9309 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 9310 9311 #define S_FW_DCB_IEEE_CMD_RECEIVED 19 9312 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 9313 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 9314 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 9315 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 9316 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 9317 9318 #define S_FW_DCB_IEEE_CMD_APPLY 18 9319 #define M_FW_DCB_IEEE_CMD_APPLY 0x1 9320 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 9321 #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 9322 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 9323 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 9324 9325 #define S_FW_DCB_IEEE_CMD_DISABLED 17 9326 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 9327 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 9328 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 9329 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 9330 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 9331 9332 #define S_FW_DCB_IEEE_CMD_MORE 16 9333 #define M_FW_DCB_IEEE_CMD_MORE 0x1 9334 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 9335 #define G_FW_DCB_IEEE_CMD_MORE(x) \ 9336 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 9337 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 9338 9339 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 9340 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 9341 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 9342 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 9343 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 9344 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 9345 9346 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 9347 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 9348 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9349 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 9350 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9351 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 9352 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 9353 9354 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 9355 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 9356 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9357 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 9358 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9359 9360 #define S_FW_DCB_IEEE_CMD_PFC_EN 0 9361 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 9362 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 9363 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 9364 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 9365 9366 #define S_FW_DCB_IEEE_CMD_CBS 16 9367 #define M_FW_DCB_IEEE_CMD_CBS 0x1 9368 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 9369 #define G_FW_DCB_IEEE_CMD_CBS(x) \ 9370 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 9371 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 9372 9373 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 9374 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 9375 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9376 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 9377 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9378 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 9379 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 9380 9381 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 9382 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 9383 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9384 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 9385 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9386 9387 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 9388 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 9389 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 9390 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 9391 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 9392 9393 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 9394 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 9395 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 9396 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 9397 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 9398 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 9399 9400 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 9401 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 9402 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9403 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 9404 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9405 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 9406 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 9407 9408 /* Hand-written */ 9409 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 9410 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 9411 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9412 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 9413 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9414 9415 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 9416 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 9417 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 9418 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 9419 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 9420 9421 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 9422 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 9423 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 9424 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 9425 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 9426 9427 9428 struct fw_error_cmd { 9429 __be32 op_to_type; 9430 __be32 len16_pkd; 9431 union fw_error { 9432 struct fw_error_exception { 9433 __be32 info[6]; 9434 } exception; 9435 struct fw_error_hwmodule { 9436 __be32 regaddr; 9437 __be32 regval; 9438 } hwmodule; 9439 struct fw_error_wr { 9440 __be16 cidx; 9441 __be16 pfn_vfn; 9442 __be32 eqid; 9443 __u8 wrhdr[16]; 9444 } wr; 9445 struct fw_error_acl { 9446 __be16 cidx; 9447 __be16 pfn_vfn; 9448 __be32 eqid; 9449 __be16 mv_pkd; 9450 __u8 val[6]; 9451 __be64 r4; 9452 } acl; 9453 } u; 9454 }; 9455 9456 #define S_FW_ERROR_CMD_FATAL 4 9457 #define M_FW_ERROR_CMD_FATAL 0x1 9458 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 9459 #define G_FW_ERROR_CMD_FATAL(x) \ 9460 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 9461 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 9462 9463 #define S_FW_ERROR_CMD_TYPE 0 9464 #define M_FW_ERROR_CMD_TYPE 0xf 9465 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 9466 #define G_FW_ERROR_CMD_TYPE(x) \ 9467 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 9468 9469 #define S_FW_ERROR_CMD_PFN 8 9470 #define M_FW_ERROR_CMD_PFN 0x7 9471 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9472 #define G_FW_ERROR_CMD_PFN(x) \ 9473 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9474 9475 #define S_FW_ERROR_CMD_VFN 0 9476 #define M_FW_ERROR_CMD_VFN 0xff 9477 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9478 #define G_FW_ERROR_CMD_VFN(x) \ 9479 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9480 9481 #define S_FW_ERROR_CMD_PFN 8 9482 #define M_FW_ERROR_CMD_PFN 0x7 9483 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9484 #define G_FW_ERROR_CMD_PFN(x) \ 9485 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9486 9487 #define S_FW_ERROR_CMD_VFN 0 9488 #define M_FW_ERROR_CMD_VFN 0xff 9489 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9490 #define G_FW_ERROR_CMD_VFN(x) \ 9491 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9492 9493 #define S_FW_ERROR_CMD_MV 15 9494 #define M_FW_ERROR_CMD_MV 0x1 9495 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 9496 #define G_FW_ERROR_CMD_MV(x) \ 9497 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 9498 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 9499 9500 struct fw_debug_cmd { 9501 __be32 op_type; 9502 __be32 len16_pkd; 9503 union fw_debug { 9504 struct fw_debug_assert { 9505 __be32 fcid; 9506 __be32 line; 9507 __be32 x; 9508 __be32 y; 9509 __u8 filename_0_7[8]; 9510 __u8 filename_8_15[8]; 9511 __be64 r3; 9512 } assert; 9513 struct fw_debug_prt { 9514 __be16 dprtstridx; 9515 __be16 r3[3]; 9516 __be32 dprtstrparam0; 9517 __be32 dprtstrparam1; 9518 __be32 dprtstrparam2; 9519 __be32 dprtstrparam3; 9520 } prt; 9521 } u; 9522 }; 9523 9524 #define S_FW_DEBUG_CMD_TYPE 0 9525 #define M_FW_DEBUG_CMD_TYPE 0xff 9526 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 9527 #define G_FW_DEBUG_CMD_TYPE(x) \ 9528 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 9529 9530 enum fw_diag_cmd_type { 9531 FW_DIAG_CMD_TYPE_OFLDIAG = 0, 9532 }; 9533 9534 enum fw_diag_cmd_ofldiag_op { 9535 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 9536 FW_DIAG_CMD_OFLDIAG_TEST_START, 9537 FW_DIAG_CMD_OFLDIAG_TEST_STOP, 9538 FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 9539 }; 9540 9541 enum fw_diag_cmd_ofldiag_status { 9542 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 9543 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 9544 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 9545 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 9546 }; 9547 9548 struct fw_diag_cmd { 9549 __be32 op_type; 9550 __be32 len16_pkd; 9551 union fw_diag_test { 9552 struct fw_diag_test_ofldiag { 9553 __u8 test_op; 9554 __u8 r3; 9555 __be16 test_status; 9556 __be32 duration; 9557 } ofldiag; 9558 } u; 9559 }; 9560 9561 #define S_FW_DIAG_CMD_TYPE 0 9562 #define M_FW_DIAG_CMD_TYPE 0xff 9563 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 9564 #define G_FW_DIAG_CMD_TYPE(x) \ 9565 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 9566 9567 struct fw_hma_cmd { 9568 __be32 op_pkd; 9569 __be32 retval_len16; 9570 __be32 mode_to_pcie_params; 9571 __be32 naddr_size; 9572 __be32 addr_size_pkd; 9573 __be32 r6; 9574 __be64 phy_address[5]; 9575 }; 9576 9577 #define S_FW_HMA_CMD_MODE 31 9578 #define M_FW_HMA_CMD_MODE 0x1 9579 #define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE) 9580 #define G_FW_HMA_CMD_MODE(x) \ 9581 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE) 9582 #define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U) 9583 9584 #define S_FW_HMA_CMD_SOC 30 9585 #define M_FW_HMA_CMD_SOC 0x1 9586 #define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC) 9587 #define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC) 9588 #define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U) 9589 9590 #define S_FW_HMA_CMD_EOC 29 9591 #define M_FW_HMA_CMD_EOC 0x1 9592 #define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC) 9593 #define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC) 9594 #define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U) 9595 9596 #define S_FW_HMA_CMD_PCIE_PARAMS 0 9597 #define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff 9598 #define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS) 9599 #define G_FW_HMA_CMD_PCIE_PARAMS(x) \ 9600 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS) 9601 9602 #define S_FW_HMA_CMD_NADDR 12 9603 #define M_FW_HMA_CMD_NADDR 0x3f 9604 #define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR) 9605 #define G_FW_HMA_CMD_NADDR(x) \ 9606 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR) 9607 9608 #define S_FW_HMA_CMD_SIZE 0 9609 #define M_FW_HMA_CMD_SIZE 0xfff 9610 #define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE) 9611 #define G_FW_HMA_CMD_SIZE(x) \ 9612 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE) 9613 9614 #define S_FW_HMA_CMD_ADDR_SIZE 11 9615 #define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff 9616 #define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE) 9617 #define G_FW_HMA_CMD_ADDR_SIZE(x) \ 9618 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE) 9619 9620 /****************************************************************************** 9621 * P C I E F W R E G I S T E R 9622 **************************************/ 9623 9624 enum pcie_fw_eval { 9625 PCIE_FW_EVAL_CRASH = 0, 9626 PCIE_FW_EVAL_PREP = 1, 9627 PCIE_FW_EVAL_CONF = 2, 9628 PCIE_FW_EVAL_INIT = 3, 9629 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 9630 PCIE_FW_EVAL_OVERHEAT = 5, 9631 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 9632 }; 9633 9634 /** 9635 * Register definitions for the PCIE_FW register which the firmware uses 9636 * to retain status across RESETs. This register should be considered 9637 * as a READ-ONLY register for Host Software and only to be used to 9638 * track firmware initialization/error state, etc. 9639 */ 9640 #define S_PCIE_FW_ERR 31 9641 #define M_PCIE_FW_ERR 0x1 9642 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 9643 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 9644 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 9645 9646 #define S_PCIE_FW_INIT 30 9647 #define M_PCIE_FW_INIT 0x1 9648 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 9649 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 9650 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 9651 9652 #define S_PCIE_FW_HALT 29 9653 #define M_PCIE_FW_HALT 0x1 9654 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 9655 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 9656 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 9657 9658 #define S_PCIE_FW_EVAL 24 9659 #define M_PCIE_FW_EVAL 0x7 9660 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 9661 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 9662 9663 #define S_PCIE_FW_STAGE 21 9664 #define M_PCIE_FW_STAGE 0x7 9665 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 9666 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 9667 9668 #define S_PCIE_FW_ASYNCNOT_VLD 20 9669 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 9670 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 9671 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 9672 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 9673 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 9674 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 9675 9676 #define S_PCIE_FW_ASYNCNOTINT 19 9677 #define M_PCIE_FW_ASYNCNOTINT 0x1 9678 #define V_PCIE_FW_ASYNCNOTINT(x) \ 9679 ((x) << S_PCIE_FW_ASYNCNOTINT) 9680 #define G_PCIE_FW_ASYNCNOTINT(x) \ 9681 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 9682 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 9683 9684 #define S_PCIE_FW_ASYNCNOT 16 9685 #define M_PCIE_FW_ASYNCNOT 0x7 9686 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 9687 #define G_PCIE_FW_ASYNCNOT(x) \ 9688 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 9689 9690 #define S_PCIE_FW_MASTER_VLD 15 9691 #define M_PCIE_FW_MASTER_VLD 0x1 9692 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 9693 #define G_PCIE_FW_MASTER_VLD(x) \ 9694 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 9695 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 9696 9697 #define S_PCIE_FW_MASTER 12 9698 #define M_PCIE_FW_MASTER 0x7 9699 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 9700 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 9701 9702 #define S_PCIE_FW_RESET_VLD 11 9703 #define M_PCIE_FW_RESET_VLD 0x1 9704 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 9705 #define G_PCIE_FW_RESET_VLD(x) \ 9706 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 9707 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 9708 9709 #define S_PCIE_FW_RESET 8 9710 #define M_PCIE_FW_RESET 0x7 9711 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 9712 #define G_PCIE_FW_RESET(x) \ 9713 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 9714 9715 #define S_PCIE_FW_REGISTERED 0 9716 #define M_PCIE_FW_REGISTERED 0xff 9717 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 9718 #define G_PCIE_FW_REGISTERED(x) \ 9719 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 9720 9721 9722 /****************************************************************************** 9723 * P C I E F W P F 0 R E G I S T E R 9724 **********************************************/ 9725 9726 /* 9727 * this register is available as 32-bit of persistent storage (across 9728 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 9729 * will not write it) 9730 */ 9731 9732 9733 /****************************************************************************** 9734 * P C I E F W P F 7 R E G I S T E R 9735 **********************************************/ 9736 9737 /* 9738 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 9739 * access the "devlog" which needing to contact firmware. The encoding is 9740 * mostly the same as that returned by the DEVLOG command except for the size 9741 * which is encoded as the number of entries in multiples-1 of 128 here rather 9742 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 9743 * and 15 means 2048. This of course in turn constrains the allowed values 9744 * for the devlog size ... 9745 */ 9746 #define PCIE_FW_PF_DEVLOG 7 9747 9748 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 9749 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 9750 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9751 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 9752 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9753 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 9754 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 9755 9756 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 9757 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 9758 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 9759 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 9760 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 9761 9762 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 9763 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 9764 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 9765 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 9766 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 9767 9768 9769 /****************************************************************************** 9770 * B I N A R Y H E A D E R F O R M A T 9771 **********************************************/ 9772 9773 /* 9774 * firmware binary header format 9775 */ 9776 struct fw_hdr { 9777 __u8 ver; 9778 __u8 chip; /* terminator chip family */ 9779 __be16 len512; /* bin length in units of 512-bytes */ 9780 __be32 fw_ver; /* firmware version */ 9781 __be32 tp_microcode_ver; /* tcp processor microcode version */ 9782 __u8 intfver_nic; 9783 __u8 intfver_vnic; 9784 __u8 intfver_ofld; 9785 __u8 intfver_ri; 9786 __u8 intfver_iscsipdu; 9787 __u8 intfver_iscsi; 9788 __u8 intfver_fcoepdu; 9789 __u8 intfver_fcoe; 9790 __u32 reserved2; 9791 __u32 reserved3; 9792 __be32 magic; /* runtime or bootstrap fw */ 9793 __be32 flags; 9794 __be32 reserved6[23]; 9795 }; 9796 9797 enum fw_hdr_chip { 9798 FW_HDR_CHIP_T4, 9799 FW_HDR_CHIP_T5, 9800 FW_HDR_CHIP_T6 9801 }; 9802 9803 #define S_FW_HDR_FW_VER_MAJOR 24 9804 #define M_FW_HDR_FW_VER_MAJOR 0xff 9805 #define V_FW_HDR_FW_VER_MAJOR(x) \ 9806 ((x) << S_FW_HDR_FW_VER_MAJOR) 9807 #define G_FW_HDR_FW_VER_MAJOR(x) \ 9808 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 9809 9810 #define S_FW_HDR_FW_VER_MINOR 16 9811 #define M_FW_HDR_FW_VER_MINOR 0xff 9812 #define V_FW_HDR_FW_VER_MINOR(x) \ 9813 ((x) << S_FW_HDR_FW_VER_MINOR) 9814 #define G_FW_HDR_FW_VER_MINOR(x) \ 9815 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 9816 9817 #define S_FW_HDR_FW_VER_MICRO 8 9818 #define M_FW_HDR_FW_VER_MICRO 0xff 9819 #define V_FW_HDR_FW_VER_MICRO(x) \ 9820 ((x) << S_FW_HDR_FW_VER_MICRO) 9821 #define G_FW_HDR_FW_VER_MICRO(x) \ 9822 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 9823 9824 #define S_FW_HDR_FW_VER_BUILD 0 9825 #define M_FW_HDR_FW_VER_BUILD 0xff 9826 #define V_FW_HDR_FW_VER_BUILD(x) \ 9827 ((x) << S_FW_HDR_FW_VER_BUILD) 9828 #define G_FW_HDR_FW_VER_BUILD(x) \ 9829 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 9830 9831 enum { 9832 T4FW_VERSION_MAJOR = 0x01, 9833 T4FW_VERSION_MINOR = 0x17, 9834 T4FW_VERSION_MICRO = 0x00, 9835 T4FW_VERSION_BUILD = 0x00, 9836 9837 T5FW_VERSION_MAJOR = 0x01, 9838 T5FW_VERSION_MINOR = 0x17, 9839 T5FW_VERSION_MICRO = 0x00, 9840 T5FW_VERSION_BUILD = 0x00, 9841 9842 T6FW_VERSION_MAJOR = 0x01, 9843 T6FW_VERSION_MINOR = 0x17, 9844 T6FW_VERSION_MICRO = 0x00, 9845 T6FW_VERSION_BUILD = 0x00, 9846 }; 9847 9848 enum { 9849 /* T4 9850 */ 9851 T4FW_HDR_INTFVER_NIC = 0x00, 9852 T4FW_HDR_INTFVER_VNIC = 0x00, 9853 T4FW_HDR_INTFVER_OFLD = 0x00, 9854 T4FW_HDR_INTFVER_RI = 0x00, 9855 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 9856 T4FW_HDR_INTFVER_ISCSI = 0x00, 9857 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 9858 T4FW_HDR_INTFVER_FCOE = 0x00, 9859 9860 /* T5 9861 */ 9862 T5FW_HDR_INTFVER_NIC = 0x00, 9863 T5FW_HDR_INTFVER_VNIC = 0x00, 9864 T5FW_HDR_INTFVER_OFLD = 0x00, 9865 T5FW_HDR_INTFVER_RI = 0x00, 9866 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 9867 T5FW_HDR_INTFVER_ISCSI = 0x00, 9868 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 9869 T5FW_HDR_INTFVER_FCOE = 0x00, 9870 9871 /* T6 9872 */ 9873 T6FW_HDR_INTFVER_NIC = 0x00, 9874 T6FW_HDR_INTFVER_VNIC = 0x00, 9875 T6FW_HDR_INTFVER_OFLD = 0x00, 9876 T6FW_HDR_INTFVER_RI = 0x00, 9877 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 9878 T6FW_HDR_INTFVER_ISCSI = 0x00, 9879 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 9880 T6FW_HDR_INTFVER_FCOE = 0x00, 9881 }; 9882 9883 enum { 9884 FW_HDR_MAGIC_RUNTIME = 0x00000000, 9885 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 9886 }; 9887 9888 enum fw_hdr_flags { 9889 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 9890 }; 9891 9892 /* 9893 * External PHY firmware binary header format 9894 */ 9895 struct fw_ephy_hdr { 9896 __u8 ver; 9897 __u8 reserved; 9898 __be16 len512; /* bin length in units of 512-bytes */ 9899 __be32 magic; 9900 9901 __be16 vendor_id; 9902 __be16 device_id; 9903 __be32 version; 9904 9905 __be32 reserved1[4]; 9906 }; 9907 9908 enum { 9909 FW_EPHY_HDR_MAGIC = 0x65706879, 9910 }; 9911 9912 struct fw_ifconf_dhcp_info { 9913 __be32 addr; 9914 __be32 mask; 9915 __be16 vlanid; 9916 __be16 mtu; 9917 __be32 gw; 9918 __u8 op; 9919 __u8 len; 9920 __u8 data[270]; 9921 }; 9922 9923 #endif /* _T4FW_INTERFACE_H_ */ 9924