1 /*- 2 * Copyright (c) 2012-2017 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed successfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 FW_SCSI_IO_BLOCK = 143, /* IO is going to be blocked due to resource failure */ 77 }; 78 79 /****************************************************************************** 80 * M E M O R Y T Y P E s 81 ******************************/ 82 83 enum fw_memtype { 84 FW_MEMTYPE_EDC0 = 0x0, 85 FW_MEMTYPE_EDC1 = 0x1, 86 FW_MEMTYPE_EXTMEM = 0x2, 87 FW_MEMTYPE_FLASH = 0x4, 88 FW_MEMTYPE_INTERNAL = 0x5, 89 FW_MEMTYPE_EXTMEM1 = 0x6, 90 FW_MEMTYPE_HMA = 0x7, 91 }; 92 93 /****************************************************************************** 94 * W O R K R E Q U E S T s 95 ********************************/ 96 97 enum fw_wr_opcodes { 98 FW_FRAG_WR = 0x1d, 99 FW_FILTER_WR = 0x02, 100 FW_ULPTX_WR = 0x04, 101 FW_TP_WR = 0x05, 102 FW_ETH_TX_PKT_WR = 0x08, 103 FW_ETH_TX_PKT2_WR = 0x44, 104 FW_ETH_TX_PKTS_WR = 0x09, 105 FW_ETH_TX_PKTS2_WR = 0x78, 106 FW_ETH_TX_EO_WR = 0x1c, 107 FW_EQ_FLUSH_WR = 0x1b, 108 FW_OFLD_CONNECTION_WR = 0x2f, 109 FW_FLOWC_WR = 0x0a, 110 FW_OFLD_TX_DATA_WR = 0x0b, 111 FW_CMD_WR = 0x10, 112 FW_ETH_TX_PKT_VM_WR = 0x11, 113 FW_ETH_TX_PKTS_VM_WR = 0x12, 114 FW_RI_RES_WR = 0x0c, 115 FW_RI_RDMA_WRITE_WR = 0x14, 116 FW_RI_SEND_WR = 0x15, 117 FW_RI_RDMA_READ_WR = 0x16, 118 FW_RI_RECV_WR = 0x17, 119 FW_RI_BIND_MW_WR = 0x18, 120 FW_RI_FR_NSMR_WR = 0x19, 121 FW_RI_FR_NSMR_TPTE_WR = 0x20, 122 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 123 FW_RI_INV_LSTAG_WR = 0x1a, 124 FW_RI_SEND_IMMEDIATE_WR = 0x15, 125 FW_RI_ATOMIC_WR = 0x16, 126 FW_RI_WR = 0x0d, 127 FW_CHNET_IFCONF_WR = 0x6b, 128 FW_RDEV_WR = 0x38, 129 FW_FOISCSI_NODE_WR = 0x60, 130 FW_FOISCSI_CTRL_WR = 0x6a, 131 FW_FOISCSI_CHAP_WR = 0x6c, 132 FW_FCOE_ELS_CT_WR = 0x30, 133 FW_SCSI_WRITE_WR = 0x31, 134 FW_SCSI_READ_WR = 0x32, 135 FW_SCSI_CMD_WR = 0x33, 136 FW_SCSI_ABRT_CLS_WR = 0x34, 137 FW_SCSI_TGT_ACC_WR = 0x35, 138 FW_SCSI_TGT_XMIT_WR = 0x36, 139 FW_SCSI_TGT_RSP_WR = 0x37, 140 FW_POFCOE_TCB_WR = 0x42, 141 FW_POFCOE_ULPTX_WR = 0x43, 142 FW_ISCSI_TX_DATA_WR = 0x45, 143 FW_PTP_TX_PKT_WR = 0x46, 144 FW_TLSTX_DATA_WR = 0x68, 145 FW_TLS_TUNNEL_OFLD_WR = 0x69, 146 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 147 FW_COISCSI_TGT_WR = 0x70, 148 FW_COISCSI_TGT_CONN_WR = 0x71, 149 FW_COISCSI_TGT_XMIT_WR = 0x72, 150 FW_COISCSI_STATS_WR = 0x73, 151 FW_ISNS_WR = 0x75, 152 FW_ISNS_XMIT_WR = 0x76, 153 FW_FILTER2_WR = 0x77, 154 FW_LASTC2E_WR = 0x80 155 }; 156 157 /* 158 * Generic work request header flit0 159 */ 160 struct fw_wr_hdr { 161 __be32 hi; 162 __be32 lo; 163 }; 164 165 /* work request opcode (hi) 166 */ 167 #define S_FW_WR_OP 24 168 #define M_FW_WR_OP 0xff 169 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 170 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 171 172 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 173 */ 174 #define S_FW_WR_ATOMIC 23 175 #define M_FW_WR_ATOMIC 0x1 176 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 177 #define G_FW_WR_ATOMIC(x) \ 178 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 179 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 180 181 /* flush flag (hi) - firmware flushes flushable work request buffered 182 * in the flow context. 183 */ 184 #define S_FW_WR_FLUSH 22 185 #define M_FW_WR_FLUSH 0x1 186 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 187 #define G_FW_WR_FLUSH(x) \ 188 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 189 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 190 191 /* completion flag (hi) - firmware generates a cpl_fw6_ack 192 */ 193 #define S_FW_WR_COMPL 21 194 #define M_FW_WR_COMPL 0x1 195 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 196 #define G_FW_WR_COMPL(x) \ 197 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 198 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 199 200 201 /* work request immediate data lengh (hi) 202 */ 203 #define S_FW_WR_IMMDLEN 0 204 #define M_FW_WR_IMMDLEN 0xff 205 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 206 #define G_FW_WR_IMMDLEN(x) \ 207 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 208 209 /* egress queue status update to associated ingress queue entry (lo) 210 */ 211 #define S_FW_WR_EQUIQ 31 212 #define M_FW_WR_EQUIQ 0x1 213 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 214 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 215 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 216 217 /* egress queue status update to egress queue status entry (lo) 218 */ 219 #define S_FW_WR_EQUEQ 30 220 #define M_FW_WR_EQUEQ 0x1 221 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 222 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 223 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 224 225 /* flow context identifier (lo) 226 */ 227 #define S_FW_WR_FLOWID 8 228 #define M_FW_WR_FLOWID 0xfffff 229 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 230 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 231 232 /* length in units of 16-bytes (lo) 233 */ 234 #define S_FW_WR_LEN16 0 235 #define M_FW_WR_LEN16 0xff 236 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 237 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 238 239 struct fw_frag_wr { 240 __be32 op_to_fragoff16; 241 __be32 flowid_len16; 242 __be64 r4; 243 }; 244 245 #define S_FW_FRAG_WR_EOF 15 246 #define M_FW_FRAG_WR_EOF 0x1 247 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 248 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 249 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 250 251 #define S_FW_FRAG_WR_FRAGOFF16 8 252 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 253 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 254 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 255 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 256 257 /* valid filter configurations for compressed tuple 258 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 259 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 260 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 261 * OV - Outer VLAN/VNIC_ID, 262 */ 263 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 264 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 265 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 266 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 267 #define HW_TPL_FR_MT_E_PR_T 0x370 268 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 269 #define HW_TPL_FR_MT_E_T_P_FC 0X353 270 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 271 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 272 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 273 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 274 #define HW_TPL_FR_M_E_PR_FC 0X2E1 275 #define HW_TPL_FR_M_E_T_FC 0X2D1 276 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 277 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 278 #define HW_TPL_FR_M_T_IV_FC 0X299 279 #define HW_TPL_FR_M_T_OV_FC 0X295 280 #define HW_TPL_FR_E_PR_T_P 0X272 281 #define HW_TPL_FR_E_PR_T_FC 0X271 282 #define HW_TPL_FR_E_IV_FC 0X249 283 #define HW_TPL_FR_E_OV_FC 0X245 284 #define HW_TPL_FR_PR_T_IV_FC 0X239 285 #define HW_TPL_FR_PR_T_OV_FC 0X235 286 #define HW_TPL_FR_IV_OV_FC 0X20D 287 #define HW_TPL_MT_M_E_PR 0X1E0 288 #define HW_TPL_MT_M_E_T 0X1D0 289 #define HW_TPL_MT_E_PR_T_FC 0X171 290 #define HW_TPL_MT_E_IV 0X148 291 #define HW_TPL_MT_E_OV 0X144 292 #define HW_TPL_MT_PR_T_IV 0X138 293 #define HW_TPL_MT_PR_T_OV 0X134 294 #define HW_TPL_M_E_PR_P 0X0E2 295 #define HW_TPL_M_E_T_P 0X0D2 296 #define HW_TPL_E_PR_T_P_FC 0X073 297 #define HW_TPL_E_IV_P 0X04A 298 #define HW_TPL_E_OV_P 0X046 299 #define HW_TPL_PR_T_IV_P 0X03A 300 #define HW_TPL_PR_T_OV_P 0X036 301 302 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 303 enum fw_filter_wr_cookie { 304 FW_FILTER_WR_SUCCESS, 305 FW_FILTER_WR_FLT_ADDED, 306 FW_FILTER_WR_FLT_DELETED, 307 FW_FILTER_WR_SMT_TBL_FULL, 308 FW_FILTER_WR_EINVAL, 309 }; 310 311 enum fw_filter_wr_nat_mode { 312 FW_FILTER_WR_NATMODE_NONE = 0, 313 FW_FILTER_WR_NATMODE_DIP , 314 FW_FILTER_WR_NATMODE_DIPDP, 315 FW_FILTER_WR_NATMODE_DIPDPSIP, 316 FW_FILTER_WR_NATMODE_DIPDPSP, 317 FW_FILTER_WR_NATMODE_SIPSP, 318 FW_FILTER_WR_NATMODE_DIPSIPSP, 319 FW_FILTER_WR_NATMODE_FOURTUPLE, 320 }; 321 322 struct fw_filter_wr { 323 __be32 op_pkd; 324 __be32 len16_pkd; 325 __be64 r3; 326 __be32 tid_to_iq; 327 __be32 del_filter_to_l2tix; 328 __be16 ethtype; 329 __be16 ethtypem; 330 __u8 frag_to_ovlan_vldm; 331 __u8 smac_sel; 332 __be16 rx_chan_rx_rpl_iq; 333 __be32 maci_to_matchtypem; 334 __u8 ptcl; 335 __u8 ptclm; 336 __u8 ttyp; 337 __u8 ttypm; 338 __be16 ivlan; 339 __be16 ivlanm; 340 __be16 ovlan; 341 __be16 ovlanm; 342 __u8 lip[16]; 343 __u8 lipm[16]; 344 __u8 fip[16]; 345 __u8 fipm[16]; 346 __be16 lp; 347 __be16 lpm; 348 __be16 fp; 349 __be16 fpm; 350 __be16 r7; 351 __u8 sma[6]; 352 }; 353 354 struct fw_filter2_wr { 355 __be32 op_pkd; 356 __be32 len16_pkd; 357 __be64 r3; 358 __be32 tid_to_iq; 359 __be32 del_filter_to_l2tix; 360 __be16 ethtype; 361 __be16 ethtypem; 362 __u8 frag_to_ovlan_vldm; 363 __u8 smac_sel; 364 __be16 rx_chan_rx_rpl_iq; 365 __be32 maci_to_matchtypem; 366 __u8 ptcl; 367 __u8 ptclm; 368 __u8 ttyp; 369 __u8 ttypm; 370 __be16 ivlan; 371 __be16 ivlanm; 372 __be16 ovlan; 373 __be16 ovlanm; 374 __u8 lip[16]; 375 __u8 lipm[16]; 376 __u8 fip[16]; 377 __u8 fipm[16]; 378 __be16 lp; 379 __be16 lpm; 380 __be16 fp; 381 __be16 fpm; 382 __be16 r7; 383 __u8 sma[6]; 384 __be16 r8; 385 __u8 filter_type_swapmac; 386 __u8 natmode_to_ulp_type; 387 __be16 newlport; 388 __be16 newfport; 389 __u8 newlip[16]; 390 __u8 newfip[16]; 391 __be32 natseqcheck; 392 __be32 r9; 393 __be64 r10; 394 __be64 r11; 395 __be64 r12; 396 __be64 r13; 397 }; 398 399 #define S_FW_FILTER_WR_TID 12 400 #define M_FW_FILTER_WR_TID 0xfffff 401 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 402 #define G_FW_FILTER_WR_TID(x) \ 403 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 404 405 #define S_FW_FILTER_WR_RQTYPE 11 406 #define M_FW_FILTER_WR_RQTYPE 0x1 407 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 408 #define G_FW_FILTER_WR_RQTYPE(x) \ 409 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 410 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 411 412 #define S_FW_FILTER_WR_NOREPLY 10 413 #define M_FW_FILTER_WR_NOREPLY 0x1 414 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 415 #define G_FW_FILTER_WR_NOREPLY(x) \ 416 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 417 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 418 419 #define S_FW_FILTER_WR_IQ 0 420 #define M_FW_FILTER_WR_IQ 0x3ff 421 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 422 #define G_FW_FILTER_WR_IQ(x) \ 423 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 424 425 #define S_FW_FILTER_WR_DEL_FILTER 31 426 #define M_FW_FILTER_WR_DEL_FILTER 0x1 427 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 428 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 429 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 430 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 431 432 #define S_FW_FILTER2_WR_DROP_ENCAP 30 433 #define M_FW_FILTER2_WR_DROP_ENCAP 0x1 434 #define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP) 435 #define G_FW_FILTER2_WR_DROP_ENCAP(x) \ 436 (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP) 437 #define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U) 438 439 #define S_FW_FILTER2_WR_TX_LOOP 29 440 #define M_FW_FILTER2_WR_TX_LOOP 0x1 441 #define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP) 442 #define G_FW_FILTER2_WR_TX_LOOP(x) \ 443 (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP) 444 #define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U) 445 446 #define S_FW_FILTER_WR_RPTTID 25 447 #define M_FW_FILTER_WR_RPTTID 0x1 448 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 449 #define G_FW_FILTER_WR_RPTTID(x) \ 450 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 451 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 452 453 #define S_FW_FILTER_WR_DROP 24 454 #define M_FW_FILTER_WR_DROP 0x1 455 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 456 #define G_FW_FILTER_WR_DROP(x) \ 457 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 458 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 459 460 #define S_FW_FILTER_WR_DIRSTEER 23 461 #define M_FW_FILTER_WR_DIRSTEER 0x1 462 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 463 #define G_FW_FILTER_WR_DIRSTEER(x) \ 464 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 465 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 466 467 #define S_FW_FILTER_WR_MASKHASH 22 468 #define M_FW_FILTER_WR_MASKHASH 0x1 469 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 470 #define G_FW_FILTER_WR_MASKHASH(x) \ 471 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 472 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 473 474 #define S_FW_FILTER_WR_DIRSTEERHASH 21 475 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 476 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 477 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 478 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 479 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 480 481 #define S_FW_FILTER_WR_LPBK 20 482 #define M_FW_FILTER_WR_LPBK 0x1 483 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 484 #define G_FW_FILTER_WR_LPBK(x) \ 485 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 486 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 487 488 #define S_FW_FILTER_WR_DMAC 19 489 #define M_FW_FILTER_WR_DMAC 0x1 490 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 491 #define G_FW_FILTER_WR_DMAC(x) \ 492 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 493 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 494 495 #define S_FW_FILTER_WR_SMAC 18 496 #define M_FW_FILTER_WR_SMAC 0x1 497 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 498 #define G_FW_FILTER_WR_SMAC(x) \ 499 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 500 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 501 502 #define S_FW_FILTER_WR_INSVLAN 17 503 #define M_FW_FILTER_WR_INSVLAN 0x1 504 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 505 #define G_FW_FILTER_WR_INSVLAN(x) \ 506 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 507 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 508 509 #define S_FW_FILTER_WR_RMVLAN 16 510 #define M_FW_FILTER_WR_RMVLAN 0x1 511 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 512 #define G_FW_FILTER_WR_RMVLAN(x) \ 513 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 514 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 515 516 #define S_FW_FILTER_WR_HITCNTS 15 517 #define M_FW_FILTER_WR_HITCNTS 0x1 518 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 519 #define G_FW_FILTER_WR_HITCNTS(x) \ 520 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 521 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 522 523 #define S_FW_FILTER_WR_TXCHAN 13 524 #define M_FW_FILTER_WR_TXCHAN 0x3 525 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 526 #define G_FW_FILTER_WR_TXCHAN(x) \ 527 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 528 529 #define S_FW_FILTER_WR_PRIO 12 530 #define M_FW_FILTER_WR_PRIO 0x1 531 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 532 #define G_FW_FILTER_WR_PRIO(x) \ 533 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 534 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 535 536 #define S_FW_FILTER_WR_L2TIX 0 537 #define M_FW_FILTER_WR_L2TIX 0xfff 538 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 539 #define G_FW_FILTER_WR_L2TIX(x) \ 540 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 541 542 #define S_FW_FILTER_WR_FRAG 7 543 #define M_FW_FILTER_WR_FRAG 0x1 544 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 545 #define G_FW_FILTER_WR_FRAG(x) \ 546 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 547 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 548 549 #define S_FW_FILTER_WR_FRAGM 6 550 #define M_FW_FILTER_WR_FRAGM 0x1 551 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 552 #define G_FW_FILTER_WR_FRAGM(x) \ 553 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 554 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 555 556 #define S_FW_FILTER_WR_IVLAN_VLD 5 557 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 558 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 559 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 560 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 561 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 562 563 #define S_FW_FILTER_WR_OVLAN_VLD 4 564 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 565 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 566 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 567 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 568 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 569 570 #define S_FW_FILTER_WR_IVLAN_VLDM 3 571 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 572 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 573 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 574 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 575 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 576 577 #define S_FW_FILTER_WR_OVLAN_VLDM 2 578 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 579 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 580 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 581 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 582 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 583 584 #define S_FW_FILTER_WR_RX_CHAN 15 585 #define M_FW_FILTER_WR_RX_CHAN 0x1 586 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 587 #define G_FW_FILTER_WR_RX_CHAN(x) \ 588 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 589 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 590 591 #define S_FW_FILTER_WR_RX_RPL_IQ 0 592 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 593 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 594 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 595 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 596 597 #define S_FW_FILTER2_WR_FILTER_TYPE 1 598 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 599 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 600 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 601 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 602 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 603 604 #define S_FW_FILTER2_WR_SWAPMAC 0 605 #define M_FW_FILTER2_WR_SWAPMAC 0x1 606 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 607 #define G_FW_FILTER2_WR_SWAPMAC(x) \ 608 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 609 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 610 611 #define S_FW_FILTER2_WR_NATMODE 5 612 #define M_FW_FILTER2_WR_NATMODE 0x7 613 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 614 #define G_FW_FILTER2_WR_NATMODE(x) \ 615 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 616 617 #define S_FW_FILTER2_WR_NATFLAGCHECK 4 618 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 619 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 620 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 621 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 622 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 623 624 #define S_FW_FILTER2_WR_ULP_TYPE 0 625 #define M_FW_FILTER2_WR_ULP_TYPE 0xf 626 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 627 #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 628 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 629 630 #define S_FW_FILTER_WR_MACI 23 631 #define M_FW_FILTER_WR_MACI 0x1ff 632 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 633 #define G_FW_FILTER_WR_MACI(x) \ 634 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 635 636 #define S_FW_FILTER_WR_MACIM 14 637 #define M_FW_FILTER_WR_MACIM 0x1ff 638 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 639 #define G_FW_FILTER_WR_MACIM(x) \ 640 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 641 642 #define S_FW_FILTER_WR_FCOE 13 643 #define M_FW_FILTER_WR_FCOE 0x1 644 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 645 #define G_FW_FILTER_WR_FCOE(x) \ 646 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 647 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 648 649 #define S_FW_FILTER_WR_FCOEM 12 650 #define M_FW_FILTER_WR_FCOEM 0x1 651 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 652 #define G_FW_FILTER_WR_FCOEM(x) \ 653 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 654 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 655 656 #define S_FW_FILTER_WR_PORT 9 657 #define M_FW_FILTER_WR_PORT 0x7 658 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 659 #define G_FW_FILTER_WR_PORT(x) \ 660 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 661 662 #define S_FW_FILTER_WR_PORTM 6 663 #define M_FW_FILTER_WR_PORTM 0x7 664 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 665 #define G_FW_FILTER_WR_PORTM(x) \ 666 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 667 668 #define S_FW_FILTER_WR_MATCHTYPE 3 669 #define M_FW_FILTER_WR_MATCHTYPE 0x7 670 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 671 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 672 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 673 674 #define S_FW_FILTER_WR_MATCHTYPEM 0 675 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 676 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 677 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 678 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 679 680 struct fw_ulptx_wr { 681 __be32 op_to_compl; 682 __be32 flowid_len16; 683 __u64 cookie; 684 }; 685 686 /* flag for packet type - control packet (0), data packet (1) 687 */ 688 #define S_FW_ULPTX_WR_DATA 28 689 #define M_FW_ULPTX_WR_DATA 0x1 690 #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA) 691 #define G_FW_ULPTX_WR_DATA(x) \ 692 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA) 693 #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U) 694 695 struct fw_tp_wr { 696 __be32 op_to_immdlen; 697 __be32 flowid_len16; 698 __u64 cookie; 699 }; 700 701 struct fw_eth_tx_pkt_wr { 702 __be32 op_immdlen; 703 __be32 equiq_to_len16; 704 __be64 r3; 705 }; 706 707 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 708 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 709 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 710 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 711 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 712 713 struct fw_eth_tx_pkt2_wr { 714 __be32 op_immdlen; 715 __be32 equiq_to_len16; 716 __be32 r3; 717 __be32 L4ChkDisable_to_IpHdrLen; 718 }; 719 720 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 721 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 722 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 723 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 724 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 725 726 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 727 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 728 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 729 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 730 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 731 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 732 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 733 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 734 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 735 736 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 737 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 738 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 739 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 740 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 741 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 742 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 743 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 744 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 745 746 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 747 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 748 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 749 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 750 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 751 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 752 753 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 754 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 755 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 756 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 757 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 758 759 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 760 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 761 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 762 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 763 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 764 765 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 766 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 767 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 768 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 769 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 770 771 struct fw_eth_tx_pkts_wr { 772 __be32 op_pkd; 773 __be32 equiq_to_len16; 774 __be32 r3; 775 __be16 plen; 776 __u8 npkt; 777 __u8 type; 778 }; 779 780 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 781 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 782 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 783 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 784 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 785 786 struct fw_eth_tx_pkt_ptp_wr { 787 __be32 op_immdlen; 788 __be32 equiq_to_len16; 789 __be64 r3; 790 }; 791 792 enum fw_eth_tx_eo_type { 793 FW_ETH_TX_EO_TYPE_UDPSEG, 794 FW_ETH_TX_EO_TYPE_TCPSEG, 795 FW_ETH_TX_EO_TYPE_NVGRESEG, 796 FW_ETH_TX_EO_TYPE_VXLANSEG, 797 FW_ETH_TX_EO_TYPE_GENEVESEG, 798 }; 799 800 struct fw_eth_tx_eo_wr { 801 __be32 op_immdlen; 802 __be32 equiq_to_len16; 803 __be64 r3; 804 union fw_eth_tx_eo { 805 struct fw_eth_tx_eo_udpseg { 806 __u8 type; 807 __u8 ethlen; 808 __be16 iplen; 809 __u8 udplen; 810 __u8 rtplen; 811 __be16 r4; 812 __be16 mss; 813 __be16 schedpktsize; 814 __be32 plen; 815 } udpseg; 816 struct fw_eth_tx_eo_tcpseg { 817 __u8 type; 818 __u8 ethlen; 819 __be16 iplen; 820 __u8 tcplen; 821 __u8 tsclk_tsoff; 822 __be16 r4; 823 __be16 mss; 824 __be16 r5; 825 __be32 plen; 826 } tcpseg; 827 struct fw_eth_tx_eo_nvgreseg { 828 __u8 type; 829 __u8 iphdroffout; 830 __be16 grehdroff; 831 __be16 iphdroffin; 832 __be16 tcphdroffin; 833 __be16 mss; 834 __be16 r4; 835 __be32 plen; 836 } nvgreseg; 837 struct fw_eth_tx_eo_vxlanseg { 838 __u8 type; 839 __u8 iphdroffout; 840 __be16 vxlanhdroff; 841 __be16 iphdroffin; 842 __be16 tcphdroffin; 843 __be16 mss; 844 __be16 r4; 845 __be32 plen; 846 847 } vxlanseg; 848 struct fw_eth_tx_eo_geneveseg { 849 __u8 type; 850 __u8 iphdroffout; 851 __be16 genevehdroff; 852 __be16 iphdroffin; 853 __be16 tcphdroffin; 854 __be16 mss; 855 __be16 r4; 856 __be32 plen; 857 } geneveseg; 858 } u; 859 }; 860 861 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 862 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 863 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 864 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 865 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 866 867 #define S_FW_ETH_TX_EO_WR_TSCLK 6 868 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 869 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 870 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 871 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 872 873 #define S_FW_ETH_TX_EO_WR_TSOFF 0 874 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 875 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 876 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 877 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 878 879 struct fw_eq_flush_wr { 880 __u8 opcode; 881 __u8 r1[3]; 882 __be32 equiq_to_len16; 883 __be64 r3; 884 }; 885 886 struct fw_ofld_connection_wr { 887 __be32 op_compl; 888 __be32 len16_pkd; 889 __u64 cookie; 890 __be64 r2; 891 __be64 r3; 892 struct fw_ofld_connection_le { 893 __be32 version_cpl; 894 __be32 filter; 895 __be32 r1; 896 __be16 lport; 897 __be16 pport; 898 union fw_ofld_connection_leip { 899 struct fw_ofld_connection_le_ipv4 { 900 __be32 pip; 901 __be32 lip; 902 __be64 r0; 903 __be64 r1; 904 __be64 r2; 905 } ipv4; 906 struct fw_ofld_connection_le_ipv6 { 907 __be64 pip_hi; 908 __be64 pip_lo; 909 __be64 lip_hi; 910 __be64 lip_lo; 911 } ipv6; 912 } u; 913 } le; 914 struct fw_ofld_connection_tcb { 915 __be32 t_state_to_astid; 916 __be16 cplrxdataack_cplpassacceptrpl; 917 __be16 rcv_adv; 918 __be32 rcv_nxt; 919 __be32 tx_max; 920 __be64 opt0; 921 __be32 opt2; 922 __be32 r1; 923 __be64 r2; 924 __be64 r3; 925 } tcb; 926 }; 927 928 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 929 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 930 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 931 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 932 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 933 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 934 M_FW_OFLD_CONNECTION_WR_VERSION) 935 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 936 937 #define S_FW_OFLD_CONNECTION_WR_CPL 30 938 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 939 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 940 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 941 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 942 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 943 944 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 945 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 946 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 947 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 948 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 949 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 950 M_FW_OFLD_CONNECTION_WR_T_STATE) 951 952 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 953 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 954 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 955 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 956 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 957 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 958 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 959 960 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 961 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 962 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 963 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 964 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 965 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 966 967 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 968 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 969 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 970 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 971 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 972 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 973 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 974 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 975 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 976 977 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 978 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 979 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 980 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 981 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 982 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 983 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 984 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 985 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 986 987 enum fw_flowc_mnem_tcpstate { 988 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 989 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 990 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 991 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 992 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 993 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 994 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 995 * will resend FIN - equiv ESTAB 996 */ 997 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 998 * will resend FIN but have 999 * received FIN 1000 */ 1001 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 1002 * will resend FIN but have 1003 * received FIN 1004 */ 1005 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 1006 * waiting for FIN 1007 */ 1008 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 1009 }; 1010 1011 enum fw_flowc_mnem_eostate { 1012 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 1013 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 1014 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 1015 * outstanding payload 1016 */ 1017 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 1018 * discarding outstanding payload 1019 */ 1020 }; 1021 1022 enum fw_flowc_mnem { 1023 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1024 FW_FLOWC_MNEM_CH = 1, 1025 FW_FLOWC_MNEM_PORT = 2, 1026 FW_FLOWC_MNEM_IQID = 3, 1027 FW_FLOWC_MNEM_SNDNXT = 4, 1028 FW_FLOWC_MNEM_RCVNXT = 5, 1029 FW_FLOWC_MNEM_SNDBUF = 6, 1030 FW_FLOWC_MNEM_MSS = 7, 1031 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1032 FW_FLOWC_MNEM_TCPSTATE = 9, 1033 FW_FLOWC_MNEM_EOSTATE = 10, 1034 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1035 FW_FLOWC_MNEM_DCBPRIO = 12, 1036 FW_FLOWC_MNEM_SND_SCALE = 13, 1037 FW_FLOWC_MNEM_RCV_SCALE = 14, 1038 FW_FLOWC_MNEM_ULP_MODE = 15, 1039 FW_FLOWC_MNEM_MAX = 16, 1040 }; 1041 1042 struct fw_flowc_mnemval { 1043 __u8 mnemonic; 1044 __u8 r4[3]; 1045 __be32 val; 1046 }; 1047 1048 struct fw_flowc_wr { 1049 __be32 op_to_nparams; 1050 __be32 flowid_len16; 1051 #ifndef C99_NOT_SUPPORTED 1052 struct fw_flowc_mnemval mnemval[0]; 1053 #endif 1054 }; 1055 1056 #define S_FW_FLOWC_WR_NPARAMS 0 1057 #define M_FW_FLOWC_WR_NPARAMS 0xff 1058 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1059 #define G_FW_FLOWC_WR_NPARAMS(x) \ 1060 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1061 1062 struct fw_ofld_tx_data_wr { 1063 __be32 op_to_immdlen; 1064 __be32 flowid_len16; 1065 __be32 plen; 1066 __be32 lsodisable_to_flags; 1067 }; 1068 1069 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1070 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1071 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1072 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1073 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1074 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1075 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1076 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1077 1078 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1079 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1080 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1081 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1082 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1083 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1084 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1085 1086 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1087 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1088 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1089 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1090 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1091 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1092 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1093 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1094 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1095 1096 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1097 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1098 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1099 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1100 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1101 1102 1103 /* Use fw_ofld_tx_data_wr structure */ 1104 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1105 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1106 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1107 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1108 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1109 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1110 1111 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1112 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1113 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1114 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1115 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1116 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1117 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1118 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1119 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1120 1121 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1122 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1123 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1124 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1125 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1126 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1127 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1128 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1129 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1130 1131 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1132 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1133 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1134 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1135 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1136 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1137 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1138 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1139 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1140 1141 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1142 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1143 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1144 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1145 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1146 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1147 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1148 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1149 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1150 1151 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1152 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1153 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1154 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1155 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1156 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1157 1158 struct fw_cmd_wr { 1159 __be32 op_dma; 1160 __be32 len16_pkd; 1161 __be64 cookie_daddr; 1162 }; 1163 1164 #define S_FW_CMD_WR_DMA 17 1165 #define M_FW_CMD_WR_DMA 0x1 1166 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1167 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1168 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1169 1170 struct fw_eth_tx_pkt_vm_wr { 1171 __be32 op_immdlen; 1172 __be32 equiq_to_len16; 1173 __be32 r3[2]; 1174 __u8 ethmacdst[6]; 1175 __u8 ethmacsrc[6]; 1176 __be16 ethtype; 1177 __be16 vlantci; 1178 }; 1179 1180 struct fw_eth_tx_pkts_vm_wr { 1181 __be32 op_pkd; 1182 __be32 equiq_to_len16; 1183 __be32 r3; 1184 __be16 plen; 1185 __u8 npkt; 1186 __u8 r4; 1187 __u8 ethmacdst[6]; 1188 __u8 ethmacsrc[6]; 1189 __be16 ethtype; 1190 __be16 vlantci; 1191 }; 1192 1193 /****************************************************************************** 1194 * R I W O R K R E Q U E S T s 1195 **************************************/ 1196 1197 enum fw_ri_wr_opcode { 1198 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1199 FW_RI_READ_REQ = 0x1, 1200 FW_RI_READ_RESP = 0x2, 1201 FW_RI_SEND = 0x3, 1202 FW_RI_SEND_WITH_INV = 0x4, 1203 FW_RI_SEND_WITH_SE = 0x5, 1204 FW_RI_SEND_WITH_SE_INV = 0x6, 1205 FW_RI_TERMINATE = 0x7, 1206 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1207 FW_RI_BIND_MW = 0x9, 1208 FW_RI_FAST_REGISTER = 0xa, 1209 FW_RI_LOCAL_INV = 0xb, 1210 FW_RI_QP_MODIFY = 0xc, 1211 FW_RI_BYPASS = 0xd, 1212 FW_RI_RECEIVE = 0xe, 1213 #if 0 1214 FW_RI_SEND_IMMEDIATE = 0x8, 1215 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1216 FW_RI_ATOMIC_REQUEST = 0xa, 1217 FW_RI_ATOMIC_RESPONSE = 0xb, 1218 1219 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1220 FW_RI_FAST_REGISTER = 0xd, 1221 FW_RI_LOCAL_INV = 0xe, 1222 #endif 1223 FW_RI_SGE_EC_CR_RETURN = 0xf, 1224 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 1225 }; 1226 1227 enum fw_ri_wr_flags { 1228 FW_RI_COMPLETION_FLAG = 0x01, 1229 FW_RI_NOTIFICATION_FLAG = 0x02, 1230 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1231 FW_RI_READ_FENCE_FLAG = 0x08, 1232 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1233 FW_RI_RDMA_READ_INVALIDATE = 0x20, 1234 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40 1235 }; 1236 1237 enum fw_ri_mpa_attrs { 1238 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1239 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1240 FW_RI_MPA_CRC_ENABLE = 0x04, 1241 FW_RI_MPA_IETF_ENABLE = 0x08 1242 }; 1243 1244 enum fw_ri_qp_caps { 1245 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1246 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1247 FW_RI_QP_BIND_ENABLE = 0x04, 1248 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1249 FW_RI_QP_STAG0_ENABLE = 0x10, 1250 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1251 }; 1252 1253 enum fw_ri_addr_type { 1254 FW_RI_ZERO_BASED_TO = 0x00, 1255 FW_RI_VA_BASED_TO = 0x01 1256 }; 1257 1258 enum fw_ri_mem_perms { 1259 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1260 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1261 FW_RI_MEM_ACCESS_REM = 0x03, 1262 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1263 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1264 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1265 }; 1266 1267 enum fw_ri_stag_type { 1268 FW_RI_STAG_NSMR = 0x00, 1269 FW_RI_STAG_SMR = 0x01, 1270 FW_RI_STAG_MW = 0x02, 1271 FW_RI_STAG_MW_RELAXED = 0x03 1272 }; 1273 1274 enum fw_ri_data_op { 1275 FW_RI_DATA_IMMD = 0x81, 1276 FW_RI_DATA_DSGL = 0x82, 1277 FW_RI_DATA_ISGL = 0x83 1278 }; 1279 1280 enum fw_ri_sgl_depth { 1281 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1282 FW_RI_SGL_DEPTH_MAX_RQ = 4 1283 }; 1284 1285 enum fw_ri_cqe_err { 1286 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1287 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1288 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1289 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1290 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1291 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1292 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1293 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1294 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1295 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1296 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1297 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1298 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1299 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1300 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1301 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1302 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1303 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1304 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1305 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1306 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1307 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1308 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1309 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1310 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1311 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1312 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1313 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1314 1315 }; 1316 1317 struct fw_ri_dsge_pair { 1318 __be32 len[2]; 1319 __be64 addr[2]; 1320 }; 1321 1322 struct fw_ri_dsgl { 1323 __u8 op; 1324 __u8 r1; 1325 __be16 nsge; 1326 __be32 len0; 1327 __be64 addr0; 1328 #ifndef C99_NOT_SUPPORTED 1329 struct fw_ri_dsge_pair sge[0]; 1330 #endif 1331 }; 1332 1333 struct fw_ri_sge { 1334 __be32 stag; 1335 __be32 len; 1336 __be64 to; 1337 }; 1338 1339 struct fw_ri_isgl { 1340 __u8 op; 1341 __u8 r1; 1342 __be16 nsge; 1343 __be32 r2; 1344 #ifndef C99_NOT_SUPPORTED 1345 struct fw_ri_sge sge[0]; 1346 #endif 1347 }; 1348 1349 struct fw_ri_immd { 1350 __u8 op; 1351 __u8 r1; 1352 __be16 r2; 1353 __be32 immdlen; 1354 #ifndef C99_NOT_SUPPORTED 1355 __u8 data[0]; 1356 #endif 1357 }; 1358 1359 struct fw_ri_tpte { 1360 __be32 valid_to_pdid; 1361 __be32 locread_to_qpid; 1362 __be32 nosnoop_pbladdr; 1363 __be32 len_lo; 1364 __be32 va_hi; 1365 __be32 va_lo_fbo; 1366 __be32 dca_mwbcnt_pstag; 1367 __be32 len_hi; 1368 }; 1369 1370 #define S_FW_RI_TPTE_VALID 31 1371 #define M_FW_RI_TPTE_VALID 0x1 1372 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1373 #define G_FW_RI_TPTE_VALID(x) \ 1374 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1375 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1376 1377 #define S_FW_RI_TPTE_STAGKEY 23 1378 #define M_FW_RI_TPTE_STAGKEY 0xff 1379 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1380 #define G_FW_RI_TPTE_STAGKEY(x) \ 1381 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1382 1383 #define S_FW_RI_TPTE_STAGSTATE 22 1384 #define M_FW_RI_TPTE_STAGSTATE 0x1 1385 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1386 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1387 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1388 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1389 1390 #define S_FW_RI_TPTE_STAGTYPE 20 1391 #define M_FW_RI_TPTE_STAGTYPE 0x3 1392 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1393 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1394 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1395 1396 #define S_FW_RI_TPTE_PDID 0 1397 #define M_FW_RI_TPTE_PDID 0xfffff 1398 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1399 #define G_FW_RI_TPTE_PDID(x) \ 1400 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1401 1402 #define S_FW_RI_TPTE_PERM 28 1403 #define M_FW_RI_TPTE_PERM 0xf 1404 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1405 #define G_FW_RI_TPTE_PERM(x) \ 1406 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1407 1408 #define S_FW_RI_TPTE_REMINVDIS 27 1409 #define M_FW_RI_TPTE_REMINVDIS 0x1 1410 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1411 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1412 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1413 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1414 1415 #define S_FW_RI_TPTE_ADDRTYPE 26 1416 #define M_FW_RI_TPTE_ADDRTYPE 1 1417 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1418 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1419 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1420 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1421 1422 #define S_FW_RI_TPTE_MWBINDEN 25 1423 #define M_FW_RI_TPTE_MWBINDEN 0x1 1424 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1425 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1426 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1427 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1428 1429 #define S_FW_RI_TPTE_PS 20 1430 #define M_FW_RI_TPTE_PS 0x1f 1431 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1432 #define G_FW_RI_TPTE_PS(x) \ 1433 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1434 1435 #define S_FW_RI_TPTE_QPID 0 1436 #define M_FW_RI_TPTE_QPID 0xfffff 1437 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1438 #define G_FW_RI_TPTE_QPID(x) \ 1439 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1440 1441 #define S_FW_RI_TPTE_NOSNOOP 31 1442 #define M_FW_RI_TPTE_NOSNOOP 0x1 1443 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1444 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1445 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1446 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1447 1448 #define S_FW_RI_TPTE_PBLADDR 0 1449 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1450 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1451 #define G_FW_RI_TPTE_PBLADDR(x) \ 1452 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1453 1454 #define S_FW_RI_TPTE_DCA 24 1455 #define M_FW_RI_TPTE_DCA 0x1f 1456 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1457 #define G_FW_RI_TPTE_DCA(x) \ 1458 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1459 1460 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1461 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1462 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1463 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1464 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1465 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1466 1467 enum fw_ri_cqe_rxtx { 1468 FW_RI_CQE_RXTX_RX = 0x0, 1469 FW_RI_CQE_RXTX_TX = 0x1, 1470 }; 1471 1472 struct fw_ri_cqe { 1473 union fw_ri_rxtx { 1474 struct fw_ri_scqe { 1475 __be32 qpid_n_stat_rxtx_type; 1476 __be32 plen; 1477 __be32 stag; 1478 __be32 wrid; 1479 } scqe; 1480 struct fw_ri_rcqe { 1481 __be32 qpid_n_stat_rxtx_type; 1482 __be32 plen; 1483 __be32 stag; 1484 __be32 msn; 1485 } rcqe; 1486 struct fw_ri_rcqe_imm { 1487 __be32 qpid_n_stat_rxtx_type; 1488 __be32 plen; 1489 __be32 mo; 1490 __be32 msn; 1491 __u64 imm_data; 1492 } imm_data_rcqe; 1493 } u; 1494 }; 1495 1496 #define S_FW_RI_CQE_QPID 12 1497 #define M_FW_RI_CQE_QPID 0xfffff 1498 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1499 #define G_FW_RI_CQE_QPID(x) \ 1500 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1501 1502 #define S_FW_RI_CQE_NOTIFY 10 1503 #define M_FW_RI_CQE_NOTIFY 0x1 1504 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1505 #define G_FW_RI_CQE_NOTIFY(x) \ 1506 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1507 1508 #define S_FW_RI_CQE_STATUS 5 1509 #define M_FW_RI_CQE_STATUS 0x1f 1510 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1511 #define G_FW_RI_CQE_STATUS(x) \ 1512 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1513 1514 1515 #define S_FW_RI_CQE_RXTX 4 1516 #define M_FW_RI_CQE_RXTX 0x1 1517 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1518 #define G_FW_RI_CQE_RXTX(x) \ 1519 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1520 1521 #define S_FW_RI_CQE_TYPE 0 1522 #define M_FW_RI_CQE_TYPE 0xf 1523 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1524 #define G_FW_RI_CQE_TYPE(x) \ 1525 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1526 1527 enum fw_ri_res_type { 1528 FW_RI_RES_TYPE_SQ, 1529 FW_RI_RES_TYPE_RQ, 1530 FW_RI_RES_TYPE_CQ, 1531 FW_RI_RES_TYPE_SRQ, 1532 }; 1533 1534 enum fw_ri_res_op { 1535 FW_RI_RES_OP_WRITE, 1536 FW_RI_RES_OP_RESET, 1537 }; 1538 1539 struct fw_ri_res { 1540 union fw_ri_restype { 1541 struct fw_ri_res_sqrq { 1542 __u8 restype; 1543 __u8 op; 1544 __be16 r3; 1545 __be32 eqid; 1546 __be32 r4[2]; 1547 __be32 fetchszm_to_iqid; 1548 __be32 dcaen_to_eqsize; 1549 __be64 eqaddr; 1550 } sqrq; 1551 struct fw_ri_res_cq { 1552 __u8 restype; 1553 __u8 op; 1554 __be16 r3; 1555 __be32 iqid; 1556 __be32 r4[2]; 1557 __be32 iqandst_to_iqandstindex; 1558 __be16 iqdroprss_to_iqesize; 1559 __be16 iqsize; 1560 __be64 iqaddr; 1561 __be32 iqns_iqro; 1562 __be32 r6_lo; 1563 __be64 r7; 1564 } cq; 1565 struct fw_ri_res_srq { 1566 __u8 restype; 1567 __u8 op; 1568 __be16 r3; 1569 __be32 eqid; 1570 __be32 r4[2]; 1571 __be32 fetchszm_to_iqid; 1572 __be32 dcaen_to_eqsize; 1573 __be64 eqaddr; 1574 __be32 srqid; 1575 __be32 pdid; 1576 __be32 hwsrqsize; 1577 __be32 hwsrqaddr; 1578 } srq; 1579 } u; 1580 }; 1581 1582 struct fw_ri_res_wr { 1583 __be32 op_nres; 1584 __be32 len16_pkd; 1585 __u64 cookie; 1586 #ifndef C99_NOT_SUPPORTED 1587 struct fw_ri_res res[0]; 1588 #endif 1589 }; 1590 1591 #define S_FW_RI_RES_WR_VFN 8 1592 #define M_FW_RI_RES_WR_VFN 0xff 1593 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1594 #define G_FW_RI_RES_WR_VFN(x) \ 1595 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1596 1597 #define S_FW_RI_RES_WR_NRES 0 1598 #define M_FW_RI_RES_WR_NRES 0xff 1599 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1600 #define G_FW_RI_RES_WR_NRES(x) \ 1601 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1602 1603 #define S_FW_RI_RES_WR_FETCHSZM 26 1604 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1605 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1606 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1607 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1608 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1609 1610 #define S_FW_RI_RES_WR_STATUSPGNS 25 1611 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1612 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1613 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1614 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1615 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1616 1617 #define S_FW_RI_RES_WR_STATUSPGRO 24 1618 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1619 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1620 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1621 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1622 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1623 1624 #define S_FW_RI_RES_WR_FETCHNS 23 1625 #define M_FW_RI_RES_WR_FETCHNS 0x1 1626 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1627 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1628 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1629 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1630 1631 #define S_FW_RI_RES_WR_FETCHRO 22 1632 #define M_FW_RI_RES_WR_FETCHRO 0x1 1633 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1634 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1635 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1636 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1637 1638 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1639 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1640 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1641 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1642 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1643 1644 #define S_FW_RI_RES_WR_CPRIO 19 1645 #define M_FW_RI_RES_WR_CPRIO 0x1 1646 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1647 #define G_FW_RI_RES_WR_CPRIO(x) \ 1648 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1649 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1650 1651 #define S_FW_RI_RES_WR_ONCHIP 18 1652 #define M_FW_RI_RES_WR_ONCHIP 0x1 1653 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1654 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1655 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1656 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1657 1658 #define S_FW_RI_RES_WR_PCIECHN 16 1659 #define M_FW_RI_RES_WR_PCIECHN 0x3 1660 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1661 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1662 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1663 1664 #define S_FW_RI_RES_WR_IQID 0 1665 #define M_FW_RI_RES_WR_IQID 0xffff 1666 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1667 #define G_FW_RI_RES_WR_IQID(x) \ 1668 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1669 1670 #define S_FW_RI_RES_WR_DCAEN 31 1671 #define M_FW_RI_RES_WR_DCAEN 0x1 1672 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1673 #define G_FW_RI_RES_WR_DCAEN(x) \ 1674 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1675 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1676 1677 #define S_FW_RI_RES_WR_DCACPU 26 1678 #define M_FW_RI_RES_WR_DCACPU 0x1f 1679 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1680 #define G_FW_RI_RES_WR_DCACPU(x) \ 1681 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1682 1683 #define S_FW_RI_RES_WR_FBMIN 23 1684 #define M_FW_RI_RES_WR_FBMIN 0x7 1685 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1686 #define G_FW_RI_RES_WR_FBMIN(x) \ 1687 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1688 1689 #define S_FW_RI_RES_WR_FBMAX 20 1690 #define M_FW_RI_RES_WR_FBMAX 0x7 1691 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1692 #define G_FW_RI_RES_WR_FBMAX(x) \ 1693 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1694 1695 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1696 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1697 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1698 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1699 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1700 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1701 1702 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1703 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1704 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1705 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1706 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1707 1708 #define S_FW_RI_RES_WR_EQSIZE 0 1709 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1710 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1711 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1712 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1713 1714 #define S_FW_RI_RES_WR_IQANDST 15 1715 #define M_FW_RI_RES_WR_IQANDST 0x1 1716 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1717 #define G_FW_RI_RES_WR_IQANDST(x) \ 1718 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1719 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1720 1721 #define S_FW_RI_RES_WR_IQANUS 14 1722 #define M_FW_RI_RES_WR_IQANUS 0x1 1723 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1724 #define G_FW_RI_RES_WR_IQANUS(x) \ 1725 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1726 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1727 1728 #define S_FW_RI_RES_WR_IQANUD 12 1729 #define M_FW_RI_RES_WR_IQANUD 0x3 1730 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1731 #define G_FW_RI_RES_WR_IQANUD(x) \ 1732 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1733 1734 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1735 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1736 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1737 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1738 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1739 1740 #define S_FW_RI_RES_WR_IQDROPRSS 15 1741 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1742 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1743 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1744 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1745 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1746 1747 #define S_FW_RI_RES_WR_IQGTSMODE 14 1748 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1749 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1750 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1751 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1752 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1753 1754 #define S_FW_RI_RES_WR_IQPCIECH 12 1755 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1756 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1757 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1758 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1759 1760 #define S_FW_RI_RES_WR_IQDCAEN 11 1761 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1762 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1763 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1764 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1765 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1766 1767 #define S_FW_RI_RES_WR_IQDCACPU 6 1768 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1769 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1770 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1771 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1772 1773 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1774 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1775 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1776 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1777 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1778 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1779 1780 #define S_FW_RI_RES_WR_IQO 3 1781 #define M_FW_RI_RES_WR_IQO 0x1 1782 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1783 #define G_FW_RI_RES_WR_IQO(x) \ 1784 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1785 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1786 1787 #define S_FW_RI_RES_WR_IQCPRIO 2 1788 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1789 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1790 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1791 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1792 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1793 1794 #define S_FW_RI_RES_WR_IQESIZE 0 1795 #define M_FW_RI_RES_WR_IQESIZE 0x3 1796 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1797 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1798 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1799 1800 #define S_FW_RI_RES_WR_IQNS 31 1801 #define M_FW_RI_RES_WR_IQNS 0x1 1802 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1803 #define G_FW_RI_RES_WR_IQNS(x) \ 1804 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1805 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1806 1807 #define S_FW_RI_RES_WR_IQRO 30 1808 #define M_FW_RI_RES_WR_IQRO 0x1 1809 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1810 #define G_FW_RI_RES_WR_IQRO(x) \ 1811 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1812 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1813 1814 struct fw_ri_rdma_write_wr { 1815 __u8 opcode; 1816 __u8 flags; 1817 __u16 wrid; 1818 __u8 r1[3]; 1819 __u8 len16; 1820 __u64 immd_data; 1821 __be32 plen; 1822 __be32 stag_sink; 1823 __be64 to_sink; 1824 #ifndef C99_NOT_SUPPORTED 1825 union { 1826 struct fw_ri_immd immd_src[0]; 1827 struct fw_ri_isgl isgl_src[0]; 1828 } u; 1829 #endif 1830 }; 1831 1832 struct fw_ri_send_wr { 1833 __u8 opcode; 1834 __u8 flags; 1835 __u16 wrid; 1836 __u8 r1[3]; 1837 __u8 len16; 1838 __be32 sendop_pkd; 1839 __be32 stag_inv; 1840 __be32 plen; 1841 __be32 r3; 1842 __be64 r4; 1843 #ifndef C99_NOT_SUPPORTED 1844 union { 1845 struct fw_ri_immd immd_src[0]; 1846 struct fw_ri_isgl isgl_src[0]; 1847 } u; 1848 #endif 1849 }; 1850 1851 #define S_FW_RI_SEND_WR_SENDOP 0 1852 #define M_FW_RI_SEND_WR_SENDOP 0xf 1853 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1854 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1855 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1856 1857 struct fw_ri_rdma_write_cmpl_wr { 1858 __u8 opcode; 1859 __u8 flags; 1860 __u16 wrid; 1861 __u8 r1[3]; 1862 __u8 len16; 1863 __u8 r2; 1864 __u8 flags_send; 1865 __u16 wrid_send; 1866 __be32 stag_inv; 1867 __be32 plen; 1868 __be32 stag_sink; 1869 __be64 to_sink; 1870 union fw_ri_cmpl { 1871 struct fw_ri_immd_cmpl { 1872 __u8 op; 1873 __u8 r1[6]; 1874 __u8 immdlen; 1875 __u8 data[16]; 1876 } immd_src; 1877 struct fw_ri_isgl isgl_src; 1878 } u_cmpl; 1879 __be64 r3; 1880 #ifndef C99_NOT_SUPPORTED 1881 union fw_ri_write { 1882 struct fw_ri_immd immd_src[0]; 1883 struct fw_ri_isgl isgl_src[0]; 1884 } u; 1885 #endif 1886 }; 1887 1888 struct fw_ri_rdma_read_wr { 1889 __u8 opcode; 1890 __u8 flags; 1891 __u16 wrid; 1892 __u8 r1[3]; 1893 __u8 len16; 1894 __be64 r2; 1895 __be32 stag_sink; 1896 __be32 to_sink_hi; 1897 __be32 to_sink_lo; 1898 __be32 plen; 1899 __be32 stag_src; 1900 __be32 to_src_hi; 1901 __be32 to_src_lo; 1902 __be32 r5; 1903 }; 1904 1905 struct fw_ri_recv_wr { 1906 __u8 opcode; 1907 __u8 r1; 1908 __u16 wrid; 1909 __u8 r2[3]; 1910 __u8 len16; 1911 struct fw_ri_isgl isgl; 1912 }; 1913 1914 struct fw_ri_bind_mw_wr { 1915 __u8 opcode; 1916 __u8 flags; 1917 __u16 wrid; 1918 __u8 r1[3]; 1919 __u8 len16; 1920 __u8 qpbinde_to_dcacpu; 1921 __u8 pgsz_shift; 1922 __u8 addr_type; 1923 __u8 mem_perms; 1924 __be32 stag_mr; 1925 __be32 stag_mw; 1926 __be32 r3; 1927 __be64 len_mw; 1928 __be64 va_fbo; 1929 __be64 r4; 1930 }; 1931 1932 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1933 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1934 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1935 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1936 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1937 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1938 1939 #define S_FW_RI_BIND_MW_WR_NS 5 1940 #define M_FW_RI_BIND_MW_WR_NS 0x1 1941 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1942 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1943 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1944 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1945 1946 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1947 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1948 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1949 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1950 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1951 1952 struct fw_ri_fr_nsmr_wr { 1953 __u8 opcode; 1954 __u8 flags; 1955 __u16 wrid; 1956 __u8 r1[3]; 1957 __u8 len16; 1958 __u8 qpbinde_to_dcacpu; 1959 __u8 pgsz_shift; 1960 __u8 addr_type; 1961 __u8 mem_perms; 1962 __be32 stag; 1963 __be32 len_hi; 1964 __be32 len_lo; 1965 __be32 va_hi; 1966 __be32 va_lo_fbo; 1967 }; 1968 1969 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1970 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1971 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1972 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1973 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1974 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1975 1976 #define S_FW_RI_FR_NSMR_WR_NS 5 1977 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1978 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1979 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1980 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1981 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1982 1983 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1984 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1985 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1986 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1987 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1988 1989 struct fw_ri_fr_nsmr_tpte_wr { 1990 __u8 opcode; 1991 __u8 flags; 1992 __u16 wrid; 1993 __u8 r1[3]; 1994 __u8 len16; 1995 __be32 r2; 1996 __be32 stag; 1997 struct fw_ri_tpte tpte; 1998 __be64 pbl[2]; 1999 }; 2000 2001 struct fw_ri_inv_lstag_wr { 2002 __u8 opcode; 2003 __u8 flags; 2004 __u16 wrid; 2005 __u8 r1[3]; 2006 __u8 len16; 2007 __be32 r2; 2008 __be32 stag_inv; 2009 }; 2010 2011 struct fw_ri_send_immediate_wr { 2012 __u8 opcode; 2013 __u8 flags; 2014 __u16 wrid; 2015 __u8 r1[3]; 2016 __u8 len16; 2017 __be32 sendimmop_pkd; 2018 __be32 r3; 2019 __be32 plen; 2020 __be32 r4; 2021 __be64 r5; 2022 #ifndef C99_NOT_SUPPORTED 2023 struct fw_ri_immd immd_src[0]; 2024 #endif 2025 }; 2026 2027 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 2028 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 2029 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2030 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2031 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2032 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 2033 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2034 2035 enum fw_ri_atomic_op { 2036 FW_RI_ATOMIC_OP_FETCHADD, 2037 FW_RI_ATOMIC_OP_SWAP, 2038 FW_RI_ATOMIC_OP_CMDSWAP, 2039 }; 2040 2041 struct fw_ri_atomic_wr { 2042 __u8 opcode; 2043 __u8 flags; 2044 __u16 wrid; 2045 __u8 r1[3]; 2046 __u8 len16; 2047 __be32 atomicop_pkd; 2048 __be64 r3; 2049 __be32 aopcode_pkd; 2050 __be32 reqid; 2051 __be32 stag; 2052 __be32 to_hi; 2053 __be32 to_lo; 2054 __be32 addswap_data_hi; 2055 __be32 addswap_data_lo; 2056 __be32 addswap_mask_hi; 2057 __be32 addswap_mask_lo; 2058 __be32 compare_data_hi; 2059 __be32 compare_data_lo; 2060 __be32 compare_mask_hi; 2061 __be32 compare_mask_lo; 2062 __be32 r5; 2063 }; 2064 2065 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 2066 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 2067 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 2068 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 2069 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2070 2071 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 2072 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2073 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2074 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2075 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2076 2077 enum fw_ri_type { 2078 FW_RI_TYPE_INIT, 2079 FW_RI_TYPE_FINI, 2080 FW_RI_TYPE_TERMINATE 2081 }; 2082 2083 enum fw_ri_init_p2ptype { 2084 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2085 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2086 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2087 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2088 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2089 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2090 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2091 }; 2092 2093 enum fw_ri_init_rqeqid_srq { 2094 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 2095 }; 2096 2097 struct fw_ri_wr { 2098 __be32 op_compl; 2099 __be32 flowid_len16; 2100 __u64 cookie; 2101 union fw_ri { 2102 struct fw_ri_init { 2103 __u8 type; 2104 __u8 mpareqbit_p2ptype; 2105 __u8 r4[2]; 2106 __u8 mpa_attrs; 2107 __u8 qp_caps; 2108 __be16 nrqe; 2109 __be32 pdid; 2110 __be32 qpid; 2111 __be32 sq_eqid; 2112 __be32 rq_eqid; 2113 __be32 scqid; 2114 __be32 rcqid; 2115 __be32 ord_max; 2116 __be32 ird_max; 2117 __be32 iss; 2118 __be32 irs; 2119 __be32 hwrqsize; 2120 __be32 hwrqaddr; 2121 __be64 r5; 2122 union fw_ri_init_p2p { 2123 struct fw_ri_rdma_write_wr write; 2124 struct fw_ri_rdma_read_wr read; 2125 struct fw_ri_send_wr send; 2126 } u; 2127 } init; 2128 struct fw_ri_fini { 2129 __u8 type; 2130 __u8 r3[7]; 2131 __be64 r4; 2132 } fini; 2133 struct fw_ri_terminate { 2134 __u8 type; 2135 __u8 r3[3]; 2136 __be32 immdlen; 2137 __u8 termmsg[40]; 2138 } terminate; 2139 } u; 2140 }; 2141 2142 #define S_FW_RI_WR_MPAREQBIT 7 2143 #define M_FW_RI_WR_MPAREQBIT 0x1 2144 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2145 #define G_FW_RI_WR_MPAREQBIT(x) \ 2146 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2147 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2148 2149 #define S_FW_RI_WR_0BRRBIT 6 2150 #define M_FW_RI_WR_0BRRBIT 0x1 2151 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2152 #define G_FW_RI_WR_0BRRBIT(x) \ 2153 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2154 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2155 2156 #define S_FW_RI_WR_P2PTYPE 0 2157 #define M_FW_RI_WR_P2PTYPE 0xf 2158 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2159 #define G_FW_RI_WR_P2PTYPE(x) \ 2160 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2161 2162 /****************************************************************************** 2163 * F O i S C S I W O R K R E Q U E S T s 2164 *********************************************/ 2165 2166 #define FW_FOISCSI_NAME_MAX_LEN 224 2167 #define FW_FOISCSI_ALIAS_MAX_LEN 224 2168 #define FW_FOISCSI_KEY_MAX_LEN 64 2169 #define FW_FOISCSI_VAL_MAX_LEN 256 2170 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 2171 #define FW_FOISCSI_INIT_NODE_MAX 8 2172 2173 enum fw_chnet_ifconf_wr_subop { 2174 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 2175 2176 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 2177 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 2178 2179 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 2180 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 2181 2182 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 2183 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 2184 2185 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 2186 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 2187 2188 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 2189 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 2190 2191 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 2192 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 2193 2194 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2195 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2196 2197 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2198 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2199 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2200 2201 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4, 2202 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6, 2203 2204 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING4, 2205 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING6, 2206 2207 FW_CHNET_IFCONF_WR_SUBOP_PMTU6_CLEAR, 2208 2209 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2210 }; 2211 2212 struct fw_chnet_ifconf_wr { 2213 __be32 op_compl; 2214 __be32 flowid_len16; 2215 __u64 cookie; 2216 __be32 if_flowid; 2217 __u8 idx; 2218 __u8 subop; 2219 __u8 retval; 2220 __u8 r2; 2221 union { 2222 __be64 r3; 2223 struct fw_chnet_ifconf_ping { 2224 __be16 ping_time; 2225 __u8 ping_rsptype; 2226 __u8 ping_param_rspcode_to_fin_bit; 2227 __u8 ping_pktsize; 2228 __u8 ping_ttl; 2229 __be16 ping_seq; 2230 } ping; 2231 struct fw_chnet_ifconf_mac { 2232 __u8 peer_mac[6]; 2233 __u8 smac_idx; 2234 } mac; 2235 } u; 2236 struct fw_chnet_ifconf_params { 2237 __be16 ping_pldsize; 2238 __be16 r0; 2239 __be16 vlanid; 2240 __be16 mtu; 2241 union fw_chnet_ifconf_addr_type { 2242 struct fw_chnet_ifconf_ipv4 { 2243 __be32 addr; 2244 __be32 mask; 2245 __be32 router; 2246 __be32 r0; 2247 __be64 r1; 2248 } ipv4; 2249 struct fw_chnet_ifconf_ipv6 { 2250 __u8 prefix_len; 2251 __u8 r0; 2252 __be16 r1; 2253 __be32 r2; 2254 __be64 addr_hi; 2255 __be64 addr_lo; 2256 __be64 router_hi; 2257 __be64 router_lo; 2258 } ipv6; 2259 } in_attr; 2260 } param; 2261 }; 2262 2263 #define S_FW_CHNET_IFCONF_WR_PING_MACBIT 1 2264 #define M_FW_CHNET_IFCONF_WR_PING_MACBIT 0x1 2265 #define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 2266 ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT) 2267 #define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 2268 (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \ 2269 M_FW_CHNET_IFCONF_WR_PING_MACBIT) 2270 #define F_FW_CHNET_IFCONF_WR_PING_MACBIT \ 2271 V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U) 2272 2273 #define S_FW_CHNET_IFCONF_WR_FIN_BIT 0 2274 #define M_FW_CHNET_IFCONF_WR_FIN_BIT 0x1 2275 #define V_FW_CHNET_IFCONF_WR_FIN_BIT(x) ((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT) 2276 #define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \ 2277 (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT) 2278 #define F_FW_CHNET_IFCONF_WR_FIN_BIT V_FW_CHNET_IFCONF_WR_FIN_BIT(1U) 2279 2280 enum fw_foiscsi_node_type { 2281 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2282 FW_FOISCSI_NODE_TYPE_TARGET, 2283 }; 2284 2285 enum fw_foiscsi_session_type { 2286 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2287 FW_FOISCSI_SESSION_TYPE_NORMAL, 2288 }; 2289 2290 enum fw_foiscsi_auth_policy { 2291 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2292 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2293 }; 2294 2295 enum fw_foiscsi_auth_method { 2296 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2297 FW_FOISCSI_AUTH_METHOD_CHAP, 2298 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2299 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2300 }; 2301 2302 enum fw_foiscsi_digest_type { 2303 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2304 FW_FOISCSI_DIGEST_TYPE_CRC32, 2305 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2306 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2307 }; 2308 2309 enum fw_foiscsi_wr_subop { 2310 FW_FOISCSI_WR_SUBOP_ADD = 1, 2311 FW_FOISCSI_WR_SUBOP_DEL = 2, 2312 FW_FOISCSI_WR_SUBOP_MOD = 4, 2313 }; 2314 2315 enum fw_coiscsi_stats_wr_subop { 2316 FW_COISCSI_WR_SUBOP_TOT = 1, 2317 FW_COISCSI_WR_SUBOP_MAX = 2, 2318 FW_COISCSI_WR_SUBOP_CUR = 3, 2319 FW_COISCSI_WR_SUBOP_CLR = 4, 2320 }; 2321 2322 enum fw_foiscsi_ctrl_state { 2323 FW_FOISCSI_CTRL_STATE_FREE = 0, 2324 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2325 FW_FOISCSI_CTRL_STATE_FAILED, 2326 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2327 FW_FOISCSI_CTRL_STATE_REDIRECT, 2328 }; 2329 2330 struct fw_rdev_wr { 2331 __be32 op_to_immdlen; 2332 __be32 alloc_to_len16; 2333 __be64 cookie; 2334 __u8 protocol; 2335 __u8 event_cause; 2336 __u8 cur_state; 2337 __u8 prev_state; 2338 __be32 flags_to_assoc_flowid; 2339 union rdev_entry { 2340 struct fcoe_rdev_entry { 2341 __be32 flowid; 2342 __u8 protocol; 2343 __u8 event_cause; 2344 __u8 flags; 2345 __u8 rjt_reason; 2346 __u8 cur_login_st; 2347 __u8 prev_login_st; 2348 __be16 rcv_fr_sz; 2349 __u8 rd_xfer_rdy_to_rport_type; 2350 __u8 vft_to_qos; 2351 __u8 org_proc_assoc_to_acc_rsp_code; 2352 __u8 enh_disc_to_tgt; 2353 __u8 wwnn[8]; 2354 __u8 wwpn[8]; 2355 __be16 iqid; 2356 __u8 fc_oui[3]; 2357 __u8 r_id[3]; 2358 } fcoe_rdev; 2359 struct iscsi_rdev_entry { 2360 __be32 flowid; 2361 __u8 protocol; 2362 __u8 event_cause; 2363 __u8 flags; 2364 __u8 r3; 2365 __be16 iscsi_opts; 2366 __be16 tcp_opts; 2367 __be16 ip_opts; 2368 __be16 max_rcv_len; 2369 __be16 max_snd_len; 2370 __be16 first_brst_len; 2371 __be16 max_brst_len; 2372 __be16 r4; 2373 __be16 def_time2wait; 2374 __be16 def_time2ret; 2375 __be16 nop_out_intrvl; 2376 __be16 non_scsi_to; 2377 __be16 isid; 2378 __be16 tsid; 2379 __be16 port; 2380 __be16 tpgt; 2381 __u8 r5[6]; 2382 __be16 iqid; 2383 } iscsi_rdev; 2384 } u; 2385 }; 2386 2387 #define S_FW_RDEV_WR_IMMDLEN 0 2388 #define M_FW_RDEV_WR_IMMDLEN 0xff 2389 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2390 #define G_FW_RDEV_WR_IMMDLEN(x) \ 2391 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2392 2393 #define S_FW_RDEV_WR_ALLOC 31 2394 #define M_FW_RDEV_WR_ALLOC 0x1 2395 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2396 #define G_FW_RDEV_WR_ALLOC(x) \ 2397 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2398 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2399 2400 #define S_FW_RDEV_WR_FREE 30 2401 #define M_FW_RDEV_WR_FREE 0x1 2402 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2403 #define G_FW_RDEV_WR_FREE(x) \ 2404 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2405 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2406 2407 #define S_FW_RDEV_WR_MODIFY 29 2408 #define M_FW_RDEV_WR_MODIFY 0x1 2409 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2410 #define G_FW_RDEV_WR_MODIFY(x) \ 2411 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2412 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2413 2414 #define S_FW_RDEV_WR_FLOWID 8 2415 #define M_FW_RDEV_WR_FLOWID 0xfffff 2416 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2417 #define G_FW_RDEV_WR_FLOWID(x) \ 2418 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2419 2420 #define S_FW_RDEV_WR_LEN16 0 2421 #define M_FW_RDEV_WR_LEN16 0xff 2422 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2423 #define G_FW_RDEV_WR_LEN16(x) \ 2424 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2425 2426 #define S_FW_RDEV_WR_FLAGS 24 2427 #define M_FW_RDEV_WR_FLAGS 0xff 2428 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2429 #define G_FW_RDEV_WR_FLAGS(x) \ 2430 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2431 2432 #define S_FW_RDEV_WR_GET_NEXT 20 2433 #define M_FW_RDEV_WR_GET_NEXT 0xf 2434 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2435 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2436 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2437 2438 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2439 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2440 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2441 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2442 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2443 2444 #define S_FW_RDEV_WR_RJT 7 2445 #define M_FW_RDEV_WR_RJT 0x1 2446 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2447 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2448 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2449 2450 #define S_FW_RDEV_WR_REASON 0 2451 #define M_FW_RDEV_WR_REASON 0x7f 2452 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2453 #define G_FW_RDEV_WR_REASON(x) \ 2454 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2455 2456 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2457 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2458 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2459 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2460 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2461 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2462 2463 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2464 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2465 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2466 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2467 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2468 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2469 2470 #define S_FW_RDEV_WR_FC_SP 5 2471 #define M_FW_RDEV_WR_FC_SP 0x1 2472 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2473 #define G_FW_RDEV_WR_FC_SP(x) \ 2474 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2475 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2476 2477 #define S_FW_RDEV_WR_RPORT_TYPE 0 2478 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2479 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2480 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2481 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2482 2483 #define S_FW_RDEV_WR_VFT 7 2484 #define M_FW_RDEV_WR_VFT 0x1 2485 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2486 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2487 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2488 2489 #define S_FW_RDEV_WR_NPIV 6 2490 #define M_FW_RDEV_WR_NPIV 0x1 2491 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2492 #define G_FW_RDEV_WR_NPIV(x) \ 2493 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2494 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2495 2496 #define S_FW_RDEV_WR_CLASS 4 2497 #define M_FW_RDEV_WR_CLASS 0x3 2498 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2499 #define G_FW_RDEV_WR_CLASS(x) \ 2500 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2501 2502 #define S_FW_RDEV_WR_SEQ_DEL 3 2503 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2504 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2505 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2506 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2507 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2508 2509 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2510 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2511 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2512 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2513 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2514 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2515 2516 #define S_FW_RDEV_WR_PREF 1 2517 #define M_FW_RDEV_WR_PREF 0x1 2518 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2519 #define G_FW_RDEV_WR_PREF(x) \ 2520 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2521 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2522 2523 #define S_FW_RDEV_WR_QOS 0 2524 #define M_FW_RDEV_WR_QOS 0x1 2525 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2526 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2527 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2528 2529 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2530 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2531 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2532 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2533 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2534 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2535 2536 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2537 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2538 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2539 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2540 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2541 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2542 2543 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2544 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2545 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2546 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2547 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2548 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2549 2550 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2551 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2552 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2553 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2554 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2555 2556 #define S_FW_RDEV_WR_ENH_DISC 7 2557 #define M_FW_RDEV_WR_ENH_DISC 0x1 2558 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2559 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2560 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2561 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2562 2563 #define S_FW_RDEV_WR_REC 6 2564 #define M_FW_RDEV_WR_REC 0x1 2565 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2566 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2567 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2568 2569 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2570 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2571 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2572 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2573 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2574 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2575 2576 #define S_FW_RDEV_WR_RETRY 4 2577 #define M_FW_RDEV_WR_RETRY 0x1 2578 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2579 #define G_FW_RDEV_WR_RETRY(x) \ 2580 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2581 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2582 2583 #define S_FW_RDEV_WR_CONF_CMPL 3 2584 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2585 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2586 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2587 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2588 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2589 2590 #define S_FW_RDEV_WR_DATA_OVLY 2 2591 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2592 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2593 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2594 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2595 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2596 2597 #define S_FW_RDEV_WR_INI 1 2598 #define M_FW_RDEV_WR_INI 0x1 2599 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2600 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2601 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2602 2603 #define S_FW_RDEV_WR_TGT 0 2604 #define M_FW_RDEV_WR_TGT 0x1 2605 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2606 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2607 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2608 2609 struct fw_foiscsi_node_wr { 2610 __be32 op_to_immdlen; 2611 __be32 no_sess_recv_to_len16; 2612 __u64 cookie; 2613 __u8 subop; 2614 __u8 status; 2615 __u8 alias_len; 2616 __u8 iqn_len; 2617 __be32 node_flowid; 2618 __be16 nodeid; 2619 __be16 login_retry; 2620 __be16 retry_timeout; 2621 __be16 r3; 2622 __u8 iqn[224]; 2623 __u8 alias[224]; 2624 __be32 isid_tval_to_isid_cval; 2625 }; 2626 2627 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2628 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2629 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2630 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2631 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2632 2633 #define S_FW_FOISCSI_NODE_WR_NO_SESS_RECV 28 2634 #define M_FW_FOISCSI_NODE_WR_NO_SESS_RECV 0x1 2635 #define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 2636 ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 2637 #define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 2638 (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \ 2639 M_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 2640 #define F_FW_FOISCSI_NODE_WR_NO_SESS_RECV \ 2641 V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U) 2642 2643 #define S_FW_FOISCSI_NODE_WR_ISID_TVAL 30 2644 #define M_FW_FOISCSI_NODE_WR_ISID_TVAL 0x3 2645 #define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 2646 ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL) 2647 #define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 2648 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL) 2649 2650 #define S_FW_FOISCSI_NODE_WR_ISID_AVAL 24 2651 #define M_FW_FOISCSI_NODE_WR_ISID_AVAL 0x3f 2652 #define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 2653 ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL) 2654 #define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 2655 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL) 2656 2657 #define S_FW_FOISCSI_NODE_WR_ISID_BVAL 8 2658 #define M_FW_FOISCSI_NODE_WR_ISID_BVAL 0xffff 2659 #define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 2660 ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL) 2661 #define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 2662 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL) 2663 2664 #define S_FW_FOISCSI_NODE_WR_ISID_CVAL 0 2665 #define M_FW_FOISCSI_NODE_WR_ISID_CVAL 0xff 2666 #define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 2667 ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL) 2668 #define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 2669 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL) 2670 2671 struct fw_foiscsi_ctrl_wr { 2672 __be32 op_to_no_fin; 2673 __be32 flowid_len16; 2674 __u64 cookie; 2675 __u8 subop; 2676 __u8 status; 2677 __u8 ctrl_state; 2678 __u8 io_state; 2679 __be32 node_id; 2680 __be32 ctrl_id; 2681 __be32 io_id; 2682 struct fw_foiscsi_sess_attr { 2683 __be32 sess_type_to_erl; 2684 __be16 max_conn; 2685 __be16 max_r2t; 2686 __be16 time2wait; 2687 __be16 time2retain; 2688 __be32 max_burst; 2689 __be32 first_burst; 2690 __be32 r1; 2691 } sess_attr; 2692 struct fw_foiscsi_conn_attr { 2693 __be32 hdigest_to_tcp_ws_en; 2694 __be32 max_rcv_dsl; 2695 __be32 ping_tmo; 2696 __be16 dst_port; 2697 __be16 src_port; 2698 union fw_foiscsi_conn_attr_addr { 2699 struct fw_foiscsi_conn_attr_ipv6 { 2700 __be64 dst_addr[2]; 2701 __be64 src_addr[2]; 2702 } ipv6_addr; 2703 struct fw_foiscsi_conn_attr_ipv4 { 2704 __be32 dst_addr; 2705 __be32 src_addr; 2706 } ipv4_addr; 2707 } u; 2708 } conn_attr; 2709 __u8 tgt_name_len; 2710 __u8 r3[7]; 2711 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2712 }; 2713 2714 #define S_FW_FOISCSI_CTRL_WR_PORTID 1 2715 #define M_FW_FOISCSI_CTRL_WR_PORTID 0x7 2716 #define V_FW_FOISCSI_CTRL_WR_PORTID(x) ((x) << S_FW_FOISCSI_CTRL_WR_PORTID) 2717 #define G_FW_FOISCSI_CTRL_WR_PORTID(x) \ 2718 (((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID) 2719 2720 #define S_FW_FOISCSI_CTRL_WR_NO_FIN 0 2721 #define M_FW_FOISCSI_CTRL_WR_NO_FIN 0x1 2722 #define V_FW_FOISCSI_CTRL_WR_NO_FIN(x) ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN) 2723 #define G_FW_FOISCSI_CTRL_WR_NO_FIN(x) \ 2724 (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN) 2725 #define F_FW_FOISCSI_CTRL_WR_NO_FIN V_FW_FOISCSI_CTRL_WR_NO_FIN(1U) 2726 2727 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2728 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2729 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2730 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2731 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2732 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2733 2734 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2735 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2736 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2737 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2738 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2739 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2740 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2741 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2742 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2743 2744 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2745 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2746 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2747 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2748 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2749 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2750 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2751 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2752 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2753 2754 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2755 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2756 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2757 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2758 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2759 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2760 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2761 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2762 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2763 2764 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2765 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2766 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2767 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2768 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2769 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2770 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2771 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2772 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2773 2774 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2775 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2776 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2777 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2778 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2779 2780 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2781 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2782 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2783 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2784 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2785 2786 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2787 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2788 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2789 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2790 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2791 2792 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2793 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2794 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2795 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2796 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2797 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2798 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2799 2800 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2801 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2802 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2803 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2804 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2805 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2806 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2807 2808 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2809 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2810 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2811 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2812 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2813 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2814 2815 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 2816 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2817 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2818 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2819 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2820 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2821 2822 #define S_FW_FOISCSI_CTRL_WR_DDP_PGIDX 16 2823 #define M_FW_FOISCSI_CTRL_WR_DDP_PGIDX 0xf 2824 #define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 2825 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 2826 #define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 2827 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 2828 2829 #define S_FW_FOISCSI_CTRL_WR_TCP_WS 12 2830 #define M_FW_FOISCSI_CTRL_WR_TCP_WS 0xf 2831 #define V_FW_FOISCSI_CTRL_WR_TCP_WS(x) ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS) 2832 #define G_FW_FOISCSI_CTRL_WR_TCP_WS(x) \ 2833 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS) 2834 2835 #define S_FW_FOISCSI_CTRL_WR_TCP_WS_EN 11 2836 #define M_FW_FOISCSI_CTRL_WR_TCP_WS_EN 0x1 2837 #define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 2838 ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 2839 #define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 2840 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 2841 #define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U) 2842 2843 struct fw_foiscsi_chap_wr { 2844 __be32 op_to_kv_flag; 2845 __be32 flowid_len16; 2846 __u64 cookie; 2847 __u8 status; 2848 union fw_foiscsi_len { 2849 struct fw_foiscsi_chap_lens { 2850 __u8 id_len; 2851 __u8 sec_len; 2852 } chapl; 2853 struct fw_foiscsi_vend_kv_lens { 2854 __u8 key_len; 2855 __u8 val_len; 2856 } vend_kvl; 2857 } lenu; 2858 __u8 node_type; 2859 __be16 node_id; 2860 __u8 r3[2]; 2861 union fw_foiscsi_chap_vend { 2862 struct fw_foiscsi_chap { 2863 __u8 chap_id[224]; 2864 __u8 chap_sec[128]; 2865 } chap; 2866 struct fw_foiscsi_vend_kv { 2867 __u8 vend_key[64]; 2868 __u8 vend_val[256]; 2869 } vend_kv; 2870 } u; 2871 }; 2872 2873 #define S_FW_FOISCSI_CHAP_WR_KV_FLAG 20 2874 #define M_FW_FOISCSI_CHAP_WR_KV_FLAG 0x1 2875 #define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x) ((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG) 2876 #define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \ 2877 (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG) 2878 #define F_FW_FOISCSI_CHAP_WR_KV_FLAG V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U) 2879 2880 /****************************************************************************** 2881 * C O i S C S I W O R K R E Q U E S T S 2882 ********************************************/ 2883 2884 enum fw_chnet_addr_type { 2885 FW_CHNET_ADDD_TYPE_NONE = 0, 2886 FW_CHNET_ADDR_TYPE_IPV4, 2887 FW_CHNET_ADDR_TYPE_IPV6, 2888 }; 2889 2890 enum fw_msg_wr_type { 2891 FW_MSG_WR_TYPE_RPL = 0, 2892 FW_MSG_WR_TYPE_ERR, 2893 FW_MSG_WR_TYPE_PLD, 2894 }; 2895 2896 struct fw_coiscsi_tgt_wr { 2897 __be32 op_compl; 2898 __be32 flowid_len16; 2899 __u64 cookie; 2900 __u8 subop; 2901 __u8 status; 2902 __be16 r4; 2903 __be32 flags; 2904 struct fw_coiscsi_tgt_conn_attr { 2905 __be32 in_tid; 2906 __be16 in_port; 2907 __u8 in_type; 2908 __u8 r6; 2909 union fw_coiscsi_tgt_conn_attr_addr { 2910 struct fw_coiscsi_tgt_conn_attr_in_addr { 2911 __be32 addr; 2912 __be32 r7; 2913 __be32 r8[2]; 2914 } in_addr; 2915 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2916 __be64 addr[2]; 2917 } in_addr6; 2918 } u; 2919 } conn_attr; 2920 }; 2921 2922 #define S_FW_COISCSI_TGT_WR_PORTID 0 2923 #define M_FW_COISCSI_TGT_WR_PORTID 0x7 2924 #define V_FW_COISCSI_TGT_WR_PORTID(x) ((x) << S_FW_COISCSI_TGT_WR_PORTID) 2925 #define G_FW_COISCSI_TGT_WR_PORTID(x) \ 2926 (((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID) 2927 2928 struct fw_coiscsi_tgt_conn_wr { 2929 __be32 op_compl; 2930 __be32 flowid_len16; 2931 __u64 cookie; 2932 __u8 subop; 2933 __u8 status; 2934 __be16 iq_id; 2935 __be32 in_stid; 2936 __be32 io_id; 2937 __be32 flags_fin; 2938 union { 2939 struct fw_coiscsi_tgt_conn_tcp { 2940 __be16 in_sport; 2941 __be16 in_dport; 2942 __u8 wscale_wsen; 2943 __u8 r4[3]; 2944 union fw_coiscsi_tgt_conn_tcp_addr { 2945 struct fw_coiscsi_tgt_conn_tcp_in_addr { 2946 __be32 saddr; 2947 __be32 daddr; 2948 } in_addr; 2949 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 2950 __be64 saddr[2]; 2951 __be64 daddr[2]; 2952 } in_addr6; 2953 } u; 2954 } conn_tcp; 2955 struct fw_coiscsi_tgt_conn_stats { 2956 __be32 ddp_reqs; 2957 __be32 ddp_cmpls; 2958 __be16 ddp_aborts; 2959 __be16 ddp_bps; 2960 } stats; 2961 } u; 2962 struct fw_coiscsi_tgt_conn_iscsi { 2963 __be32 hdigest_to_ddp_pgsz; 2964 __be32 tgt_id; 2965 __be16 max_r2t; 2966 __be16 r5; 2967 __be32 max_burst; 2968 __be32 max_rdsl; 2969 __be32 max_tdsl; 2970 __be32 cur_sn; 2971 __be32 r6; 2972 } conn_iscsi; 2973 }; 2974 2975 #define S_FW_COISCSI_TGT_CONN_WR_PORTID 0 2976 #define M_FW_COISCSI_TGT_CONN_WR_PORTID 0x7 2977 #define V_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 2978 ((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID) 2979 #define G_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 2980 (((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \ 2981 M_FW_COISCSI_TGT_CONN_WR_PORTID) 2982 2983 #define S_FW_COISCSI_TGT_CONN_WR_FIN 0 2984 #define M_FW_COISCSI_TGT_CONN_WR_FIN 0x1 2985 #define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN) 2986 #define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \ 2987 (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN) 2988 #define F_FW_COISCSI_TGT_CONN_WR_FIN V_FW_COISCSI_TGT_CONN_WR_FIN(1U) 2989 2990 #define S_FW_COISCSI_TGT_CONN_WR_WSCALE 1 2991 #define M_FW_COISCSI_TGT_CONN_WR_WSCALE 0xf 2992 #define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 2993 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE) 2994 #define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 2995 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \ 2996 M_FW_COISCSI_TGT_CONN_WR_WSCALE) 2997 2998 #define S_FW_COISCSI_TGT_CONN_WR_WSEN 0 2999 #define M_FW_COISCSI_TGT_CONN_WR_WSEN 0x1 3000 #define V_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 3001 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN) 3002 #define G_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 3003 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN) 3004 #define F_FW_COISCSI_TGT_CONN_WR_WSEN V_FW_COISCSI_TGT_CONN_WR_WSEN(1U) 3005 3006 struct fw_coiscsi_tgt_xmit_wr { 3007 __be32 op_to_immdlen; 3008 union { 3009 struct cmpl_stat { 3010 __be32 cmpl_status_pkd; 3011 } cs; 3012 struct flowid_len { 3013 __be32 flowid_len16; 3014 } fllen; 3015 } u; 3016 __u64 cookie; 3017 __be16 iq_id; 3018 __be16 r3; 3019 __be32 pz_off; 3020 __be32 t_xfer_len; 3021 union { 3022 __be32 tag; 3023 __be32 datasn; 3024 __be32 ddp_status; 3025 } cu; 3026 }; 3027 3028 #define S_FW_COISCSI_TGT_XMIT_WR_DDGST 23 3029 #define M_FW_COISCSI_TGT_XMIT_WR_DDGST 0x1 3030 #define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 3031 ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST) 3032 #define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 3033 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST) 3034 #define F_FW_COISCSI_TGT_XMIT_WR_DDGST V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U) 3035 3036 #define S_FW_COISCSI_TGT_XMIT_WR_HDGST 22 3037 #define M_FW_COISCSI_TGT_XMIT_WR_HDGST 0x1 3038 #define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3039 ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST) 3040 #define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3041 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST) 3042 #define F_FW_COISCSI_TGT_XMIT_WR_HDGST V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U) 3043 3044 #define S_FW_COISCSI_TGT_XMIT_WR_DDP 20 3045 #define M_FW_COISCSI_TGT_XMIT_WR_DDP 0x1 3046 #define V_FW_COISCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP) 3047 #define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \ 3048 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP) 3049 #define F_FW_COISCSI_TGT_XMIT_WR_DDP V_FW_COISCSI_TGT_XMIT_WR_DDP(1U) 3050 3051 #define S_FW_COISCSI_TGT_XMIT_WR_ABORT 19 3052 #define M_FW_COISCSI_TGT_XMIT_WR_ABORT 0x1 3053 #define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3054 ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT) 3055 #define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3056 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT) 3057 #define F_FW_COISCSI_TGT_XMIT_WR_ABORT V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U) 3058 3059 #define S_FW_COISCSI_TGT_XMIT_WR_FINAL 18 3060 #define M_FW_COISCSI_TGT_XMIT_WR_FINAL 0x1 3061 #define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3062 ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL) 3063 #define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3064 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL) 3065 #define F_FW_COISCSI_TGT_XMIT_WR_FINAL V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U) 3066 3067 #define S_FW_COISCSI_TGT_XMIT_WR_PADLEN 16 3068 #define M_FW_COISCSI_TGT_XMIT_WR_PADLEN 0x3 3069 #define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3070 ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3071 #define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3072 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \ 3073 M_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3074 3075 #define S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 15 3076 #define M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 0x1 3077 #define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3078 ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3079 #define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3080 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \ 3081 M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3082 #define F_FW_COISCSI_TGT_XMIT_WR_INCSTATSN \ 3083 V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U) 3084 3085 #define S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0 3086 #define M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0xff 3087 #define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3088 ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 3089 #define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3090 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \ 3091 M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 3092 3093 #define S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 8 3094 #define M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 0xff 3095 #define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3096 ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3097 #define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3098 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \ 3099 M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3100 3101 struct fw_coiscsi_stats_wr { 3102 __be32 op_compl; 3103 __be32 flowid_len16; 3104 __u64 cookie; 3105 __u8 subop; 3106 __u8 status; 3107 union fw_coiscsi_stats { 3108 struct fw_coiscsi_resource { 3109 __u8 num_ipv4_tgt; 3110 __u8 num_ipv6_tgt; 3111 __be16 num_l2t_entries; 3112 __be16 num_csocks; 3113 __be16 num_tasks; 3114 __be16 num_ppods_zone[11]; 3115 __be32 num_bufll64; 3116 __u8 r2[12]; 3117 } rsrc; 3118 } u; 3119 }; 3120 3121 #define S_FW_COISCSI_STATS_WR_PORTID 0 3122 #define M_FW_COISCSI_STATS_WR_PORTID 0x7 3123 #define V_FW_COISCSI_STATS_WR_PORTID(x) ((x) << S_FW_COISCSI_STATS_WR_PORTID) 3124 #define G_FW_COISCSI_STATS_WR_PORTID(x) \ 3125 (((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID) 3126 3127 struct fw_isns_wr { 3128 __be32 op_compl; 3129 __be32 flowid_len16; 3130 __u64 cookie; 3131 __u8 subop; 3132 __u8 status; 3133 __be16 iq_id; 3134 __be16 vlanid; 3135 __be16 r4; 3136 struct fw_tcp_conn_attr { 3137 __be32 in_tid; 3138 __be16 in_port; 3139 __u8 in_type; 3140 __u8 r6; 3141 union fw_tcp_conn_attr_addr { 3142 struct fw_tcp_conn_attr_in_addr { 3143 __be32 addr; 3144 __be32 r7; 3145 __be32 r8[2]; 3146 } in_addr; 3147 struct fw_tcp_conn_attr_in_addr6 { 3148 __be64 addr[2]; 3149 } in_addr6; 3150 } u; 3151 } conn_attr; 3152 }; 3153 3154 #define S_FW_ISNS_WR_PORTID 0 3155 #define M_FW_ISNS_WR_PORTID 0x7 3156 #define V_FW_ISNS_WR_PORTID(x) ((x) << S_FW_ISNS_WR_PORTID) 3157 #define G_FW_ISNS_WR_PORTID(x) \ 3158 (((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID) 3159 3160 struct fw_isns_xmit_wr { 3161 __be32 op_to_immdlen; 3162 __be32 flowid_len16; 3163 __u64 cookie; 3164 __be16 iq_id; 3165 __be16 r4; 3166 __be32 xfer_len; 3167 __be64 r5; 3168 }; 3169 3170 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 3171 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 3172 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 3173 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 3174 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 3175 3176 /****************************************************************************** 3177 * F O F C O E W O R K R E Q U E S T s 3178 *******************************************/ 3179 3180 struct fw_fcoe_els_ct_wr { 3181 __be32 op_immdlen; 3182 __be32 flowid_len16; 3183 __be64 cookie; 3184 __be16 iqid; 3185 __u8 tmo_val; 3186 __u8 els_ct_type; 3187 __u8 ctl_pri; 3188 __u8 cp_en_class; 3189 __be16 xfer_cnt; 3190 __u8 fl_to_sp; 3191 __u8 l_id[3]; 3192 __u8 r5; 3193 __u8 r_id[3]; 3194 __be64 rsp_dmaaddr; 3195 __be32 rsp_dmalen; 3196 __be32 r6; 3197 }; 3198 3199 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 3200 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 3201 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 3202 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 3203 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 3204 3205 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 3206 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 3207 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 3208 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 3209 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 3210 3211 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 3212 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 3213 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 3214 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 3215 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 3216 3217 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 3218 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 3219 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 3220 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 3221 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 3222 3223 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 3224 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 3225 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 3226 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 3227 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 3228 3229 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 3230 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 3231 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 3232 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 3233 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 3234 3235 #define S_FW_FCOE_ELS_CT_WR_FL 2 3236 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 3237 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 3238 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 3239 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 3240 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 3241 3242 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 3243 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 3244 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 3245 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 3246 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 3247 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 3248 3249 #define S_FW_FCOE_ELS_CT_WR_SP 0 3250 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 3251 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 3252 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 3253 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 3254 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 3255 3256 /****************************************************************************** 3257 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 3258 *****************************************************************************/ 3259 3260 struct fw_scsi_write_wr { 3261 __be32 op_immdlen; 3262 __be32 flowid_len16; 3263 __be64 cookie; 3264 __be16 iqid; 3265 __u8 tmo_val; 3266 __u8 use_xfer_cnt; 3267 union fw_scsi_write_priv { 3268 struct fcoe_write_priv { 3269 __u8 ctl_pri; 3270 __u8 cp_en_class; 3271 __u8 r3_lo[2]; 3272 } fcoe; 3273 struct iscsi_write_priv { 3274 __u8 r3[4]; 3275 } iscsi; 3276 } u; 3277 __be32 xfer_cnt; 3278 __be32 ini_xfer_cnt; 3279 __be64 rsp_dmaaddr; 3280 __be32 rsp_dmalen; 3281 __be32 r4; 3282 }; 3283 3284 #define S_FW_SCSI_WRITE_WR_OPCODE 24 3285 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 3286 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 3287 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 3288 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 3289 3290 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 3291 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 3292 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 3293 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 3294 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 3295 3296 #define S_FW_SCSI_WRITE_WR_FLOWID 8 3297 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 3298 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 3299 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 3300 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 3301 3302 #define S_FW_SCSI_WRITE_WR_LEN16 0 3303 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 3304 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 3305 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 3306 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 3307 3308 #define S_FW_SCSI_WRITE_WR_CP_EN 6 3309 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 3310 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 3311 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 3312 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 3313 3314 #define S_FW_SCSI_WRITE_WR_CLASS 4 3315 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 3316 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 3317 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 3318 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 3319 3320 struct fw_scsi_read_wr { 3321 __be32 op_immdlen; 3322 __be32 flowid_len16; 3323 __be64 cookie; 3324 __be16 iqid; 3325 __u8 tmo_val; 3326 __u8 use_xfer_cnt; 3327 union fw_scsi_read_priv { 3328 struct fcoe_read_priv { 3329 __u8 ctl_pri; 3330 __u8 cp_en_class; 3331 __u8 r3_lo[2]; 3332 } fcoe; 3333 struct iscsi_read_priv { 3334 __u8 r3[4]; 3335 } iscsi; 3336 } u; 3337 __be32 xfer_cnt; 3338 __be32 ini_xfer_cnt; 3339 __be64 rsp_dmaaddr; 3340 __be32 rsp_dmalen; 3341 __be32 r4; 3342 }; 3343 3344 #define S_FW_SCSI_READ_WR_OPCODE 24 3345 #define M_FW_SCSI_READ_WR_OPCODE 0xff 3346 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 3347 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 3348 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 3349 3350 #define S_FW_SCSI_READ_WR_IMMDLEN 0 3351 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 3352 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 3353 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 3354 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 3355 3356 #define S_FW_SCSI_READ_WR_FLOWID 8 3357 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 3358 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 3359 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 3360 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 3361 3362 #define S_FW_SCSI_READ_WR_LEN16 0 3363 #define M_FW_SCSI_READ_WR_LEN16 0xff 3364 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 3365 #define G_FW_SCSI_READ_WR_LEN16(x) \ 3366 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 3367 3368 #define S_FW_SCSI_READ_WR_CP_EN 6 3369 #define M_FW_SCSI_READ_WR_CP_EN 0x3 3370 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 3371 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 3372 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 3373 3374 #define S_FW_SCSI_READ_WR_CLASS 4 3375 #define M_FW_SCSI_READ_WR_CLASS 0x3 3376 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 3377 #define G_FW_SCSI_READ_WR_CLASS(x) \ 3378 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 3379 3380 struct fw_scsi_cmd_wr { 3381 __be32 op_immdlen; 3382 __be32 flowid_len16; 3383 __be64 cookie; 3384 __be16 iqid; 3385 __u8 tmo_val; 3386 __u8 r3; 3387 union fw_scsi_cmd_priv { 3388 struct fcoe_cmd_priv { 3389 __u8 ctl_pri; 3390 __u8 cp_en_class; 3391 __u8 r4_lo[2]; 3392 } fcoe; 3393 struct iscsi_cmd_priv { 3394 __u8 r4[4]; 3395 } iscsi; 3396 } u; 3397 __u8 r5[8]; 3398 __be64 rsp_dmaaddr; 3399 __be32 rsp_dmalen; 3400 __be32 r6; 3401 }; 3402 3403 #define S_FW_SCSI_CMD_WR_OPCODE 24 3404 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 3405 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 3406 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 3407 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 3408 3409 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 3410 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 3411 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 3412 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 3413 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 3414 3415 #define S_FW_SCSI_CMD_WR_FLOWID 8 3416 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 3417 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 3418 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 3419 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 3420 3421 #define S_FW_SCSI_CMD_WR_LEN16 0 3422 #define M_FW_SCSI_CMD_WR_LEN16 0xff 3423 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 3424 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 3425 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 3426 3427 #define S_FW_SCSI_CMD_WR_CP_EN 6 3428 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 3429 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 3430 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 3431 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 3432 3433 #define S_FW_SCSI_CMD_WR_CLASS 4 3434 #define M_FW_SCSI_CMD_WR_CLASS 0x3 3435 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 3436 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 3437 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 3438 3439 struct fw_scsi_abrt_cls_wr { 3440 __be32 op_immdlen; 3441 __be32 flowid_len16; 3442 __be64 cookie; 3443 __be16 iqid; 3444 __u8 tmo_val; 3445 __u8 sub_opcode_to_chk_all_io; 3446 __u8 r3[4]; 3447 __be64 t_cookie; 3448 }; 3449 3450 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 3451 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 3452 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 3453 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 3454 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 3455 3456 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 3457 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 3458 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3459 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3460 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3461 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3462 3463 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 3464 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 3465 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 3466 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 3467 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 3468 3469 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 3470 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 3471 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 3472 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 3473 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 3474 3475 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 3476 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 3477 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3478 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3479 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3480 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3481 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3482 3483 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3484 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3485 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3486 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3487 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3488 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3489 3490 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3491 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3492 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3493 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3494 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3495 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3496 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3497 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 3498 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 3499 3500 struct fw_scsi_tgt_acc_wr { 3501 __be32 op_immdlen; 3502 __be32 flowid_len16; 3503 __be64 cookie; 3504 __be16 iqid; 3505 __u8 r3; 3506 __u8 use_burst_len; 3507 union fw_scsi_tgt_acc_priv { 3508 struct fcoe_tgt_acc_priv { 3509 __u8 ctl_pri; 3510 __u8 cp_en_class; 3511 __u8 r4_lo[2]; 3512 } fcoe; 3513 struct iscsi_tgt_acc_priv { 3514 __u8 r4[4]; 3515 } iscsi; 3516 } u; 3517 __be32 burst_len; 3518 __be32 rel_off; 3519 __be64 r5; 3520 __be32 r6; 3521 __be32 tot_xfer_len; 3522 }; 3523 3524 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3525 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3526 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3527 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3528 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3529 3530 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3531 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3532 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3533 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3534 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3535 3536 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3537 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3538 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3539 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3540 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3541 3542 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3543 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3544 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3545 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3546 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3547 3548 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3549 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3550 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3551 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3552 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3553 3554 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3555 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3556 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3557 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3558 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 3559 3560 struct fw_scsi_tgt_xmit_wr { 3561 __be32 op_immdlen; 3562 __be32 flowid_len16; 3563 __be64 cookie; 3564 __be16 iqid; 3565 __u8 auto_rsp; 3566 __u8 use_xfer_cnt; 3567 union fw_scsi_tgt_xmit_priv { 3568 struct fcoe_tgt_xmit_priv { 3569 __u8 ctl_pri; 3570 __u8 cp_en_class; 3571 __u8 r3_lo[2]; 3572 } fcoe; 3573 struct iscsi_tgt_xmit_priv { 3574 __u8 r3[4]; 3575 } iscsi; 3576 } u; 3577 __be32 xfer_cnt; 3578 __be32 r4; 3579 __be64 r5; 3580 __be32 r6; 3581 __be32 tot_xfer_len; 3582 }; 3583 3584 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3585 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3586 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3587 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3588 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3589 3590 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3591 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3592 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3593 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3594 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3595 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3596 3597 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3598 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3599 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3600 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3601 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3602 3603 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3604 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3605 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3606 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3607 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3608 3609 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3610 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3611 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3612 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3613 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3614 3615 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3616 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3617 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3618 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3619 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 3620 3621 struct fw_scsi_tgt_rsp_wr { 3622 __be32 op_immdlen; 3623 __be32 flowid_len16; 3624 __be64 cookie; 3625 __be16 iqid; 3626 __u8 r3[2]; 3627 union fw_scsi_tgt_rsp_priv { 3628 struct fcoe_tgt_rsp_priv { 3629 __u8 ctl_pri; 3630 __u8 cp_en_class; 3631 __u8 r4_lo[2]; 3632 } fcoe; 3633 struct iscsi_tgt_rsp_priv { 3634 __u8 r4[4]; 3635 } iscsi; 3636 } u; 3637 __u8 r5[8]; 3638 }; 3639 3640 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3641 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3642 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3643 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3644 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3645 3646 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3647 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3648 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3649 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3650 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3651 3652 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3653 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3654 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3655 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3656 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3657 3658 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3659 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3660 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3661 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3662 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3663 3664 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3665 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3666 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3667 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3668 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3669 3670 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3671 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3672 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3673 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3674 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3675 3676 struct fw_pofcoe_tcb_wr { 3677 __be32 op_compl; 3678 __be32 equiq_to_len16; 3679 __be32 r4; 3680 __be32 xfer_len; 3681 __be32 tid_to_port; 3682 __be16 x_id; 3683 __be16 vlan_id; 3684 __be64 cookie; 3685 __be32 s_id; 3686 __be32 d_id; 3687 __be32 tag; 3688 __be16 r6; 3689 __be16 iqid; 3690 }; 3691 3692 #define S_FW_POFCOE_TCB_WR_TID 12 3693 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 3694 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3695 #define G_FW_POFCOE_TCB_WR_TID(x) \ 3696 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3697 3698 #define S_FW_POFCOE_TCB_WR_ALLOC 4 3699 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3700 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3701 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3702 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3703 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3704 3705 #define S_FW_POFCOE_TCB_WR_FREE 3 3706 #define M_FW_POFCOE_TCB_WR_FREE 0x1 3707 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3708 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 3709 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3710 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3711 3712 #define S_FW_POFCOE_TCB_WR_PORT 0 3713 #define M_FW_POFCOE_TCB_WR_PORT 0x7 3714 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3715 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 3716 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3717 3718 struct fw_pofcoe_ulptx_wr { 3719 __be32 op_pkd; 3720 __be32 equiq_to_len16; 3721 __u64 cookie; 3722 }; 3723 3724 /******************************************************************* 3725 * T10 DIF related definition 3726 *******************************************************************/ 3727 struct fw_tx_pi_header { 3728 __be16 op_to_inline; 3729 __u8 pi_interval_tag_type; 3730 __u8 num_pi; 3731 __be32 pi_start4_pi_end4; 3732 __u8 tag_gen_enabled_pkd; 3733 __u8 num_pi_dsg; 3734 __be16 app_tag; 3735 __be32 ref_tag; 3736 }; 3737 3738 #define S_FW_TX_PI_HEADER_OP 8 3739 #define M_FW_TX_PI_HEADER_OP 0xff 3740 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3741 #define G_FW_TX_PI_HEADER_OP(x) \ 3742 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3743 3744 #define S_FW_TX_PI_HEADER_ULPTXMORE 7 3745 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3746 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3747 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3748 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3749 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3750 3751 #define S_FW_TX_PI_HEADER_PI_CONTROL 4 3752 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3753 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3754 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3755 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3756 3757 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3758 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3759 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3760 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3761 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3762 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3763 3764 #define S_FW_TX_PI_HEADER_VALIDATE 1 3765 #define M_FW_TX_PI_HEADER_VALIDATE 0x1 3766 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3767 #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3768 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3769 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3770 3771 #define S_FW_TX_PI_HEADER_INLINE 0 3772 #define M_FW_TX_PI_HEADER_INLINE 0x1 3773 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3774 #define G_FW_TX_PI_HEADER_INLINE(x) \ 3775 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3776 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3777 3778 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3779 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3780 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3781 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3782 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3783 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3784 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3785 3786 #define S_FW_TX_PI_HEADER_TAG_TYPE 5 3787 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3788 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3789 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3790 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3791 3792 #define S_FW_TX_PI_HEADER_PI_START4 22 3793 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3794 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3795 #define G_FW_TX_PI_HEADER_PI_START4(x) \ 3796 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3797 3798 #define S_FW_TX_PI_HEADER_PI_END4 0 3799 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3800 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3801 #define G_FW_TX_PI_HEADER_PI_END4(x) \ 3802 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3803 3804 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3805 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3806 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3807 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3808 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3809 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3810 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3811 3812 enum fw_pi_error_type { 3813 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3814 }; 3815 3816 struct fw_pi_error { 3817 __be32 err_type_pkd; 3818 __be32 flowid_len16; 3819 __be16 r2; 3820 __be16 app_tag; 3821 __be32 ref_tag; 3822 __be32 pisc[4]; 3823 }; 3824 3825 #define S_FW_PI_ERROR_ERR_TYPE 24 3826 #define M_FW_PI_ERROR_ERR_TYPE 0xff 3827 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3828 #define G_FW_PI_ERROR_ERR_TYPE(x) \ 3829 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3830 3831 struct fw_tlstx_data_wr { 3832 __be32 op_to_immdlen; 3833 __be32 flowid_len16; 3834 __be32 plen; 3835 __be32 lsodisable_to_flags; 3836 __be32 r5; 3837 __be32 ctxloc_to_exp; 3838 __be16 mfs; 3839 __be16 adjustedplen_pkd; 3840 __be16 expinplenmax_pkd; 3841 __u8 pdusinplenmax_pkd; 3842 __u8 r10; 3843 }; 3844 3845 #define S_FW_TLSTX_DATA_WR_OPCODE 24 3846 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff 3847 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 3848 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 3849 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 3850 3851 #define S_FW_TLSTX_DATA_WR_COMPL 21 3852 #define M_FW_TLSTX_DATA_WR_COMPL 0x1 3853 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 3854 #define G_FW_TLSTX_DATA_WR_COMPL(x) \ 3855 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 3856 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 3857 3858 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0 3859 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 3860 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 3861 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 3862 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 3863 3864 #define S_FW_TLSTX_DATA_WR_FLOWID 8 3865 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 3866 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 3867 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 3868 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 3869 3870 #define S_FW_TLSTX_DATA_WR_LEN16 0 3871 #define M_FW_TLSTX_DATA_WR_LEN16 0xff 3872 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 3873 #define G_FW_TLSTX_DATA_WR_LEN16(x) \ 3874 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 3875 3876 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31 3877 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 3878 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3879 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 3880 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3881 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 3882 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 3883 3884 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 3885 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 3886 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 3887 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 3888 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 3889 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 3890 3891 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 3892 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 3893 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3894 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3895 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3896 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 3897 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3898 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 3899 3900 #define S_FW_TLSTX_DATA_WR_FLAGS 0 3901 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 3902 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 3903 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 3904 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 3905 3906 #define S_FW_TLSTX_DATA_WR_CTXLOC 30 3907 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 3908 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 3909 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 3910 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 3911 3912 #define S_FW_TLSTX_DATA_WR_IVDSGL 29 3913 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 3914 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 3915 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 3916 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 3917 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 3918 3919 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24 3920 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 3921 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 3922 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 3923 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 3924 3925 #define S_FW_TLSTX_DATA_WR_NUMIVS 14 3926 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 3927 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 3928 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 3929 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 3930 3931 #define S_FW_TLSTX_DATA_WR_EXP 0 3932 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff 3933 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 3934 #define G_FW_TLSTX_DATA_WR_EXP(x) \ 3935 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 3936 3937 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 3938 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 3939 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3940 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3941 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3942 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 3943 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3944 3945 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 3946 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 3947 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3948 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3949 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3950 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 3951 M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3952 3953 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 3954 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 3955 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3956 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3957 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3958 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 3959 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3960 3961 struct fw_crypto_lookaside_wr { 3962 __be32 op_to_cctx_size; 3963 __be32 len16_pkd; 3964 __be32 session_id; 3965 __be32 rx_chid_to_rx_q_id; 3966 __be32 key_addr; 3967 __be32 pld_size_hash_size; 3968 __be64 cookie; 3969 }; 3970 3971 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 3972 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 3973 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3974 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3975 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3976 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 3977 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3978 3979 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 3980 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 3981 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3982 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3983 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3984 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 3985 M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3986 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 3987 3988 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 3989 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 3990 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3991 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3992 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3993 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 3994 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3995 3996 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 3997 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 3998 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3999 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 4000 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 4001 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 4002 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 4003 4004 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 4005 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 4006 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4007 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4008 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4009 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 4010 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4011 4012 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 4013 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 4014 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4015 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4016 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4017 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 4018 M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4019 4020 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 4021 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 4022 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4023 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4024 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4025 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 4026 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4027 4028 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 4029 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 4030 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4031 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 4032 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4033 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 4034 4035 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 4036 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 4037 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4038 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4039 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4040 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 4041 M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4042 4043 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 4044 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 4045 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4046 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 4047 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4048 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 4049 4050 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 4051 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 4052 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4053 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4054 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4055 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 4056 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4057 4058 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 4059 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 4060 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4061 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4062 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4063 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 4064 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4065 4066 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 4067 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 4068 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4069 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4070 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4071 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 4072 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4073 4074 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 4075 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 4076 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4077 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4078 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4079 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 4080 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4081 4082 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 4083 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 4084 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4085 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4086 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4087 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 4088 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 4089 4090 struct fw_tls_tunnel_ofld_wr { 4091 __be32 op_compl; 4092 __be32 flowid_len16; 4093 __be32 plen; 4094 __be32 r4; 4095 }; 4096 4097 /****************************************************************************** 4098 * C O M M A N D s 4099 *********************/ 4100 4101 /* 4102 * The maximum length of time, in miliseconds, that we expect any firmware 4103 * command to take to execute and return a reply to the host. The RESET 4104 * and INITIALIZE commands can take a fair amount of time to execute but 4105 * most execute in far less time than this maximum. This constant is used 4106 * by host software to determine how long to wait for a firmware command 4107 * reply before declaring the firmware as dead/unreachable ... 4108 */ 4109 #define FW_CMD_MAX_TIMEOUT 10000 4110 4111 /* 4112 * If a host driver does a HELLO and discovers that there's already a MASTER 4113 * selected, we may have to wait for that MASTER to finish issuing RESET, 4114 * configuration and INITIALIZE commands. Also, there's a possibility that 4115 * our own HELLO may get lost if it happens right as the MASTER is issuign a 4116 * RESET command, so we need to be willing to make a few retries of our HELLO. 4117 */ 4118 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 4119 #define FW_CMD_HELLO_RETRIES 3 4120 4121 enum fw_cmd_opcodes { 4122 FW_LDST_CMD = 0x01, 4123 FW_RESET_CMD = 0x03, 4124 FW_HELLO_CMD = 0x04, 4125 FW_BYE_CMD = 0x05, 4126 FW_INITIALIZE_CMD = 0x06, 4127 FW_CAPS_CONFIG_CMD = 0x07, 4128 FW_PARAMS_CMD = 0x08, 4129 FW_PFVF_CMD = 0x09, 4130 FW_IQ_CMD = 0x10, 4131 FW_EQ_MNGT_CMD = 0x11, 4132 FW_EQ_ETH_CMD = 0x12, 4133 FW_EQ_CTRL_CMD = 0x13, 4134 FW_EQ_OFLD_CMD = 0x21, 4135 FW_VI_CMD = 0x14, 4136 FW_VI_MAC_CMD = 0x15, 4137 FW_VI_RXMODE_CMD = 0x16, 4138 FW_VI_ENABLE_CMD = 0x17, 4139 FW_VI_STATS_CMD = 0x1a, 4140 FW_ACL_MAC_CMD = 0x18, 4141 FW_ACL_VLAN_CMD = 0x19, 4142 FW_PORT_CMD = 0x1b, 4143 FW_PORT_STATS_CMD = 0x1c, 4144 FW_PORT_LB_STATS_CMD = 0x1d, 4145 FW_PORT_TRACE_CMD = 0x1e, 4146 FW_PORT_TRACE_MMAP_CMD = 0x1f, 4147 FW_RSS_IND_TBL_CMD = 0x20, 4148 FW_RSS_GLB_CONFIG_CMD = 0x22, 4149 FW_RSS_VI_CONFIG_CMD = 0x23, 4150 FW_SCHED_CMD = 0x24, 4151 FW_DEVLOG_CMD = 0x25, 4152 FW_WATCHDOG_CMD = 0x27, 4153 FW_CLIP_CMD = 0x28, 4154 FW_CLIP2_CMD = 0x29, 4155 FW_CHNET_IFACE_CMD = 0x26, 4156 FW_FCOE_RES_INFO_CMD = 0x31, 4157 FW_FCOE_LINK_CMD = 0x32, 4158 FW_FCOE_VNP_CMD = 0x33, 4159 FW_FCOE_SPARAMS_CMD = 0x35, 4160 FW_FCOE_STATS_CMD = 0x37, 4161 FW_FCOE_FCF_CMD = 0x38, 4162 FW_DCB_IEEE_CMD = 0x3a, 4163 FW_DIAG_CMD = 0x3d, 4164 FW_PTP_CMD = 0x3e, 4165 FW_HMA_CMD = 0x3f, 4166 FW_LASTC2E_CMD = 0x40, 4167 FW_ERROR_CMD = 0x80, 4168 FW_DEBUG_CMD = 0x81, 4169 }; 4170 4171 enum fw_cmd_cap { 4172 FW_CMD_CAP_PF = 0x01, 4173 FW_CMD_CAP_DMAQ = 0x02, 4174 FW_CMD_CAP_PORT = 0x04, 4175 FW_CMD_CAP_PORTPROMISC = 0x08, 4176 FW_CMD_CAP_PORTSTATS = 0x10, 4177 FW_CMD_CAP_VF = 0x80, 4178 }; 4179 4180 /* 4181 * Generic command header flit0 4182 */ 4183 struct fw_cmd_hdr { 4184 __be32 hi; 4185 __be32 lo; 4186 }; 4187 4188 #define S_FW_CMD_OP 24 4189 #define M_FW_CMD_OP 0xff 4190 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 4191 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 4192 4193 #define S_FW_CMD_REQUEST 23 4194 #define M_FW_CMD_REQUEST 0x1 4195 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 4196 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 4197 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 4198 4199 #define S_FW_CMD_READ 22 4200 #define M_FW_CMD_READ 0x1 4201 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 4202 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 4203 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 4204 4205 #define S_FW_CMD_WRITE 21 4206 #define M_FW_CMD_WRITE 0x1 4207 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 4208 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 4209 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 4210 4211 #define S_FW_CMD_EXEC 20 4212 #define M_FW_CMD_EXEC 0x1 4213 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 4214 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 4215 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 4216 4217 #define S_FW_CMD_RAMASK 20 4218 #define M_FW_CMD_RAMASK 0xf 4219 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 4220 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 4221 4222 #define S_FW_CMD_RETVAL 8 4223 #define M_FW_CMD_RETVAL 0xff 4224 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 4225 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 4226 4227 #define S_FW_CMD_LEN16 0 4228 #define M_FW_CMD_LEN16 0xff 4229 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 4230 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 4231 4232 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 4233 4234 /* 4235 * address spaces 4236 */ 4237 enum fw_ldst_addrspc { 4238 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 4239 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 4240 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 4241 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 4242 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 4243 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 4244 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 4245 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 4246 FW_LDST_ADDRSPC_MDIO = 0x0018, 4247 FW_LDST_ADDRSPC_MPS = 0x0020, 4248 FW_LDST_ADDRSPC_FUNC = 0x0028, 4249 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 4250 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 4251 FW_LDST_ADDRSPC_LE = 0x0030, 4252 FW_LDST_ADDRSPC_I2C = 0x0038, 4253 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 4254 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 4255 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 4256 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 4257 }; 4258 4259 /* 4260 * MDIO VSC8634 register access control field 4261 */ 4262 enum fw_ldst_mdio_vsc8634_aid { 4263 FW_LDST_MDIO_VS_STANDARD, 4264 FW_LDST_MDIO_VS_EXTENDED, 4265 FW_LDST_MDIO_VS_GPIO 4266 }; 4267 4268 enum fw_ldst_mps_fid { 4269 FW_LDST_MPS_ATRB, 4270 FW_LDST_MPS_RPLC 4271 }; 4272 4273 enum fw_ldst_func_access_ctl { 4274 FW_LDST_FUNC_ACC_CTL_VIID, 4275 FW_LDST_FUNC_ACC_CTL_FID 4276 }; 4277 4278 enum fw_ldst_func_mod_index { 4279 FW_LDST_FUNC_MPS 4280 }; 4281 4282 struct fw_ldst_cmd { 4283 __be32 op_to_addrspace; 4284 __be32 cycles_to_len16; 4285 union fw_ldst { 4286 struct fw_ldst_addrval { 4287 __be32 addr; 4288 __be32 val; 4289 } addrval; 4290 struct fw_ldst_idctxt { 4291 __be32 physid; 4292 __be32 msg_ctxtflush; 4293 __be32 ctxt_data7; 4294 __be32 ctxt_data6; 4295 __be32 ctxt_data5; 4296 __be32 ctxt_data4; 4297 __be32 ctxt_data3; 4298 __be32 ctxt_data2; 4299 __be32 ctxt_data1; 4300 __be32 ctxt_data0; 4301 } idctxt; 4302 struct fw_ldst_mdio { 4303 __be16 paddr_mmd; 4304 __be16 raddr; 4305 __be16 vctl; 4306 __be16 rval; 4307 } mdio; 4308 struct fw_ldst_cim_rq { 4309 __u8 req_first64[8]; 4310 __u8 req_second64[8]; 4311 __u8 resp_first64[8]; 4312 __u8 resp_second64[8]; 4313 __be32 r3[2]; 4314 } cim_rq; 4315 union fw_ldst_mps { 4316 struct fw_ldst_mps_rplc { 4317 __be16 fid_idx; 4318 __be16 rplcpf_pkd; 4319 __be32 rplc255_224; 4320 __be32 rplc223_192; 4321 __be32 rplc191_160; 4322 __be32 rplc159_128; 4323 __be32 rplc127_96; 4324 __be32 rplc95_64; 4325 __be32 rplc63_32; 4326 __be32 rplc31_0; 4327 } rplc; 4328 struct fw_ldst_mps_atrb { 4329 __be16 fid_mpsid; 4330 __be16 r2[3]; 4331 __be32 r3[2]; 4332 __be32 r4; 4333 __be32 atrb; 4334 __be16 vlan[16]; 4335 } atrb; 4336 } mps; 4337 struct fw_ldst_func { 4338 __u8 access_ctl; 4339 __u8 mod_index; 4340 __be16 ctl_id; 4341 __be32 offset; 4342 __be64 data0; 4343 __be64 data1; 4344 } func; 4345 struct fw_ldst_pcie { 4346 __u8 ctrl_to_fn; 4347 __u8 bnum; 4348 __u8 r; 4349 __u8 ext_r; 4350 __u8 select_naccess; 4351 __u8 pcie_fn; 4352 __be16 nset_pkd; 4353 __be32 data[12]; 4354 } pcie; 4355 struct fw_ldst_i2c_deprecated { 4356 __u8 pid_pkd; 4357 __u8 base; 4358 __u8 boffset; 4359 __u8 data; 4360 __be32 r9; 4361 } i2c_deprecated; 4362 struct fw_ldst_i2c { 4363 __u8 pid; 4364 __u8 did; 4365 __u8 boffset; 4366 __u8 blen; 4367 __be32 r9; 4368 __u8 data[48]; 4369 } i2c; 4370 struct fw_ldst_le { 4371 __be32 index; 4372 __be32 r9; 4373 __u8 val[33]; 4374 __u8 r11[7]; 4375 } le; 4376 } u; 4377 }; 4378 4379 #define S_FW_LDST_CMD_ADDRSPACE 0 4380 #define M_FW_LDST_CMD_ADDRSPACE 0xff 4381 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 4382 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 4383 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 4384 4385 #define S_FW_LDST_CMD_CYCLES 16 4386 #define M_FW_LDST_CMD_CYCLES 0xffff 4387 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 4388 #define G_FW_LDST_CMD_CYCLES(x) \ 4389 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 4390 4391 #define S_FW_LDST_CMD_MSG 31 4392 #define M_FW_LDST_CMD_MSG 0x1 4393 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 4394 #define G_FW_LDST_CMD_MSG(x) \ 4395 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 4396 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 4397 4398 #define S_FW_LDST_CMD_CTXTFLUSH 30 4399 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 4400 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 4401 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 4402 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 4403 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 4404 4405 #define S_FW_LDST_CMD_PADDR 8 4406 #define M_FW_LDST_CMD_PADDR 0x1f 4407 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 4408 #define G_FW_LDST_CMD_PADDR(x) \ 4409 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 4410 4411 #define S_FW_LDST_CMD_MMD 0 4412 #define M_FW_LDST_CMD_MMD 0x1f 4413 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 4414 #define G_FW_LDST_CMD_MMD(x) \ 4415 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 4416 4417 #define S_FW_LDST_CMD_FID 15 4418 #define M_FW_LDST_CMD_FID 0x1 4419 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 4420 #define G_FW_LDST_CMD_FID(x) \ 4421 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 4422 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 4423 4424 #define S_FW_LDST_CMD_IDX 0 4425 #define M_FW_LDST_CMD_IDX 0x7fff 4426 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 4427 #define G_FW_LDST_CMD_IDX(x) \ 4428 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 4429 4430 #define S_FW_LDST_CMD_RPLCPF 0 4431 #define M_FW_LDST_CMD_RPLCPF 0xff 4432 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 4433 #define G_FW_LDST_CMD_RPLCPF(x) \ 4434 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 4435 4436 #define S_FW_LDST_CMD_MPSID 0 4437 #define M_FW_LDST_CMD_MPSID 0x7fff 4438 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 4439 #define G_FW_LDST_CMD_MPSID(x) \ 4440 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 4441 4442 #define S_FW_LDST_CMD_CTRL 7 4443 #define M_FW_LDST_CMD_CTRL 0x1 4444 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 4445 #define G_FW_LDST_CMD_CTRL(x) \ 4446 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 4447 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 4448 4449 #define S_FW_LDST_CMD_LC 4 4450 #define M_FW_LDST_CMD_LC 0x1 4451 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 4452 #define G_FW_LDST_CMD_LC(x) \ 4453 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 4454 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 4455 4456 #define S_FW_LDST_CMD_AI 3 4457 #define M_FW_LDST_CMD_AI 0x1 4458 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 4459 #define G_FW_LDST_CMD_AI(x) \ 4460 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 4461 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 4462 4463 #define S_FW_LDST_CMD_FN 0 4464 #define M_FW_LDST_CMD_FN 0x7 4465 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 4466 #define G_FW_LDST_CMD_FN(x) \ 4467 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 4468 4469 #define S_FW_LDST_CMD_SELECT 4 4470 #define M_FW_LDST_CMD_SELECT 0xf 4471 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 4472 #define G_FW_LDST_CMD_SELECT(x) \ 4473 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 4474 4475 #define S_FW_LDST_CMD_NACCESS 0 4476 #define M_FW_LDST_CMD_NACCESS 0xf 4477 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 4478 #define G_FW_LDST_CMD_NACCESS(x) \ 4479 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 4480 4481 #define S_FW_LDST_CMD_NSET 14 4482 #define M_FW_LDST_CMD_NSET 0x3 4483 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 4484 #define G_FW_LDST_CMD_NSET(x) \ 4485 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 4486 4487 #define S_FW_LDST_CMD_PID 6 4488 #define M_FW_LDST_CMD_PID 0x3 4489 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 4490 #define G_FW_LDST_CMD_PID(x) \ 4491 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 4492 4493 struct fw_reset_cmd { 4494 __be32 op_to_write; 4495 __be32 retval_len16; 4496 __be32 val; 4497 __be32 halt_pkd; 4498 }; 4499 4500 #define S_FW_RESET_CMD_HALT 31 4501 #define M_FW_RESET_CMD_HALT 0x1 4502 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 4503 #define G_FW_RESET_CMD_HALT(x) \ 4504 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 4505 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 4506 4507 enum { 4508 FW_HELLO_CMD_STAGE_OS = 0, 4509 FW_HELLO_CMD_STAGE_PREOS0 = 1, 4510 FW_HELLO_CMD_STAGE_PREOS1 = 2, 4511 FW_HELLO_CMD_STAGE_POSTOS = 3, 4512 }; 4513 4514 struct fw_hello_cmd { 4515 __be32 op_to_write; 4516 __be32 retval_len16; 4517 __be32 err_to_clearinit; 4518 __be32 fwrev; 4519 }; 4520 4521 #define S_FW_HELLO_CMD_ERR 31 4522 #define M_FW_HELLO_CMD_ERR 0x1 4523 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 4524 #define G_FW_HELLO_CMD_ERR(x) \ 4525 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 4526 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 4527 4528 #define S_FW_HELLO_CMD_INIT 30 4529 #define M_FW_HELLO_CMD_INIT 0x1 4530 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 4531 #define G_FW_HELLO_CMD_INIT(x) \ 4532 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 4533 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 4534 4535 #define S_FW_HELLO_CMD_MASTERDIS 29 4536 #define M_FW_HELLO_CMD_MASTERDIS 0x1 4537 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 4538 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 4539 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 4540 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 4541 4542 #define S_FW_HELLO_CMD_MASTERFORCE 28 4543 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 4544 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 4545 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 4546 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 4547 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 4548 4549 #define S_FW_HELLO_CMD_MBMASTER 24 4550 #define M_FW_HELLO_CMD_MBMASTER 0xf 4551 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 4552 #define G_FW_HELLO_CMD_MBMASTER(x) \ 4553 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 4554 4555 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 4556 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 4557 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 4558 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 4559 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 4560 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 4561 4562 #define S_FW_HELLO_CMD_MBASYNCNOT 20 4563 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 4564 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 4565 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 4566 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 4567 4568 #define S_FW_HELLO_CMD_STAGE 17 4569 #define M_FW_HELLO_CMD_STAGE 0x7 4570 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 4571 #define G_FW_HELLO_CMD_STAGE(x) \ 4572 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 4573 4574 #define S_FW_HELLO_CMD_CLEARINIT 16 4575 #define M_FW_HELLO_CMD_CLEARINIT 0x1 4576 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 4577 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 4578 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 4579 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 4580 4581 struct fw_bye_cmd { 4582 __be32 op_to_write; 4583 __be32 retval_len16; 4584 __be64 r3; 4585 }; 4586 4587 struct fw_initialize_cmd { 4588 __be32 op_to_write; 4589 __be32 retval_len16; 4590 __be64 r3; 4591 }; 4592 4593 enum fw_caps_config_hm { 4594 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 4595 FW_CAPS_CONFIG_HM_PL = 0x00000002, 4596 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 4597 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 4598 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 4599 FW_CAPS_CONFIG_HM_TP = 0x00000020, 4600 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 4601 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 4602 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 4603 FW_CAPS_CONFIG_HM_MC = 0x00000200, 4604 FW_CAPS_CONFIG_HM_LE = 0x00000400, 4605 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 4606 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 4607 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 4608 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 4609 FW_CAPS_CONFIG_HM_MI = 0x00008000, 4610 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 4611 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 4612 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 4613 FW_CAPS_CONFIG_HM_MA = 0x00080000, 4614 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 4615 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 4616 FW_CAPS_CONFIG_HM_UART = 0x00400000, 4617 FW_CAPS_CONFIG_HM_SF = 0x00800000, 4618 }; 4619 4620 /* 4621 * The VF Register Map. 4622 * 4623 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 4624 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 4625 * the Slice to Module Map Table (see below) in the Physical Function Register 4626 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 4627 * and Offset registers in the PF Register Map. The MBDATA base address is 4628 * quite constrained as it determines the Mailbox Data addresses for both PFs 4629 * and VFs, and therefore must fit in both the VF and PF Register Maps without 4630 * overlapping other registers. 4631 */ 4632 #define FW_T4VF_SGE_BASE_ADDR 0x0000 4633 #define FW_T4VF_MPS_BASE_ADDR 0x0100 4634 #define FW_T4VF_PL_BASE_ADDR 0x0200 4635 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4636 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4637 #define FW_T4VF_CIM_BASE_ADDR 0x0300 4638 4639 #define FW_T4VF_REGMAP_START 0x0000 4640 #define FW_T4VF_REGMAP_SIZE 0x0400 4641 4642 enum fw_caps_config_nbm { 4643 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 4644 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 4645 }; 4646 4647 enum fw_caps_config_link { 4648 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 4649 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 4650 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 4651 }; 4652 4653 enum fw_caps_config_switch { 4654 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 4655 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 4656 }; 4657 4658 enum fw_caps_config_nic { 4659 FW_CAPS_CONFIG_NIC = 0x00000001, 4660 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 4661 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 4662 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 4663 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4664 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4665 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 4666 }; 4667 4668 enum fw_caps_config_toe { 4669 FW_CAPS_CONFIG_TOE = 0x00000001, 4670 }; 4671 4672 enum fw_caps_config_rdma { 4673 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 4674 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 4675 }; 4676 4677 enum fw_caps_config_iscsi { 4678 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 4679 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 4680 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 4681 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 4682 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 4683 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4684 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4685 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4686 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4687 }; 4688 4689 enum fw_caps_config_crypto { 4690 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 4691 FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 4692 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004, 4693 }; 4694 4695 enum fw_caps_config_fcoe { 4696 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 4697 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 4698 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4699 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4700 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 4701 }; 4702 4703 enum fw_memtype_cf { 4704 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4705 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4706 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4707 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4708 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4709 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 4710 }; 4711 4712 struct fw_caps_config_cmd { 4713 __be32 op_to_write; 4714 __be32 cfvalid_to_len16; 4715 __be32 r2; 4716 __be32 hwmbitmap; 4717 __be16 nbmcaps; 4718 __be16 linkcaps; 4719 __be16 switchcaps; 4720 __be16 r3; 4721 __be16 niccaps; 4722 __be16 toecaps; 4723 __be16 rdmacaps; 4724 __be16 cryptocaps; 4725 __be16 iscsicaps; 4726 __be16 fcoecaps; 4727 __be32 cfcsum; 4728 __be32 finiver; 4729 __be32 finicsum; 4730 }; 4731 4732 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4733 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4734 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4735 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4736 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4737 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4738 4739 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4740 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4741 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4742 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4743 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4744 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4745 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4746 4747 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4748 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4749 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4750 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4751 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4752 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4753 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4754 4755 /* 4756 * params command mnemonics 4757 */ 4758 enum fw_params_mnem { 4759 FW_PARAMS_MNEM_DEV = 1, /* device params */ 4760 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 4761 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 4762 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4763 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 4764 FW_PARAMS_MNEM_LAST 4765 }; 4766 4767 /* 4768 * device parameters 4769 */ 4770 #define S_FW_PARAMS_PARAM_FILTER_MODE 16 4771 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff 4772 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \ 4773 ((x) << S_FW_PARAMS_PARAM_FILTER_MODE) 4774 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \ 4775 (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \ 4776 M_FW_PARAMS_PARAM_FILTER_MODE) 4777 4778 #define S_FW_PARAMS_PARAM_FILTER_MASK 0 4779 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff 4780 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \ 4781 ((x) << S_FW_PARAMS_PARAM_FILTER_MASK) 4782 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \ 4783 (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \ 4784 M_FW_PARAMS_PARAM_FILTER_MASK) 4785 4786 enum fw_params_param_dev { 4787 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 4788 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4789 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4790 * allocated by the device's 4791 * Lookup Engine 4792 */ 4793 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 4794 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 4795 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 4796 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 4797 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 4798 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 4799 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 4800 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4801 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4802 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4803 FW_PARAMS_PARAM_DEV_CF = 0x0D, 4804 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4805 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4806 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4807 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4808 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4809 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4810 */ 4811 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4812 */ 4813 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4814 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4815 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4816 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4817 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4818 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 4819 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 4820 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 4821 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 4822 4823 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 4824 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 4825 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 4826 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 4827 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22, 4828 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 4829 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 4830 FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25, 4831 FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26, 4832 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 4833 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, 4834 FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29, 4835 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A, 4836 FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B, 4837 FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C, 4838 FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D, 4839 FW_PARAMS_PARAM_DEV_FILTER = 0x2E, 4840 FW_PARAMS_PARAM_DEV_CLIP2_CMD = 0x2F, 4841 }; 4842 4843 /* 4844 * dev bypass parameters; actions and modes 4845 */ 4846 enum fw_params_param_dev_bypass { 4847 4848 /* actions 4849 */ 4850 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4851 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4852 4853 /* modes 4854 */ 4855 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4856 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4857 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4858 }; 4859 4860 enum fw_params_param_dev_phyfw { 4861 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4862 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4863 }; 4864 4865 enum fw_params_param_dev_diag { 4866 FW_PARAM_DEV_DIAG_TMP = 0x00, 4867 FW_PARAM_DEV_DIAG_VDD = 0x01, 4868 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 4869 FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR = 0x03, 4870 }; 4871 4872 enum fw_params_param_dev_filter{ 4873 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, 4874 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, 4875 }; 4876 4877 enum fw_params_param_dev_fwcache { 4878 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4879 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 4880 }; 4881 4882 /* 4883 * physical and virtual function parameters 4884 */ 4885 enum fw_params_param_pfvf { 4886 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 4887 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 4888 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 4889 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 4890 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 4891 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 4892 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 4893 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 4894 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 4895 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 4896 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 4897 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 4898 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 4899 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 4900 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 4901 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 4902 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 4903 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 4904 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 4905 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 4906 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 4907 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 4908 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 4909 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 4910 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4911 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4912 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 4913 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 4914 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 4915 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 4916 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 4917 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 4918 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 4919 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 4920 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 4921 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 4922 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 4923 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 4924 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 4925 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4926 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4927 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4928 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4929 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4930 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4931 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4932 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4933 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4934 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 4935 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 4936 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 4937 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 4938 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 4939 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, 4940 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E, 4941 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F, 4942 FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40, 4943 }; 4944 4945 /* 4946 * virtual link state as seen by the specified VF 4947 */ 4948 enum vf_link_states { 4949 VF_LINK_STATE_AUTO = 0x00, 4950 VF_LINK_STATE_ENABLE = 0x01, 4951 VF_LINK_STATE_DISABLE = 0x02, 4952 }; 4953 4954 /* 4955 * dma queue parameters 4956 */ 4957 enum fw_params_param_dmaq { 4958 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 4959 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4960 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4961 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 4962 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 4963 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 4964 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4965 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4966 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4967 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15, 4968 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4969 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 4970 }; 4971 4972 /* 4973 * chnet parameters 4974 */ 4975 enum fw_params_param_chnet { 4976 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4977 }; 4978 4979 enum fw_params_param_chnet_flags { 4980 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4981 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4982 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4983 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6_SLAAC = 0x8, 4984 }; 4985 4986 #define S_FW_PARAMS_MNEM 24 4987 #define M_FW_PARAMS_MNEM 0xff 4988 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 4989 #define G_FW_PARAMS_MNEM(x) \ 4990 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 4991 4992 #define S_FW_PARAMS_PARAM_X 16 4993 #define M_FW_PARAMS_PARAM_X 0xff 4994 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 4995 #define G_FW_PARAMS_PARAM_X(x) \ 4996 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 4997 4998 #define S_FW_PARAMS_PARAM_Y 8 4999 #define M_FW_PARAMS_PARAM_Y 0xff 5000 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 5001 #define G_FW_PARAMS_PARAM_Y(x) \ 5002 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 5003 5004 #define S_FW_PARAMS_PARAM_Z 0 5005 #define M_FW_PARAMS_PARAM_Z 0xff 5006 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 5007 #define G_FW_PARAMS_PARAM_Z(x) \ 5008 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 5009 5010 #define S_FW_PARAMS_PARAM_XYZ 0 5011 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 5012 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 5013 #define G_FW_PARAMS_PARAM_XYZ(x) \ 5014 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 5015 5016 #define S_FW_PARAMS_PARAM_YZ 0 5017 #define M_FW_PARAMS_PARAM_YZ 0xffff 5018 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 5019 #define G_FW_PARAMS_PARAM_YZ(x) \ 5020 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 5021 5022 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 5023 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 5024 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 5025 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 5026 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 5027 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 5028 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 5029 5030 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 5031 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 5032 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 5033 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 5034 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 5035 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 5036 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 5037 5038 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 5039 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 5040 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 5041 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 5042 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 5043 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 5044 5045 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 5046 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 5047 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 5048 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 5049 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 5050 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 5051 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 5052 5053 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 5054 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 5055 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 5056 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 5057 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 5058 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 5059 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 5060 5061 struct fw_params_cmd { 5062 __be32 op_to_vfn; 5063 __be32 retval_len16; 5064 struct fw_params_param { 5065 __be32 mnem; 5066 __be32 val; 5067 } param[7]; 5068 }; 5069 5070 #define S_FW_PARAMS_CMD_PFN 8 5071 #define M_FW_PARAMS_CMD_PFN 0x7 5072 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 5073 #define G_FW_PARAMS_CMD_PFN(x) \ 5074 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 5075 5076 #define S_FW_PARAMS_CMD_VFN 0 5077 #define M_FW_PARAMS_CMD_VFN 0xff 5078 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 5079 #define G_FW_PARAMS_CMD_VFN(x) \ 5080 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 5081 5082 struct fw_pfvf_cmd { 5083 __be32 op_to_vfn; 5084 __be32 retval_len16; 5085 __be32 niqflint_niq; 5086 __be32 type_to_neq; 5087 __be32 tc_to_nexactf; 5088 __be32 r_caps_to_nethctrl; 5089 __be16 nricq; 5090 __be16 nriqp; 5091 __be32 r4; 5092 }; 5093 5094 #define S_FW_PFVF_CMD_PFN 8 5095 #define M_FW_PFVF_CMD_PFN 0x7 5096 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 5097 #define G_FW_PFVF_CMD_PFN(x) \ 5098 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 5099 5100 #define S_FW_PFVF_CMD_VFN 0 5101 #define M_FW_PFVF_CMD_VFN 0xff 5102 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 5103 #define G_FW_PFVF_CMD_VFN(x) \ 5104 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 5105 5106 #define S_FW_PFVF_CMD_NIQFLINT 20 5107 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 5108 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 5109 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 5110 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 5111 5112 #define S_FW_PFVF_CMD_NIQ 0 5113 #define M_FW_PFVF_CMD_NIQ 0xfffff 5114 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 5115 #define G_FW_PFVF_CMD_NIQ(x) \ 5116 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 5117 5118 #define S_FW_PFVF_CMD_TYPE 31 5119 #define M_FW_PFVF_CMD_TYPE 0x1 5120 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 5121 #define G_FW_PFVF_CMD_TYPE(x) \ 5122 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 5123 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 5124 5125 #define S_FW_PFVF_CMD_CMASK 24 5126 #define M_FW_PFVF_CMD_CMASK 0xf 5127 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 5128 #define G_FW_PFVF_CMD_CMASK(x) \ 5129 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 5130 5131 #define S_FW_PFVF_CMD_PMASK 20 5132 #define M_FW_PFVF_CMD_PMASK 0xf 5133 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 5134 #define G_FW_PFVF_CMD_PMASK(x) \ 5135 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 5136 5137 #define S_FW_PFVF_CMD_NEQ 0 5138 #define M_FW_PFVF_CMD_NEQ 0xfffff 5139 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 5140 #define G_FW_PFVF_CMD_NEQ(x) \ 5141 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 5142 5143 #define S_FW_PFVF_CMD_TC 24 5144 #define M_FW_PFVF_CMD_TC 0xff 5145 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 5146 #define G_FW_PFVF_CMD_TC(x) \ 5147 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 5148 5149 #define S_FW_PFVF_CMD_NVI 16 5150 #define M_FW_PFVF_CMD_NVI 0xff 5151 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 5152 #define G_FW_PFVF_CMD_NVI(x) \ 5153 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 5154 5155 #define S_FW_PFVF_CMD_NEXACTF 0 5156 #define M_FW_PFVF_CMD_NEXACTF 0xffff 5157 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 5158 #define G_FW_PFVF_CMD_NEXACTF(x) \ 5159 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 5160 5161 #define S_FW_PFVF_CMD_R_CAPS 24 5162 #define M_FW_PFVF_CMD_R_CAPS 0xff 5163 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 5164 #define G_FW_PFVF_CMD_R_CAPS(x) \ 5165 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 5166 5167 #define S_FW_PFVF_CMD_WX_CAPS 16 5168 #define M_FW_PFVF_CMD_WX_CAPS 0xff 5169 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 5170 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 5171 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 5172 5173 #define S_FW_PFVF_CMD_NETHCTRL 0 5174 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 5175 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 5176 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 5177 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 5178 5179 /* 5180 * ingress queue type; the first 1K ingress queues can have associated 0, 5181 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 5182 * capabilities 5183 */ 5184 enum fw_iq_type { 5185 FW_IQ_TYPE_FL_INT_CAP, 5186 FW_IQ_TYPE_NO_FL_INT_CAP, 5187 FW_IQ_TYPE_VF_CQ 5188 }; 5189 5190 enum fw_iq_iqtype { 5191 FW_IQ_IQTYPE_OTHER, 5192 FW_IQ_IQTYPE_NIC, 5193 FW_IQ_IQTYPE_OFLD, 5194 }; 5195 5196 struct fw_iq_cmd { 5197 __be32 op_to_vfn; 5198 __be32 alloc_to_len16; 5199 __be16 physiqid; 5200 __be16 iqid; 5201 __be16 fl0id; 5202 __be16 fl1id; 5203 __be32 type_to_iqandstindex; 5204 __be16 iqdroprss_to_iqesize; 5205 __be16 iqsize; 5206 __be64 iqaddr; 5207 __be32 iqns_to_fl0congen; 5208 __be16 fl0dcaen_to_fl0cidxfthresh; 5209 __be16 fl0size; 5210 __be64 fl0addr; 5211 __be32 fl1cngchmap_to_fl1congen; 5212 __be16 fl1dcaen_to_fl1cidxfthresh; 5213 __be16 fl1size; 5214 __be64 fl1addr; 5215 }; 5216 5217 #define S_FW_IQ_CMD_PFN 8 5218 #define M_FW_IQ_CMD_PFN 0x7 5219 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 5220 #define G_FW_IQ_CMD_PFN(x) \ 5221 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 5222 5223 #define S_FW_IQ_CMD_VFN 0 5224 #define M_FW_IQ_CMD_VFN 0xff 5225 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 5226 #define G_FW_IQ_CMD_VFN(x) \ 5227 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 5228 5229 #define S_FW_IQ_CMD_ALLOC 31 5230 #define M_FW_IQ_CMD_ALLOC 0x1 5231 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 5232 #define G_FW_IQ_CMD_ALLOC(x) \ 5233 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 5234 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 5235 5236 #define S_FW_IQ_CMD_FREE 30 5237 #define M_FW_IQ_CMD_FREE 0x1 5238 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 5239 #define G_FW_IQ_CMD_FREE(x) \ 5240 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 5241 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 5242 5243 #define S_FW_IQ_CMD_MODIFY 29 5244 #define M_FW_IQ_CMD_MODIFY 0x1 5245 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 5246 #define G_FW_IQ_CMD_MODIFY(x) \ 5247 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 5248 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 5249 5250 #define S_FW_IQ_CMD_IQSTART 28 5251 #define M_FW_IQ_CMD_IQSTART 0x1 5252 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 5253 #define G_FW_IQ_CMD_IQSTART(x) \ 5254 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 5255 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 5256 5257 #define S_FW_IQ_CMD_IQSTOP 27 5258 #define M_FW_IQ_CMD_IQSTOP 0x1 5259 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 5260 #define G_FW_IQ_CMD_IQSTOP(x) \ 5261 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 5262 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 5263 5264 #define S_FW_IQ_CMD_TYPE 29 5265 #define M_FW_IQ_CMD_TYPE 0x7 5266 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 5267 #define G_FW_IQ_CMD_TYPE(x) \ 5268 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 5269 5270 #define S_FW_IQ_CMD_IQASYNCH 28 5271 #define M_FW_IQ_CMD_IQASYNCH 0x1 5272 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 5273 #define G_FW_IQ_CMD_IQASYNCH(x) \ 5274 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 5275 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 5276 5277 #define S_FW_IQ_CMD_VIID 16 5278 #define M_FW_IQ_CMD_VIID 0xfff 5279 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 5280 #define G_FW_IQ_CMD_VIID(x) \ 5281 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 5282 5283 #define S_FW_IQ_CMD_IQANDST 15 5284 #define M_FW_IQ_CMD_IQANDST 0x1 5285 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 5286 #define G_FW_IQ_CMD_IQANDST(x) \ 5287 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 5288 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 5289 5290 #define S_FW_IQ_CMD_IQANUS 14 5291 #define M_FW_IQ_CMD_IQANUS 0x1 5292 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 5293 #define G_FW_IQ_CMD_IQANUS(x) \ 5294 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 5295 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 5296 5297 #define S_FW_IQ_CMD_IQANUD 12 5298 #define M_FW_IQ_CMD_IQANUD 0x3 5299 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 5300 #define G_FW_IQ_CMD_IQANUD(x) \ 5301 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 5302 5303 #define S_FW_IQ_CMD_IQANDSTINDEX 0 5304 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 5305 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 5306 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 5307 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 5308 5309 #define S_FW_IQ_CMD_IQDROPRSS 15 5310 #define M_FW_IQ_CMD_IQDROPRSS 0x1 5311 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 5312 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 5313 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 5314 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 5315 5316 #define S_FW_IQ_CMD_IQGTSMODE 14 5317 #define M_FW_IQ_CMD_IQGTSMODE 0x1 5318 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 5319 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 5320 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 5321 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 5322 5323 #define S_FW_IQ_CMD_IQPCIECH 12 5324 #define M_FW_IQ_CMD_IQPCIECH 0x3 5325 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 5326 #define G_FW_IQ_CMD_IQPCIECH(x) \ 5327 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 5328 5329 #define S_FW_IQ_CMD_IQDCAEN 11 5330 #define M_FW_IQ_CMD_IQDCAEN 0x1 5331 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 5332 #define G_FW_IQ_CMD_IQDCAEN(x) \ 5333 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 5334 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 5335 5336 #define S_FW_IQ_CMD_IQDCACPU 6 5337 #define M_FW_IQ_CMD_IQDCACPU 0x1f 5338 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 5339 #define G_FW_IQ_CMD_IQDCACPU(x) \ 5340 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 5341 5342 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 5343 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 5344 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 5345 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 5346 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 5347 5348 #define S_FW_IQ_CMD_IQO 3 5349 #define M_FW_IQ_CMD_IQO 0x1 5350 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 5351 #define G_FW_IQ_CMD_IQO(x) \ 5352 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 5353 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 5354 5355 #define S_FW_IQ_CMD_IQCPRIO 2 5356 #define M_FW_IQ_CMD_IQCPRIO 0x1 5357 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 5358 #define G_FW_IQ_CMD_IQCPRIO(x) \ 5359 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 5360 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 5361 5362 #define S_FW_IQ_CMD_IQESIZE 0 5363 #define M_FW_IQ_CMD_IQESIZE 0x3 5364 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 5365 #define G_FW_IQ_CMD_IQESIZE(x) \ 5366 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 5367 5368 #define S_FW_IQ_CMD_IQNS 31 5369 #define M_FW_IQ_CMD_IQNS 0x1 5370 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 5371 #define G_FW_IQ_CMD_IQNS(x) \ 5372 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 5373 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 5374 5375 #define S_FW_IQ_CMD_IQRO 30 5376 #define M_FW_IQ_CMD_IQRO 0x1 5377 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 5378 #define G_FW_IQ_CMD_IQRO(x) \ 5379 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 5380 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 5381 5382 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 5383 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 5384 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 5385 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 5386 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 5387 5388 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 5389 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 5390 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 5391 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 5392 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 5393 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 5394 5395 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 5396 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 5397 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 5398 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 5399 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 5400 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 5401 5402 #define S_FW_IQ_CMD_IQTYPE 24 5403 #define M_FW_IQ_CMD_IQTYPE 0x3 5404 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 5405 #define G_FW_IQ_CMD_IQTYPE(x) \ 5406 (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE) 5407 5408 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 5409 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 5410 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 5411 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 5412 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 5413 5414 #define S_FW_IQ_CMD_FL0CONGDROP 16 5415 #define M_FW_IQ_CMD_FL0CONGDROP 0x1 5416 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 5417 #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 5418 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 5419 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 5420 5421 #define S_FW_IQ_CMD_FL0CACHELOCK 15 5422 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 5423 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 5424 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 5425 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 5426 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 5427 5428 #define S_FW_IQ_CMD_FL0DBP 14 5429 #define M_FW_IQ_CMD_FL0DBP 0x1 5430 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 5431 #define G_FW_IQ_CMD_FL0DBP(x) \ 5432 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 5433 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 5434 5435 #define S_FW_IQ_CMD_FL0DATANS 13 5436 #define M_FW_IQ_CMD_FL0DATANS 0x1 5437 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 5438 #define G_FW_IQ_CMD_FL0DATANS(x) \ 5439 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 5440 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 5441 5442 #define S_FW_IQ_CMD_FL0DATARO 12 5443 #define M_FW_IQ_CMD_FL0DATARO 0x1 5444 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 5445 #define G_FW_IQ_CMD_FL0DATARO(x) \ 5446 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 5447 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 5448 5449 #define S_FW_IQ_CMD_FL0CONGCIF 11 5450 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 5451 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 5452 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 5453 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 5454 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 5455 5456 #define S_FW_IQ_CMD_FL0ONCHIP 10 5457 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 5458 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 5459 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 5460 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 5461 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 5462 5463 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 5464 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 5465 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 5466 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 5467 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 5468 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 5469 5470 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 5471 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 5472 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 5473 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 5474 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 5475 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 5476 5477 #define S_FW_IQ_CMD_FL0FETCHNS 7 5478 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 5479 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 5480 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 5481 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 5482 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 5483 5484 #define S_FW_IQ_CMD_FL0FETCHRO 6 5485 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 5486 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 5487 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 5488 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 5489 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 5490 5491 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 5492 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 5493 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 5494 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 5495 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 5496 5497 #define S_FW_IQ_CMD_FL0CPRIO 3 5498 #define M_FW_IQ_CMD_FL0CPRIO 0x1 5499 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 5500 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 5501 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 5502 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 5503 5504 #define S_FW_IQ_CMD_FL0PADEN 2 5505 #define M_FW_IQ_CMD_FL0PADEN 0x1 5506 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 5507 #define G_FW_IQ_CMD_FL0PADEN(x) \ 5508 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 5509 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 5510 5511 #define S_FW_IQ_CMD_FL0PACKEN 1 5512 #define M_FW_IQ_CMD_FL0PACKEN 0x1 5513 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 5514 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 5515 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 5516 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 5517 5518 #define S_FW_IQ_CMD_FL0CONGEN 0 5519 #define M_FW_IQ_CMD_FL0CONGEN 0x1 5520 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 5521 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 5522 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 5523 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 5524 5525 #define S_FW_IQ_CMD_FL0DCAEN 15 5526 #define M_FW_IQ_CMD_FL0DCAEN 0x1 5527 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 5528 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 5529 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 5530 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 5531 5532 #define S_FW_IQ_CMD_FL0DCACPU 10 5533 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 5534 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 5535 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 5536 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 5537 5538 #define S_FW_IQ_CMD_FL0FBMIN 7 5539 #define M_FW_IQ_CMD_FL0FBMIN 0x7 5540 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 5541 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 5542 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 5543 5544 #define S_FW_IQ_CMD_FL0FBMAX 4 5545 #define M_FW_IQ_CMD_FL0FBMAX 0x7 5546 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 5547 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 5548 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 5549 5550 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 5551 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 5552 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 5553 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 5554 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 5555 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 5556 5557 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 5558 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 5559 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 5560 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 5561 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 5562 5563 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 5564 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 5565 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 5566 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 5567 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 5568 5569 #define S_FW_IQ_CMD_FL1CONGDROP 16 5570 #define M_FW_IQ_CMD_FL1CONGDROP 0x1 5571 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 5572 #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 5573 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 5574 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 5575 5576 #define S_FW_IQ_CMD_FL1CACHELOCK 15 5577 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 5578 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 5579 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 5580 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 5581 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 5582 5583 #define S_FW_IQ_CMD_FL1DBP 14 5584 #define M_FW_IQ_CMD_FL1DBP 0x1 5585 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 5586 #define G_FW_IQ_CMD_FL1DBP(x) \ 5587 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 5588 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 5589 5590 #define S_FW_IQ_CMD_FL1DATANS 13 5591 #define M_FW_IQ_CMD_FL1DATANS 0x1 5592 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 5593 #define G_FW_IQ_CMD_FL1DATANS(x) \ 5594 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 5595 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 5596 5597 #define S_FW_IQ_CMD_FL1DATARO 12 5598 #define M_FW_IQ_CMD_FL1DATARO 0x1 5599 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 5600 #define G_FW_IQ_CMD_FL1DATARO(x) \ 5601 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 5602 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 5603 5604 #define S_FW_IQ_CMD_FL1CONGCIF 11 5605 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 5606 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 5607 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 5608 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 5609 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 5610 5611 #define S_FW_IQ_CMD_FL1ONCHIP 10 5612 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 5613 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 5614 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 5615 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 5616 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 5617 5618 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 5619 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 5620 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 5621 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 5622 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 5623 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 5624 5625 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 5626 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 5627 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 5628 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 5629 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 5630 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 5631 5632 #define S_FW_IQ_CMD_FL1FETCHNS 7 5633 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 5634 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 5635 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 5636 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 5637 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 5638 5639 #define S_FW_IQ_CMD_FL1FETCHRO 6 5640 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 5641 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 5642 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 5643 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 5644 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 5645 5646 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 5647 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 5648 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 5649 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 5650 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 5651 5652 #define S_FW_IQ_CMD_FL1CPRIO 3 5653 #define M_FW_IQ_CMD_FL1CPRIO 0x1 5654 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 5655 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 5656 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 5657 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 5658 5659 #define S_FW_IQ_CMD_FL1PADEN 2 5660 #define M_FW_IQ_CMD_FL1PADEN 0x1 5661 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 5662 #define G_FW_IQ_CMD_FL1PADEN(x) \ 5663 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 5664 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 5665 5666 #define S_FW_IQ_CMD_FL1PACKEN 1 5667 #define M_FW_IQ_CMD_FL1PACKEN 0x1 5668 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 5669 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 5670 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 5671 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 5672 5673 #define S_FW_IQ_CMD_FL1CONGEN 0 5674 #define M_FW_IQ_CMD_FL1CONGEN 0x1 5675 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 5676 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 5677 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 5678 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 5679 5680 #define S_FW_IQ_CMD_FL1DCAEN 15 5681 #define M_FW_IQ_CMD_FL1DCAEN 0x1 5682 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 5683 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 5684 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 5685 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 5686 5687 #define S_FW_IQ_CMD_FL1DCACPU 10 5688 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 5689 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 5690 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 5691 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 5692 5693 #define S_FW_IQ_CMD_FL1FBMIN 7 5694 #define M_FW_IQ_CMD_FL1FBMIN 0x7 5695 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 5696 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 5697 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 5698 5699 #define S_FW_IQ_CMD_FL1FBMAX 4 5700 #define M_FW_IQ_CMD_FL1FBMAX 0x7 5701 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 5702 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 5703 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 5704 5705 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 5706 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 5707 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 5708 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 5709 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 5710 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 5711 5712 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 5713 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 5714 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 5715 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 5716 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 5717 5718 struct fw_eq_mngt_cmd { 5719 __be32 op_to_vfn; 5720 __be32 alloc_to_len16; 5721 __be32 cmpliqid_eqid; 5722 __be32 physeqid_pkd; 5723 __be32 fetchszm_to_iqid; 5724 __be32 dcaen_to_eqsize; 5725 __be64 eqaddr; 5726 }; 5727 5728 #define S_FW_EQ_MNGT_CMD_PFN 8 5729 #define M_FW_EQ_MNGT_CMD_PFN 0x7 5730 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5731 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 5732 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5733 5734 #define S_FW_EQ_MNGT_CMD_VFN 0 5735 #define M_FW_EQ_MNGT_CMD_VFN 0xff 5736 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5737 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 5738 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5739 5740 #define S_FW_EQ_MNGT_CMD_ALLOC 31 5741 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5742 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5743 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5744 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5745 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5746 5747 #define S_FW_EQ_MNGT_CMD_FREE 30 5748 #define M_FW_EQ_MNGT_CMD_FREE 0x1 5749 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5750 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 5751 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5752 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5753 5754 #define S_FW_EQ_MNGT_CMD_MODIFY 29 5755 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5756 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5757 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5758 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5759 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5760 5761 #define S_FW_EQ_MNGT_CMD_EQSTART 28 5762 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5763 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5764 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5765 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5766 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5767 5768 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 5769 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5770 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5771 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5772 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5773 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5774 5775 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5776 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5777 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5778 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5779 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5780 5781 #define S_FW_EQ_MNGT_CMD_EQID 0 5782 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5783 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5784 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 5785 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5786 5787 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5788 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5789 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5790 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5791 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5792 5793 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5794 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5795 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5796 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5797 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5798 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5799 5800 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5801 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5802 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5803 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5804 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5805 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5806 5807 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5808 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5809 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5810 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5811 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5812 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5813 5814 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 5815 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5816 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5817 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5818 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5819 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5820 5821 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 5822 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5823 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5824 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5825 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5826 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5827 5828 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5829 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5830 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5831 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5832 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5833 5834 #define S_FW_EQ_MNGT_CMD_CPRIO 19 5835 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5836 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5837 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5838 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5839 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5840 5841 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 5842 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5843 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5844 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5845 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5846 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5847 5848 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 5849 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5850 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5851 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5852 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5853 5854 #define S_FW_EQ_MNGT_CMD_IQID 0 5855 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 5856 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5857 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 5858 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5859 5860 #define S_FW_EQ_MNGT_CMD_DCAEN 31 5861 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5862 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5863 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5864 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5865 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5866 5867 #define S_FW_EQ_MNGT_CMD_DCACPU 26 5868 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5869 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5870 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5871 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5872 5873 #define S_FW_EQ_MNGT_CMD_FBMIN 23 5874 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5875 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5876 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5877 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5878 5879 #define S_FW_EQ_MNGT_CMD_FBMAX 20 5880 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5881 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5882 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5883 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5884 5885 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5886 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5887 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5888 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5889 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5890 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5891 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5892 5893 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5894 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5895 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5896 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5897 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5898 5899 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 5900 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5901 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5902 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5903 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 5904 5905 struct fw_eq_eth_cmd { 5906 __be32 op_to_vfn; 5907 __be32 alloc_to_len16; 5908 __be32 eqid_pkd; 5909 __be32 physeqid_pkd; 5910 __be32 fetchszm_to_iqid; 5911 __be32 dcaen_to_eqsize; 5912 __be64 eqaddr; 5913 __be32 autoequiqe_to_viid; 5914 __be32 timeren_timerix; 5915 __be64 r9; 5916 }; 5917 5918 #define S_FW_EQ_ETH_CMD_PFN 8 5919 #define M_FW_EQ_ETH_CMD_PFN 0x7 5920 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5921 #define G_FW_EQ_ETH_CMD_PFN(x) \ 5922 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5923 5924 #define S_FW_EQ_ETH_CMD_VFN 0 5925 #define M_FW_EQ_ETH_CMD_VFN 0xff 5926 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5927 #define G_FW_EQ_ETH_CMD_VFN(x) \ 5928 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5929 5930 #define S_FW_EQ_ETH_CMD_ALLOC 31 5931 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 5932 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5933 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5934 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5935 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5936 5937 #define S_FW_EQ_ETH_CMD_FREE 30 5938 #define M_FW_EQ_ETH_CMD_FREE 0x1 5939 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5940 #define G_FW_EQ_ETH_CMD_FREE(x) \ 5941 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5942 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5943 5944 #define S_FW_EQ_ETH_CMD_MODIFY 29 5945 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 5946 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5947 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5948 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5949 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5950 5951 #define S_FW_EQ_ETH_CMD_EQSTART 28 5952 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 5953 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5954 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5955 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5956 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5957 5958 #define S_FW_EQ_ETH_CMD_EQSTOP 27 5959 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5960 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5961 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5962 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5963 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5964 5965 #define S_FW_EQ_ETH_CMD_EQID 0 5966 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 5967 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5968 #define G_FW_EQ_ETH_CMD_EQID(x) \ 5969 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5970 5971 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 5972 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5973 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5974 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5975 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5976 5977 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 5978 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5979 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5980 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5981 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5982 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5983 5984 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5985 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5986 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5987 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5988 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 5989 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 5990 5991 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 5992 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 5993 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 5994 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 5995 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 5996 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 5997 5998 #define S_FW_EQ_ETH_CMD_FETCHNS 23 5999 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 6000 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 6001 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 6002 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 6003 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 6004 6005 #define S_FW_EQ_ETH_CMD_FETCHRO 22 6006 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 6007 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 6008 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 6009 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 6010 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 6011 6012 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 6013 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 6014 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 6015 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 6016 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 6017 6018 #define S_FW_EQ_ETH_CMD_CPRIO 19 6019 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 6020 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 6021 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 6022 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 6023 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 6024 6025 #define S_FW_EQ_ETH_CMD_ONCHIP 18 6026 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 6027 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 6028 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 6029 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 6030 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 6031 6032 #define S_FW_EQ_ETH_CMD_PCIECHN 16 6033 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 6034 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 6035 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 6036 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 6037 6038 #define S_FW_EQ_ETH_CMD_IQID 0 6039 #define M_FW_EQ_ETH_CMD_IQID 0xffff 6040 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 6041 #define G_FW_EQ_ETH_CMD_IQID(x) \ 6042 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 6043 6044 #define S_FW_EQ_ETH_CMD_DCAEN 31 6045 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 6046 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 6047 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 6048 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 6049 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 6050 6051 #define S_FW_EQ_ETH_CMD_DCACPU 26 6052 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 6053 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 6054 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 6055 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 6056 6057 #define S_FW_EQ_ETH_CMD_FBMIN 23 6058 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 6059 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 6060 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 6061 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 6062 6063 #define S_FW_EQ_ETH_CMD_FBMAX 20 6064 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 6065 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 6066 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 6067 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 6068 6069 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 6070 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 6071 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 6072 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 6073 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 6074 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 6075 6076 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 6077 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 6078 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 6079 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 6080 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 6081 6082 #define S_FW_EQ_ETH_CMD_EQSIZE 0 6083 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 6084 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 6085 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 6086 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 6087 6088 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 6089 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 6090 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 6091 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 6092 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 6093 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 6094 6095 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 6096 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 6097 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 6098 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 6099 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 6100 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 6101 6102 #define S_FW_EQ_ETH_CMD_VIID 16 6103 #define M_FW_EQ_ETH_CMD_VIID 0xfff 6104 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 6105 #define G_FW_EQ_ETH_CMD_VIID(x) \ 6106 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 6107 6108 #define S_FW_EQ_ETH_CMD_TIMEREN 3 6109 #define M_FW_EQ_ETH_CMD_TIMEREN 0x1 6110 #define V_FW_EQ_ETH_CMD_TIMEREN(x) ((x) << S_FW_EQ_ETH_CMD_TIMEREN) 6111 #define G_FW_EQ_ETH_CMD_TIMEREN(x) \ 6112 (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN) 6113 #define F_FW_EQ_ETH_CMD_TIMEREN V_FW_EQ_ETH_CMD_TIMEREN(1U) 6114 6115 #define S_FW_EQ_ETH_CMD_TIMERIX 0 6116 #define M_FW_EQ_ETH_CMD_TIMERIX 0x7 6117 #define V_FW_EQ_ETH_CMD_TIMERIX(x) ((x) << S_FW_EQ_ETH_CMD_TIMERIX) 6118 #define G_FW_EQ_ETH_CMD_TIMERIX(x) \ 6119 (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX) 6120 6121 struct fw_eq_ctrl_cmd { 6122 __be32 op_to_vfn; 6123 __be32 alloc_to_len16; 6124 __be32 cmpliqid_eqid; 6125 __be32 physeqid_pkd; 6126 __be32 fetchszm_to_iqid; 6127 __be32 dcaen_to_eqsize; 6128 __be64 eqaddr; 6129 }; 6130 6131 #define S_FW_EQ_CTRL_CMD_PFN 8 6132 #define M_FW_EQ_CTRL_CMD_PFN 0x7 6133 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 6134 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 6135 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 6136 6137 #define S_FW_EQ_CTRL_CMD_VFN 0 6138 #define M_FW_EQ_CTRL_CMD_VFN 0xff 6139 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 6140 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 6141 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 6142 6143 #define S_FW_EQ_CTRL_CMD_ALLOC 31 6144 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 6145 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 6146 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 6147 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 6148 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 6149 6150 #define S_FW_EQ_CTRL_CMD_FREE 30 6151 #define M_FW_EQ_CTRL_CMD_FREE 0x1 6152 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 6153 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 6154 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 6155 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 6156 6157 #define S_FW_EQ_CTRL_CMD_MODIFY 29 6158 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 6159 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 6160 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 6161 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 6162 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 6163 6164 #define S_FW_EQ_CTRL_CMD_EQSTART 28 6165 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 6166 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 6167 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 6168 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 6169 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 6170 6171 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 6172 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 6173 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 6174 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 6175 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 6176 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 6177 6178 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 6179 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 6180 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 6181 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 6182 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 6183 6184 #define S_FW_EQ_CTRL_CMD_EQID 0 6185 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 6186 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 6187 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 6188 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 6189 6190 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 6191 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 6192 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 6193 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 6194 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 6195 6196 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 6197 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 6198 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 6199 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 6200 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 6201 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 6202 6203 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 6204 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 6205 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 6206 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 6207 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 6208 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 6209 6210 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 6211 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 6212 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 6213 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 6214 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 6215 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 6216 6217 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 6218 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 6219 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 6220 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 6221 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 6222 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 6223 6224 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 6225 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 6226 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 6227 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 6228 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 6229 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 6230 6231 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 6232 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 6233 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 6234 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 6235 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 6236 6237 #define S_FW_EQ_CTRL_CMD_CPRIO 19 6238 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 6239 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 6240 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 6241 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 6242 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 6243 6244 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 6245 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 6246 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 6247 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 6248 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 6249 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 6250 6251 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 6252 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 6253 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 6254 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 6255 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 6256 6257 #define S_FW_EQ_CTRL_CMD_IQID 0 6258 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 6259 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 6260 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 6261 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 6262 6263 #define S_FW_EQ_CTRL_CMD_DCAEN 31 6264 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 6265 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 6266 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 6267 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 6268 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 6269 6270 #define S_FW_EQ_CTRL_CMD_DCACPU 26 6271 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 6272 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 6273 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 6274 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 6275 6276 #define S_FW_EQ_CTRL_CMD_FBMIN 23 6277 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 6278 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 6279 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 6280 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 6281 6282 #define S_FW_EQ_CTRL_CMD_FBMAX 20 6283 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 6284 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 6285 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 6286 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 6287 6288 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 6289 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 6290 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6291 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6292 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6293 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6294 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 6295 6296 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 6297 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 6298 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6299 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 6300 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6301 6302 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 6303 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 6304 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 6305 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 6306 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 6307 6308 struct fw_eq_ofld_cmd { 6309 __be32 op_to_vfn; 6310 __be32 alloc_to_len16; 6311 __be32 eqid_pkd; 6312 __be32 physeqid_pkd; 6313 __be32 fetchszm_to_iqid; 6314 __be32 dcaen_to_eqsize; 6315 __be64 eqaddr; 6316 }; 6317 6318 #define S_FW_EQ_OFLD_CMD_PFN 8 6319 #define M_FW_EQ_OFLD_CMD_PFN 0x7 6320 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 6321 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 6322 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 6323 6324 #define S_FW_EQ_OFLD_CMD_VFN 0 6325 #define M_FW_EQ_OFLD_CMD_VFN 0xff 6326 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 6327 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 6328 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 6329 6330 #define S_FW_EQ_OFLD_CMD_ALLOC 31 6331 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 6332 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 6333 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 6334 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 6335 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 6336 6337 #define S_FW_EQ_OFLD_CMD_FREE 30 6338 #define M_FW_EQ_OFLD_CMD_FREE 0x1 6339 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 6340 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 6341 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 6342 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 6343 6344 #define S_FW_EQ_OFLD_CMD_MODIFY 29 6345 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 6346 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 6347 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 6348 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 6349 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 6350 6351 #define S_FW_EQ_OFLD_CMD_EQSTART 28 6352 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 6353 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 6354 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 6355 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 6356 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 6357 6358 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 6359 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 6360 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 6361 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 6362 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 6363 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 6364 6365 #define S_FW_EQ_OFLD_CMD_EQID 0 6366 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 6367 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 6368 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 6369 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 6370 6371 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 6372 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 6373 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 6374 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 6375 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 6376 6377 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 6378 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 6379 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 6380 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 6381 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 6382 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 6383 6384 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 6385 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 6386 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 6387 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 6388 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 6389 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 6390 6391 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 6392 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 6393 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 6394 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 6395 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 6396 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 6397 6398 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 6399 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 6400 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 6401 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 6402 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 6403 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 6404 6405 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 6406 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 6407 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 6408 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 6409 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 6410 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 6411 6412 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 6413 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 6414 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 6415 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 6416 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 6417 6418 #define S_FW_EQ_OFLD_CMD_CPRIO 19 6419 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 6420 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 6421 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 6422 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 6423 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 6424 6425 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 6426 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 6427 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 6428 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 6429 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 6430 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 6431 6432 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 6433 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 6434 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 6435 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 6436 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 6437 6438 #define S_FW_EQ_OFLD_CMD_IQID 0 6439 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 6440 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 6441 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 6442 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 6443 6444 #define S_FW_EQ_OFLD_CMD_DCAEN 31 6445 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 6446 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 6447 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 6448 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 6449 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 6450 6451 #define S_FW_EQ_OFLD_CMD_DCACPU 26 6452 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 6453 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 6454 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 6455 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 6456 6457 #define S_FW_EQ_OFLD_CMD_FBMIN 23 6458 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 6459 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 6460 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 6461 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 6462 6463 #define S_FW_EQ_OFLD_CMD_FBMAX 20 6464 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 6465 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 6466 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 6467 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 6468 6469 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 6470 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 6471 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6472 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6473 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6474 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6475 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 6476 6477 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 6478 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 6479 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6480 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 6481 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6482 6483 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 6484 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 6485 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 6486 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 6487 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 6488 6489 /* Following macros present here only to maintain backward 6490 * compatibiity. Driver must not use these anymore */ 6491 /* Macros for VIID parsing: 6492 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 6493 #define S_FW_VIID_PFN 8 6494 #define M_FW_VIID_PFN 0x7 6495 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 6496 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 6497 6498 #define S_FW_VIID_VIVLD 7 6499 #define M_FW_VIID_VIVLD 0x1 6500 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 6501 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 6502 6503 #define S_FW_VIID_VIN 0 6504 #define M_FW_VIID_VIN 0x7F 6505 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 6506 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 6507 6508 /* Macros for VIID parsing: 6509 VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */ 6510 #define S_FW_256VIID_PFN 9 6511 #define M_FW_256VIID_PFN 0x7 6512 #define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN) 6513 #define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN) 6514 6515 #define S_FW_256VIID_VIVLD 8 6516 #define M_FW_256VIID_VIVLD 0x1 6517 #define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD) 6518 #define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD) 6519 6520 #define S_FW_256VIID_VIN 0 6521 #define M_FW_256VIID_VIN 0xFF 6522 #define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN) 6523 #define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN) 6524 6525 enum fw_vi_func { 6526 FW_VI_FUNC_ETH, 6527 FW_VI_FUNC_OFLD, 6528 FW_VI_FUNC_IWARP, 6529 FW_VI_FUNC_OPENISCSI, 6530 FW_VI_FUNC_OPENFCOE, 6531 FW_VI_FUNC_FOISCSI, 6532 FW_VI_FUNC_FOFCOE, 6533 FW_VI_FUNC_FW, 6534 }; 6535 6536 struct fw_vi_cmd { 6537 __be32 op_to_vfn; 6538 __be32 alloc_to_len16; 6539 __be16 type_to_viid; 6540 __u8 mac[6]; 6541 __u8 portid_pkd; 6542 __u8 nmac; 6543 __u8 nmac0[6]; 6544 __be16 norss_rsssize; 6545 __u8 nmac1[6]; 6546 __be16 idsiiq_pkd; 6547 __u8 nmac2[6]; 6548 __be16 idseiq_pkd; 6549 __u8 nmac3[6]; 6550 __be64 r9; 6551 __be64 r10; 6552 }; 6553 6554 #define S_FW_VI_CMD_PFN 8 6555 #define M_FW_VI_CMD_PFN 0x7 6556 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 6557 #define G_FW_VI_CMD_PFN(x) \ 6558 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 6559 6560 #define S_FW_VI_CMD_VFN 0 6561 #define M_FW_VI_CMD_VFN 0xff 6562 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 6563 #define G_FW_VI_CMD_VFN(x) \ 6564 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 6565 6566 #define S_FW_VI_CMD_ALLOC 31 6567 #define M_FW_VI_CMD_ALLOC 0x1 6568 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 6569 #define G_FW_VI_CMD_ALLOC(x) \ 6570 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 6571 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 6572 6573 #define S_FW_VI_CMD_FREE 30 6574 #define M_FW_VI_CMD_FREE 0x1 6575 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 6576 #define G_FW_VI_CMD_FREE(x) \ 6577 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 6578 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 6579 6580 #define S_FW_VI_CMD_VFVLD 24 6581 #define M_FW_VI_CMD_VFVLD 0x1 6582 #define V_FW_VI_CMD_VFVLD(x) ((x) << S_FW_VI_CMD_VFVLD) 6583 #define G_FW_VI_CMD_VFVLD(x) \ 6584 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD) 6585 #define F_FW_VI_CMD_VFVLD V_FW_VI_CMD_VFVLD(1U) 6586 6587 #define S_FW_VI_CMD_VIN 16 6588 #define M_FW_VI_CMD_VIN 0xff 6589 #define V_FW_VI_CMD_VIN(x) ((x) << S_FW_VI_CMD_VIN) 6590 #define G_FW_VI_CMD_VIN(x) \ 6591 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN) 6592 6593 #define S_FW_VI_CMD_TYPE 15 6594 #define M_FW_VI_CMD_TYPE 0x1 6595 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 6596 #define G_FW_VI_CMD_TYPE(x) \ 6597 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 6598 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 6599 6600 #define S_FW_VI_CMD_FUNC 12 6601 #define M_FW_VI_CMD_FUNC 0x7 6602 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 6603 #define G_FW_VI_CMD_FUNC(x) \ 6604 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 6605 6606 #define S_FW_VI_CMD_VIID 0 6607 #define M_FW_VI_CMD_VIID 0xfff 6608 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 6609 #define G_FW_VI_CMD_VIID(x) \ 6610 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 6611 6612 #define S_FW_VI_CMD_PORTID 4 6613 #define M_FW_VI_CMD_PORTID 0xf 6614 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 6615 #define G_FW_VI_CMD_PORTID(x) \ 6616 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 6617 6618 #define S_FW_VI_CMD_NORSS 11 6619 #define M_FW_VI_CMD_NORSS 0x1 6620 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 6621 #define G_FW_VI_CMD_NORSS(x) \ 6622 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 6623 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 6624 6625 #define S_FW_VI_CMD_RSSSIZE 0 6626 #define M_FW_VI_CMD_RSSSIZE 0x7ff 6627 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 6628 #define G_FW_VI_CMD_RSSSIZE(x) \ 6629 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 6630 6631 #define S_FW_VI_CMD_IDSIIQ 0 6632 #define M_FW_VI_CMD_IDSIIQ 0x3ff 6633 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 6634 #define G_FW_VI_CMD_IDSIIQ(x) \ 6635 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 6636 6637 #define S_FW_VI_CMD_IDSEIQ 0 6638 #define M_FW_VI_CMD_IDSEIQ 0x3ff 6639 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 6640 #define G_FW_VI_CMD_IDSEIQ(x) \ 6641 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 6642 6643 /* Special VI_MAC command index ids */ 6644 #define FW_VI_MAC_ADD_MAC 0x3FF 6645 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 6646 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 6647 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 6648 6649 enum fw_vi_mac_smac { 6650 FW_VI_MAC_MPS_TCAM_ENTRY, 6651 FW_VI_MAC_MPS_TCAM_ONLY, 6652 FW_VI_MAC_SMT_ONLY, 6653 FW_VI_MAC_SMT_AND_MPSTCAM 6654 }; 6655 6656 enum fw_vi_mac_result { 6657 FW_VI_MAC_R_SUCCESS, 6658 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 6659 FW_VI_MAC_R_SMAC_FAIL, 6660 FW_VI_MAC_R_F_ACL_CHECK 6661 }; 6662 6663 enum fw_vi_mac_entry_types { 6664 FW_VI_MAC_TYPE_EXACTMAC, 6665 FW_VI_MAC_TYPE_HASHVEC, 6666 FW_VI_MAC_TYPE_RAW, 6667 FW_VI_MAC_TYPE_EXACTMAC_VNI, 6668 }; 6669 6670 struct fw_vi_mac_cmd { 6671 __be32 op_to_viid; 6672 __be32 freemacs_to_len16; 6673 union fw_vi_mac { 6674 struct fw_vi_mac_exact { 6675 __be16 valid_to_idx; 6676 __u8 macaddr[6]; 6677 } exact[7]; 6678 struct fw_vi_mac_hash { 6679 __be64 hashvec; 6680 } hash; 6681 struct fw_vi_mac_raw { 6682 __be32 raw_idx_pkd; 6683 __be32 data0_pkd; 6684 __be32 data1[2]; 6685 __be64 data0m_pkd; 6686 __be32 data1m[2]; 6687 } raw; 6688 struct fw_vi_mac_vni { 6689 __be16 valid_to_idx; 6690 __u8 macaddr[6]; 6691 __be16 r7; 6692 __u8 macaddr_mask[6]; 6693 __be32 lookup_type_to_vni; 6694 __be32 vni_mask_pkd; 6695 } exact_vni[2]; 6696 } u; 6697 }; 6698 6699 #define S_FW_VI_MAC_CMD_SMTID 12 6700 #define M_FW_VI_MAC_CMD_SMTID 0xff 6701 #define V_FW_VI_MAC_CMD_SMTID(x) ((x) << S_FW_VI_MAC_CMD_SMTID) 6702 #define G_FW_VI_MAC_CMD_SMTID(x) \ 6703 (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID) 6704 6705 #define S_FW_VI_MAC_CMD_VIID 0 6706 #define M_FW_VI_MAC_CMD_VIID 0xfff 6707 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 6708 #define G_FW_VI_MAC_CMD_VIID(x) \ 6709 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 6710 6711 #define S_FW_VI_MAC_CMD_FREEMACS 31 6712 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 6713 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 6714 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 6715 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 6716 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 6717 6718 #define S_FW_VI_MAC_CMD_IS_SMAC 30 6719 #define M_FW_VI_MAC_CMD_IS_SMAC 0x1 6720 #define V_FW_VI_MAC_CMD_IS_SMAC(x) ((x) << S_FW_VI_MAC_CMD_IS_SMAC) 6721 #define G_FW_VI_MAC_CMD_IS_SMAC(x) \ 6722 (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC) 6723 #define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U) 6724 6725 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 6726 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 6727 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 6728 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 6729 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 6730 6731 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 6732 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 6733 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 6734 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 6735 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 6736 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 6737 6738 #define S_FW_VI_MAC_CMD_VALID 15 6739 #define M_FW_VI_MAC_CMD_VALID 0x1 6740 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 6741 #define G_FW_VI_MAC_CMD_VALID(x) \ 6742 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 6743 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 6744 6745 #define S_FW_VI_MAC_CMD_PRIO 12 6746 #define M_FW_VI_MAC_CMD_PRIO 0x7 6747 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 6748 #define G_FW_VI_MAC_CMD_PRIO(x) \ 6749 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 6750 6751 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 6752 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 6753 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 6754 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 6755 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 6756 6757 #define S_FW_VI_MAC_CMD_IDX 0 6758 #define M_FW_VI_MAC_CMD_IDX 0x3ff 6759 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 6760 #define G_FW_VI_MAC_CMD_IDX(x) \ 6761 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 6762 6763 #define S_FW_VI_MAC_CMD_RAW_IDX 16 6764 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 6765 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 6766 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 6767 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 6768 6769 #define S_FW_VI_MAC_CMD_DATA0 0 6770 #define M_FW_VI_MAC_CMD_DATA0 0xffff 6771 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 6772 #define G_FW_VI_MAC_CMD_DATA0(x) \ 6773 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 6774 6775 #define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31 6776 #define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1 6777 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE) 6778 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \ 6779 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE) 6780 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U) 6781 6782 #define S_FW_VI_MAC_CMD_DIP_HIT 30 6783 #define M_FW_VI_MAC_CMD_DIP_HIT 0x1 6784 #define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT) 6785 #define G_FW_VI_MAC_CMD_DIP_HIT(x) \ 6786 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT) 6787 #define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U) 6788 6789 #define S_FW_VI_MAC_CMD_VNI 0 6790 #define M_FW_VI_MAC_CMD_VNI 0xffffff 6791 #define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI) 6792 #define G_FW_VI_MAC_CMD_VNI(x) \ 6793 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI) 6794 6795 /* Extracting loopback port number passed from driver. 6796 * as a part of fw_vi_mac_vni For non loopback entries 6797 * ignore the field and update port number from flowc. 6798 * Fw will ignore if physical port number received. 6799 * expected range (4-7). 6800 */ 6801 6802 #define S_FW_VI_MAC_CMD_PORT 24 6803 #define M_FW_VI_MAC_CMD_PORT 0x7 6804 #define V_FW_VI_MAC_CMD_PORT(x) ((x) << S_FW_VI_MAC_CMD_PORT) 6805 #define G_FW_VI_MAC_CMD_PORT(x) \ 6806 (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT) 6807 6808 #define S_FW_VI_MAC_CMD_VNI_MASK 0 6809 #define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff 6810 #define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK) 6811 #define G_FW_VI_MAC_CMD_VNI_MASK(x) \ 6812 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK) 6813 6814 /* T4 max MTU supported */ 6815 #define T4_MAX_MTU_SUPPORTED 9600 6816 #define FW_RXMODE_MTU_NO_CHG 65535 6817 6818 struct fw_vi_rxmode_cmd { 6819 __be32 op_to_viid; 6820 __be32 retval_len16; 6821 __be32 mtu_to_vlanexen; 6822 __be32 r4_lo; 6823 }; 6824 6825 #define S_FW_VI_RXMODE_CMD_VIID 0 6826 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 6827 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 6828 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 6829 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6830 6831 #define S_FW_VI_RXMODE_CMD_MTU 16 6832 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 6833 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6834 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 6835 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6836 6837 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6838 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6839 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6840 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6841 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6842 6843 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6844 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6845 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6846 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6847 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6848 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6849 6850 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6851 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6852 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6853 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6854 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6855 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6856 6857 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6858 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6859 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6860 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6861 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 6862 6863 struct fw_vi_enable_cmd { 6864 __be32 op_to_viid; 6865 __be32 ien_to_len16; 6866 __be16 blinkdur; 6867 __be16 r3; 6868 __be32 r4; 6869 }; 6870 6871 #define S_FW_VI_ENABLE_CMD_VIID 0 6872 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 6873 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6874 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 6875 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6876 6877 #define S_FW_VI_ENABLE_CMD_IEN 31 6878 #define M_FW_VI_ENABLE_CMD_IEN 0x1 6879 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6880 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 6881 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6882 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6883 6884 #define S_FW_VI_ENABLE_CMD_EEN 30 6885 #define M_FW_VI_ENABLE_CMD_EEN 0x1 6886 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6887 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 6888 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6889 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6890 6891 #define S_FW_VI_ENABLE_CMD_LED 29 6892 #define M_FW_VI_ENABLE_CMD_LED 0x1 6893 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6894 #define G_FW_VI_ENABLE_CMD_LED(x) \ 6895 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6896 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 6897 6898 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6899 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6900 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6901 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6902 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6903 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6904 6905 /* VI VF stats offset definitions */ 6906 #define VI_VF_NUM_STATS 16 6907 enum fw_vi_stats_vf_index { 6908 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 6909 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 6910 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 6911 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 6912 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 6913 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 6914 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 6915 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 6916 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 6917 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 6918 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 6919 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 6920 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 6921 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 6922 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 6923 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 6924 }; 6925 6926 /* VI PF stats offset definitions */ 6927 #define VI_PF_NUM_STATS 17 6928 enum fw_vi_stats_pf_index { 6929 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 6930 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 6931 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 6932 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 6933 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 6934 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 6935 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 6936 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 6937 FW_VI_PF_STAT_RX_BYTES_IX, 6938 FW_VI_PF_STAT_RX_FRAMES_IX, 6939 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 6940 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 6941 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 6942 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 6943 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 6944 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 6945 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 6946 }; 6947 6948 struct fw_vi_stats_cmd { 6949 __be32 op_to_viid; 6950 __be32 retval_len16; 6951 union fw_vi_stats { 6952 struct fw_vi_stats_ctl { 6953 __be16 nstats_ix; 6954 __be16 r6; 6955 __be32 r7; 6956 __be64 stat0; 6957 __be64 stat1; 6958 __be64 stat2; 6959 __be64 stat3; 6960 __be64 stat4; 6961 __be64 stat5; 6962 } ctl; 6963 struct fw_vi_stats_pf { 6964 __be64 tx_bcast_bytes; 6965 __be64 tx_bcast_frames; 6966 __be64 tx_mcast_bytes; 6967 __be64 tx_mcast_frames; 6968 __be64 tx_ucast_bytes; 6969 __be64 tx_ucast_frames; 6970 __be64 tx_offload_bytes; 6971 __be64 tx_offload_frames; 6972 __be64 rx_pf_bytes; 6973 __be64 rx_pf_frames; 6974 __be64 rx_bcast_bytes; 6975 __be64 rx_bcast_frames; 6976 __be64 rx_mcast_bytes; 6977 __be64 rx_mcast_frames; 6978 __be64 rx_ucast_bytes; 6979 __be64 rx_ucast_frames; 6980 __be64 rx_err_frames; 6981 } pf; 6982 struct fw_vi_stats_vf { 6983 __be64 tx_bcast_bytes; 6984 __be64 tx_bcast_frames; 6985 __be64 tx_mcast_bytes; 6986 __be64 tx_mcast_frames; 6987 __be64 tx_ucast_bytes; 6988 __be64 tx_ucast_frames; 6989 __be64 tx_drop_frames; 6990 __be64 tx_offload_bytes; 6991 __be64 tx_offload_frames; 6992 __be64 rx_bcast_bytes; 6993 __be64 rx_bcast_frames; 6994 __be64 rx_mcast_bytes; 6995 __be64 rx_mcast_frames; 6996 __be64 rx_ucast_bytes; 6997 __be64 rx_ucast_frames; 6998 __be64 rx_err_frames; 6999 } vf; 7000 } u; 7001 }; 7002 7003 #define S_FW_VI_STATS_CMD_VIID 0 7004 #define M_FW_VI_STATS_CMD_VIID 0xfff 7005 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 7006 #define G_FW_VI_STATS_CMD_VIID(x) \ 7007 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 7008 7009 #define S_FW_VI_STATS_CMD_NSTATS 12 7010 #define M_FW_VI_STATS_CMD_NSTATS 0x7 7011 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 7012 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 7013 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 7014 7015 #define S_FW_VI_STATS_CMD_IX 0 7016 #define M_FW_VI_STATS_CMD_IX 0x1f 7017 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 7018 #define G_FW_VI_STATS_CMD_IX(x) \ 7019 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 7020 7021 struct fw_acl_mac_cmd { 7022 __be32 op_to_vfn; 7023 __be32 en_to_len16; 7024 __u8 nmac; 7025 __u8 r3[7]; 7026 __be16 r4; 7027 __u8 macaddr0[6]; 7028 __be16 r5; 7029 __u8 macaddr1[6]; 7030 __be16 r6; 7031 __u8 macaddr2[6]; 7032 __be16 r7; 7033 __u8 macaddr3[6]; 7034 }; 7035 7036 #define S_FW_ACL_MAC_CMD_PFN 8 7037 #define M_FW_ACL_MAC_CMD_PFN 0x7 7038 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 7039 #define G_FW_ACL_MAC_CMD_PFN(x) \ 7040 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 7041 7042 #define S_FW_ACL_MAC_CMD_VFN 0 7043 #define M_FW_ACL_MAC_CMD_VFN 0xff 7044 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 7045 #define G_FW_ACL_MAC_CMD_VFN(x) \ 7046 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 7047 7048 #define S_FW_ACL_MAC_CMD_EN 31 7049 #define M_FW_ACL_MAC_CMD_EN 0x1 7050 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 7051 #define G_FW_ACL_MAC_CMD_EN(x) \ 7052 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 7053 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 7054 7055 struct fw_acl_vlan_cmd { 7056 __be32 op_to_vfn; 7057 __be32 en_to_len16; 7058 __u8 nvlan; 7059 __u8 dropnovlan_fm; 7060 __u8 r3_lo[6]; 7061 __be16 vlanid[16]; 7062 }; 7063 7064 #define S_FW_ACL_VLAN_CMD_PFN 8 7065 #define M_FW_ACL_VLAN_CMD_PFN 0x7 7066 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 7067 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 7068 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 7069 7070 #define S_FW_ACL_VLAN_CMD_VFN 0 7071 #define M_FW_ACL_VLAN_CMD_VFN 0xff 7072 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 7073 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 7074 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 7075 7076 #define S_FW_ACL_VLAN_CMD_EN 31 7077 #define M_FW_ACL_VLAN_CMD_EN 0x1 7078 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 7079 #define G_FW_ACL_VLAN_CMD_EN(x) \ 7080 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 7081 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 7082 7083 #define S_FW_ACL_VLAN_CMD_TRANSPARENT 30 7084 #define M_FW_ACL_VLAN_CMD_TRANSPARENT 0x1 7085 #define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 7086 ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT) 7087 #define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 7088 (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT) 7089 #define F_FW_ACL_VLAN_CMD_TRANSPARENT V_FW_ACL_VLAN_CMD_TRANSPARENT(1U) 7090 7091 #define S_FW_ACL_VLAN_CMD_PMASK 16 7092 #define M_FW_ACL_VLAN_CMD_PMASK 0xf 7093 #define V_FW_ACL_VLAN_CMD_PMASK(x) ((x) << S_FW_ACL_VLAN_CMD_PMASK) 7094 #define G_FW_ACL_VLAN_CMD_PMASK(x) \ 7095 (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK) 7096 7097 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 7098 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 7099 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 7100 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 7101 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 7102 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 7103 7104 #define S_FW_ACL_VLAN_CMD_FM 6 7105 #define M_FW_ACL_VLAN_CMD_FM 0x1 7106 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 7107 #define G_FW_ACL_VLAN_CMD_FM(x) \ 7108 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 7109 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 7110 7111 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 7112 enum fw_port_cap { 7113 FW_PORT_CAP_SPEED_100M = 0x0001, 7114 FW_PORT_CAP_SPEED_1G = 0x0002, 7115 FW_PORT_CAP_SPEED_25G = 0x0004, 7116 FW_PORT_CAP_SPEED_10G = 0x0008, 7117 FW_PORT_CAP_SPEED_40G = 0x0010, 7118 FW_PORT_CAP_SPEED_100G = 0x0020, 7119 FW_PORT_CAP_FC_RX = 0x0040, 7120 FW_PORT_CAP_FC_TX = 0x0080, 7121 FW_PORT_CAP_ANEG = 0x0100, 7122 FW_PORT_CAP_MDIAUTO = 0x0200, 7123 FW_PORT_CAP_MDISTRAIGHT = 0x0400, 7124 FW_PORT_CAP_FEC_RS = 0x0800, 7125 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 7126 FW_PORT_CAP_FORCE_PAUSE = 0x2000, 7127 FW_PORT_CAP_802_3_PAUSE = 0x4000, 7128 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 7129 }; 7130 7131 #define S_FW_PORT_CAP_SPEED 0 7132 #define M_FW_PORT_CAP_SPEED 0x3f 7133 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 7134 #define G_FW_PORT_CAP_SPEED(x) \ 7135 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 7136 7137 #define S_FW_PORT_CAP_FC 6 7138 #define M_FW_PORT_CAP_FC 0x3 7139 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 7140 #define G_FW_PORT_CAP_FC(x) \ 7141 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 7142 7143 #define S_FW_PORT_CAP_ANEG 8 7144 #define M_FW_PORT_CAP_ANEG 0x1 7145 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 7146 #define G_FW_PORT_CAP_ANEG(x) \ 7147 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 7148 7149 #define S_FW_PORT_CAP_FEC 11 7150 #define M_FW_PORT_CAP_FEC 0x3 7151 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 7152 #define G_FW_PORT_CAP_FEC(x) \ 7153 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 7154 7155 #define S_FW_PORT_CAP_FORCE_PAUSE 13 7156 #define M_FW_PORT_CAP_FORCE_PAUSE 0x1 7157 #define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE) 7158 #define G_FW_PORT_CAP_FORCE_PAUSE(x) \ 7159 (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE) 7160 7161 #define S_FW_PORT_CAP_802_3 14 7162 #define M_FW_PORT_CAP_802_3 0x3 7163 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 7164 #define G_FW_PORT_CAP_802_3(x) \ 7165 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 7166 7167 enum fw_port_mdi { 7168 FW_PORT_CAP_MDI_UNCHANGED, 7169 FW_PORT_CAP_MDI_AUTO, 7170 FW_PORT_CAP_MDI_F_STRAIGHT, 7171 FW_PORT_CAP_MDI_F_CROSSOVER 7172 }; 7173 7174 #define S_FW_PORT_CAP_MDI 9 7175 #define M_FW_PORT_CAP_MDI 3 7176 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 7177 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 7178 7179 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 7180 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 7181 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 7182 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 7183 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 7184 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 7185 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 7186 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 7187 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 7188 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 7189 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 7190 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 7191 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 7192 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 7193 #define FW_PORT_CAP32_FC_RX 0x00010000UL 7194 #define FW_PORT_CAP32_FC_TX 0x00020000UL 7195 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 7196 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 7197 #define FW_PORT_CAP32_ANEG 0x00100000UL 7198 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL 7199 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 7200 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 7201 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 7202 #define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL 7203 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 7204 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 7205 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 7206 #define FW_PORT_CAP32_FORCE_FEC 0x20000000UL 7207 #define FW_PORT_CAP32_RESERVED2 0xc0000000UL 7208 7209 #define S_FW_PORT_CAP32_SPEED 0 7210 #define M_FW_PORT_CAP32_SPEED 0xfff 7211 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 7212 #define G_FW_PORT_CAP32_SPEED(x) \ 7213 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 7214 7215 #define S_FW_PORT_CAP32_FC 16 7216 #define M_FW_PORT_CAP32_FC 0x3 7217 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) 7218 #define G_FW_PORT_CAP32_FC(x) \ 7219 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC) 7220 7221 #define S_FW_PORT_CAP32_802_3 18 7222 #define M_FW_PORT_CAP32_802_3 0x3 7223 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) 7224 #define G_FW_PORT_CAP32_802_3(x) \ 7225 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3) 7226 7227 #define S_FW_PORT_CAP32_ANEG 20 7228 #define M_FW_PORT_CAP32_ANEG 0x1 7229 #define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG) 7230 #define G_FW_PORT_CAP32_ANEG(x) \ 7231 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG) 7232 7233 #define S_FW_PORT_CAP32_FORCE_PAUSE 28 7234 #define M_FW_PORT_CAP32_FORCE_PAUSE 0x1 7235 #define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE) 7236 #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \ 7237 (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE) 7238 7239 enum fw_port_mdi32 { 7240 FW_PORT_CAP32_MDI_UNCHANGED, 7241 FW_PORT_CAP32_MDI_AUTO, 7242 FW_PORT_CAP32_MDI_F_STRAIGHT, 7243 FW_PORT_CAP32_MDI_F_CROSSOVER 7244 }; 7245 7246 #define S_FW_PORT_CAP32_MDI 21 7247 #define M_FW_PORT_CAP32_MDI 3 7248 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 7249 #define G_FW_PORT_CAP32_MDI(x) \ 7250 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 7251 7252 #define S_FW_PORT_CAP32_FEC 23 7253 #define M_FW_PORT_CAP32_FEC 0x1f 7254 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) 7255 #define G_FW_PORT_CAP32_FEC(x) \ 7256 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC) 7257 7258 /* macros to isolate various 32-bit Port Capabilities sub-fields */ 7259 #define CAP32_SPEED(__cap32) \ 7260 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32) 7261 7262 #define CAP32_FEC(__cap32) \ 7263 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32) 7264 7265 #define CAP32_FC(__cap32) \ 7266 (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32) 7267 7268 static inline bool 7269 fec_supported(uint32_t caps) 7270 { 7271 7272 return ((caps & (FW_PORT_CAP32_SPEED_25G | FW_PORT_CAP32_SPEED_50G | 7273 FW_PORT_CAP32_SPEED_100G)) != 0); 7274 } 7275 7276 enum fw_port_action { 7277 FW_PORT_ACTION_L1_CFG = 0x0001, 7278 FW_PORT_ACTION_L2_CFG = 0x0002, 7279 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 7280 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 7281 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 7282 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 7283 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 7284 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 7285 FW_PORT_ACTION_L1_CFG32 = 0x0009, 7286 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 7287 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 7288 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 7289 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 7290 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 7291 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 7292 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 7293 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 7294 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 7295 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 7296 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 7297 FW_PORT_ACTION_PHY_RESET = 0x0040, 7298 FW_PORT_ACTION_PMA_RESET = 0x0041, 7299 FW_PORT_ACTION_PCS_RESET = 0x0042, 7300 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 7301 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 7302 FW_PORT_ACTION_AN_RESET = 0x0045, 7303 }; 7304 7305 enum fw_port_l2cfg_ctlbf { 7306 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 7307 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 7308 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 7309 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 7310 FW_PORT_L2_CTLBF_IVLAN = 0x10, 7311 FW_PORT_L2_CTLBF_TXIPG = 0x20, 7312 FW_PORT_L2_CTLBF_MTU = 0x40, 7313 FW_PORT_L2_CTLBF_OVLAN_FILT = 0x80, 7314 }; 7315 7316 enum fw_dcb_app_tlv_sf { 7317 FW_DCB_APP_SF_ETHERTYPE, 7318 FW_DCB_APP_SF_SOCKET_TCP, 7319 FW_DCB_APP_SF_SOCKET_UDP, 7320 FW_DCB_APP_SF_SOCKET_ALL, 7321 }; 7322 7323 enum fw_port_dcb_versions { 7324 FW_PORT_DCB_VER_UNKNOWN, 7325 FW_PORT_DCB_VER_CEE1D0, 7326 FW_PORT_DCB_VER_CEE1D01, 7327 FW_PORT_DCB_VER_IEEE, 7328 FW_PORT_DCB_VER_AUTO=7 7329 }; 7330 7331 enum fw_port_dcb_cfg { 7332 FW_PORT_DCB_CFG_PG = 0x01, 7333 FW_PORT_DCB_CFG_PFC = 0x02, 7334 FW_PORT_DCB_CFG_APPL = 0x04 7335 }; 7336 7337 enum fw_port_dcb_cfg_rc { 7338 FW_PORT_DCB_CFG_SUCCESS = 0x0, 7339 FW_PORT_DCB_CFG_ERROR = 0x1 7340 }; 7341 7342 enum fw_port_dcb_type { 7343 FW_PORT_DCB_TYPE_PGID = 0x00, 7344 FW_PORT_DCB_TYPE_PGRATE = 0x01, 7345 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 7346 FW_PORT_DCB_TYPE_PFC = 0x03, 7347 FW_PORT_DCB_TYPE_APP_ID = 0x04, 7348 FW_PORT_DCB_TYPE_CONTROL = 0x05, 7349 }; 7350 7351 enum fw_port_dcb_feature_state { 7352 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 7353 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 7354 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 7355 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 7356 }; 7357 7358 enum fw_port_diag_ops { 7359 FW_PORT_DIAGS_TEMP = 0x00, 7360 FW_PORT_DIAGS_TX_POWER = 0x01, 7361 FW_PORT_DIAGS_RX_POWER = 0x02, 7362 FW_PORT_DIAGS_TX_DIS = 0x03, 7363 }; 7364 7365 struct fw_port_cmd { 7366 __be32 op_to_portid; 7367 __be32 action_to_len16; 7368 union fw_port { 7369 struct fw_port_l1cfg { 7370 __be32 rcap; 7371 __be32 r; 7372 } l1cfg; 7373 struct fw_port_l2cfg { 7374 __u8 ctlbf; 7375 __u8 ovlan3_to_ivlan0; 7376 __be16 ivlantype; 7377 __be16 txipg_force_pinfo; 7378 __be16 mtu; 7379 __be16 ovlan0mask; 7380 __be16 ovlan0type; 7381 __be16 ovlan1mask; 7382 __be16 ovlan1type; 7383 __be16 ovlan2mask; 7384 __be16 ovlan2type; 7385 __be16 ovlan3mask; 7386 __be16 ovlan3type; 7387 } l2cfg; 7388 struct fw_port_info { 7389 __be32 lstatus_to_modtype; 7390 __be16 pcap; 7391 __be16 acap; 7392 __be16 mtu; 7393 __u8 cbllen; 7394 __u8 auxlinfo; 7395 __u8 dcbxdis_pkd; 7396 __u8 r8_lo; 7397 __be16 lpacap; 7398 __be64 r9; 7399 } info; 7400 struct fw_port_diags { 7401 __u8 diagop; 7402 __u8 r[3]; 7403 __be32 diagval; 7404 } diags; 7405 union fw_port_dcb { 7406 struct fw_port_dcb_pgid { 7407 __u8 type; 7408 __u8 apply_pkd; 7409 __u8 r10_lo[2]; 7410 __be32 pgid; 7411 __be64 r11; 7412 } pgid; 7413 struct fw_port_dcb_pgrate { 7414 __u8 type; 7415 __u8 apply_pkd; 7416 __u8 r10_lo[5]; 7417 __u8 num_tcs_supported; 7418 __u8 pgrate[8]; 7419 __u8 tsa[8]; 7420 } pgrate; 7421 struct fw_port_dcb_priorate { 7422 __u8 type; 7423 __u8 apply_pkd; 7424 __u8 r10_lo[6]; 7425 __u8 strict_priorate[8]; 7426 } priorate; 7427 struct fw_port_dcb_pfc { 7428 __u8 type; 7429 __u8 pfcen; 7430 __u8 apply_pkd; 7431 __u8 r10_lo[4]; 7432 __u8 max_pfc_tcs; 7433 __be64 r11; 7434 } pfc; 7435 struct fw_port_app_priority { 7436 __u8 type; 7437 __u8 apply_pkd; 7438 __u8 r10_lo; 7439 __u8 idx; 7440 __u8 user_prio_map; 7441 __u8 sel_field; 7442 __be16 protocolid; 7443 __be64 r12; 7444 } app_priority; 7445 struct fw_port_dcb_control { 7446 __u8 type; 7447 __u8 all_syncd_pkd; 7448 __be16 dcb_version_to_app_state; 7449 __be32 r11; 7450 __be64 r12; 7451 } control; 7452 } dcb; 7453 struct fw_port_l1cfg32 { 7454 __be32 rcap32; 7455 __be32 r; 7456 } l1cfg32; 7457 struct fw_port_info32 { 7458 __be32 lstatus32_to_cbllen32; 7459 __be32 auxlinfo32_mtu32; 7460 __be32 linkattr32; 7461 __be32 pcaps32; 7462 __be32 acaps32; 7463 __be32 lpacaps32; 7464 } info32; 7465 } u; 7466 }; 7467 7468 #define S_FW_PORT_CMD_READ 22 7469 #define M_FW_PORT_CMD_READ 0x1 7470 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 7471 #define G_FW_PORT_CMD_READ(x) \ 7472 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 7473 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 7474 7475 #define S_FW_PORT_CMD_PORTID 0 7476 #define M_FW_PORT_CMD_PORTID 0xf 7477 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 7478 #define G_FW_PORT_CMD_PORTID(x) \ 7479 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 7480 7481 #define S_FW_PORT_CMD_ACTION 16 7482 #define M_FW_PORT_CMD_ACTION 0xffff 7483 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 7484 #define G_FW_PORT_CMD_ACTION(x) \ 7485 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 7486 7487 #define S_FW_PORT_CMD_OVLAN3 7 7488 #define M_FW_PORT_CMD_OVLAN3 0x1 7489 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 7490 #define G_FW_PORT_CMD_OVLAN3(x) \ 7491 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 7492 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 7493 7494 #define S_FW_PORT_CMD_OVLAN2 6 7495 #define M_FW_PORT_CMD_OVLAN2 0x1 7496 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 7497 #define G_FW_PORT_CMD_OVLAN2(x) \ 7498 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 7499 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 7500 7501 #define S_FW_PORT_CMD_OVLAN1 5 7502 #define M_FW_PORT_CMD_OVLAN1 0x1 7503 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 7504 #define G_FW_PORT_CMD_OVLAN1(x) \ 7505 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 7506 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 7507 7508 #define S_FW_PORT_CMD_OVLAN0 4 7509 #define M_FW_PORT_CMD_OVLAN0 0x1 7510 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 7511 #define G_FW_PORT_CMD_OVLAN0(x) \ 7512 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 7513 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 7514 7515 #define S_FW_PORT_CMD_IVLAN0 3 7516 #define M_FW_PORT_CMD_IVLAN0 0x1 7517 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 7518 #define G_FW_PORT_CMD_IVLAN0(x) \ 7519 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 7520 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 7521 7522 #define S_FW_PORT_CMD_OVLAN_FILT 2 7523 #define M_FW_PORT_CMD_OVLAN_FILT 0x1 7524 #define V_FW_PORT_CMD_OVLAN_FILT(x) ((x) << S_FW_PORT_CMD_OVLAN_FILT) 7525 #define G_FW_PORT_CMD_OVLAN_FILT(x) \ 7526 (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT) 7527 #define F_FW_PORT_CMD_OVLAN_FILT V_FW_PORT_CMD_OVLAN_FILT(1U) 7528 7529 #define S_FW_PORT_CMD_TXIPG 3 7530 #define M_FW_PORT_CMD_TXIPG 0x1fff 7531 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 7532 #define G_FW_PORT_CMD_TXIPG(x) \ 7533 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 7534 7535 #define S_FW_PORT_CMD_FORCE_PINFO 0 7536 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 7537 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 7538 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 7539 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 7540 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 7541 7542 #define S_FW_PORT_CMD_LSTATUS 31 7543 #define M_FW_PORT_CMD_LSTATUS 0x1 7544 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 7545 #define G_FW_PORT_CMD_LSTATUS(x) \ 7546 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 7547 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 7548 7549 #define S_FW_PORT_CMD_LSPEED 24 7550 #define M_FW_PORT_CMD_LSPEED 0x3f 7551 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 7552 #define G_FW_PORT_CMD_LSPEED(x) \ 7553 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 7554 7555 #define S_FW_PORT_CMD_TXPAUSE 23 7556 #define M_FW_PORT_CMD_TXPAUSE 0x1 7557 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 7558 #define G_FW_PORT_CMD_TXPAUSE(x) \ 7559 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 7560 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 7561 7562 #define S_FW_PORT_CMD_RXPAUSE 22 7563 #define M_FW_PORT_CMD_RXPAUSE 0x1 7564 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 7565 #define G_FW_PORT_CMD_RXPAUSE(x) \ 7566 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 7567 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 7568 7569 #define S_FW_PORT_CMD_MDIOCAP 21 7570 #define M_FW_PORT_CMD_MDIOCAP 0x1 7571 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 7572 #define G_FW_PORT_CMD_MDIOCAP(x) \ 7573 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 7574 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 7575 7576 #define S_FW_PORT_CMD_MDIOADDR 16 7577 #define M_FW_PORT_CMD_MDIOADDR 0x1f 7578 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 7579 #define G_FW_PORT_CMD_MDIOADDR(x) \ 7580 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 7581 7582 #define S_FW_PORT_CMD_LPTXPAUSE 15 7583 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 7584 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 7585 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 7586 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 7587 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 7588 7589 #define S_FW_PORT_CMD_LPRXPAUSE 14 7590 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 7591 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 7592 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 7593 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 7594 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 7595 7596 #define S_FW_PORT_CMD_PTYPE 8 7597 #define M_FW_PORT_CMD_PTYPE 0x1f 7598 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 7599 #define G_FW_PORT_CMD_PTYPE(x) \ 7600 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 7601 7602 #define S_FW_PORT_CMD_LINKDNRC 5 7603 #define M_FW_PORT_CMD_LINKDNRC 0x7 7604 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 7605 #define G_FW_PORT_CMD_LINKDNRC(x) \ 7606 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 7607 7608 #define S_FW_PORT_CMD_MODTYPE 0 7609 #define M_FW_PORT_CMD_MODTYPE 0x1f 7610 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 7611 #define G_FW_PORT_CMD_MODTYPE(x) \ 7612 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 7613 7614 #define S_FW_PORT_AUXLINFO_KX4 2 7615 #define M_FW_PORT_AUXLINFO_KX4 0x1 7616 #define V_FW_PORT_AUXLINFO_KX4(x) \ 7617 ((x) << S_FW_PORT_AUXLINFO_KX4) 7618 #define G_FW_PORT_AUXLINFO_KX4(x) \ 7619 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 7620 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 7621 7622 #define S_FW_PORT_AUXLINFO_KR 1 7623 #define M_FW_PORT_AUXLINFO_KR 0x1 7624 #define V_FW_PORT_AUXLINFO_KR(x) \ 7625 ((x) << S_FW_PORT_AUXLINFO_KR) 7626 #define G_FW_PORT_AUXLINFO_KR(x) \ 7627 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 7628 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 7629 7630 #define S_FW_PORT_CMD_DCBXDIS 7 7631 #define M_FW_PORT_CMD_DCBXDIS 0x1 7632 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 7633 #define G_FW_PORT_CMD_DCBXDIS(x) \ 7634 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 7635 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 7636 7637 #define S_FW_PORT_CMD_APPLY 7 7638 #define M_FW_PORT_CMD_APPLY 0x1 7639 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 7640 #define G_FW_PORT_CMD_APPLY(x) \ 7641 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 7642 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 7643 7644 #define S_FW_PORT_CMD_ALL_SYNCD 7 7645 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 7646 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 7647 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 7648 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 7649 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 7650 7651 #define S_FW_PORT_CMD_DCB_VERSION 12 7652 #define M_FW_PORT_CMD_DCB_VERSION 0x7 7653 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 7654 #define G_FW_PORT_CMD_DCB_VERSION(x) \ 7655 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 7656 7657 #define S_FW_PORT_CMD_PFC_STATE 8 7658 #define M_FW_PORT_CMD_PFC_STATE 0xf 7659 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 7660 #define G_FW_PORT_CMD_PFC_STATE(x) \ 7661 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 7662 7663 #define S_FW_PORT_CMD_ETS_STATE 4 7664 #define M_FW_PORT_CMD_ETS_STATE 0xf 7665 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 7666 #define G_FW_PORT_CMD_ETS_STATE(x) \ 7667 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 7668 7669 #define S_FW_PORT_CMD_APP_STATE 0 7670 #define M_FW_PORT_CMD_APP_STATE 0xf 7671 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 7672 #define G_FW_PORT_CMD_APP_STATE(x) \ 7673 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 7674 7675 #define S_FW_PORT_CMD_LSTATUS32 31 7676 #define M_FW_PORT_CMD_LSTATUS32 0x1 7677 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 7678 #define G_FW_PORT_CMD_LSTATUS32(x) \ 7679 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32) 7680 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 7681 7682 #define S_FW_PORT_CMD_LINKDNRC32 28 7683 #define M_FW_PORT_CMD_LINKDNRC32 0x7 7684 #define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32) 7685 #define G_FW_PORT_CMD_LINKDNRC32(x) \ 7686 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 7687 7688 #define S_FW_PORT_CMD_DCBXDIS32 27 7689 #define M_FW_PORT_CMD_DCBXDIS32 0x1 7690 #define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32) 7691 #define G_FW_PORT_CMD_DCBXDIS32(x) \ 7692 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32) 7693 #define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U) 7694 7695 #define S_FW_PORT_CMD_MDIOCAP32 26 7696 #define M_FW_PORT_CMD_MDIOCAP32 0x1 7697 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 7698 #define G_FW_PORT_CMD_MDIOCAP32(x) \ 7699 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32) 7700 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 7701 7702 #define S_FW_PORT_CMD_MDIOADDR32 21 7703 #define M_FW_PORT_CMD_MDIOADDR32 0x1f 7704 #define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32) 7705 #define G_FW_PORT_CMD_MDIOADDR32(x) \ 7706 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 7707 7708 #define S_FW_PORT_CMD_PORTTYPE32 13 7709 #define M_FW_PORT_CMD_PORTTYPE32 0xff 7710 #define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32) 7711 #define G_FW_PORT_CMD_PORTTYPE32(x) \ 7712 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 7713 7714 #define S_FW_PORT_CMD_MODTYPE32 8 7715 #define M_FW_PORT_CMD_MODTYPE32 0x1f 7716 #define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32) 7717 #define G_FW_PORT_CMD_MODTYPE32(x) \ 7718 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 7719 7720 #define S_FW_PORT_CMD_CBLLEN32 0 7721 #define M_FW_PORT_CMD_CBLLEN32 0xff 7722 #define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32) 7723 #define G_FW_PORT_CMD_CBLLEN32(x) \ 7724 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32) 7725 7726 #define S_FW_PORT_CMD_AUXLINFO32 24 7727 #define M_FW_PORT_CMD_AUXLINFO32 0xff 7728 #define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32) 7729 #define G_FW_PORT_CMD_AUXLINFO32(x) \ 7730 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32) 7731 7732 #define S_FW_PORT_AUXLINFO32_KX4 2 7733 #define M_FW_PORT_AUXLINFO32_KX4 0x1 7734 #define V_FW_PORT_AUXLINFO32_KX4(x) \ 7735 ((x) << S_FW_PORT_AUXLINFO32_KX4) 7736 #define G_FW_PORT_AUXLINFO32_KX4(x) \ 7737 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4) 7738 #define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U) 7739 7740 #define S_FW_PORT_AUXLINFO32_KR 1 7741 #define M_FW_PORT_AUXLINFO32_KR 0x1 7742 #define V_FW_PORT_AUXLINFO32_KR(x) \ 7743 ((x) << S_FW_PORT_AUXLINFO32_KR) 7744 #define G_FW_PORT_AUXLINFO32_KR(x) \ 7745 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR) 7746 #define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U) 7747 7748 #define S_FW_PORT_CMD_MTU32 0 7749 #define M_FW_PORT_CMD_MTU32 0xffff 7750 #define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32) 7751 #define G_FW_PORT_CMD_MTU32(x) \ 7752 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32) 7753 7754 /* 7755 * These are configured into the VPD and hence tools that generate 7756 * VPD may use this enumeration. 7757 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 7758 * 7759 * REMEMBER: 7760 * Update the Common Code t4_hw.c:t4_get_port_type_description() 7761 * with any new Firmware Port Technology Types! 7762 */ 7763 enum fw_port_type { 7764 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 7765 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 7766 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 7767 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 7768 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 7769 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 7770 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 7771 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 7772 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 7773 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 7774 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 7775 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 7776 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 7777 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 7778 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 7779 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 7780 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 7781 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 7782 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 7783 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 7784 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 7785 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 7786 FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/ 7787 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 7788 }; 7789 7790 /* These are read from module's EEPROM and determined once the 7791 module is inserted. */ 7792 enum fw_port_module_type { 7793 FW_PORT_MOD_TYPE_NA = 0x0, 7794 FW_PORT_MOD_TYPE_LR = 0x1, 7795 FW_PORT_MOD_TYPE_SR = 0x2, 7796 FW_PORT_MOD_TYPE_ER = 0x3, 7797 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 7798 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 7799 FW_PORT_MOD_TYPE_LRM = 0x6, 7800 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 7801 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 7802 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 7803 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 7804 }; 7805 7806 /* used by FW and tools may use this to generate VPD */ 7807 enum fw_port_mod_sub_type { 7808 FW_PORT_MOD_SUB_TYPE_NA, 7809 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 7810 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 7811 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 7812 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 7813 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 7814 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 7815 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 7816 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 7817 7818 /* 7819 * The following will never been in the VPD. They are TWINAX cable 7820 * lengths decoded from SFP+ module i2c PROMs. These should almost 7821 * certainly go somewhere else ... 7822 */ 7823 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 7824 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 7825 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 7826 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 7827 }; 7828 7829 /* link down reason codes (3b) */ 7830 enum fw_port_link_dn_rc { 7831 FW_PORT_LINK_DN_RC_NONE, 7832 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 7833 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 7834 FW_PORT_LINK_DN_RESERVED3, 7835 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 7836 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 7837 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 7838 FW_PORT_LINK_DN_RESERVED7 7839 }; 7840 enum fw_port_stats_tx_index { 7841 FW_STAT_TX_PORT_BYTES_IX = 0, 7842 FW_STAT_TX_PORT_FRAMES_IX, 7843 FW_STAT_TX_PORT_BCAST_IX, 7844 FW_STAT_TX_PORT_MCAST_IX, 7845 FW_STAT_TX_PORT_UCAST_IX, 7846 FW_STAT_TX_PORT_ERROR_IX, 7847 FW_STAT_TX_PORT_64B_IX, 7848 FW_STAT_TX_PORT_65B_127B_IX, 7849 FW_STAT_TX_PORT_128B_255B_IX, 7850 FW_STAT_TX_PORT_256B_511B_IX, 7851 FW_STAT_TX_PORT_512B_1023B_IX, 7852 FW_STAT_TX_PORT_1024B_1518B_IX, 7853 FW_STAT_TX_PORT_1519B_MAX_IX, 7854 FW_STAT_TX_PORT_DROP_IX, 7855 FW_STAT_TX_PORT_PAUSE_IX, 7856 FW_STAT_TX_PORT_PPP0_IX, 7857 FW_STAT_TX_PORT_PPP1_IX, 7858 FW_STAT_TX_PORT_PPP2_IX, 7859 FW_STAT_TX_PORT_PPP3_IX, 7860 FW_STAT_TX_PORT_PPP4_IX, 7861 FW_STAT_TX_PORT_PPP5_IX, 7862 FW_STAT_TX_PORT_PPP6_IX, 7863 FW_STAT_TX_PORT_PPP7_IX, 7864 FW_NUM_PORT_TX_STATS 7865 }; 7866 7867 enum fw_port_stat_rx_index { 7868 FW_STAT_RX_PORT_BYTES_IX = 0, 7869 FW_STAT_RX_PORT_FRAMES_IX, 7870 FW_STAT_RX_PORT_BCAST_IX, 7871 FW_STAT_RX_PORT_MCAST_IX, 7872 FW_STAT_RX_PORT_UCAST_IX, 7873 FW_STAT_RX_PORT_MTU_ERROR_IX, 7874 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 7875 FW_STAT_RX_PORT_CRC_ERROR_IX, 7876 FW_STAT_RX_PORT_LEN_ERROR_IX, 7877 FW_STAT_RX_PORT_SYM_ERROR_IX, 7878 FW_STAT_RX_PORT_64B_IX, 7879 FW_STAT_RX_PORT_65B_127B_IX, 7880 FW_STAT_RX_PORT_128B_255B_IX, 7881 FW_STAT_RX_PORT_256B_511B_IX, 7882 FW_STAT_RX_PORT_512B_1023B_IX, 7883 FW_STAT_RX_PORT_1024B_1518B_IX, 7884 FW_STAT_RX_PORT_1519B_MAX_IX, 7885 FW_STAT_RX_PORT_PAUSE_IX, 7886 FW_STAT_RX_PORT_PPP0_IX, 7887 FW_STAT_RX_PORT_PPP1_IX, 7888 FW_STAT_RX_PORT_PPP2_IX, 7889 FW_STAT_RX_PORT_PPP3_IX, 7890 FW_STAT_RX_PORT_PPP4_IX, 7891 FW_STAT_RX_PORT_PPP5_IX, 7892 FW_STAT_RX_PORT_PPP6_IX, 7893 FW_STAT_RX_PORT_PPP7_IX, 7894 FW_STAT_RX_PORT_LESS_64B_IX, 7895 FW_STAT_RX_PORT_MAC_ERROR_IX, 7896 FW_NUM_PORT_RX_STATS 7897 }; 7898 /* port stats */ 7899 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 7900 FW_NUM_PORT_RX_STATS) 7901 7902 7903 struct fw_port_stats_cmd { 7904 __be32 op_to_portid; 7905 __be32 retval_len16; 7906 union fw_port_stats { 7907 struct fw_port_stats_ctl { 7908 __u8 nstats_bg_bm; 7909 __u8 tx_ix; 7910 __be16 r6; 7911 __be32 r7; 7912 __be64 stat0; 7913 __be64 stat1; 7914 __be64 stat2; 7915 __be64 stat3; 7916 __be64 stat4; 7917 __be64 stat5; 7918 } ctl; 7919 struct fw_port_stats_all { 7920 __be64 tx_bytes; 7921 __be64 tx_frames; 7922 __be64 tx_bcast; 7923 __be64 tx_mcast; 7924 __be64 tx_ucast; 7925 __be64 tx_error; 7926 __be64 tx_64b; 7927 __be64 tx_65b_127b; 7928 __be64 tx_128b_255b; 7929 __be64 tx_256b_511b; 7930 __be64 tx_512b_1023b; 7931 __be64 tx_1024b_1518b; 7932 __be64 tx_1519b_max; 7933 __be64 tx_drop; 7934 __be64 tx_pause; 7935 __be64 tx_ppp0; 7936 __be64 tx_ppp1; 7937 __be64 tx_ppp2; 7938 __be64 tx_ppp3; 7939 __be64 tx_ppp4; 7940 __be64 tx_ppp5; 7941 __be64 tx_ppp6; 7942 __be64 tx_ppp7; 7943 __be64 rx_bytes; 7944 __be64 rx_frames; 7945 __be64 rx_bcast; 7946 __be64 rx_mcast; 7947 __be64 rx_ucast; 7948 __be64 rx_mtu_error; 7949 __be64 rx_mtu_crc_error; 7950 __be64 rx_crc_error; 7951 __be64 rx_len_error; 7952 __be64 rx_sym_error; 7953 __be64 rx_64b; 7954 __be64 rx_65b_127b; 7955 __be64 rx_128b_255b; 7956 __be64 rx_256b_511b; 7957 __be64 rx_512b_1023b; 7958 __be64 rx_1024b_1518b; 7959 __be64 rx_1519b_max; 7960 __be64 rx_pause; 7961 __be64 rx_ppp0; 7962 __be64 rx_ppp1; 7963 __be64 rx_ppp2; 7964 __be64 rx_ppp3; 7965 __be64 rx_ppp4; 7966 __be64 rx_ppp5; 7967 __be64 rx_ppp6; 7968 __be64 rx_ppp7; 7969 __be64 rx_less_64b; 7970 __be64 rx_bg_drop; 7971 __be64 rx_bg_trunc; 7972 } all; 7973 } u; 7974 }; 7975 7976 #define S_FW_PORT_STATS_CMD_NSTATS 4 7977 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 7978 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 7979 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 7980 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 7981 7982 #define S_FW_PORT_STATS_CMD_BG_BM 0 7983 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 7984 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 7985 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 7986 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 7987 7988 #define S_FW_PORT_STATS_CMD_TX 7 7989 #define M_FW_PORT_STATS_CMD_TX 0x1 7990 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 7991 #define G_FW_PORT_STATS_CMD_TX(x) \ 7992 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 7993 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 7994 7995 #define S_FW_PORT_STATS_CMD_IX 0 7996 #define M_FW_PORT_STATS_CMD_IX 0x3f 7997 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 7998 #define G_FW_PORT_STATS_CMD_IX(x) \ 7999 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 8000 8001 /* port loopback stats */ 8002 #define FW_NUM_LB_STATS 14 8003 enum fw_port_lb_stats_index { 8004 FW_STAT_LB_PORT_BYTES_IX, 8005 FW_STAT_LB_PORT_FRAMES_IX, 8006 FW_STAT_LB_PORT_BCAST_IX, 8007 FW_STAT_LB_PORT_MCAST_IX, 8008 FW_STAT_LB_PORT_UCAST_IX, 8009 FW_STAT_LB_PORT_ERROR_IX, 8010 FW_STAT_LB_PORT_64B_IX, 8011 FW_STAT_LB_PORT_65B_127B_IX, 8012 FW_STAT_LB_PORT_128B_255B_IX, 8013 FW_STAT_LB_PORT_256B_511B_IX, 8014 FW_STAT_LB_PORT_512B_1023B_IX, 8015 FW_STAT_LB_PORT_1024B_1518B_IX, 8016 FW_STAT_LB_PORT_1519B_MAX_IX, 8017 FW_STAT_LB_PORT_DROP_FRAMES_IX 8018 }; 8019 8020 struct fw_port_lb_stats_cmd { 8021 __be32 op_to_lbport; 8022 __be32 retval_len16; 8023 union fw_port_lb_stats { 8024 struct fw_port_lb_stats_ctl { 8025 __u8 nstats_bg_bm; 8026 __u8 ix_pkd; 8027 __be16 r6; 8028 __be32 r7; 8029 __be64 stat0; 8030 __be64 stat1; 8031 __be64 stat2; 8032 __be64 stat3; 8033 __be64 stat4; 8034 __be64 stat5; 8035 } ctl; 8036 struct fw_port_lb_stats_all { 8037 __be64 tx_bytes; 8038 __be64 tx_frames; 8039 __be64 tx_bcast; 8040 __be64 tx_mcast; 8041 __be64 tx_ucast; 8042 __be64 tx_error; 8043 __be64 tx_64b; 8044 __be64 tx_65b_127b; 8045 __be64 tx_128b_255b; 8046 __be64 tx_256b_511b; 8047 __be64 tx_512b_1023b; 8048 __be64 tx_1024b_1518b; 8049 __be64 tx_1519b_max; 8050 __be64 rx_lb_drop; 8051 __be64 rx_lb_trunc; 8052 } all; 8053 } u; 8054 }; 8055 8056 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 8057 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 8058 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 8059 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 8060 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 8061 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 8062 8063 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 8064 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 8065 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 8066 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 8067 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 8068 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 8069 8070 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 8071 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 8072 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 8073 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 8074 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 8075 8076 #define S_FW_PORT_LB_STATS_CMD_IX 0 8077 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 8078 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 8079 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 8080 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 8081 8082 /* Trace related defines */ 8083 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 8084 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 8085 8086 struct fw_port_trace_cmd { 8087 __be32 op_to_portid; 8088 __be32 retval_len16; 8089 __be16 traceen_to_pciech; 8090 __be16 qnum; 8091 __be32 r5; 8092 }; 8093 8094 #define S_FW_PORT_TRACE_CMD_PORTID 0 8095 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 8096 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 8097 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 8098 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 8099 8100 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 8101 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 8102 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 8103 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 8104 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 8105 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 8106 8107 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 8108 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 8109 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 8110 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 8111 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 8112 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 8113 8114 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 8115 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 8116 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 8117 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 8118 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 8119 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 8120 8121 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 8122 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 8123 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 8124 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 8125 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 8126 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 8127 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 8128 8129 #define S_FW_PORT_TRACE_CMD_PCIECH 6 8130 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 8131 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 8132 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 8133 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 8134 8135 struct fw_port_trace_mmap_cmd { 8136 __be32 op_to_portid; 8137 __be32 retval_len16; 8138 __be32 fid_to_skipoffset; 8139 __be32 minpktsize_capturemax; 8140 __u8 map[224]; 8141 }; 8142 8143 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 8144 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 8145 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 8146 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 8147 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 8148 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 8149 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 8150 8151 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 8152 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 8153 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 8154 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 8155 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 8156 8157 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 8158 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 8159 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 8160 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 8161 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 8162 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 8163 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 8164 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 8165 8166 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 8167 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 8168 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 8169 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 8170 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 8171 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 8172 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 8173 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 8174 8175 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 8176 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 8177 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 8178 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 8179 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 8180 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 8181 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 8182 8183 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 8184 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 8185 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 8186 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 8187 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 8188 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 8189 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 8190 8191 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 8192 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 8193 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 8194 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 8195 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 8196 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 8197 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 8198 8199 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 8200 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 8201 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 8202 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 8203 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 8204 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 8205 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 8206 8207 enum fw_ptp_subop { 8208 8209 /* none */ 8210 FW_PTP_SC_INIT_TIMER = 0x00, 8211 FW_PTP_SC_TX_TYPE = 0x01, 8212 8213 /* init */ 8214 FW_PTP_SC_RXTIME_STAMP = 0x08, 8215 FW_PTP_SC_RDRX_TYPE = 0x09, 8216 8217 /* ts */ 8218 FW_PTP_SC_ADJ_FREQ = 0x10, 8219 FW_PTP_SC_ADJ_TIME = 0x11, 8220 FW_PTP_SC_ADJ_FTIME = 0x12, 8221 FW_PTP_SC_WALL_CLOCK = 0x13, 8222 FW_PTP_SC_GET_TIME = 0x14, 8223 FW_PTP_SC_SET_TIME = 0x15, 8224 }; 8225 8226 struct fw_ptp_cmd { 8227 __be32 op_to_portid; 8228 __be32 retval_len16; 8229 union fw_ptp { 8230 struct fw_ptp_sc { 8231 __u8 sc; 8232 __u8 r3[7]; 8233 } scmd; 8234 struct fw_ptp_init { 8235 __u8 sc; 8236 __u8 txchan; 8237 __be16 absid; 8238 __be16 mode; 8239 __be16 ptp_rx_ctrl_pkd; 8240 } init; 8241 struct fw_ptp_ts { 8242 __u8 sc; 8243 __u8 sign; 8244 __be16 r3; 8245 __be32 ppb; 8246 __be64 tm; 8247 } ts; 8248 } u; 8249 __be64 r3; 8250 }; 8251 8252 #define S_FW_PTP_CMD_PORTID 0 8253 #define M_FW_PTP_CMD_PORTID 0xf 8254 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 8255 #define G_FW_PTP_CMD_PORTID(x) \ 8256 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 8257 8258 #define S_FW_PTP_CMD_PTP_RX_CTRL 15 8259 #define M_FW_PTP_CMD_PTP_RX_CTRL 0x1 8260 #define V_FW_PTP_CMD_PTP_RX_CTRL(x) ((x) << S_FW_PTP_CMD_PTP_RX_CTRL) 8261 #define G_FW_PTP_CMD_PTP_RX_CTRL(x) \ 8262 (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL) 8263 #define F_FW_PTP_CMD_PTP_RX_CTRL V_FW_PTP_CMD_PTP_RX_CTRL(1U) 8264 8265 8266 struct fw_rss_ind_tbl_cmd { 8267 __be32 op_to_viid; 8268 __be32 retval_len16; 8269 __be16 niqid; 8270 __be16 startidx; 8271 __be32 r3; 8272 __be32 iq0_to_iq2; 8273 __be32 iq3_to_iq5; 8274 __be32 iq6_to_iq8; 8275 __be32 iq9_to_iq11; 8276 __be32 iq12_to_iq14; 8277 __be32 iq15_to_iq17; 8278 __be32 iq18_to_iq20; 8279 __be32 iq21_to_iq23; 8280 __be32 iq24_to_iq26; 8281 __be32 iq27_to_iq29; 8282 __be32 iq30_iq31; 8283 __be32 r15_lo; 8284 }; 8285 8286 #define S_FW_RSS_IND_TBL_CMD_VIID 0 8287 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 8288 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 8289 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 8290 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 8291 8292 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 8293 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 8294 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 8295 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 8296 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 8297 8298 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 8299 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 8300 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 8301 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 8302 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 8303 8304 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 8305 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 8306 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 8307 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 8308 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 8309 8310 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 8311 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 8312 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 8313 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 8314 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 8315 8316 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 8317 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 8318 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 8319 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 8320 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 8321 8322 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 8323 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 8324 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 8325 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 8326 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 8327 8328 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 8329 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 8330 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 8331 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 8332 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 8333 8334 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 8335 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 8336 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 8337 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 8338 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 8339 8340 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 8341 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 8342 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 8343 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 8344 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 8345 8346 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 8347 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 8348 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 8349 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 8350 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 8351 8352 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 8353 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 8354 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 8355 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 8356 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 8357 8358 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 8359 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 8360 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 8361 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 8362 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 8363 8364 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 8365 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 8366 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 8367 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 8368 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 8369 8370 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 8371 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 8372 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 8373 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 8374 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 8375 8376 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 8377 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 8378 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 8379 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 8380 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 8381 8382 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 8383 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 8384 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 8385 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 8386 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 8387 8388 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 8389 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 8390 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 8391 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 8392 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 8393 8394 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 8395 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 8396 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 8397 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 8398 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 8399 8400 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 8401 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 8402 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 8403 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 8404 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 8405 8406 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 8407 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 8408 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 8409 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 8410 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 8411 8412 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 8413 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 8414 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 8415 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 8416 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 8417 8418 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 8419 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 8420 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 8421 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 8422 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 8423 8424 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 8425 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 8426 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 8427 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 8428 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 8429 8430 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 8431 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 8432 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 8433 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 8434 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 8435 8436 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 8437 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 8438 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 8439 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 8440 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 8441 8442 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 8443 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 8444 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 8445 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 8446 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 8447 8448 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 8449 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 8450 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 8451 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 8452 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 8453 8454 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 8455 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 8456 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 8457 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 8458 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 8459 8460 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 8461 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 8462 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 8463 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 8464 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 8465 8466 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 8467 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 8468 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 8469 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 8470 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 8471 8472 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 8473 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 8474 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 8475 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 8476 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 8477 8478 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 8479 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 8480 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 8481 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 8482 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 8483 8484 struct fw_rss_glb_config_cmd { 8485 __be32 op_to_write; 8486 __be32 retval_len16; 8487 union fw_rss_glb_config { 8488 struct fw_rss_glb_config_manual { 8489 __be32 mode_pkd; 8490 __be32 r3; 8491 __be64 r4; 8492 __be64 r5; 8493 } manual; 8494 struct fw_rss_glb_config_basicvirtual { 8495 __be32 mode_keymode; 8496 __be32 synmapen_to_hashtoeplitz; 8497 __be64 r8; 8498 __be64 r9; 8499 } basicvirtual; 8500 } u; 8501 }; 8502 8503 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 8504 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 8505 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 8506 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 8507 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 8508 8509 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 8510 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 8511 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 8512 8513 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 8514 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 8515 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8516 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8517 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8518 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 8519 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8520 8521 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 8522 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 8523 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 8524 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 8525 8526 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 8527 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 8528 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8529 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8530 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8531 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 8532 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8533 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 8534 8535 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 8536 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 8537 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8538 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8539 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8540 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 8541 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8542 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 8543 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 8544 8545 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 8546 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 8547 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8548 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8549 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8550 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 8551 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8552 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 8553 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 8554 8555 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 8556 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 8557 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8558 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8559 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8560 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 8561 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8562 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 8563 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 8564 8565 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 8566 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 8567 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8568 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8569 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8570 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 8571 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8572 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 8573 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 8574 8575 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 8576 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 8577 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8578 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8579 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8580 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 8581 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8582 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 8583 8584 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 8585 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 8586 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8587 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8588 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8589 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 8590 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8591 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 8592 8593 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 8594 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 8595 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8596 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8597 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8598 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 8599 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8600 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 8601 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 8602 8603 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 8604 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 8605 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8606 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8607 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8608 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 8609 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8610 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 8611 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 8612 8613 struct fw_rss_vi_config_cmd { 8614 __be32 op_to_viid; 8615 __be32 retval_len16; 8616 union fw_rss_vi_config { 8617 struct fw_rss_vi_config_manual { 8618 __be64 r3; 8619 __be64 r4; 8620 __be64 r5; 8621 } manual; 8622 struct fw_rss_vi_config_basicvirtual { 8623 __be32 r6; 8624 __be32 defaultq_to_udpen; 8625 __be32 secretkeyidx_pkd; 8626 __be32 secretkeyxor; 8627 __be64 r10; 8628 } basicvirtual; 8629 } u; 8630 }; 8631 8632 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 8633 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 8634 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 8635 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 8636 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 8637 8638 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 8639 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 8640 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8641 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8642 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8643 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 8644 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8645 8646 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 8647 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 8648 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8649 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8650 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8651 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 8652 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8653 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 8654 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 8655 8656 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 8657 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 8658 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8659 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8660 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8661 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 8662 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8663 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 8664 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 8665 8666 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 8667 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 8668 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8669 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8670 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8671 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 8672 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8673 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 8674 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 8675 8676 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 8677 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 8678 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8679 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8680 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8681 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 8682 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8683 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 8684 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 8685 8686 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 8687 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 8688 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 8689 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 8690 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 8691 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 8692 8693 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 8694 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 8695 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8696 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8697 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8698 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 8699 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8700 8701 enum fw_sched_sc { 8702 FW_SCHED_SC_CONFIG = 0, 8703 FW_SCHED_SC_PARAMS = 1, 8704 }; 8705 8706 enum fw_sched_type { 8707 FW_SCHED_TYPE_PKTSCHED = 0, 8708 FW_SCHED_TYPE_STREAMSCHED = 1, 8709 }; 8710 8711 enum fw_sched_params_level { 8712 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 8713 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 8714 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 8715 }; 8716 8717 enum fw_sched_params_mode { 8718 FW_SCHED_PARAMS_MODE_CLASS = 0, 8719 FW_SCHED_PARAMS_MODE_FLOW = 1, 8720 }; 8721 8722 enum fw_sched_params_unit { 8723 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 8724 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 8725 }; 8726 8727 enum fw_sched_params_rate { 8728 FW_SCHED_PARAMS_RATE_REL = 0, 8729 FW_SCHED_PARAMS_RATE_ABS = 1, 8730 }; 8731 8732 struct fw_sched_cmd { 8733 __be32 op_to_write; 8734 __be32 retval_len16; 8735 union fw_sched { 8736 struct fw_sched_config { 8737 __u8 sc; 8738 __u8 type; 8739 __u8 minmaxen; 8740 __u8 r3[5]; 8741 __u8 nclasses[4]; 8742 __be32 r4; 8743 } config; 8744 struct fw_sched_params { 8745 __u8 sc; 8746 __u8 type; 8747 __u8 level; 8748 __u8 mode; 8749 __u8 unit; 8750 __u8 rate; 8751 __u8 ch; 8752 __u8 cl; 8753 __be32 min; 8754 __be32 max; 8755 __be16 weight; 8756 __be16 pktsize; 8757 __be16 burstsize; 8758 __be16 r4; 8759 } params; 8760 } u; 8761 }; 8762 8763 /* 8764 * length of the formatting string 8765 */ 8766 #define FW_DEVLOG_FMT_LEN 192 8767 8768 /* 8769 * maximum number of the formatting string parameters 8770 */ 8771 #define FW_DEVLOG_FMT_PARAMS_NUM 8 8772 8773 /* 8774 * priority levels 8775 */ 8776 enum fw_devlog_level { 8777 FW_DEVLOG_LEVEL_EMERG = 0x0, 8778 FW_DEVLOG_LEVEL_CRIT = 0x1, 8779 FW_DEVLOG_LEVEL_ERR = 0x2, 8780 FW_DEVLOG_LEVEL_NOTICE = 0x3, 8781 FW_DEVLOG_LEVEL_INFO = 0x4, 8782 FW_DEVLOG_LEVEL_DEBUG = 0x5, 8783 FW_DEVLOG_LEVEL_MAX = 0x5, 8784 }; 8785 8786 /* 8787 * facilities that may send a log message 8788 */ 8789 enum fw_devlog_facility { 8790 FW_DEVLOG_FACILITY_CORE = 0x00, 8791 FW_DEVLOG_FACILITY_CF = 0x01, 8792 FW_DEVLOG_FACILITY_SCHED = 0x02, 8793 FW_DEVLOG_FACILITY_TIMER = 0x04, 8794 FW_DEVLOG_FACILITY_RES = 0x06, 8795 FW_DEVLOG_FACILITY_HW = 0x08, 8796 FW_DEVLOG_FACILITY_FLR = 0x10, 8797 FW_DEVLOG_FACILITY_DMAQ = 0x12, 8798 FW_DEVLOG_FACILITY_PHY = 0x14, 8799 FW_DEVLOG_FACILITY_MAC = 0x16, 8800 FW_DEVLOG_FACILITY_PORT = 0x18, 8801 FW_DEVLOG_FACILITY_VI = 0x1A, 8802 FW_DEVLOG_FACILITY_FILTER = 0x1C, 8803 FW_DEVLOG_FACILITY_ACL = 0x1E, 8804 FW_DEVLOG_FACILITY_TM = 0x20, 8805 FW_DEVLOG_FACILITY_QFC = 0x22, 8806 FW_DEVLOG_FACILITY_DCB = 0x24, 8807 FW_DEVLOG_FACILITY_ETH = 0x26, 8808 FW_DEVLOG_FACILITY_OFLD = 0x28, 8809 FW_DEVLOG_FACILITY_RI = 0x2A, 8810 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 8811 FW_DEVLOG_FACILITY_FCOE = 0x2E, 8812 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 8813 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 8814 FW_DEVLOG_FACILITY_CHNET = 0x34, 8815 FW_DEVLOG_FACILITY_COISCSI = 0x36, 8816 FW_DEVLOG_FACILITY_MAX = 0x38, 8817 }; 8818 8819 /* 8820 * log message format 8821 */ 8822 struct fw_devlog_e { 8823 __be64 timestamp; 8824 __be32 seqno; 8825 __be16 reserved1; 8826 __u8 level; 8827 __u8 facility; 8828 __u8 fmt[FW_DEVLOG_FMT_LEN]; 8829 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 8830 __be32 reserved3[4]; 8831 }; 8832 8833 struct fw_devlog_cmd { 8834 __be32 op_to_write; 8835 __be32 retval_len16; 8836 __u8 level; 8837 __u8 r2[7]; 8838 __be32 memtype_devlog_memaddr16_devlog; 8839 __be32 memsize_devlog; 8840 __be32 r3[2]; 8841 }; 8842 8843 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 8844 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 8845 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8846 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8847 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8848 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8849 8850 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 8851 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 8852 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8853 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8854 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8855 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 8856 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8857 8858 enum fw_watchdog_actions { 8859 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 8860 FW_WATCHDOG_ACTION_FLR = 1, 8861 FW_WATCHDOG_ACTION_BYPASS = 2, 8862 FW_WATCHDOG_ACTION_TMPCHK = 3, 8863 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 8864 8865 FW_WATCHDOG_ACTION_MAX = 5, 8866 }; 8867 8868 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 8869 8870 struct fw_watchdog_cmd { 8871 __be32 op_to_vfn; 8872 __be32 retval_len16; 8873 __be32 timeout; 8874 __be32 action; 8875 }; 8876 8877 #define S_FW_WATCHDOG_CMD_PFN 8 8878 #define M_FW_WATCHDOG_CMD_PFN 0x7 8879 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 8880 #define G_FW_WATCHDOG_CMD_PFN(x) \ 8881 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 8882 8883 #define S_FW_WATCHDOG_CMD_VFN 0 8884 #define M_FW_WATCHDOG_CMD_VFN 0xff 8885 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 8886 #define G_FW_WATCHDOG_CMD_VFN(x) \ 8887 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 8888 8889 struct fw_clip_cmd { 8890 __be32 op_to_write; 8891 __be32 alloc_to_len16; 8892 __be64 ip_hi; 8893 __be64 ip_lo; 8894 __be32 r4[2]; 8895 }; 8896 8897 #define S_FW_CLIP_CMD_ALLOC 31 8898 #define M_FW_CLIP_CMD_ALLOC 0x1 8899 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 8900 #define G_FW_CLIP_CMD_ALLOC(x) \ 8901 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 8902 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 8903 8904 #define S_FW_CLIP_CMD_FREE 30 8905 #define M_FW_CLIP_CMD_FREE 0x1 8906 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 8907 #define G_FW_CLIP_CMD_FREE(x) \ 8908 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 8909 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 8910 8911 #define S_FW_CLIP_CMD_INDEX 16 8912 #define M_FW_CLIP_CMD_INDEX 0x1fff 8913 #define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX) 8914 #define G_FW_CLIP_CMD_INDEX(x) \ 8915 (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX) 8916 8917 struct fw_clip2_cmd { 8918 __be32 op_to_write; 8919 __be32 alloc_to_len16; 8920 __be64 ip_hi; 8921 __be64 ip_lo; 8922 __be64 ipm_hi; 8923 __be64 ipm_lo; 8924 __be32 r4[2]; 8925 }; 8926 8927 /****************************************************************************** 8928 * F O i S C S I C O M M A N D s 8929 **************************************/ 8930 8931 #define FW_CHNET_IFACE_ADDR_MAX 3 8932 8933 enum fw_chnet_iface_cmd_subop { 8934 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 8935 8936 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 8937 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 8938 8939 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 8940 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 8941 8942 FW_CHNET_IFACE_CMD_SUBOP_MAX, 8943 }; 8944 8945 struct fw_chnet_iface_cmd { 8946 __be32 op_to_portid; 8947 __be32 retval_len16; 8948 __u8 subop; 8949 __u8 r2[2]; 8950 __u8 flags; 8951 __be32 ifid_ifstate; 8952 __be16 mtu; 8953 __be16 vlanid; 8954 __be32 r3; 8955 __be16 r4; 8956 __u8 mac[6]; 8957 }; 8958 8959 #define S_FW_CHNET_IFACE_CMD_PORTID 0 8960 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 8961 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 8962 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 8963 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 8964 8965 #define S_FW_CHNET_IFACE_CMD_RSS_IQID 16 8966 #define M_FW_CHNET_IFACE_CMD_RSS_IQID 0xffff 8967 #define V_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 8968 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID) 8969 #define G_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 8970 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID) 8971 8972 #define S_FW_CHNET_IFACE_CMD_RSS_IQID_F 0 8973 #define M_FW_CHNET_IFACE_CMD_RSS_IQID_F 0x1 8974 #define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 8975 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F) 8976 #define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 8977 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) & \ 8978 M_FW_CHNET_IFACE_CMD_RSS_IQID_F) 8979 #define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U) 8980 8981 #define S_FW_CHNET_IFACE_CMD_IFID 8 8982 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 8983 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 8984 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 8985 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 8986 8987 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 8988 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 8989 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 8990 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 8991 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 8992 8993 struct fw_fcoe_res_info_cmd { 8994 __be32 op_to_read; 8995 __be32 retval_len16; 8996 __be16 e_d_tov; 8997 __be16 r_a_tov_seq; 8998 __be16 r_a_tov_els; 8999 __be16 r_r_tov; 9000 __be32 max_xchgs; 9001 __be32 max_ssns; 9002 __be32 used_xchgs; 9003 __be32 used_ssns; 9004 __be32 max_fcfs; 9005 __be32 max_vnps; 9006 __be32 used_fcfs; 9007 __be32 used_vnps; 9008 }; 9009 9010 struct fw_fcoe_link_cmd { 9011 __be32 op_to_portid; 9012 __be32 retval_len16; 9013 __be32 sub_opcode_fcfi; 9014 __u8 r3; 9015 __u8 lstatus; 9016 __be16 flags; 9017 __u8 r4; 9018 __u8 set_vlan; 9019 __be16 vlan_id; 9020 __be32 vnpi_pkd; 9021 __be16 r6; 9022 __u8 phy_mac[6]; 9023 __u8 vnport_wwnn[8]; 9024 __u8 vnport_wwpn[8]; 9025 }; 9026 9027 #define S_FW_FCOE_LINK_CMD_PORTID 0 9028 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 9029 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 9030 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 9031 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 9032 9033 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 9034 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 9035 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 9036 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 9037 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 9038 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 9039 9040 #define S_FW_FCOE_LINK_CMD_FCFI 0 9041 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 9042 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 9043 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 9044 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 9045 9046 #define S_FW_FCOE_LINK_CMD_VNPI 0 9047 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 9048 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 9049 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 9050 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 9051 9052 struct fw_fcoe_vnp_cmd { 9053 __be32 op_to_fcfi; 9054 __be32 alloc_to_len16; 9055 __be32 gen_wwn_to_vnpi; 9056 __be32 vf_id; 9057 __be16 iqid; 9058 __u8 vnport_mac[6]; 9059 __u8 vnport_wwnn[8]; 9060 __u8 vnport_wwpn[8]; 9061 __u8 cmn_srv_parms[16]; 9062 __u8 clsp_word_0_1[8]; 9063 }; 9064 9065 #define S_FW_FCOE_VNP_CMD_FCFI 0 9066 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 9067 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 9068 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 9069 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 9070 9071 #define S_FW_FCOE_VNP_CMD_ALLOC 31 9072 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 9073 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 9074 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 9075 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 9076 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 9077 9078 #define S_FW_FCOE_VNP_CMD_FREE 30 9079 #define M_FW_FCOE_VNP_CMD_FREE 0x1 9080 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 9081 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 9082 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 9083 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 9084 9085 #define S_FW_FCOE_VNP_CMD_MODIFY 29 9086 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 9087 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 9088 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 9089 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 9090 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 9091 9092 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 9093 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 9094 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 9095 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 9096 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 9097 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 9098 9099 #define S_FW_FCOE_VNP_CMD_PERSIST 21 9100 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 9101 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 9102 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 9103 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 9104 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 9105 9106 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 9107 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 9108 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 9109 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 9110 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 9111 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 9112 9113 #define S_FW_FCOE_VNP_CMD_VNPI 0 9114 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 9115 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 9116 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 9117 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 9118 9119 struct fw_fcoe_sparams_cmd { 9120 __be32 op_to_portid; 9121 __be32 retval_len16; 9122 __u8 r3[7]; 9123 __u8 cos; 9124 __u8 lport_wwnn[8]; 9125 __u8 lport_wwpn[8]; 9126 __u8 cmn_srv_parms[16]; 9127 __u8 cls_srv_parms[16]; 9128 }; 9129 9130 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 9131 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 9132 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 9133 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 9134 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 9135 9136 struct fw_fcoe_stats_cmd { 9137 __be32 op_to_flowid; 9138 __be32 free_to_len16; 9139 union fw_fcoe_stats { 9140 struct fw_fcoe_stats_ctl { 9141 __u8 nstats_port; 9142 __u8 port_valid_ix; 9143 __be16 r6; 9144 __be32 r7; 9145 __be64 stat0; 9146 __be64 stat1; 9147 __be64 stat2; 9148 __be64 stat3; 9149 __be64 stat4; 9150 __be64 stat5; 9151 } ctl; 9152 struct fw_fcoe_port_stats { 9153 __be64 tx_bcast_bytes; 9154 __be64 tx_bcast_frames; 9155 __be64 tx_mcast_bytes; 9156 __be64 tx_mcast_frames; 9157 __be64 tx_ucast_bytes; 9158 __be64 tx_ucast_frames; 9159 __be64 tx_drop_frames; 9160 __be64 tx_offload_bytes; 9161 __be64 tx_offload_frames; 9162 __be64 rx_bcast_bytes; 9163 __be64 rx_bcast_frames; 9164 __be64 rx_mcast_bytes; 9165 __be64 rx_mcast_frames; 9166 __be64 rx_ucast_bytes; 9167 __be64 rx_ucast_frames; 9168 __be64 rx_err_frames; 9169 } port_stats; 9170 struct fw_fcoe_fcf_stats { 9171 __be32 fip_tx_bytes; 9172 __be32 fip_tx_fr; 9173 __be64 fcf_ka; 9174 __be64 mcast_adv_rcvd; 9175 __be16 ucast_adv_rcvd; 9176 __be16 sol_sent; 9177 __be16 vlan_req; 9178 __be16 vlan_rpl; 9179 __be16 clr_vlink; 9180 __be16 link_down; 9181 __be16 link_up; 9182 __be16 logo; 9183 __be16 flogi_req; 9184 __be16 flogi_rpl; 9185 __be16 fdisc_req; 9186 __be16 fdisc_rpl; 9187 __be16 fka_prd_chg; 9188 __be16 fc_map_chg; 9189 __be16 vfid_chg; 9190 __u8 no_fka_req; 9191 __u8 no_vnp; 9192 } fcf_stats; 9193 struct fw_fcoe_pcb_stats { 9194 __be64 tx_bytes; 9195 __be64 tx_frames; 9196 __be64 rx_bytes; 9197 __be64 rx_frames; 9198 __be32 vnp_ka; 9199 __be32 unsol_els_rcvd; 9200 __be64 unsol_cmd_rcvd; 9201 __be16 implicit_logo; 9202 __be16 flogi_inv_sparm; 9203 __be16 fdisc_inv_sparm; 9204 __be16 flogi_rjt; 9205 __be16 fdisc_rjt; 9206 __be16 no_ssn; 9207 __be16 mac_flt_fail; 9208 __be16 inv_fr_rcvd; 9209 } pcb_stats; 9210 struct fw_fcoe_scb_stats { 9211 __be64 tx_bytes; 9212 __be64 tx_frames; 9213 __be64 rx_bytes; 9214 __be64 rx_frames; 9215 __be32 host_abrt_req; 9216 __be32 adap_auto_abrt; 9217 __be32 adap_abrt_rsp; 9218 __be32 host_ios_req; 9219 __be16 ssn_offl_ios; 9220 __be16 ssn_not_rdy_ios; 9221 __u8 rx_data_ddp_err; 9222 __u8 ddp_flt_set_err; 9223 __be16 rx_data_fr_err; 9224 __u8 bad_st_abrt_req; 9225 __u8 no_io_abrt_req; 9226 __u8 abort_tmo; 9227 __u8 abort_tmo_2; 9228 __be32 abort_req; 9229 __u8 no_ppod_res_tmo; 9230 __u8 bp_tmo; 9231 __u8 adap_auto_cls; 9232 __u8 no_io_cls_req; 9233 __be32 host_cls_req; 9234 __be64 unsol_cmd_rcvd; 9235 __be32 plogi_req_rcvd; 9236 __be32 prli_req_rcvd; 9237 __be16 logo_req_rcvd; 9238 __be16 prlo_req_rcvd; 9239 __be16 plogi_rjt_rcvd; 9240 __be16 prli_rjt_rcvd; 9241 __be32 adisc_req_rcvd; 9242 __be32 rscn_rcvd; 9243 __be32 rrq_req_rcvd; 9244 __be32 unsol_els_rcvd; 9245 __u8 adisc_rjt_rcvd; 9246 __u8 scr_rjt; 9247 __u8 ct_rjt; 9248 __u8 inval_bls_rcvd; 9249 __be32 ba_rjt_rcvd; 9250 } scb_stats; 9251 } u; 9252 }; 9253 9254 #define S_FW_FCOE_STATS_CMD_FLOWID 0 9255 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 9256 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 9257 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 9258 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 9259 9260 #define S_FW_FCOE_STATS_CMD_FREE 30 9261 #define M_FW_FCOE_STATS_CMD_FREE 0x1 9262 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 9263 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 9264 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 9265 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 9266 9267 #define S_FW_FCOE_STATS_CMD_NSTATS 4 9268 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 9269 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 9270 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 9271 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 9272 9273 #define S_FW_FCOE_STATS_CMD_PORT 0 9274 #define M_FW_FCOE_STATS_CMD_PORT 0x3 9275 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 9276 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 9277 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 9278 9279 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 9280 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 9281 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 9282 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 9283 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 9284 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 9285 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 9286 9287 #define S_FW_FCOE_STATS_CMD_IX 0 9288 #define M_FW_FCOE_STATS_CMD_IX 0x3f 9289 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 9290 #define G_FW_FCOE_STATS_CMD_IX(x) \ 9291 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 9292 9293 struct fw_fcoe_fcf_cmd { 9294 __be32 op_to_fcfi; 9295 __be32 retval_len16; 9296 __be16 priority_pkd; 9297 __u8 mac[6]; 9298 __u8 name_id[8]; 9299 __u8 fabric[8]; 9300 __be16 vf_id; 9301 __be16 max_fcoe_size; 9302 __u8 vlan_id; 9303 __u8 fc_map[3]; 9304 __be32 fka_adv; 9305 __be32 r6; 9306 __u8 r7_hi; 9307 __u8 fpma_to_portid; 9308 __u8 spma_mac[6]; 9309 __be64 r8; 9310 }; 9311 9312 #define S_FW_FCOE_FCF_CMD_FCFI 0 9313 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 9314 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 9315 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 9316 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 9317 9318 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 9319 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 9320 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 9321 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 9322 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 9323 9324 #define S_FW_FCOE_FCF_CMD_FPMA 6 9325 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 9326 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 9327 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 9328 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 9329 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 9330 9331 #define S_FW_FCOE_FCF_CMD_SPMA 5 9332 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 9333 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 9334 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 9335 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 9336 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 9337 9338 #define S_FW_FCOE_FCF_CMD_LOGIN 4 9339 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 9340 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 9341 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 9342 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 9343 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 9344 9345 #define S_FW_FCOE_FCF_CMD_PORTID 0 9346 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 9347 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 9348 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 9349 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 9350 9351 /****************************************************************************** 9352 * E R R O R a n d D E B U G C O M M A N D s 9353 ******************************************************/ 9354 9355 enum fw_error_type { 9356 FW_ERROR_TYPE_EXCEPTION = 0x0, 9357 FW_ERROR_TYPE_HWMODULE = 0x1, 9358 FW_ERROR_TYPE_WR = 0x2, 9359 FW_ERROR_TYPE_ACL = 0x3, 9360 }; 9361 9362 enum fw_dcb_ieee_locations { 9363 FW_IEEE_LOC_LOCAL, 9364 FW_IEEE_LOC_PEER, 9365 FW_IEEE_LOC_OPERATIONAL, 9366 }; 9367 9368 struct fw_dcb_ieee_cmd { 9369 __be32 op_to_location; 9370 __be32 changed_to_len16; 9371 union fw_dcbx_stats { 9372 struct fw_dcbx_pfc_stats_ieee { 9373 __be32 pfc_mbc_pkd; 9374 __be32 pfc_willing_to_pfc_en; 9375 } dcbx_pfc_stats; 9376 struct fw_dcbx_ets_stats_ieee { 9377 __be32 cbs_to_ets_max_tc; 9378 __be32 pg_table; 9379 __u8 pg_percent[8]; 9380 __u8 tsa[8]; 9381 } dcbx_ets_stats; 9382 struct fw_dcbx_app_stats_ieee { 9383 __be32 num_apps_pkd; 9384 __be32 r6; 9385 __be32 app[4]; 9386 } dcbx_app_stats; 9387 struct fw_dcbx_control { 9388 __be32 multi_peer_invalidated; 9389 __u8 version; 9390 __u8 r6[3]; 9391 } dcbx_control; 9392 } u; 9393 }; 9394 9395 #define S_FW_DCB_IEEE_CMD_PORT 8 9396 #define M_FW_DCB_IEEE_CMD_PORT 0x7 9397 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 9398 #define G_FW_DCB_IEEE_CMD_PORT(x) \ 9399 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 9400 9401 #define S_FW_DCB_IEEE_CMD_FEATURE 2 9402 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 9403 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 9404 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 9405 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 9406 9407 #define S_FW_DCB_IEEE_CMD_LOCATION 0 9408 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 9409 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 9410 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 9411 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 9412 9413 #define S_FW_DCB_IEEE_CMD_CHANGED 20 9414 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 9415 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 9416 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 9417 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 9418 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 9419 9420 #define S_FW_DCB_IEEE_CMD_RECEIVED 19 9421 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 9422 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 9423 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 9424 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 9425 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 9426 9427 #define S_FW_DCB_IEEE_CMD_APPLY 18 9428 #define M_FW_DCB_IEEE_CMD_APPLY 0x1 9429 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 9430 #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 9431 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 9432 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 9433 9434 #define S_FW_DCB_IEEE_CMD_DISABLED 17 9435 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 9436 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 9437 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 9438 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 9439 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 9440 9441 #define S_FW_DCB_IEEE_CMD_MORE 16 9442 #define M_FW_DCB_IEEE_CMD_MORE 0x1 9443 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 9444 #define G_FW_DCB_IEEE_CMD_MORE(x) \ 9445 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 9446 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 9447 9448 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 9449 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 9450 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 9451 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 9452 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 9453 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 9454 9455 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 9456 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 9457 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9458 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 9459 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9460 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 9461 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 9462 9463 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 9464 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 9465 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9466 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 9467 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9468 9469 #define S_FW_DCB_IEEE_CMD_PFC_EN 0 9470 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 9471 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 9472 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 9473 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 9474 9475 #define S_FW_DCB_IEEE_CMD_CBS 16 9476 #define M_FW_DCB_IEEE_CMD_CBS 0x1 9477 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 9478 #define G_FW_DCB_IEEE_CMD_CBS(x) \ 9479 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 9480 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 9481 9482 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 9483 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 9484 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9485 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 9486 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9487 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 9488 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 9489 9490 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 9491 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 9492 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9493 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 9494 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9495 9496 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 9497 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 9498 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 9499 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 9500 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 9501 9502 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 9503 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 9504 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 9505 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 9506 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 9507 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 9508 9509 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 9510 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 9511 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9512 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 9513 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9514 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 9515 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 9516 9517 /* Hand-written */ 9518 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 9519 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 9520 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9521 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 9522 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9523 9524 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 9525 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 9526 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 9527 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 9528 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 9529 9530 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 9531 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 9532 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 9533 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 9534 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 9535 9536 9537 struct fw_error_cmd { 9538 __be32 op_to_type; 9539 __be32 len16_pkd; 9540 union fw_error { 9541 struct fw_error_exception { 9542 __be32 info[6]; 9543 } exception; 9544 struct fw_error_hwmodule { 9545 __be32 regaddr; 9546 __be32 regval; 9547 } hwmodule; 9548 struct fw_error_wr { 9549 __be16 cidx; 9550 __be16 pfn_vfn; 9551 __be32 eqid; 9552 __u8 wrhdr[16]; 9553 } wr; 9554 struct fw_error_acl { 9555 __be16 cidx; 9556 __be16 pfn_vfn; 9557 __be32 eqid; 9558 __be16 mv_pkd; 9559 __u8 val[6]; 9560 __be64 r4; 9561 } acl; 9562 } u; 9563 }; 9564 9565 #define S_FW_ERROR_CMD_FATAL 4 9566 #define M_FW_ERROR_CMD_FATAL 0x1 9567 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 9568 #define G_FW_ERROR_CMD_FATAL(x) \ 9569 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 9570 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 9571 9572 #define S_FW_ERROR_CMD_TYPE 0 9573 #define M_FW_ERROR_CMD_TYPE 0xf 9574 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 9575 #define G_FW_ERROR_CMD_TYPE(x) \ 9576 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 9577 9578 #define S_FW_ERROR_CMD_PFN 8 9579 #define M_FW_ERROR_CMD_PFN 0x7 9580 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9581 #define G_FW_ERROR_CMD_PFN(x) \ 9582 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9583 9584 #define S_FW_ERROR_CMD_VFN 0 9585 #define M_FW_ERROR_CMD_VFN 0xff 9586 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9587 #define G_FW_ERROR_CMD_VFN(x) \ 9588 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9589 9590 #define S_FW_ERROR_CMD_PFN 8 9591 #define M_FW_ERROR_CMD_PFN 0x7 9592 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9593 #define G_FW_ERROR_CMD_PFN(x) \ 9594 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9595 9596 #define S_FW_ERROR_CMD_VFN 0 9597 #define M_FW_ERROR_CMD_VFN 0xff 9598 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9599 #define G_FW_ERROR_CMD_VFN(x) \ 9600 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9601 9602 #define S_FW_ERROR_CMD_MV 15 9603 #define M_FW_ERROR_CMD_MV 0x1 9604 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 9605 #define G_FW_ERROR_CMD_MV(x) \ 9606 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 9607 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 9608 9609 struct fw_debug_cmd { 9610 __be32 op_type; 9611 __be32 len16_pkd; 9612 union fw_debug { 9613 struct fw_debug_assert { 9614 __be32 fcid; 9615 __be32 line; 9616 __be32 x; 9617 __be32 y; 9618 __u8 filename_0_7[8]; 9619 __u8 filename_8_15[8]; 9620 __be64 r3; 9621 } assert; 9622 struct fw_debug_prt { 9623 __be16 dprtstridx; 9624 __be16 r3[3]; 9625 __be32 dprtstrparam0; 9626 __be32 dprtstrparam1; 9627 __be32 dprtstrparam2; 9628 __be32 dprtstrparam3; 9629 } prt; 9630 } u; 9631 }; 9632 9633 #define S_FW_DEBUG_CMD_TYPE 0 9634 #define M_FW_DEBUG_CMD_TYPE 0xff 9635 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 9636 #define G_FW_DEBUG_CMD_TYPE(x) \ 9637 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 9638 9639 enum fw_diag_cmd_type { 9640 FW_DIAG_CMD_TYPE_OFLDIAG = 0, 9641 }; 9642 9643 enum fw_diag_cmd_ofldiag_op { 9644 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 9645 FW_DIAG_CMD_OFLDIAG_TEST_START, 9646 FW_DIAG_CMD_OFLDIAG_TEST_STOP, 9647 FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 9648 }; 9649 9650 enum fw_diag_cmd_ofldiag_status { 9651 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 9652 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 9653 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 9654 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 9655 }; 9656 9657 struct fw_diag_cmd { 9658 __be32 op_type; 9659 __be32 len16_pkd; 9660 union fw_diag_test { 9661 struct fw_diag_test_ofldiag { 9662 __u8 test_op; 9663 __u8 r3; 9664 __be16 test_status; 9665 __be32 duration; 9666 } ofldiag; 9667 } u; 9668 }; 9669 9670 #define S_FW_DIAG_CMD_TYPE 0 9671 #define M_FW_DIAG_CMD_TYPE 0xff 9672 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 9673 #define G_FW_DIAG_CMD_TYPE(x) \ 9674 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 9675 9676 struct fw_hma_cmd { 9677 __be32 op_pkd; 9678 __be32 retval_len16; 9679 __be32 mode_to_pcie_params; 9680 __be32 naddr_size; 9681 __be32 addr_size_pkd; 9682 __be32 r6; 9683 __be64 phy_address[5]; 9684 }; 9685 9686 #define S_FW_HMA_CMD_MODE 31 9687 #define M_FW_HMA_CMD_MODE 0x1 9688 #define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE) 9689 #define G_FW_HMA_CMD_MODE(x) \ 9690 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE) 9691 #define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U) 9692 9693 #define S_FW_HMA_CMD_SOC 30 9694 #define M_FW_HMA_CMD_SOC 0x1 9695 #define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC) 9696 #define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC) 9697 #define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U) 9698 9699 #define S_FW_HMA_CMD_EOC 29 9700 #define M_FW_HMA_CMD_EOC 0x1 9701 #define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC) 9702 #define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC) 9703 #define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U) 9704 9705 #define S_FW_HMA_CMD_PCIE_PARAMS 0 9706 #define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff 9707 #define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS) 9708 #define G_FW_HMA_CMD_PCIE_PARAMS(x) \ 9709 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS) 9710 9711 #define S_FW_HMA_CMD_NADDR 12 9712 #define M_FW_HMA_CMD_NADDR 0x3f 9713 #define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR) 9714 #define G_FW_HMA_CMD_NADDR(x) \ 9715 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR) 9716 9717 #define S_FW_HMA_CMD_SIZE 0 9718 #define M_FW_HMA_CMD_SIZE 0xfff 9719 #define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE) 9720 #define G_FW_HMA_CMD_SIZE(x) \ 9721 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE) 9722 9723 #define S_FW_HMA_CMD_ADDR_SIZE 11 9724 #define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff 9725 #define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE) 9726 #define G_FW_HMA_CMD_ADDR_SIZE(x) \ 9727 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE) 9728 9729 /****************************************************************************** 9730 * P C I E F W R E G I S T E R 9731 **************************************/ 9732 9733 enum pcie_fw_eval { 9734 PCIE_FW_EVAL_CRASH = 0, 9735 PCIE_FW_EVAL_PREP = 1, 9736 PCIE_FW_EVAL_CONF = 2, 9737 PCIE_FW_EVAL_INIT = 3, 9738 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 9739 PCIE_FW_EVAL_OVERHEAT = 5, 9740 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 9741 }; 9742 9743 /** 9744 * Register definitions for the PCIE_FW register which the firmware uses 9745 * to retain status across RESETs. This register should be considered 9746 * as a READ-ONLY register for Host Software and only to be used to 9747 * track firmware initialization/error state, etc. 9748 */ 9749 #define S_PCIE_FW_ERR 31 9750 #define M_PCIE_FW_ERR 0x1 9751 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 9752 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 9753 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 9754 9755 #define S_PCIE_FW_INIT 30 9756 #define M_PCIE_FW_INIT 0x1 9757 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 9758 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 9759 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 9760 9761 #define S_PCIE_FW_HALT 29 9762 #define M_PCIE_FW_HALT 0x1 9763 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 9764 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 9765 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 9766 9767 #define S_PCIE_FW_EVAL 24 9768 #define M_PCIE_FW_EVAL 0x7 9769 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 9770 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 9771 9772 #define S_PCIE_FW_STAGE 21 9773 #define M_PCIE_FW_STAGE 0x7 9774 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 9775 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 9776 9777 #define S_PCIE_FW_ASYNCNOT_VLD 20 9778 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 9779 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 9780 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 9781 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 9782 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 9783 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 9784 9785 #define S_PCIE_FW_ASYNCNOTINT 19 9786 #define M_PCIE_FW_ASYNCNOTINT 0x1 9787 #define V_PCIE_FW_ASYNCNOTINT(x) \ 9788 ((x) << S_PCIE_FW_ASYNCNOTINT) 9789 #define G_PCIE_FW_ASYNCNOTINT(x) \ 9790 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 9791 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 9792 9793 #define S_PCIE_FW_ASYNCNOT 16 9794 #define M_PCIE_FW_ASYNCNOT 0x7 9795 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 9796 #define G_PCIE_FW_ASYNCNOT(x) \ 9797 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 9798 9799 #define S_PCIE_FW_MASTER_VLD 15 9800 #define M_PCIE_FW_MASTER_VLD 0x1 9801 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 9802 #define G_PCIE_FW_MASTER_VLD(x) \ 9803 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 9804 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 9805 9806 #define S_PCIE_FW_MASTER 12 9807 #define M_PCIE_FW_MASTER 0x7 9808 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 9809 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 9810 9811 #define S_PCIE_FW_RESET_VLD 11 9812 #define M_PCIE_FW_RESET_VLD 0x1 9813 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 9814 #define G_PCIE_FW_RESET_VLD(x) \ 9815 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 9816 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 9817 9818 #define S_PCIE_FW_RESET 8 9819 #define M_PCIE_FW_RESET 0x7 9820 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 9821 #define G_PCIE_FW_RESET(x) \ 9822 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 9823 9824 #define S_PCIE_FW_REGISTERED 0 9825 #define M_PCIE_FW_REGISTERED 0xff 9826 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 9827 #define G_PCIE_FW_REGISTERED(x) \ 9828 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 9829 9830 9831 /****************************************************************************** 9832 * P C I E F W P F 0 R E G I S T E R 9833 **********************************************/ 9834 9835 /* 9836 * this register is available as 32-bit of persistent storage (across 9837 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 9838 * will not write it) 9839 */ 9840 9841 9842 /****************************************************************************** 9843 * P C I E F W P F 7 R E G I S T E R 9844 **********************************************/ 9845 9846 /* 9847 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 9848 * access the "devlog" which needing to contact firmware. The encoding is 9849 * mostly the same as that returned by the DEVLOG command except for the size 9850 * which is encoded as the number of entries in multiples-1 of 128 here rather 9851 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 9852 * and 15 means 2048. This of course in turn constrains the allowed values 9853 * for the devlog size ... 9854 */ 9855 #define PCIE_FW_PF_DEVLOG 7 9856 9857 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 9858 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 9859 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9860 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 9861 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9862 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 9863 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 9864 9865 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 9866 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 9867 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 9868 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 9869 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 9870 9871 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 9872 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 9873 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 9874 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 9875 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 9876 9877 9878 /****************************************************************************** 9879 * B I N A R Y H E A D E R F O R M A T 9880 **********************************************/ 9881 9882 /* 9883 * firmware binary header format 9884 */ 9885 struct fw_hdr { 9886 __u8 ver; 9887 __u8 chip; /* terminator chip family */ 9888 __be16 len512; /* bin length in units of 512-bytes */ 9889 __be32 fw_ver; /* firmware version */ 9890 __be32 tp_microcode_ver; /* tcp processor microcode version */ 9891 __u8 intfver_nic; 9892 __u8 intfver_vnic; 9893 __u8 intfver_ofld; 9894 __u8 intfver_ri; 9895 __u8 intfver_iscsipdu; 9896 __u8 intfver_iscsi; 9897 __u8 intfver_fcoepdu; 9898 __u8 intfver_fcoe; 9899 __u32 reserved2; 9900 __u32 reserved3; 9901 __be32 magic; /* runtime or bootstrap fw */ 9902 __be32 flags; 9903 __be32 reserved6[23]; 9904 }; 9905 9906 enum fw_hdr_chip { 9907 FW_HDR_CHIP_T4, 9908 FW_HDR_CHIP_T5, 9909 FW_HDR_CHIP_T6 9910 }; 9911 9912 #define S_FW_HDR_FW_VER_MAJOR 24 9913 #define M_FW_HDR_FW_VER_MAJOR 0xff 9914 #define V_FW_HDR_FW_VER_MAJOR(x) \ 9915 ((x) << S_FW_HDR_FW_VER_MAJOR) 9916 #define G_FW_HDR_FW_VER_MAJOR(x) \ 9917 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 9918 9919 #define S_FW_HDR_FW_VER_MINOR 16 9920 #define M_FW_HDR_FW_VER_MINOR 0xff 9921 #define V_FW_HDR_FW_VER_MINOR(x) \ 9922 ((x) << S_FW_HDR_FW_VER_MINOR) 9923 #define G_FW_HDR_FW_VER_MINOR(x) \ 9924 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 9925 9926 #define S_FW_HDR_FW_VER_MICRO 8 9927 #define M_FW_HDR_FW_VER_MICRO 0xff 9928 #define V_FW_HDR_FW_VER_MICRO(x) \ 9929 ((x) << S_FW_HDR_FW_VER_MICRO) 9930 #define G_FW_HDR_FW_VER_MICRO(x) \ 9931 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 9932 9933 #define S_FW_HDR_FW_VER_BUILD 0 9934 #define M_FW_HDR_FW_VER_BUILD 0xff 9935 #define V_FW_HDR_FW_VER_BUILD(x) \ 9936 ((x) << S_FW_HDR_FW_VER_BUILD) 9937 #define G_FW_HDR_FW_VER_BUILD(x) \ 9938 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 9939 9940 enum { 9941 T4FW_VERSION_MAJOR = 1, 9942 T4FW_VERSION_MINOR = 24, 9943 T4FW_VERSION_MICRO = 12, 9944 T4FW_VERSION_BUILD = 0, 9945 9946 T5FW_VERSION_MAJOR = 1, 9947 T5FW_VERSION_MINOR = 24, 9948 T5FW_VERSION_MICRO = 12, 9949 T5FW_VERSION_BUILD = 0, 9950 9951 T6FW_VERSION_MAJOR = 1, 9952 T6FW_VERSION_MINOR = 24, 9953 T6FW_VERSION_MICRO = 12, 9954 T6FW_VERSION_BUILD = 0, 9955 }; 9956 9957 enum { 9958 /* T4 9959 */ 9960 T4FW_HDR_INTFVER_NIC = 0x00, 9961 T4FW_HDR_INTFVER_VNIC = 0x00, 9962 T4FW_HDR_INTFVER_OFLD = 0x00, 9963 T4FW_HDR_INTFVER_RI = 0x00, 9964 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 9965 T4FW_HDR_INTFVER_ISCSI = 0x00, 9966 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 9967 T4FW_HDR_INTFVER_FCOE = 0x00, 9968 9969 /* T5 9970 */ 9971 T5FW_HDR_INTFVER_NIC = 0x00, 9972 T5FW_HDR_INTFVER_VNIC = 0x00, 9973 T5FW_HDR_INTFVER_OFLD = 0x00, 9974 T5FW_HDR_INTFVER_RI = 0x00, 9975 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 9976 T5FW_HDR_INTFVER_ISCSI = 0x00, 9977 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 9978 T5FW_HDR_INTFVER_FCOE = 0x00, 9979 9980 /* T6 9981 */ 9982 T6FW_HDR_INTFVER_NIC = 0x00, 9983 T6FW_HDR_INTFVER_VNIC = 0x00, 9984 T6FW_HDR_INTFVER_OFLD = 0x00, 9985 T6FW_HDR_INTFVER_RI = 0x00, 9986 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 9987 T6FW_HDR_INTFVER_ISCSI = 0x00, 9988 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 9989 T6FW_HDR_INTFVER_FCOE = 0x00, 9990 }; 9991 9992 #define FW_VERSION32(MAJOR, MINOR, MICRO, BUILD) ( \ 9993 V_FW_HDR_FW_VER_MAJOR(MAJOR) | V_FW_HDR_FW_VER_MINOR(MINOR) | \ 9994 V_FW_HDR_FW_VER_MICRO(MICRO) | V_FW_HDR_FW_VER_BUILD(BUILD)) 9995 9996 enum { 9997 FW_HDR_MAGIC_RUNTIME = 0x00000000, 9998 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 9999 }; 10000 10001 enum fw_hdr_flags { 10002 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 10003 }; 10004 10005 /* 10006 * External PHY firmware binary header format 10007 */ 10008 struct fw_ephy_hdr { 10009 __u8 ver; 10010 __u8 reserved; 10011 __be16 len512; /* bin length in units of 512-bytes */ 10012 __be32 magic; 10013 10014 __be16 vendor_id; 10015 __be16 device_id; 10016 __be32 version; 10017 10018 __be32 reserved1[4]; 10019 }; 10020 10021 enum { 10022 FW_EPHY_HDR_MAGIC = 0x65706879, 10023 }; 10024 10025 struct fw_ifconf_dhcp_info { 10026 __be32 addr; 10027 __be32 mask; 10028 __be16 vlanid; 10029 __be16 mtu; 10030 __be32 gw; 10031 __u8 op; 10032 __u8 len; 10033 __u8 data[270]; 10034 }; 10035 10036 struct fw_ifconf_ping_info { 10037 __be16 ping_pldsize; 10038 }; 10039 10040 #endif /* _T4FW_INTERFACE_H_ */ 10041