xref: /freebsd/sys/dev/cxgbe/firmware/t5fw_cfg.txt (revision 031beb4e)
1f72b68a1SNavdeep Parhar# Firmware configuration file.
2f72b68a1SNavdeep Parhar#
3f72b68a1SNavdeep Parhar# Global limits (some are hardware limits, others are due to the firmware).
4f72b68a1SNavdeep Parhar# nvi = 128		virtual interfaces
5f72b68a1SNavdeep Parhar# niqflint = 1023	ingress queues with freelists and/or interrupts
6f72b68a1SNavdeep Parhar# nethctrl = 64K	Ethernet or ctrl egress queues
7f72b68a1SNavdeep Parhar# neq = 64K		egress queues of all kinds, including freelists
812845013SNavdeep Parhar# nexactf = 512		MPS TCAM entries, can oversubscribe.
9f72b68a1SNavdeep Parhar#
10f72b68a1SNavdeep Parhar
11f72b68a1SNavdeep Parhar[global]
12f72b68a1SNavdeep Parhar	rss_glb_config_mode = basicvirtual
13f72b68a1SNavdeep Parhar	rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
14f72b68a1SNavdeep Parhar
1592ad6ac7SNavdeep Parhar	# PL_TIMEOUT register
16c47c408aSNavdeep Parhar	pl_timeout_value = 10000	# the timeout value in units of us
1792ad6ac7SNavdeep Parhar
18c47c408aSNavdeep Parhar	# SGE_THROTTLE_CONTROL
19c47c408aSNavdeep Parhar	bar2throttlecount = 500		# bar2throttlecount in us
20c47c408aSNavdeep Parhar
21c47c408aSNavdeep Parhar	sge_timer_value = 1, 5, 10, 50, 100, 200	# SGE_TIMER_VALUE* in usecs
22c47c408aSNavdeep Parhar
23c47c408aSNavdeep Parhar	reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
24c47c408aSNavdeep Parhar					# SGE_VFIFO_SIZE is not set, then
25c47c408aSNavdeep Parhar					# firmware will set it up in function
26c47c408aSNavdeep Parhar					# of number of egress queues used
27c47c408aSNavdeep Parhar
28c47c408aSNavdeep Parhar	reg[0x1130] = 0x00d5ffeb	# SGE_DBP_FETCH_THRESHOLD, fetch
29c47c408aSNavdeep Parhar					# threshold set to queue depth
30c47c408aSNavdeep Parhar					# minus 128-entries for FL and HP
31c47c408aSNavdeep Parhar					# queues, and 0xfff for LP which
32c47c408aSNavdeep Parhar					# prompts the firmware to set it up
33c47c408aSNavdeep Parhar					# in function of egress queues
34c47c408aSNavdeep Parhar					# used
35c47c408aSNavdeep Parhar
36c47c408aSNavdeep Parhar	reg[0x113c] = 0x0002ffc0	# SGE_VFIFO_SIZE, set to 0x2ffc0 which
37c47c408aSNavdeep Parhar					# prompts the firmware to set it up in
38c47c408aSNavdeep Parhar					# function of number of egress queues
39c47c408aSNavdeep Parhar					# used
40f72b68a1SNavdeep Parhar
4148d05478SNavdeep Parhar	# enable TP_OUT_CONFIG.IPIDSPLITMODE
4248d05478SNavdeep Parhar	reg[0x7d04] = 0x00010000/0x00010000
4348d05478SNavdeep Parhar
44dd991bd5SNavdeep Parhar	# disable TP_PARA_REG3.RxFragEn
45dd991bd5SNavdeep Parhar	reg[0x7d6c] = 0x00000000/0x00007000
46dd991bd5SNavdeep Parhar
47dd991bd5SNavdeep Parhar	# enable TP_PARA_REG6.EnableCSnd
48dd991bd5SNavdeep Parhar	reg[0x7d78] = 0x00000400/0x00000000
49dd991bd5SNavdeep Parhar
50c47c408aSNavdeep Parhar	reg[0x7dc0] = 0x0e2f8849	# TP_SHIFT_CNT
5148d05478SNavdeep Parhar
52f72b68a1SNavdeep Parhar	filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
53f72b68a1SNavdeep Parhar	filterMask = protocol, fcoe
54f72b68a1SNavdeep Parhar
55fc2aa1fcSNavdeep Parhar	tp_pmrx = 36, 512
56f72b68a1SNavdeep Parhar	tp_pmrx_pagesize = 64K
57c47c408aSNavdeep Parhar
58c47c408aSNavdeep Parhar	# TP number of RX channels (0 = auto)
59c47c408aSNavdeep Parhar	tp_nrxch = 0
60c47c408aSNavdeep Parhar
61fc2aa1fcSNavdeep Parhar	tp_pmtx = 46, 512
62f72b68a1SNavdeep Parhar	tp_pmtx_pagesize = 64K
63f72b68a1SNavdeep Parhar
64c47c408aSNavdeep Parhar	# TP number of TX channels (0 = auto)
65c47c408aSNavdeep Parhar	tp_ntxch = 0
6600cc2faaSNavdeep Parhar
6748d05478SNavdeep Parhar	# TP OFLD MTUs
6848d05478SNavdeep Parhar	tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
6948d05478SNavdeep Parhar
70c47c408aSNavdeep Parhar	# TP_GLOBAL_CONFIG
71c47c408aSNavdeep Parhar	reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
72c47c408aSNavdeep Parhar
73c47c408aSNavdeep Parhar	# TP_PC_CONFIG
74c47c408aSNavdeep Parhar	reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
75c47c408aSNavdeep Parhar
76c47c408aSNavdeep Parhar	# TP_PARA_REG0
77c47c408aSNavdeep Parhar	reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
78c47c408aSNavdeep Parhar
79c47c408aSNavdeep Parhar	# cluster, lan, or wan.
80c47c408aSNavdeep Parhar	tp_tcptuning = lan
81c47c408aSNavdeep Parhar
8248d05478SNavdeep Parhar	# MC configuration
8348d05478SNavdeep Parhar	mc_mode_brc[0] = 1		# mc0 - 1: enable BRC, 0: enable RBC
8448d05478SNavdeep Parhar	mc_mode_brc[1] = 1		# mc1 - 1: enable BRC, 0: enable RBC
8548d05478SNavdeep Parhar
86dd991bd5SNavdeep Parhar	# ULP_TX_CONFIG
87dd991bd5SNavdeep Parhar	reg[0x8dc0] = 0x00000004/0x00000004 # Enable more error msg for ...
88dd991bd5SNavdeep Parhar					    # TPT error.
89dd991bd5SNavdeep Parhar
90f72b68a1SNavdeep Parhar# PFs 0-3.  These get 8 MSI/8 MSI-X vectors each.  VFs are supported by
91460f25e5SNavdeep Parhar# these 4 PFs only.
92f72b68a1SNavdeep Parhar[function "0"]
93460f25e5SNavdeep Parhar	wx_caps = all
94460f25e5SNavdeep Parhar	r_caps = all
95305e7e92SNavdeep Parhar	nvi = 1
96305e7e92SNavdeep Parhar	rssnvi = 0
97305e7e92SNavdeep Parhar	niqflint = 2
98305e7e92SNavdeep Parhar	nethctrl = 2
99305e7e92SNavdeep Parhar	neq = 4
100305e7e92SNavdeep Parhar	nexactf = 2
101460f25e5SNavdeep Parhar	cmask = all
102460f25e5SNavdeep Parhar	pmask = 0x1
103f72b68a1SNavdeep Parhar
104f72b68a1SNavdeep Parhar[function "1"]
105460f25e5SNavdeep Parhar	wx_caps = all
106460f25e5SNavdeep Parhar	r_caps = all
107305e7e92SNavdeep Parhar	nvi = 1
108305e7e92SNavdeep Parhar	rssnvi = 0
109305e7e92SNavdeep Parhar	niqflint = 2
110305e7e92SNavdeep Parhar	nethctrl = 2
111305e7e92SNavdeep Parhar	neq = 4
112305e7e92SNavdeep Parhar	nexactf = 2
113460f25e5SNavdeep Parhar	cmask = all
114460f25e5SNavdeep Parhar	pmask = 0x2
115f72b68a1SNavdeep Parhar
116f72b68a1SNavdeep Parhar[function "2"]
117460f25e5SNavdeep Parhar	wx_caps = all
118460f25e5SNavdeep Parhar	r_caps = all
119305e7e92SNavdeep Parhar	nvi = 1
120305e7e92SNavdeep Parhar	rssnvi = 0
121305e7e92SNavdeep Parhar	niqflint = 2
122305e7e92SNavdeep Parhar	nethctrl = 2
123305e7e92SNavdeep Parhar	neq = 4
124305e7e92SNavdeep Parhar	nexactf = 2
125460f25e5SNavdeep Parhar	cmask = all
126460f25e5SNavdeep Parhar	pmask = 0x4
127f72b68a1SNavdeep Parhar
128f72b68a1SNavdeep Parhar[function "3"]
129460f25e5SNavdeep Parhar	wx_caps = all
130460f25e5SNavdeep Parhar	r_caps = all
131305e7e92SNavdeep Parhar	nvi = 1
132305e7e92SNavdeep Parhar	rssnvi = 0
133305e7e92SNavdeep Parhar	niqflint = 2
134305e7e92SNavdeep Parhar	nethctrl = 2
135305e7e92SNavdeep Parhar	neq = 4
136305e7e92SNavdeep Parhar	nexactf = 2
137460f25e5SNavdeep Parhar	cmask = all
138460f25e5SNavdeep Parhar	pmask = 0x8
139f72b68a1SNavdeep Parhar
140f72b68a1SNavdeep Parhar# PF4 is the resource-rich PF that the bus/nexus driver attaches to.
141f72b68a1SNavdeep Parhar# It gets 32 MSI/128 MSI-X vectors.
142f72b68a1SNavdeep Parhar[function "4"]
143f72b68a1SNavdeep Parhar	wx_caps = all
144f72b68a1SNavdeep Parhar	r_caps = all
145f72b68a1SNavdeep Parhar	nvi = 32
146305e7e92SNavdeep Parhar	rssnvi = 16
14712845013SNavdeep Parhar	niqflint = 512
14812845013SNavdeep Parhar	nethctrl = 1024
14912845013SNavdeep Parhar	neq = 2048
1502829f76dSNavdeep Parhar	nqpcq = 8192
151460f25e5SNavdeep Parhar	nexactf = 456
152f72b68a1SNavdeep Parhar	cmask = all
153f72b68a1SNavdeep Parhar	pmask = all
154ac4031d8SNavdeep Parhar	nethofld = 8192
155f72b68a1SNavdeep Parhar
156f72b68a1SNavdeep Parhar	# driver will mask off features it won't use
157fc2aa1fcSNavdeep Parhar	protocol = ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif
158f72b68a1SNavdeep Parhar
159f72b68a1SNavdeep Parhar	tp_l2t = 4096
160f72b68a1SNavdeep Parhar	tp_ddp = 2
161fc2aa1fcSNavdeep Parhar	tp_ddp_iscsi = 2
162fc2aa1fcSNavdeep Parhar	tp_stag = 2
163fc2aa1fcSNavdeep Parhar	tp_pbl = 5
164fc2aa1fcSNavdeep Parhar	tp_rq = 7
165f72b68a1SNavdeep Parhar
166f72b68a1SNavdeep Parhar	# TCAM has 8K cells; each region must start at a multiple of 128 cell.
167f72b68a1SNavdeep Parhar	# Each entry in these categories takes 4 cells each.  nhash will use the
168f72b68a1SNavdeep Parhar	# TCAM iff there is room left (that is, the rest don't add up to 2048).
169f72b68a1SNavdeep Parhar	nroute = 32
170f72b68a1SNavdeep Parhar	nclip = 32
171f72b68a1SNavdeep Parhar	nfilter = 1008
172f72b68a1SNavdeep Parhar	nserver = 512
173f72b68a1SNavdeep Parhar	nhash = 16384
174f72b68a1SNavdeep Parhar
175f72b68a1SNavdeep Parhar# PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
176f72b68a1SNavdeep Parhar# Not used right now.
177f72b68a1SNavdeep Parhar[function "5"]
178f72b68a1SNavdeep Parhar	nvi = 1
17912845013SNavdeep Parhar	rssnvi = 0
180f72b68a1SNavdeep Parhar
181f72b68a1SNavdeep Parhar# PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
182f72b68a1SNavdeep Parhar# Not used right now.
183f72b68a1SNavdeep Parhar[function "6"]
184f72b68a1SNavdeep Parhar	nvi = 1
18512845013SNavdeep Parhar	rssnvi = 0
186f72b68a1SNavdeep Parhar
187f72b68a1SNavdeep Parhar# The following function, 1023, is not an actual PCIE function but is used to
188f72b68a1SNavdeep Parhar# configure and reserve firmware internal resources that come from the global
189f72b68a1SNavdeep Parhar# resource pool.
190f72b68a1SNavdeep Parhar[function "1023"]
191f72b68a1SNavdeep Parhar	wx_caps = all
192f72b68a1SNavdeep Parhar	r_caps = all
193f72b68a1SNavdeep Parhar	nvi = 4
19412845013SNavdeep Parhar	rssnvi = 0
195f72b68a1SNavdeep Parhar	cmask = all
196f72b68a1SNavdeep Parhar	pmask = all
197f72b68a1SNavdeep Parhar	nexactf = 8
198f72b68a1SNavdeep Parhar	nfilter = 16
199f72b68a1SNavdeep Parhar
200460f25e5SNavdeep Parhar# For Virtual functions, we only allow NIC functionality and we only allow
201460f25e5SNavdeep Parhar# access to one port (1 << PF).  Note that because of limitations in the
202460f25e5SNavdeep Parhar# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
203460f25e5SNavdeep Parhar# and GTS registers, the number of Ingress and Egress Queues must be a power
204460f25e5SNavdeep Parhar# of 2.
205460f25e5SNavdeep Parhar#
206460f25e5SNavdeep Parhar[function "0/*"]
207460f25e5SNavdeep Parhar	wx_caps = 0x82
208460f25e5SNavdeep Parhar	r_caps = 0x86
209460f25e5SNavdeep Parhar	nvi = 1
210305e7e92SNavdeep Parhar	rssnvi = 0
211460f25e5SNavdeep Parhar	niqflint = 2
212460f25e5SNavdeep Parhar	nethctrl = 2
213460f25e5SNavdeep Parhar	neq = 4
214460f25e5SNavdeep Parhar	nexactf = 2
215460f25e5SNavdeep Parhar	cmask = all
216460f25e5SNavdeep Parhar	pmask = 0x1
217460f25e5SNavdeep Parhar
218460f25e5SNavdeep Parhar[function "1/*"]
219460f25e5SNavdeep Parhar	wx_caps = 0x82
220460f25e5SNavdeep Parhar	r_caps = 0x86
221460f25e5SNavdeep Parhar	nvi = 1
222305e7e92SNavdeep Parhar	rssnvi = 0
223460f25e5SNavdeep Parhar	niqflint = 2
224460f25e5SNavdeep Parhar	nethctrl = 2
225460f25e5SNavdeep Parhar	neq = 4
226460f25e5SNavdeep Parhar	nexactf = 2
227460f25e5SNavdeep Parhar	cmask = all
228460f25e5SNavdeep Parhar	pmask = 0x2
229460f25e5SNavdeep Parhar
230460f25e5SNavdeep Parhar[function "2/*"]
231460f25e5SNavdeep Parhar	wx_caps = 0x82
232460f25e5SNavdeep Parhar	r_caps = 0x86
233460f25e5SNavdeep Parhar	nvi = 1
234305e7e92SNavdeep Parhar	rssnvi = 0
235460f25e5SNavdeep Parhar	niqflint = 2
236460f25e5SNavdeep Parhar	nethctrl = 2
237460f25e5SNavdeep Parhar	neq = 4
238460f25e5SNavdeep Parhar	nexactf = 2
239460f25e5SNavdeep Parhar	cmask = all
240460f25e5SNavdeep Parhar	pmask = 0x4
241460f25e5SNavdeep Parhar
242460f25e5SNavdeep Parhar[function "3/*"]
243460f25e5SNavdeep Parhar	wx_caps = 0x82
244460f25e5SNavdeep Parhar	r_caps = 0x86
245460f25e5SNavdeep Parhar	nvi = 1
246305e7e92SNavdeep Parhar	rssnvi = 0
247460f25e5SNavdeep Parhar	niqflint = 2
248460f25e5SNavdeep Parhar	nethctrl = 2
249460f25e5SNavdeep Parhar	neq = 4
250460f25e5SNavdeep Parhar	nexactf = 2
251460f25e5SNavdeep Parhar	cmask = all
252460f25e5SNavdeep Parhar	pmask = 0x8
253460f25e5SNavdeep Parhar
254f72b68a1SNavdeep Parhar# MPS has 192K buffer space for ingress packets from the wire as well as
255f72b68a1SNavdeep Parhar# loopback path of the L2 switch.
256f72b68a1SNavdeep Parhar[port "0"]
257f72b68a1SNavdeep Parhar	dcb = none
258f72b68a1SNavdeep Parhar	bg_mem = 25
259f72b68a1SNavdeep Parhar	lpbk_mem = 25
260f72b68a1SNavdeep Parhar	hwm = 30
261f72b68a1SNavdeep Parhar	lwm = 15
262f72b68a1SNavdeep Parhar	dwm = 30
263f72b68a1SNavdeep Parhar
264f72b68a1SNavdeep Parhar[port "1"]
265f72b68a1SNavdeep Parhar	dcb = none
266f72b68a1SNavdeep Parhar	bg_mem = 25
267f72b68a1SNavdeep Parhar	lpbk_mem = 25
268f72b68a1SNavdeep Parhar	hwm = 30
269f72b68a1SNavdeep Parhar	lwm = 15
270f72b68a1SNavdeep Parhar	dwm = 30
271f72b68a1SNavdeep Parhar
272f72b68a1SNavdeep Parhar[port "2"]
273f72b68a1SNavdeep Parhar	dcb = none
274f72b68a1SNavdeep Parhar	bg_mem = 25
275f72b68a1SNavdeep Parhar	lpbk_mem = 25
276f72b68a1SNavdeep Parhar	hwm = 30
277f72b68a1SNavdeep Parhar	lwm = 15
278f72b68a1SNavdeep Parhar	dwm = 30
279f72b68a1SNavdeep Parhar
280f72b68a1SNavdeep Parhar[port "3"]
281f72b68a1SNavdeep Parhar	dcb = none
282f72b68a1SNavdeep Parhar	bg_mem = 25
283f72b68a1SNavdeep Parhar	lpbk_mem = 25
284f72b68a1SNavdeep Parhar	hwm = 30
285f72b68a1SNavdeep Parhar	lwm = 15
286f72b68a1SNavdeep Parhar	dwm = 30
287f72b68a1SNavdeep Parhar
288f72b68a1SNavdeep Parhar[fini]
289f72b68a1SNavdeep Parhar	version = 0x1
290305e7e92SNavdeep Parhar	checksum = 0x34da8705
291f72b68a1SNavdeep Parhar#
292f72b68a1SNavdeep Parhar#
293