1# Firmware configuration file.
2#
3# Global limits (some are hardware limits, others are due to the firmware).
4# nvi = 128		virtual interfaces
5# niqflint = 1023	ingress queues with freelists and/or interrupts
6# nethctrl = 64K	Ethernet or ctrl egress queues
7# neq = 64K		egress queues of all kinds, including freelists
8# nexactf = 512		MPS TCAM entries, can oversubscribe.
9#
10
11[global]
12	rss_glb_config_mode = basicvirtual
13	rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
14
15	# PL_TIMEOUT register
16	pl_timeout_value = 10000	# the timeout value in units of us
17
18	# SGE_THROTTLE_CONTROL
19	bar2throttlecount = 500		# bar2throttlecount in us
20
21	sge_timer_value = 1, 5, 10, 50, 100, 200	# SGE_TIMER_VALUE* in usecs
22
23	reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
24					# SGE_VFIFO_SIZE is not set, then
25					# firmware will set it up in function
26					# of number of egress queues used
27
28	reg[0x1130] = 0x00d5ffeb	# SGE_DBP_FETCH_THRESHOLD, fetch
29					# threshold set to queue depth
30					# minus 128-entries for FL and HP
31					# queues, and 0xfff for LP which
32					# prompts the firmware to set it up
33					# in function of egress queues
34					# used
35
36	reg[0x113c] = 0x0002ffc0	# SGE_VFIFO_SIZE, set to 0x2ffc0 which
37					# prompts the firmware to set it up in
38					# function of number of egress queues
39					# used
40
41	# enable TP_OUT_CONFIG.IPIDSPLITMODE
42	reg[0x7d04] = 0x00010000/0x00010000
43
44	# disable TP_PARA_REG3.RxFragEn
45	reg[0x7d6c] = 0x00000000/0x00007000
46
47	# enable TP_PARA_REG6.EnableCSnd
48	reg[0x7d78] = 0x00000400/0x00000000
49
50	reg[0x7dc0] = 0x0e2f8849	# TP_SHIFT_CNT
51
52	filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
53	filterMask = port, protocol
54
55	tp_pmrx = 20, 512
56	tp_pmrx_pagesize = 16K
57
58	# TP number of RX channels (0 = auto)
59	tp_nrxch = 0
60
61	tp_pmtx = 40, 512
62	tp_pmtx_pagesize = 64K
63
64	# TP number of TX channels (0 = auto)
65	tp_ntxch = 0
66
67	# TP OFLD MTUs
68	tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
69
70	# TP_GLOBAL_CONFIG
71	reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
72
73	# TP_PC_CONFIG
74	reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
75
76	# TP_PC_CONFIG2
77	reg[0x7d4c] = 0x00010000/0x00010000 # set DisableNewPshFlag
78
79	# TP_PARA_REG0
80	reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
81
82	# TP_PARA_REG3
83	reg[0x7d6c] = 0x28000000/0x28000000 # set EnableTnlCngHdr
84					    # set RxMacCheck (Note:
85					    # Only for hash filter,
86					    # no tcp offload)
87
88	# TP_PIO_ADDR:TP_RX_LPBK
89	reg[tp_pio:0x28] = 0x00208208/0x00ffffff # set commit limits to 8
90
91	# MC configuration
92	mc_mode_brc[0] = 0		# mc0 - 1: enable BRC, 0: enable RBC
93	mc_mode_brc[1] = 0		# mc1 - 1: enable BRC, 0: enable RBC
94
95	# ULP_TX_CONFIG
96	reg[0x8dc0] = 0x00000004/0x00000004 # Enable more error msg for ...
97					    # TPT error.
98
99# PFs 0-3.  These get 8 MSI/8 MSI-X vectors each.  VFs are supported by
100# these 4 PFs only.
101[function "0"]
102	wx_caps = all
103	r_caps = all
104	nvi = 1
105	rssnvi = 0
106	niqflint = 2
107	nethctrl = 2
108	neq = 4
109	nexactf = 2
110	cmask = all
111	pmask = 0x1
112
113[function "1"]
114	wx_caps = all
115	r_caps = all
116	nvi = 1
117	rssnvi = 0
118	niqflint = 2
119	nethctrl = 2
120	neq = 4
121	nexactf = 2
122	cmask = all
123	pmask = 0x2
124
125[function "2"]
126	wx_caps = all
127	r_caps = all
128	nvi = 1
129	rssnvi = 0
130	niqflint = 2
131	nethctrl = 2
132	neq = 4
133	nexactf = 2
134	cmask = all
135	pmask = 0x4
136
137[function "3"]
138	wx_caps = all
139	r_caps = all
140	nvi = 1
141	rssnvi = 0
142	niqflint = 2
143	nethctrl = 2
144	neq = 4
145	nexactf = 2
146	cmask = all
147	pmask = 0x8
148
149# PF4 is the resource-rich PF that the bus/nexus driver attaches to.
150# It gets 32 MSI/128 MSI-X vectors.
151[function "4"]
152	wx_caps = all
153	r_caps = all
154	nvi = 32
155	rssnvi = 16
156	niqflint = 512
157	nethctrl = 1024
158	neq = 2048
159	nqpcq = 8192
160	nexactf = 456
161	cmask = all
162	pmask = all
163
164	# driver will mask off features it won't use
165	protocol = nic_hashfilter
166
167	tp_l2t = 4096
168
169	# TCAM has 8K cells; each region must start at a multiple of 128 cell.
170	# Each entry in these categories takes 4 cells each.  nhash will use the
171	# TCAM iff there is room left (that is, the rest don't add up to 2048).
172	nroute = 32
173	nclip = 32
174	nfilter = 1008
175	nserver = 512
176	nhash = 524288
177
178# PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
179# Not used right now.
180[function "5"]
181	nvi = 1
182	rssnvi = 0
183
184# PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
185# Not used right now.
186[function "6"]
187	nvi = 1
188	rssnvi = 0
189
190# The following function, 1023, is not an actual PCIE function but is used to
191# configure and reserve firmware internal resources that come from the global
192# resource pool.
193[function "1023"]
194	wx_caps = all
195	r_caps = all
196	nvi = 4
197	rssnvi = 0
198	cmask = all
199	pmask = all
200	nexactf = 8
201	nfilter = 16
202
203# For Virtual functions, we only allow NIC functionality and we only allow
204# access to one port (1 << PF).  Note that because of limitations in the
205# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
206# and GTS registers, the number of Ingress and Egress Queues must be a power
207# of 2.
208#
209[function "0/*"]
210	wx_caps = 0x82
211	r_caps = 0x86
212	nvi = 1
213	rssnvi = 0
214	niqflint = 2
215	nethctrl = 2
216	neq = 4
217	nexactf = 2
218	cmask = all
219	pmask = 0x1
220
221[function "1/*"]
222	wx_caps = 0x82
223	r_caps = 0x86
224	nvi = 1
225	rssnvi = 0
226	niqflint = 2
227	nethctrl = 2
228	neq = 4
229	nexactf = 2
230	cmask = all
231	pmask = 0x2
232
233[function "2/*"]
234	wx_caps = 0x82
235	r_caps = 0x86
236	nvi = 1
237	rssnvi = 0
238	niqflint = 2
239	nethctrl = 2
240	neq = 4
241	nexactf = 2
242	cmask = all
243	pmask = 0x4
244
245[function "3/*"]
246	wx_caps = 0x82
247	r_caps = 0x86
248	nvi = 1
249	rssnvi = 0
250	niqflint = 2
251	nethctrl = 2
252	neq = 4
253	nexactf = 2
254	cmask = all
255	pmask = 0x8
256
257# MPS has 192K buffer space for ingress packets from the wire as well as
258# loopback path of the L2 switch.
259[port "0"]
260	dcb = none
261	bg_mem = 25
262	lpbk_mem = 25
263	hwm = 30
264	lwm = 15
265	dwm = 30
266
267[port "1"]
268	dcb = none
269	bg_mem = 25
270	lpbk_mem = 25
271	hwm = 30
272	lwm = 15
273	dwm = 30
274
275[port "2"]
276	dcb = none
277	bg_mem = 25
278	lpbk_mem = 25
279	hwm = 30
280	lwm = 15
281	dwm = 30
282
283[port "3"]
284	dcb = none
285	bg_mem = 25
286	lpbk_mem = 25
287	hwm = 30
288	lwm = 15
289	dwm = 30
290
291[fini]
292	version = 0x1
293	checksum = 0x7a962d44
294#
295#
296