189f651e7SNavdeep Parhar# Firmware configuration file.
289f651e7SNavdeep Parhar#
389f651e7SNavdeep Parhar# Global limits (some are hardware limits, others are due to the firmware).
489f651e7SNavdeep Parhar# nvi = 128		virtual interfaces
589f651e7SNavdeep Parhar# niqflint = 1023	ingress queues with freelists and/or interrupts
689f651e7SNavdeep Parhar# nethctrl = 64K	Ethernet or ctrl egress queues
789f651e7SNavdeep Parhar# neq = 64K		egress queues of all kinds, including freelists
889f651e7SNavdeep Parhar# nexactf = 512		MPS TCAM entries, can oversubscribe.
989f651e7SNavdeep Parhar
1089f651e7SNavdeep Parhar[global]
1189f651e7SNavdeep Parhar	rss_glb_config_mode = basicvirtual
1289f651e7SNavdeep Parhar	rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
1389f651e7SNavdeep Parhar
1489f651e7SNavdeep Parhar	# PL_TIMEOUT register
1589f651e7SNavdeep Parhar	pl_timeout_value = 200		# the timeout value in units of us
1689f651e7SNavdeep Parhar
1789f651e7SNavdeep Parhar	sge_timer_value = 1, 5, 10, 50, 100, 200	# SGE_TIMER_VALUE* in usecs
1889f651e7SNavdeep Parhar
1989f651e7SNavdeep Parhar	reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
2089f651e7SNavdeep Parhar
2189f651e7SNavdeep Parhar	reg[0x7dc0] = 0x0e2f8849	# TP_SHIFT_CNT
2289f651e7SNavdeep Parhar
2389f651e7SNavdeep Parhar	#Tick granularities in kbps
2489f651e7SNavdeep Parhar	tsch_ticks = 100000, 10000, 1000, 10
2589f651e7SNavdeep Parhar
2689f651e7SNavdeep Parhar	filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
2789f651e7SNavdeep Parhar	filterMask = port, protocol
2889f651e7SNavdeep Parhar
2989f651e7SNavdeep Parhar	tp_pmrx = 20, 512
3089f651e7SNavdeep Parhar	tp_pmrx_pagesize = 16K
3189f651e7SNavdeep Parhar
3289f651e7SNavdeep Parhar	# TP number of RX channels (0 = auto)
3389f651e7SNavdeep Parhar	tp_nrxch = 0
3489f651e7SNavdeep Parhar
3589f651e7SNavdeep Parhar	tp_pmtx = 40, 512
3689f651e7SNavdeep Parhar	tp_pmtx_pagesize = 64K
3789f651e7SNavdeep Parhar
3889f651e7SNavdeep Parhar	# TP number of TX channels (0 = auto)
3989f651e7SNavdeep Parhar	tp_ntxch = 0
4089f651e7SNavdeep Parhar
4189f651e7SNavdeep Parhar	# TP OFLD MTUs
4289f651e7SNavdeep Parhar	tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
4389f651e7SNavdeep Parhar
4489f651e7SNavdeep Parhar	# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
4589f651e7SNavdeep Parhar	reg[0x7d04] = 0x00010008/0x00010008
4689f651e7SNavdeep Parhar
4789f651e7SNavdeep Parhar	# TP_GLOBAL_CONFIG
4889f651e7SNavdeep Parhar	reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
4989f651e7SNavdeep Parhar
5089f651e7SNavdeep Parhar	# TP_PC_CONFIG
5189f651e7SNavdeep Parhar	reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
5289f651e7SNavdeep Parhar
5389f651e7SNavdeep Parhar	# TP_PC_CONFIG2
5489f651e7SNavdeep Parhar	reg[0x7d4c] = 0x00010000/0x00010000 # set DisableNewPshFlag
5589f651e7SNavdeep Parhar
5689f651e7SNavdeep Parhar	# TP_PARA_REG0
5789f651e7SNavdeep Parhar	reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
5889f651e7SNavdeep Parhar
5989f651e7SNavdeep Parhar	# TP_PARA_REG3
6089f651e7SNavdeep Parhar	reg[0x7d6c] = 0x28000000/0x28000000 # set EnableTnlCngHdr
6189f651e7SNavdeep Parhar					    # set RxMacCheck (Note:
6289f651e7SNavdeep Parhar					    # Only for hash filter,
6389f651e7SNavdeep Parhar					    # no tcp offload)
6489f651e7SNavdeep Parhar
6589f651e7SNavdeep Parhar	# LE_DB_CONFIG
6689f651e7SNavdeep Parhar	reg[0x19c04] = 0x00000000/0x02040000 # LE IPv4 compression disabled
6789f651e7SNavdeep Parhar					     # EXTN_HASH_IPV4 Disable
6889f651e7SNavdeep Parhar
6989f651e7SNavdeep Parhar	# LE_DB_RSP_CODE_0
7089f651e7SNavdeep Parhar	reg[0x19c74] = 0x00000004/0x0000000f # TCAM_ACTV_HIT = 4
7189f651e7SNavdeep Parhar
7289f651e7SNavdeep Parhar	# LE_DB_RSP_CODE_1
7389f651e7SNavdeep Parhar	reg[0x19c78] = 0x08000000/0x0e000000 # HASH_ACTV_HIT = 4
7489f651e7SNavdeep Parhar
7589f651e7SNavdeep Parhar	# LE_DB_HASH_CONFIG
7689f651e7SNavdeep Parhar	reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
7789f651e7SNavdeep Parhar
7889f651e7SNavdeep Parhar	# MC configuration
7989f651e7SNavdeep Parhar	mc_mode_brc[0] = 0		# mc0 - 1: enable BRC, 0: enable RBC
8089f651e7SNavdeep Parhar
8189f651e7SNavdeep Parhar# PFs 0-3.  These get 8 MSI/8 MSI-X vectors each.  VFs are supported by
8289f651e7SNavdeep Parhar# these 4 PFs only.
8389f651e7SNavdeep Parhar[function "0"]
8489f651e7SNavdeep Parhar	wx_caps = all
8589f651e7SNavdeep Parhar	r_caps = all
86305e7e92SNavdeep Parhar	nvi = 1
87305e7e92SNavdeep Parhar	rssnvi = 0
88305e7e92SNavdeep Parhar	niqflint = 2
89305e7e92SNavdeep Parhar	nethctrl = 2
90305e7e92SNavdeep Parhar	neq = 4
91305e7e92SNavdeep Parhar	nexactf = 2
9289f651e7SNavdeep Parhar	cmask = all
9389f651e7SNavdeep Parhar	pmask = 0x1
9489f651e7SNavdeep Parhar
9589f651e7SNavdeep Parhar[function "1"]
9689f651e7SNavdeep Parhar	wx_caps = all
9789f651e7SNavdeep Parhar	r_caps = all
98305e7e92SNavdeep Parhar	nvi = 1
99305e7e92SNavdeep Parhar	rssnvi = 0
100305e7e92SNavdeep Parhar	niqflint = 2
101305e7e92SNavdeep Parhar	nethctrl = 2
102305e7e92SNavdeep Parhar	neq = 4
103305e7e92SNavdeep Parhar	nexactf = 2
10489f651e7SNavdeep Parhar	cmask = all
10589f651e7SNavdeep Parhar	pmask = 0x2
10689f651e7SNavdeep Parhar
10789f651e7SNavdeep Parhar[function "2"]
10889f651e7SNavdeep Parhar	wx_caps = all
10989f651e7SNavdeep Parhar	r_caps = all
110305e7e92SNavdeep Parhar	nvi = 1
111305e7e92SNavdeep Parhar	rssnvi = 0
112305e7e92SNavdeep Parhar	niqflint = 2
113305e7e92SNavdeep Parhar	nethctrl = 2
114305e7e92SNavdeep Parhar	neq = 4
115305e7e92SNavdeep Parhar	nexactf = 2
11689f651e7SNavdeep Parhar	cmask = all
11789f651e7SNavdeep Parhar	pmask = 0x4
11889f651e7SNavdeep Parhar
11989f651e7SNavdeep Parhar[function "3"]
12089f651e7SNavdeep Parhar	wx_caps = all
12189f651e7SNavdeep Parhar	r_caps = all
122305e7e92SNavdeep Parhar	nvi = 1
123305e7e92SNavdeep Parhar	rssnvi = 0
124305e7e92SNavdeep Parhar	niqflint = 2
125305e7e92SNavdeep Parhar	nethctrl = 2
126305e7e92SNavdeep Parhar	neq = 4
127305e7e92SNavdeep Parhar	nexactf = 2
12889f651e7SNavdeep Parhar	cmask = all
12989f651e7SNavdeep Parhar	pmask = 0x8
13089f651e7SNavdeep Parhar
13189f651e7SNavdeep Parhar# PF4 is the resource-rich PF that the bus/nexus driver attaches to.
13289f651e7SNavdeep Parhar# It gets 32 MSI/128 MSI-X vectors.
13389f651e7SNavdeep Parhar[function "4"]
13489f651e7SNavdeep Parhar	wx_caps = all
13589f651e7SNavdeep Parhar	r_caps = all
13689f651e7SNavdeep Parhar	nvi = 32
137305e7e92SNavdeep Parhar	rssnvi = 32
13889f651e7SNavdeep Parhar	niqflint = 512
13989f651e7SNavdeep Parhar	nethctrl = 1024
14089f651e7SNavdeep Parhar	neq = 2048
14189f651e7SNavdeep Parhar	nqpcq = 8192
14289f651e7SNavdeep Parhar	nexactf = 456
14389f651e7SNavdeep Parhar	cmask = all
14489f651e7SNavdeep Parhar	pmask = all
14589f651e7SNavdeep Parhar	nclip = 320
14689f651e7SNavdeep Parhar
14789f651e7SNavdeep Parhar	# TCAM has 6K cells; each region must start at a multiple of 128 cell.
14889f651e7SNavdeep Parhar	# Each entry in these categories takes 2 cells each.  nhash will use the
14989f651e7SNavdeep Parhar	# TCAM iff there is room left (that is, the rest don't add up to 3072).
15089f651e7SNavdeep Parhar	nfilter = 2032
15189f651e7SNavdeep Parhar	nserver = 512
15289f651e7SNavdeep Parhar	nhpfilter = 0
15389f651e7SNavdeep Parhar	nhash = 524288
15489f651e7SNavdeep Parhar	protocol = nic_hashfilter
15589f651e7SNavdeep Parhar	tp_l2t = 4096
15689f651e7SNavdeep Parhar
15789f651e7SNavdeep Parhar# PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
15889f651e7SNavdeep Parhar# Not used right now.
15989f651e7SNavdeep Parhar[function "5"]
16089f651e7SNavdeep Parhar	nvi = 1
16189f651e7SNavdeep Parhar	rssnvi = 0
16289f651e7SNavdeep Parhar
16389f651e7SNavdeep Parhar# PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
16489f651e7SNavdeep Parhar# Not used right now.
16589f651e7SNavdeep Parhar[function "6"]
16689f651e7SNavdeep Parhar	nvi = 1
16789f651e7SNavdeep Parhar	rssnvi = 0
16889f651e7SNavdeep Parhar
16989f651e7SNavdeep Parhar# The following function, 1023, is not an actual PCIE function but is used to
17089f651e7SNavdeep Parhar# configure and reserve firmware internal resources that come from the global
17189f651e7SNavdeep Parhar# resource pool.
17289f651e7SNavdeep Parhar#
17389f651e7SNavdeep Parhar[function "1023"]
17489f651e7SNavdeep Parhar	wx_caps = all
17589f651e7SNavdeep Parhar	r_caps = all
17689f651e7SNavdeep Parhar	nvi = 4
17789f651e7SNavdeep Parhar	rssnvi = 0
17889f651e7SNavdeep Parhar	cmask = all
17989f651e7SNavdeep Parhar	pmask = all
18089f651e7SNavdeep Parhar	nexactf = 8
18189f651e7SNavdeep Parhar	nfilter = 16
18289f651e7SNavdeep Parhar
18389f651e7SNavdeep Parhar
18489f651e7SNavdeep Parhar# For Virtual functions, we only allow NIC functionality and we only allow
18589f651e7SNavdeep Parhar# access to one port (1 << PF).  Note that because of limitations in the
18689f651e7SNavdeep Parhar# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
18789f651e7SNavdeep Parhar# and GTS registers, the number of Ingress and Egress Queues must be a power
18889f651e7SNavdeep Parhar# of 2.
18989f651e7SNavdeep Parhar#
19089f651e7SNavdeep Parhar[function "0/*"]
19189f651e7SNavdeep Parhar	wx_caps = 0x82
19289f651e7SNavdeep Parhar	r_caps = 0x86
19389f651e7SNavdeep Parhar	nvi = 1
194305e7e92SNavdeep Parhar	rssnvi = 0
19589f651e7SNavdeep Parhar	niqflint = 2
19689f651e7SNavdeep Parhar	nethctrl = 2
19789f651e7SNavdeep Parhar	neq = 4
19889f651e7SNavdeep Parhar	nexactf = 2
19989f651e7SNavdeep Parhar	cmask = all
20089f651e7SNavdeep Parhar	pmask = 0x1
20189f651e7SNavdeep Parhar
20289f651e7SNavdeep Parhar[function "1/*"]
20389f651e7SNavdeep Parhar	wx_caps = 0x82
20489f651e7SNavdeep Parhar	r_caps = 0x86
20589f651e7SNavdeep Parhar	nvi = 1
206305e7e92SNavdeep Parhar	rssnvi = 0
20789f651e7SNavdeep Parhar	niqflint = 2
20889f651e7SNavdeep Parhar	nethctrl = 2
20989f651e7SNavdeep Parhar	neq = 4
21089f651e7SNavdeep Parhar	nexactf = 2
21189f651e7SNavdeep Parhar	cmask = all
21289f651e7SNavdeep Parhar	pmask = 0x2
21389f651e7SNavdeep Parhar
21489f651e7SNavdeep Parhar[function "2/*"]
21589f651e7SNavdeep Parhar	wx_caps = 0x82
21689f651e7SNavdeep Parhar	r_caps = 0x86
21789f651e7SNavdeep Parhar	nvi = 1
218305e7e92SNavdeep Parhar	rssnvi = 0
21989f651e7SNavdeep Parhar	niqflint = 2
22089f651e7SNavdeep Parhar	nethctrl = 2
22189f651e7SNavdeep Parhar	neq = 4
22289f651e7SNavdeep Parhar	nexactf = 2
22389f651e7SNavdeep Parhar	cmask = all
22489f651e7SNavdeep Parhar	pmask = 0x1
22589f651e7SNavdeep Parhar
22689f651e7SNavdeep Parhar[function "3/*"]
22789f651e7SNavdeep Parhar	wx_caps = 0x82
22889f651e7SNavdeep Parhar	r_caps = 0x86
22989f651e7SNavdeep Parhar	nvi = 1
230305e7e92SNavdeep Parhar	rssnvi = 0
23189f651e7SNavdeep Parhar	niqflint = 2
23289f651e7SNavdeep Parhar	nethctrl = 2
23389f651e7SNavdeep Parhar	neq = 4
23489f651e7SNavdeep Parhar	nexactf = 2
23589f651e7SNavdeep Parhar	cmask = all
23689f651e7SNavdeep Parhar	pmask = 0x2
23789f651e7SNavdeep Parhar
23889f651e7SNavdeep Parhar# MPS has 192K buffer space for ingress packets from the wire as well as
23989f651e7SNavdeep Parhar# loopback path of the L2 switch.
24089f651e7SNavdeep Parhar[port "0"]
24189f651e7SNavdeep Parhar	dcb = none
24289f651e7SNavdeep Parhar	#bg_mem = 25
24389f651e7SNavdeep Parhar	#lpbk_mem = 25
24489f651e7SNavdeep Parhar	hwm = 60
24589f651e7SNavdeep Parhar	lwm = 15
24689f651e7SNavdeep Parhar	dwm = 30
24789f651e7SNavdeep Parhar
24889f651e7SNavdeep Parhar[port "1"]
24989f651e7SNavdeep Parhar	dcb = none
25089f651e7SNavdeep Parhar	#bg_mem = 25
25189f651e7SNavdeep Parhar	#lpbk_mem = 25
25289f651e7SNavdeep Parhar	hwm = 60
25389f651e7SNavdeep Parhar	lwm = 15
25489f651e7SNavdeep Parhar	dwm = 30
25589f651e7SNavdeep Parhar
25689f651e7SNavdeep Parhar[fini]
25789f651e7SNavdeep Parhar	version = 0x1
258305e7e92SNavdeep Parhar	checksum = 0x5e0e0eb7
25989f651e7SNavdeep Parhar#
26089f651e7SNavdeep Parhar#
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