1 /* 2 * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * - Redistributions in binary form must reproduce the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer in the documentation and/or other materials 20 * provided with the distribution. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * SOFTWARE. 30 * 31 * $FreeBSD$ 32 */ 33 #ifndef __IW_CXGB4_H__ 34 #define __IW_CXGB4_H__ 35 36 #include <linux/list.h> 37 #include <linux/spinlock.h> 38 #include <linux/idr.h> 39 #include <linux/completion.h> 40 #include <linux/netdevice.h> 41 #include <linux/sched.h> 42 #include <linux/pci.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/wait.h> 45 #include <linux/kref.h> 46 #include <linux/timer.h> 47 #include <linux/io.h> 48 #include <sys/vmem.h> 49 50 #include <asm/byteorder.h> 51 52 #include <netinet/in.h> 53 #include <netinet/toecore.h> 54 55 #include <rdma/ib_verbs.h> 56 #include <rdma/iw_cm.h> 57 58 #undef prefetch 59 60 #include "common/common.h" 61 #include "common/t4_msg.h" 62 #include "common/t4_regs.h" 63 #include "common/t4_tcb.h" 64 #include "t4_l2t.h" 65 66 #define DRV_NAME "iw_cxgbe" 67 #define MOD DRV_NAME ":" 68 #define KTR_IW_CXGBE KTR_SPARE3 69 70 extern int c4iw_debug; 71 #define PDBG(fmt, args...) \ 72 do { \ 73 if (c4iw_debug) \ 74 printf(MOD fmt, ## args); \ 75 } while (0) 76 77 #include "t4.h" 78 79 static inline void *cplhdr(struct mbuf *m) 80 { 81 return mtod(m, void*); 82 } 83 84 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start) 85 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start) 86 87 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */ 88 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */ 89 90 struct c4iw_id_table { 91 u32 flags; 92 u32 start; /* logical minimal id */ 93 u32 last; /* hint for find */ 94 u32 max; 95 spinlock_t lock; 96 unsigned long *table; 97 }; 98 99 struct c4iw_resource { 100 struct c4iw_id_table tpt_table; 101 struct c4iw_id_table qid_table; 102 struct c4iw_id_table pdid_table; 103 }; 104 105 struct c4iw_qid_list { 106 struct list_head entry; 107 u32 qid; 108 }; 109 110 struct c4iw_dev_ucontext { 111 struct list_head qpids; 112 struct list_head cqids; 113 struct mutex lock; 114 }; 115 116 enum c4iw_rdev_flags { 117 T4_FATAL_ERROR = (1<<0), 118 }; 119 120 struct c4iw_stat { 121 u64 total; 122 u64 cur; 123 u64 max; 124 u64 fail; 125 }; 126 127 struct c4iw_stats { 128 struct mutex lock; 129 struct c4iw_stat qid; 130 struct c4iw_stat pd; 131 struct c4iw_stat stag; 132 struct c4iw_stat pbl; 133 struct c4iw_stat rqt; 134 u64 db_full; 135 u64 db_empty; 136 u64 db_drop; 137 u64 db_state_transitions; 138 }; 139 140 struct c4iw_rdev { 141 struct adapter *adap; 142 struct c4iw_resource resource; 143 unsigned long qpshift; 144 u32 qpmask; 145 unsigned long cqshift; 146 u32 cqmask; 147 struct c4iw_dev_ucontext uctx; 148 vmem_t *rqt_arena; 149 vmem_t *pbl_arena; 150 u32 flags; 151 struct c4iw_stats stats; 152 }; 153 154 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev) 155 { 156 return rdev->flags & T4_FATAL_ERROR; 157 } 158 159 static inline int c4iw_num_stags(struct c4iw_rdev *rdev) 160 { 161 return (int)(rdev->adap->vres.stag.size >> 5); 162 } 163 164 #define C4IW_WR_TO (10*HZ) 165 166 struct c4iw_wr_wait { 167 int ret; 168 atomic_t completion; 169 }; 170 171 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp) 172 { 173 wr_waitp->ret = 0; 174 atomic_set(&wr_waitp->completion, 0); 175 } 176 177 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret) 178 { 179 wr_waitp->ret = ret; 180 atomic_set(&wr_waitp->completion, 1); 181 wakeup(wr_waitp); 182 } 183 184 static inline int 185 c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp, 186 u32 hwtid, u32 qpid, const char *func) 187 { 188 struct adapter *sc = rdev->adap; 189 unsigned to = C4IW_WR_TO; 190 191 while (!atomic_read(&wr_waitp->completion)) { 192 tsleep(wr_waitp, 0, "c4iw_wait", to); 193 if (SIGPENDING(curthread)) { 194 printf("%s - Device %s not responding - " 195 "tid %u qpid %u\n", func, 196 device_get_nameunit(sc->dev), hwtid, qpid); 197 if (c4iw_fatal_error(rdev)) { 198 wr_waitp->ret = -EIO; 199 break; 200 } 201 to = to << 2; 202 } 203 } 204 if (wr_waitp->ret) 205 CTR4(KTR_IW_CXGBE, "%s: FW reply %d tid %u qpid %u", 206 device_get_nameunit(sc->dev), wr_waitp->ret, hwtid, qpid); 207 return (wr_waitp->ret); 208 } 209 210 enum db_state { 211 NORMAL = 0, 212 FLOW_CONTROL = 1, 213 RECOVERY = 2 214 }; 215 216 struct c4iw_dev { 217 struct ib_device ibdev; 218 struct c4iw_rdev rdev; 219 u32 device_cap_flags; 220 struct idr cqidr; 221 struct idr qpidr; 222 struct idr mmidr; 223 spinlock_t lock; 224 struct dentry *debugfs_root; 225 enum db_state db_state; 226 int qpcnt; 227 }; 228 229 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev) 230 { 231 return container_of(ibdev, struct c4iw_dev, ibdev); 232 } 233 234 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev) 235 { 236 return container_of(rdev, struct c4iw_dev, rdev); 237 } 238 239 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid) 240 { 241 return idr_find(&rhp->cqidr, cqid); 242 } 243 244 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid) 245 { 246 return idr_find(&rhp->qpidr, qpid); 247 } 248 249 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid) 250 { 251 return idr_find(&rhp->mmidr, mmid); 252 } 253 254 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr, 255 void *handle, u32 id, int lock) 256 { 257 int ret; 258 int newid; 259 260 do { 261 if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC)) 262 return -ENOMEM; 263 if (lock) 264 spin_lock_irq(&rhp->lock); 265 ret = idr_get_new_above(idr, handle, id, &newid); 266 BUG_ON(!ret && newid != id); 267 if (lock) 268 spin_unlock_irq(&rhp->lock); 269 } while (ret == -EAGAIN); 270 271 return ret; 272 } 273 274 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr, 275 void *handle, u32 id) 276 { 277 return _insert_handle(rhp, idr, handle, id, 1); 278 } 279 280 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr, 281 void *handle, u32 id) 282 { 283 return _insert_handle(rhp, idr, handle, id, 0); 284 } 285 286 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr, 287 u32 id, int lock) 288 { 289 if (lock) 290 spin_lock_irq(&rhp->lock); 291 idr_remove(idr, id); 292 if (lock) 293 spin_unlock_irq(&rhp->lock); 294 } 295 296 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id) 297 { 298 _remove_handle(rhp, idr, id, 1); 299 } 300 301 static inline void remove_handle_nolock(struct c4iw_dev *rhp, 302 struct idr *idr, u32 id) 303 { 304 _remove_handle(rhp, idr, id, 0); 305 } 306 307 struct c4iw_pd { 308 struct ib_pd ibpd; 309 u32 pdid; 310 struct c4iw_dev *rhp; 311 }; 312 313 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd) 314 { 315 return container_of(ibpd, struct c4iw_pd, ibpd); 316 } 317 318 struct tpt_attributes { 319 u64 len; 320 u64 va_fbo; 321 enum fw_ri_mem_perms perms; 322 u32 stag; 323 u32 pdid; 324 u32 qpid; 325 u32 pbl_addr; 326 u32 pbl_size; 327 u32 state:1; 328 u32 type:2; 329 u32 rsvd:1; 330 u32 remote_invaliate_disable:1; 331 u32 zbva:1; 332 u32 mw_bind_enable:1; 333 u32 page_size:5; 334 }; 335 336 struct c4iw_mr { 337 struct ib_mr ibmr; 338 struct ib_umem *umem; 339 struct c4iw_dev *rhp; 340 u64 kva; 341 struct tpt_attributes attr; 342 }; 343 344 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr) 345 { 346 return container_of(ibmr, struct c4iw_mr, ibmr); 347 } 348 349 struct c4iw_mw { 350 struct ib_mw ibmw; 351 struct c4iw_dev *rhp; 352 u64 kva; 353 struct tpt_attributes attr; 354 }; 355 356 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw) 357 { 358 return container_of(ibmw, struct c4iw_mw, ibmw); 359 } 360 361 struct c4iw_fr_page_list { 362 struct ib_fast_reg_page_list ibpl; 363 DECLARE_PCI_UNMAP_ADDR(mapping); 364 dma_addr_t dma_addr; 365 struct c4iw_dev *dev; 366 int size; 367 }; 368 369 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list( 370 struct ib_fast_reg_page_list *ibpl) 371 { 372 return container_of(ibpl, struct c4iw_fr_page_list, ibpl); 373 } 374 375 struct c4iw_cq { 376 struct ib_cq ibcq; 377 struct c4iw_dev *rhp; 378 struct t4_cq cq; 379 spinlock_t lock; 380 spinlock_t comp_handler_lock; 381 atomic_t refcnt; 382 wait_queue_head_t wait; 383 }; 384 385 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq) 386 { 387 return container_of(ibcq, struct c4iw_cq, ibcq); 388 } 389 390 struct c4iw_mpa_attributes { 391 u8 initiator; 392 u8 recv_marker_enabled; 393 u8 xmit_marker_enabled; 394 u8 crc_enabled; 395 u8 enhanced_rdma_conn; 396 u8 version; 397 u8 p2p_type; 398 }; 399 400 struct c4iw_qp_attributes { 401 u32 scq; 402 u32 rcq; 403 u32 sq_num_entries; 404 u32 rq_num_entries; 405 u32 sq_max_sges; 406 u32 sq_max_sges_rdma_write; 407 u32 rq_max_sges; 408 u32 state; 409 u8 enable_rdma_read; 410 u8 enable_rdma_write; 411 u8 enable_bind; 412 u8 enable_mmid0_fastreg; 413 u32 max_ord; 414 u32 max_ird; 415 u32 pd; 416 u32 next_state; 417 char terminate_buffer[52]; 418 u32 terminate_msg_len; 419 u8 is_terminate_local; 420 struct c4iw_mpa_attributes mpa_attr; 421 struct c4iw_ep *llp_stream_handle; 422 u8 layer_etype; 423 u8 ecode; 424 u16 sq_db_inc; 425 u16 rq_db_inc; 426 }; 427 428 struct c4iw_qp { 429 struct ib_qp ibqp; 430 struct c4iw_dev *rhp; 431 struct c4iw_ep *ep; 432 struct c4iw_qp_attributes attr; 433 struct t4_wq wq; 434 spinlock_t lock; 435 struct mutex mutex; 436 atomic_t refcnt; 437 wait_queue_head_t wait; 438 struct timer_list timer; 439 int sq_sig_all; 440 }; 441 442 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp) 443 { 444 return container_of(ibqp, struct c4iw_qp, ibqp); 445 } 446 447 struct c4iw_ucontext { 448 struct ib_ucontext ibucontext; 449 struct c4iw_dev_ucontext uctx; 450 u32 key; 451 spinlock_t mmap_lock; 452 struct list_head mmaps; 453 }; 454 455 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c) 456 { 457 return container_of(c, struct c4iw_ucontext, ibucontext); 458 } 459 460 struct c4iw_mm_entry { 461 struct list_head entry; 462 u64 addr; 463 u32 key; 464 unsigned len; 465 }; 466 467 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext, 468 u32 key, unsigned len) 469 { 470 struct list_head *pos, *nxt; 471 struct c4iw_mm_entry *mm; 472 473 spin_lock(&ucontext->mmap_lock); 474 list_for_each_safe(pos, nxt, &ucontext->mmaps) { 475 476 mm = list_entry(pos, struct c4iw_mm_entry, entry); 477 if (mm->key == key && mm->len == len) { 478 list_del_init(&mm->entry); 479 spin_unlock(&ucontext->mmap_lock); 480 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", 481 __func__, key, (unsigned long long) mm->addr, 482 mm->len); 483 return mm; 484 } 485 } 486 spin_unlock(&ucontext->mmap_lock); 487 return NULL; 488 } 489 490 static inline void insert_mmap(struct c4iw_ucontext *ucontext, 491 struct c4iw_mm_entry *mm) 492 { 493 spin_lock(&ucontext->mmap_lock); 494 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key, 495 (unsigned long long) mm->addr, mm->len); 496 list_add_tail(&mm->entry, &ucontext->mmaps); 497 spin_unlock(&ucontext->mmap_lock); 498 } 499 500 enum c4iw_qp_attr_mask { 501 C4IW_QP_ATTR_NEXT_STATE = 1 << 0, 502 C4IW_QP_ATTR_SQ_DB = 1<<1, 503 C4IW_QP_ATTR_RQ_DB = 1<<2, 504 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7, 505 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8, 506 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9, 507 C4IW_QP_ATTR_MAX_ORD = 1 << 11, 508 C4IW_QP_ATTR_MAX_IRD = 1 << 12, 509 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22, 510 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23, 511 C4IW_QP_ATTR_MPA_ATTR = 1 << 24, 512 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25, 513 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ | 514 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 515 C4IW_QP_ATTR_MAX_ORD | 516 C4IW_QP_ATTR_MAX_IRD | 517 C4IW_QP_ATTR_LLP_STREAM_HANDLE | 518 C4IW_QP_ATTR_STREAM_MSG_BUFFER | 519 C4IW_QP_ATTR_MPA_ATTR | 520 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE) 521 }; 522 523 int c4iw_modify_qp(struct c4iw_dev *rhp, 524 struct c4iw_qp *qhp, 525 enum c4iw_qp_attr_mask mask, 526 struct c4iw_qp_attributes *attrs, 527 int internal); 528 529 enum c4iw_qp_state { 530 C4IW_QP_STATE_IDLE, 531 C4IW_QP_STATE_RTS, 532 C4IW_QP_STATE_ERROR, 533 C4IW_QP_STATE_TERMINATE, 534 C4IW_QP_STATE_CLOSING, 535 C4IW_QP_STATE_TOT 536 }; 537 538 static inline int c4iw_convert_state(enum ib_qp_state ib_state) 539 { 540 switch (ib_state) { 541 case IB_QPS_RESET: 542 case IB_QPS_INIT: 543 return C4IW_QP_STATE_IDLE; 544 case IB_QPS_RTS: 545 return C4IW_QP_STATE_RTS; 546 case IB_QPS_SQD: 547 return C4IW_QP_STATE_CLOSING; 548 case IB_QPS_SQE: 549 return C4IW_QP_STATE_TERMINATE; 550 case IB_QPS_ERR: 551 return C4IW_QP_STATE_ERROR; 552 default: 553 return -1; 554 } 555 } 556 557 static inline int to_ib_qp_state(int c4iw_qp_state) 558 { 559 switch (c4iw_qp_state) { 560 case C4IW_QP_STATE_IDLE: 561 return IB_QPS_INIT; 562 case C4IW_QP_STATE_RTS: 563 return IB_QPS_RTS; 564 case C4IW_QP_STATE_CLOSING: 565 return IB_QPS_SQD; 566 case C4IW_QP_STATE_TERMINATE: 567 return IB_QPS_SQE; 568 case C4IW_QP_STATE_ERROR: 569 return IB_QPS_ERR; 570 } 571 return IB_QPS_ERR; 572 } 573 574 static inline u32 c4iw_ib_to_tpt_access(int a) 575 { 576 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 577 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) | 578 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) | 579 FW_RI_MEM_ACCESS_LOCAL_READ; 580 } 581 582 static inline u32 c4iw_ib_to_tpt_bind_access(int acc) 583 { 584 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | 585 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0); 586 } 587 588 enum c4iw_mmid_state { 589 C4IW_STAG_STATE_VALID, 590 C4IW_STAG_STATE_INVALID 591 }; 592 593 #define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications" 594 595 #define MPA_KEY_REQ "MPA ID Req Frame" 596 #define MPA_KEY_REP "MPA ID Rep Frame" 597 598 #define MPA_MAX_PRIVATE_DATA 256 599 #define MPA_ENHANCED_RDMA_CONN 0x10 600 #define MPA_REJECT 0x20 601 #define MPA_CRC 0x40 602 #define MPA_MARKERS 0x80 603 #define MPA_FLAGS_MASK 0xE0 604 605 #define MPA_V2_PEER2PEER_MODEL 0x8000 606 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000 607 #define MPA_V2_RDMA_WRITE_RTR 0x8000 608 #define MPA_V2_RDMA_READ_RTR 0x4000 609 #define MPA_V2_IRD_ORD_MASK 0x3FFF 610 611 #define c4iw_put_ep(ep) { \ 612 CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \ 613 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \ 614 WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \ 615 kref_put(&((ep)->kref), _c4iw_free_ep); \ 616 } 617 618 #define c4iw_get_ep(ep) { \ 619 CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \ 620 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \ 621 kref_get(&((ep)->kref)); \ 622 } 623 624 void _c4iw_free_ep(struct kref *kref); 625 626 struct mpa_message { 627 u8 key[16]; 628 u8 flags; 629 u8 revision; 630 __be16 private_data_size; 631 u8 private_data[0]; 632 }; 633 634 struct mpa_v2_conn_params { 635 __be16 ird; 636 __be16 ord; 637 }; 638 639 struct terminate_message { 640 u8 layer_etype; 641 u8 ecode; 642 __be16 hdrct_rsvd; 643 u8 len_hdrs[0]; 644 }; 645 646 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28) 647 648 enum c4iw_layers_types { 649 LAYER_RDMAP = 0x00, 650 LAYER_DDP = 0x10, 651 LAYER_MPA = 0x20, 652 RDMAP_LOCAL_CATA = 0x00, 653 RDMAP_REMOTE_PROT = 0x01, 654 RDMAP_REMOTE_OP = 0x02, 655 DDP_LOCAL_CATA = 0x00, 656 DDP_TAGGED_ERR = 0x01, 657 DDP_UNTAGGED_ERR = 0x02, 658 DDP_LLP = 0x03 659 }; 660 661 enum c4iw_rdma_ecodes { 662 RDMAP_INV_STAG = 0x00, 663 RDMAP_BASE_BOUNDS = 0x01, 664 RDMAP_ACC_VIOL = 0x02, 665 RDMAP_STAG_NOT_ASSOC = 0x03, 666 RDMAP_TO_WRAP = 0x04, 667 RDMAP_INV_VERS = 0x05, 668 RDMAP_INV_OPCODE = 0x06, 669 RDMAP_STREAM_CATA = 0x07, 670 RDMAP_GLOBAL_CATA = 0x08, 671 RDMAP_CANT_INV_STAG = 0x09, 672 RDMAP_UNSPECIFIED = 0xff 673 }; 674 675 enum c4iw_ddp_ecodes { 676 DDPT_INV_STAG = 0x00, 677 DDPT_BASE_BOUNDS = 0x01, 678 DDPT_STAG_NOT_ASSOC = 0x02, 679 DDPT_TO_WRAP = 0x03, 680 DDPT_INV_VERS = 0x04, 681 DDPU_INV_QN = 0x01, 682 DDPU_INV_MSN_NOBUF = 0x02, 683 DDPU_INV_MSN_RANGE = 0x03, 684 DDPU_INV_MO = 0x04, 685 DDPU_MSG_TOOBIG = 0x05, 686 DDPU_INV_VERS = 0x06 687 }; 688 689 enum c4iw_mpa_ecodes { 690 MPA_CRC_ERR = 0x02, 691 MPA_MARKER_ERR = 0x03, 692 MPA_LOCAL_CATA = 0x05, 693 MPA_INSUFF_IRD = 0x06, 694 MPA_NOMATCH_RTR = 0x07, 695 }; 696 697 enum c4iw_ep_state { 698 IDLE = 0, 699 LISTEN, 700 CONNECTING, 701 MPA_REQ_WAIT, 702 MPA_REQ_SENT, 703 MPA_REQ_RCVD, 704 MPA_REP_SENT, 705 FPDU_MODE, 706 ABORTING, 707 CLOSING, 708 MORIBUND, 709 DEAD, 710 }; 711 712 enum c4iw_ep_flags { 713 PEER_ABORT_IN_PROGRESS = 0, 714 ABORT_REQ_IN_PROGRESS = 1, 715 RELEASE_RESOURCES = 2, 716 CLOSE_SENT = 3, 717 TIMEOUT = 4, 718 QP_REFERENCED = 5 719 }; 720 721 enum c4iw_ep_history { 722 ACT_OPEN_REQ = 0, 723 ACT_OFLD_CONN = 1, 724 ACT_OPEN_RPL = 2, 725 ACT_ESTAB = 3, 726 PASS_ACCEPT_REQ = 4, 727 PASS_ESTAB = 5, 728 ABORT_UPCALL = 6, 729 ESTAB_UPCALL = 7, 730 CLOSE_UPCALL = 8, 731 ULP_ACCEPT = 9, 732 ULP_REJECT = 10, 733 TIMEDOUT = 11, 734 PEER_ABORT = 12, 735 PEER_CLOSE = 13, 736 CONNREQ_UPCALL = 14, 737 ABORT_CONN = 15, 738 DISCONN_UPCALL = 16, 739 EP_DISC_CLOSE = 17, 740 EP_DISC_ABORT = 18, 741 CONN_RPL_UPCALL = 19, 742 ACT_RETRY_NOMEM = 20, 743 ACT_RETRY_INUSE = 21, 744 CLOSE_CON_RPL = 22, 745 EP_DISC_FAIL = 24, 746 QP_REFED = 25, 747 QP_DEREFED = 26, 748 CM_ID_REFED = 27, 749 CM_ID_DEREFED = 28 750 }; 751 752 struct c4iw_ep_common { 753 TAILQ_ENTRY(c4iw_ep_common) entry; /* Work queue attachment */ 754 struct iw_cm_id *cm_id; 755 struct c4iw_qp *qp; 756 struct c4iw_dev *dev; 757 enum c4iw_ep_state state; 758 struct kref kref; 759 struct mutex mutex; 760 struct sockaddr_in local_addr; 761 struct sockaddr_in remote_addr; 762 struct c4iw_wr_wait wr_wait; 763 unsigned long flags; 764 unsigned long history; 765 int rpl_err; 766 int rpl_done; 767 struct thread *thread; 768 struct socket *so; 769 }; 770 771 struct c4iw_listen_ep { 772 struct c4iw_ep_common com; 773 unsigned int stid; 774 int backlog; 775 }; 776 777 struct c4iw_ep { 778 struct c4iw_ep_common com; 779 struct c4iw_ep *parent_ep; 780 struct timer_list timer; 781 struct list_head entry; 782 unsigned int atid; 783 u32 hwtid; 784 u32 snd_seq; 785 u32 rcv_seq; 786 struct l2t_entry *l2t; 787 struct dst_entry *dst; 788 struct c4iw_mpa_attributes mpa_attr; 789 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA]; 790 unsigned int mpa_pkt_len; 791 u32 ird; 792 u32 ord; 793 u32 smac_idx; 794 u32 tx_chan; 795 u32 mtu; 796 u16 mss; 797 u16 emss; 798 u16 plen; 799 u16 rss_qid; 800 u16 txq_idx; 801 u16 ctrlq_idx; 802 u8 tos; 803 u8 retry_with_mpa_v1; 804 u8 tried_with_mpa_v1; 805 }; 806 807 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id) 808 { 809 return cm_id->provider_data; 810 } 811 812 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id) 813 { 814 return cm_id->provider_data; 815 } 816 817 static inline int compute_wscale(int win) 818 { 819 int wscale = 0; 820 821 while (wscale < 14 && (65535<<wscale) < win) 822 wscale++; 823 return wscale; 824 } 825 826 u32 c4iw_id_alloc(struct c4iw_id_table *alloc); 827 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj); 828 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num, 829 u32 reserved, u32 flags); 830 void c4iw_id_table_free(struct c4iw_id_table *alloc); 831 832 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m); 833 834 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new, 835 struct l2t_entry *l2t); 836 u32 c4iw_get_resource(struct c4iw_id_table *id_table); 837 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry); 838 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid); 839 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev); 840 int c4iw_pblpool_create(struct c4iw_rdev *rdev); 841 int c4iw_rqtpool_create(struct c4iw_rdev *rdev); 842 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev); 843 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev); 844 void c4iw_destroy_resource(struct c4iw_resource *rscp); 845 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev); 846 int c4iw_register_device(struct c4iw_dev *dev); 847 void c4iw_unregister_device(struct c4iw_dev *dev); 848 int __init c4iw_cm_init(void); 849 void __exit c4iw_cm_term(void); 850 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, 851 struct c4iw_dev_ucontext *uctx); 852 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, 853 struct c4iw_dev_ucontext *uctx); 854 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 855 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 856 struct ib_send_wr **bad_wr); 857 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 858 struct ib_recv_wr **bad_wr); 859 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, 860 struct ib_mw_bind *mw_bind); 861 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 862 int c4iw_create_listen_ep(struct iw_cm_id *cm_id, int backlog); 863 void c4iw_destroy_listen_ep(struct iw_cm_id *cm_id); 864 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); 865 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len); 866 void c4iw_qp_add_ref(struct ib_qp *qp); 867 void c4iw_qp_rem_ref(struct ib_qp *qp); 868 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list); 869 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl( 870 struct ib_device *device, 871 int page_list_len); 872 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth); 873 int c4iw_dealloc_mw(struct ib_mw *mw); 874 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type); 875 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64 876 virt, int acc, struct ib_udata *udata, int mr_id); 877 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc); 878 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd, 879 struct ib_phys_buf *buffer_list, 880 int num_phys_buf, 881 int acc, 882 u64 *iova_start); 883 int c4iw_reregister_phys_mem(struct ib_mr *mr, 884 int mr_rereg_mask, 885 struct ib_pd *pd, 886 struct ib_phys_buf *buffer_list, 887 int num_phys_buf, 888 int acc, u64 *iova_start); 889 int c4iw_dereg_mr(struct ib_mr *ib_mr); 890 int c4iw_destroy_cq(struct ib_cq *ib_cq); 891 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, struct ib_cq_init_attr *attr, 892 struct ib_ucontext *ib_context, 893 struct ib_udata *udata); 894 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata); 895 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 896 int c4iw_destroy_qp(struct ib_qp *ib_qp); 897 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, 898 struct ib_qp_init_attr *attrs, 899 struct ib_udata *udata); 900 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 901 int attr_mask, struct ib_udata *udata); 902 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 903 int attr_mask, struct ib_qp_init_attr *init_attr); 904 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn); 905 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size); 906 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 907 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size); 908 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size); 909 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m); 910 void c4iw_flush_hw_cq(struct t4_cq *cq); 911 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 912 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count); 913 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp); 914 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count); 915 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count); 916 int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *); 917 u16 c4iw_rqes_posted(struct c4iw_qp *qhp); 918 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); 919 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 920 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid, 921 struct c4iw_dev_ucontext *uctx); 922 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 923 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid, 924 struct c4iw_dev_ucontext *uctx); 925 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe); 926 void process_newconn(struct iw_cm_id *parent_cm_id, 927 struct socket *child_so); 928 929 extern struct cxgb4_client t4c_client; 930 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; 931 extern int c4iw_max_read_depth; 932 933 #if defined(__i386__) || defined(__amd64__) 934 #define L1_CACHE_BYTES 128 935 #else 936 #define L1_CACHE_BYTES 32 937 #endif 938 939 void your_reg_device(struct c4iw_dev *dev); 940 941 #define SGE_CTRLQ_NUM 0 942 943 #endif 944