1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "opt_inet.h" 38 39 #ifdef TCP_OFFLOAD 40 #include <linux/types.h> 41 #include <linux/kref.h> 42 #include <rdma/ib_umem.h> 43 #include <asm/atomic.h> 44 45 #include <common/t4_msg.h> 46 #include "iw_cxgbe.h" 47 48 #define T4_ULPTX_MIN_IO 32 49 #define C4IW_MAX_INLINE_SIZE 96 50 #define T4_ULPTX_MAX_DMA 1024 51 52 static int 53 mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length) 54 { 55 56 return (is_t5(dev->rdev.adap) && length >= 8*1024*1024*1024ULL); 57 } 58 59 static int 60 _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr, u32 len, 61 void *data, int wait) 62 { 63 struct adapter *sc = rdev->adap; 64 struct ulp_mem_io *ulpmc; 65 struct ulptx_sgl *sgl; 66 u8 wr_len; 67 int ret = 0; 68 struct c4iw_wr_wait wr_wait; 69 struct wrqe *wr; 70 71 addr &= 0x7FFFFFF; 72 73 if (wait) 74 c4iw_init_wr_wait(&wr_wait); 75 wr_len = roundup(sizeof *ulpmc + sizeof *sgl, 16); 76 77 wr = alloc_wrqe(wr_len, &sc->sge.ctrlq[0]); 78 if (wr == NULL) 79 return -ENOMEM; 80 ulpmc = wrtod(wr); 81 82 memset(ulpmc, 0, wr_len); 83 INIT_ULPTX_WR(ulpmc, wr_len, 0, 0); 84 ulpmc->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR) | 85 (wait ? F_FW_WR_COMPL : 0)); 86 ulpmc->wr.wr_lo = wait ? (u64)(unsigned long)&wr_wait : 0; 87 ulpmc->wr.wr_mid = cpu_to_be32(V_FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16))); 88 ulpmc->cmd = cpu_to_be32(V_ULPTX_CMD(ULP_TX_MEM_WRITE) | 89 V_T5_ULP_MEMIO_ORDER(1) | 90 V_T5_ULP_MEMIO_FID(sc->sge.ofld_rxq[0].iq.abs_id)); 91 ulpmc->dlen = cpu_to_be32(V_ULP_MEMIO_DATA_LEN(len>>5)); 92 ulpmc->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(ulpmc->wr), 16)); 93 ulpmc->lock_addr = cpu_to_be32(V_ULP_MEMIO_ADDR(addr)); 94 95 sgl = (struct ulptx_sgl *)(ulpmc + 1); 96 sgl->cmd_nsge = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 97 V_ULPTX_NSGE(1)); 98 sgl->len0 = cpu_to_be32(len); 99 sgl->addr0 = cpu_to_be64((u64)data); 100 101 t4_wrq_tx(sc, wr); 102 103 if (wait) 104 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, NULL, __func__); 105 return ret; 106 } 107 108 109 static int 110 _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data) 111 { 112 struct adapter *sc = rdev->adap; 113 struct ulp_mem_io *ulpmc; 114 struct ulptx_idata *ulpsc; 115 u8 wr_len, *to_dp, *from_dp; 116 int copy_len, num_wqe, i, ret = 0; 117 struct c4iw_wr_wait wr_wait; 118 struct wrqe *wr; 119 u32 cmd; 120 121 cmd = cpu_to_be32(V_ULPTX_CMD(ULP_TX_MEM_WRITE)); 122 123 cmd |= cpu_to_be32(F_T5_ULP_MEMIO_IMM); 124 125 addr &= 0x7FFFFFF; 126 CTR3(KTR_IW_CXGBE, "%s addr 0x%x len %u", __func__, addr, len); 127 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE); 128 c4iw_init_wr_wait(&wr_wait); 129 for (i = 0; i < num_wqe; i++) { 130 131 copy_len = min(len, C4IW_MAX_INLINE_SIZE); 132 wr_len = roundup(sizeof *ulpmc + sizeof *ulpsc + 133 roundup(copy_len, T4_ULPTX_MIN_IO), 16); 134 135 wr = alloc_wrqe(wr_len, &sc->sge.ctrlq[0]); 136 if (wr == NULL) 137 return -ENOMEM; 138 ulpmc = wrtod(wr); 139 140 memset(ulpmc, 0, wr_len); 141 INIT_ULPTX_WR(ulpmc, wr_len, 0, 0); 142 143 if (i == (num_wqe-1)) { 144 ulpmc->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR) | 145 F_FW_WR_COMPL); 146 ulpmc->wr.wr_lo = 147 (__force __be64)(unsigned long) &wr_wait; 148 } else 149 ulpmc->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR)); 150 ulpmc->wr.wr_mid = cpu_to_be32( 151 V_FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16))); 152 153 ulpmc->cmd = cmd; 154 ulpmc->dlen = cpu_to_be32(V_ULP_MEMIO_DATA_LEN( 155 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO))); 156 ulpmc->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(ulpmc->wr), 157 16)); 158 ulpmc->lock_addr = cpu_to_be32(V_ULP_MEMIO_ADDR(addr + i * 3)); 159 160 ulpsc = (struct ulptx_idata *)(ulpmc + 1); 161 ulpsc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM)); 162 ulpsc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO)); 163 164 to_dp = (u8 *)(ulpsc + 1); 165 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE; 166 if (data) 167 memcpy(to_dp, from_dp, copy_len); 168 else 169 memset(to_dp, 0, copy_len); 170 if (copy_len % T4_ULPTX_MIN_IO) 171 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO - 172 (copy_len % T4_ULPTX_MIN_IO)); 173 t4_wrq_tx(sc, wr); 174 len -= C4IW_MAX_INLINE_SIZE; 175 } 176 177 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, NULL, __func__); 178 return ret; 179 } 180 181 static int 182 _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data) 183 { 184 struct c4iw_dev *rhp = rdev_to_c4iw_dev(rdev); 185 u32 remain = len; 186 u32 dmalen; 187 int ret = 0; 188 dma_addr_t daddr; 189 dma_addr_t save; 190 191 daddr = dma_map_single(rhp->ibdev.dma_device, data, len, DMA_TO_DEVICE); 192 if (dma_mapping_error(rhp->ibdev.dma_device, daddr)) 193 return -1; 194 save = daddr; 195 196 while (remain > inline_threshold) { 197 if (remain < T4_ULPTX_MAX_DMA) { 198 if (remain & ~T4_ULPTX_MIN_IO) 199 dmalen = remain & ~(T4_ULPTX_MIN_IO-1); 200 else 201 dmalen = remain; 202 } else 203 dmalen = T4_ULPTX_MAX_DMA; 204 remain -= dmalen; 205 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, 206 (void *)daddr, !remain); 207 if (ret) 208 goto out; 209 addr += dmalen >> 5; 210 data = (u8 *)data + dmalen; 211 daddr = daddr + dmalen; 212 } 213 if (remain) 214 ret = _c4iw_write_mem_inline(rdev, addr, remain, data); 215 out: 216 dma_unmap_single(rhp->ibdev.dma_device, save, len, DMA_TO_DEVICE); 217 return ret; 218 } 219 220 /* 221 * write len bytes of data into addr (32B aligned address) 222 * If data is NULL, clear len byte of memory to zero. 223 */ 224 static int 225 write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, 226 void *data) 227 { 228 if (rdev->adap->params.ulptx_memwrite_dsgl && use_dsgl) { 229 if (len > inline_threshold) { 230 if (_c4iw_write_mem_dma(rdev, addr, len, data)) { 231 log(LOG_ERR, "%s: dma map " 232 "failure (non fatal)\n", __func__); 233 return _c4iw_write_mem_inline(rdev, addr, len, 234 data); 235 } else 236 return 0; 237 } else 238 return _c4iw_write_mem_inline(rdev, addr, len, data); 239 } else 240 return _c4iw_write_mem_inline(rdev, addr, len, data); 241 } 242 243 244 /* 245 * Build and write a TPT entry. 246 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size, 247 * pbl_size and pbl_addr 248 * OUT: stag index 249 */ 250 static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry, 251 u32 *stag, u8 stag_state, u32 pdid, 252 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm, 253 int bind_enabled, u32 zbva, u64 to, 254 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr) 255 { 256 int err; 257 struct fw_ri_tpte tpt; 258 u32 stag_idx; 259 static atomic_t key; 260 261 if (c4iw_fatal_error(rdev)) 262 return -EIO; 263 264 stag_state = stag_state > 0; 265 stag_idx = (*stag) >> 8; 266 267 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) { 268 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table); 269 if (!stag_idx) { 270 mutex_lock(&rdev->stats.lock); 271 rdev->stats.stag.fail++; 272 mutex_unlock(&rdev->stats.lock); 273 return -ENOMEM; 274 } 275 mutex_lock(&rdev->stats.lock); 276 rdev->stats.stag.cur += 32; 277 if (rdev->stats.stag.cur > rdev->stats.stag.max) 278 rdev->stats.stag.max = rdev->stats.stag.cur; 279 mutex_unlock(&rdev->stats.lock); 280 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff); 281 } 282 CTR5(KTR_IW_CXGBE, 283 "%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x", 284 __func__, stag_state, type, pdid, stag_idx); 285 286 /* write TPT entry */ 287 if (reset_tpt_entry) 288 memset(&tpt, 0, sizeof(tpt)); 289 else { 290 if (page_size > ilog2(C4IW_MAX_PAGE_SIZE) - 12) 291 return -EINVAL; 292 tpt.valid_to_pdid = cpu_to_be32(F_FW_RI_TPTE_VALID | 293 V_FW_RI_TPTE_STAGKEY((*stag & M_FW_RI_TPTE_STAGKEY)) | 294 V_FW_RI_TPTE_STAGSTATE(stag_state) | 295 V_FW_RI_TPTE_STAGTYPE(type) | V_FW_RI_TPTE_PDID(pdid)); 296 tpt.locread_to_qpid = cpu_to_be32(V_FW_RI_TPTE_PERM(perm) | 297 (bind_enabled ? F_FW_RI_TPTE_MWBINDEN : 0) | 298 V_FW_RI_TPTE_ADDRTYPE((zbva ? FW_RI_ZERO_BASED_TO : 299 FW_RI_VA_BASED_TO))| 300 V_FW_RI_TPTE_PS(page_size)); 301 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32( 302 V_FW_RI_TPTE_PBLADDR(PBL_OFF(rdev, pbl_addr)>>3)); 303 tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL)); 304 tpt.va_hi = cpu_to_be32((u32)(to >> 32)); 305 tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL)); 306 tpt.dca_mwbcnt_pstag = cpu_to_be32(0); 307 tpt.len_hi = cpu_to_be32((u32)(len >> 32)); 308 } 309 err = write_adapter_mem(rdev, stag_idx + 310 (rdev->adap->vres.stag.start >> 5), 311 sizeof(tpt), &tpt); 312 313 if (reset_tpt_entry) { 314 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx); 315 mutex_lock(&rdev->stats.lock); 316 rdev->stats.stag.cur -= 32; 317 mutex_unlock(&rdev->stats.lock); 318 } 319 return err; 320 } 321 322 static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl, 323 u32 pbl_addr, u32 pbl_size) 324 { 325 int err; 326 327 CTR4(KTR_IW_CXGBE, "%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d", 328 __func__, pbl_addr, rdev->adap->vres.pbl.start, pbl_size); 329 330 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl); 331 return err; 332 } 333 334 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size, 335 u32 pbl_addr) 336 { 337 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 338 pbl_size, pbl_addr); 339 } 340 341 static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid) 342 { 343 *stag = T4_STAG_UNSET; 344 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0, 345 0UL, 0, 0, 0, 0); 346 } 347 348 static int deallocate_window(struct c4iw_rdev *rdev, u32 stag) 349 { 350 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0, 351 0); 352 } 353 354 static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid, 355 u32 pbl_size, u32 pbl_addr) 356 { 357 *stag = T4_STAG_UNSET; 358 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0, 359 0UL, 0, 0, pbl_size, pbl_addr); 360 } 361 362 static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag) 363 { 364 u32 mmid; 365 366 mhp->attr.state = 1; 367 mhp->attr.stag = stag; 368 mmid = stag >> 8; 369 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 370 CTR3(KTR_IW_CXGBE, "%s mmid 0x%x mhp %p", __func__, mmid, mhp); 371 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid); 372 } 373 374 static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php, 375 struct c4iw_mr *mhp, int shift) 376 { 377 u32 stag = T4_STAG_UNSET; 378 int ret; 379 380 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid, 381 FW_RI_STAG_NSMR, mhp->attr.len ? mhp->attr.perms : 0, 382 mhp->attr.mw_bind_enable, mhp->attr.zbva, 383 mhp->attr.va_fbo, mhp->attr.len ? mhp->attr.len : -1, shift - 12, 384 mhp->attr.pbl_size, mhp->attr.pbl_addr); 385 if (ret) 386 return ret; 387 388 ret = finish_mem_reg(mhp, stag); 389 if (ret) 390 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 391 mhp->attr.pbl_addr); 392 return ret; 393 } 394 395 static int alloc_pbl(struct c4iw_mr *mhp, int npages) 396 { 397 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev, 398 npages << 3); 399 400 if (!mhp->attr.pbl_addr) 401 return -ENOMEM; 402 403 mhp->attr.pbl_size = npages; 404 405 return 0; 406 } 407 408 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc) 409 { 410 struct c4iw_dev *rhp; 411 struct c4iw_pd *php; 412 struct c4iw_mr *mhp; 413 int ret; 414 u32 stag = T4_STAG_UNSET; 415 416 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 417 php = to_c4iw_pd(pd); 418 rhp = php->rhp; 419 420 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 421 if (!mhp) 422 return ERR_PTR(-ENOMEM); 423 424 mhp->rhp = rhp; 425 mhp->attr.pdid = php->pdid; 426 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 427 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND; 428 mhp->attr.zbva = 0; 429 mhp->attr.va_fbo = 0; 430 mhp->attr.page_size = 0; 431 mhp->attr.len = ~0ULL; 432 mhp->attr.pbl_size = 0; 433 434 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid, 435 FW_RI_STAG_NSMR, mhp->attr.perms, 436 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0); 437 if (ret) 438 goto err1; 439 440 ret = finish_mem_reg(mhp, stag); 441 if (ret) 442 goto err2; 443 return &mhp->ibmr; 444 err2: 445 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 446 mhp->attr.pbl_addr); 447 err1: 448 kfree(mhp); 449 return ERR_PTR(ret); 450 } 451 452 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 453 u64 virt, int acc, struct ib_udata *udata) 454 { 455 __be64 *pages; 456 int shift, n, len; 457 int i, k, entry; 458 int err = 0; 459 struct scatterlist *sg; 460 struct c4iw_dev *rhp; 461 struct c4iw_pd *php; 462 struct c4iw_mr *mhp; 463 464 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 465 466 if (length == ~0ULL) 467 return ERR_PTR(-EINVAL); 468 469 if ((length + start) < start) 470 return ERR_PTR(-EINVAL); 471 472 php = to_c4iw_pd(pd); 473 rhp = php->rhp; 474 475 if (mr_exceeds_hw_limits(rhp, length)) 476 return ERR_PTR(-EINVAL); 477 478 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 479 if (!mhp) 480 return ERR_PTR(-ENOMEM); 481 482 mhp->rhp = rhp; 483 484 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0); 485 if (IS_ERR(mhp->umem)) { 486 err = PTR_ERR(mhp->umem); 487 kfree(mhp); 488 return ERR_PTR(err); 489 } 490 491 shift = ffs(mhp->umem->page_size) - 1; 492 493 n = mhp->umem->nmap; 494 err = alloc_pbl(mhp, n); 495 if (err) 496 goto err; 497 498 pages = (__be64 *) __get_free_page(GFP_KERNEL); 499 if (!pages) { 500 err = -ENOMEM; 501 goto err_pbl; 502 } 503 504 i = n = 0; 505 for_each_sg(mhp->umem->sg_head.sgl, sg, mhp->umem->nmap, entry) { 506 len = sg_dma_len(sg) >> shift; 507 for (k = 0; k < len; ++k) { 508 pages[i++] = cpu_to_be64(sg_dma_address(sg) + 509 mhp->umem->page_size * k); 510 if (i == PAGE_SIZE / sizeof *pages) { 511 err = write_pbl(&mhp->rhp->rdev, 512 pages, 513 mhp->attr.pbl_addr + (n << 3), i); 514 if (err) 515 goto pbl_done; 516 n += i; 517 i = 0; 518 519 } 520 } 521 } 522 523 if (i) 524 err = write_pbl(&mhp->rhp->rdev, pages, 525 mhp->attr.pbl_addr + (n << 3), i); 526 527 pbl_done: 528 free_page((unsigned long) pages); 529 if (err) 530 goto err_pbl; 531 532 mhp->attr.pdid = php->pdid; 533 mhp->attr.zbva = 0; 534 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 535 mhp->attr.va_fbo = virt; 536 mhp->attr.page_size = shift - 12; 537 mhp->attr.len = length; 538 539 err = register_mem(rhp, php, mhp, shift); 540 if (err) 541 goto err_pbl; 542 543 return &mhp->ibmr; 544 545 err_pbl: 546 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 547 mhp->attr.pbl_size << 3); 548 549 err: 550 ib_umem_release(mhp->umem); 551 kfree(mhp); 552 return ERR_PTR(err); 553 } 554 555 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 556 struct ib_udata *udata) 557 { 558 struct c4iw_dev *rhp; 559 struct c4iw_pd *php; 560 struct c4iw_mw *mhp; 561 u32 mmid; 562 u32 stag = 0; 563 int ret; 564 565 if (type != IB_MW_TYPE_1) 566 return ERR_PTR(-EINVAL); 567 568 php = to_c4iw_pd(pd); 569 rhp = php->rhp; 570 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 571 if (!mhp) 572 return ERR_PTR(-ENOMEM); 573 ret = allocate_window(&rhp->rdev, &stag, php->pdid); 574 if (ret) { 575 kfree(mhp); 576 return ERR_PTR(ret); 577 } 578 mhp->rhp = rhp; 579 mhp->attr.pdid = php->pdid; 580 mhp->attr.type = FW_RI_STAG_MW; 581 mhp->attr.stag = stag; 582 mmid = (stag) >> 8; 583 mhp->ibmw.rkey = stag; 584 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 585 deallocate_window(&rhp->rdev, mhp->attr.stag); 586 kfree(mhp); 587 return ERR_PTR(-ENOMEM); 588 } 589 CTR4(KTR_IW_CXGBE, "%s mmid 0x%x mhp %p stag 0x%x", __func__, mmid, mhp, 590 stag); 591 return &(mhp->ibmw); 592 } 593 594 int c4iw_dealloc_mw(struct ib_mw *mw) 595 { 596 struct c4iw_dev *rhp; 597 struct c4iw_mw *mhp; 598 u32 mmid; 599 600 mhp = to_c4iw_mw(mw); 601 rhp = mhp->rhp; 602 mmid = (mw->rkey) >> 8; 603 remove_handle(rhp, &rhp->mmidr, mmid); 604 deallocate_window(&rhp->rdev, mhp->attr.stag); 605 kfree(mhp); 606 CTR4(KTR_IW_CXGBE, "%s ib_mw %p mmid 0x%x ptr %p", __func__, mw, mmid, 607 mhp); 608 return 0; 609 } 610 611 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, 612 enum ib_mr_type mr_type, 613 u32 max_num_sg, struct ib_udata *udata) 614 { 615 struct c4iw_dev *rhp; 616 struct c4iw_pd *php; 617 struct c4iw_mr *mhp; 618 u32 mmid; 619 u32 stag = 0; 620 int ret = 0; 621 int length = roundup(max_num_sg * sizeof(u64), 32); 622 623 php = to_c4iw_pd(pd); 624 rhp = php->rhp; 625 626 if (mr_type != IB_MR_TYPE_MEM_REG || 627 max_num_sg > t4_max_fr_depth(&rhp->rdev, use_dsgl)) 628 return ERR_PTR(-EINVAL); 629 630 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 631 if (!mhp) { 632 ret = -ENOMEM; 633 goto err; 634 } 635 636 mhp->mpl = dma_alloc_coherent(rhp->ibdev.dma_device, 637 length, &mhp->mpl_addr, GFP_KERNEL); 638 if (!mhp->mpl) { 639 ret = -ENOMEM; 640 goto err_mpl; 641 } 642 mhp->max_mpl_len = length; 643 644 mhp->rhp = rhp; 645 ret = alloc_pbl(mhp, max_num_sg); 646 if (ret) 647 goto err1; 648 mhp->attr.pbl_size = max_num_sg; 649 ret = allocate_stag(&rhp->rdev, &stag, php->pdid, 650 mhp->attr.pbl_size, mhp->attr.pbl_addr); 651 if (ret) 652 goto err2; 653 mhp->attr.pdid = php->pdid; 654 mhp->attr.type = FW_RI_STAG_NSMR; 655 mhp->attr.stag = stag; 656 mhp->attr.state = 0; 657 mmid = (stag) >> 8; 658 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 659 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 660 ret = -ENOMEM; 661 goto err3; 662 } 663 664 PDBG("%s mmid 0x%x mhp %p stag 0x%x\n", __func__, mmid, mhp, stag); 665 return &(mhp->ibmr); 666 err3: 667 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size, 668 mhp->attr.pbl_addr); 669 err2: 670 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 671 mhp->attr.pbl_size << 3); 672 err1: 673 dma_free_coherent(rhp->ibdev.dma_device, 674 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr); 675 err_mpl: 676 kfree(mhp); 677 err: 678 return ERR_PTR(ret); 679 } 680 static int c4iw_set_page(struct ib_mr *ibmr, u64 addr) 681 { 682 struct c4iw_mr *mhp = to_c4iw_mr(ibmr); 683 684 if (unlikely(mhp->mpl_len == mhp->attr.pbl_size)) 685 return -ENOMEM; 686 687 mhp->mpl[mhp->mpl_len++] = addr; 688 689 return 0; 690 } 691 692 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, 693 int sg_nents, unsigned int *sg_offset) 694 { 695 struct c4iw_mr *mhp = to_c4iw_mr(ibmr); 696 697 mhp->mpl_len = 0; 698 699 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, c4iw_set_page); 700 } 701 702 703 int c4iw_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 704 { 705 struct c4iw_dev *rhp; 706 struct c4iw_mr *mhp; 707 u32 mmid; 708 709 CTR2(KTR_IW_CXGBE, "%s ib_mr %p", __func__, ib_mr); 710 711 mhp = to_c4iw_mr(ib_mr); 712 rhp = mhp->rhp; 713 mmid = mhp->attr.stag >> 8; 714 remove_handle(rhp, &rhp->mmidr, mmid); 715 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 716 mhp->attr.pbl_addr); 717 if (mhp->attr.pbl_size) 718 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 719 mhp->attr.pbl_size << 3); 720 if (mhp->kva) 721 kfree((void *) (unsigned long) mhp->kva); 722 if (mhp->umem) 723 ib_umem_release(mhp->umem); 724 CTR3(KTR_IW_CXGBE, "%s mmid 0x%x ptr %p", __func__, mmid, mhp); 725 kfree(mhp); 726 return 0; 727 } 728 729 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey) 730 { 731 struct c4iw_mr *mhp; 732 unsigned long flags; 733 734 spin_lock_irqsave(&rhp->lock, flags); 735 mhp = get_mhp(rhp, rkey >> 8); 736 if (mhp) 737 mhp->attr.state = 0; 738 spin_unlock_irqrestore(&rhp->lock, flags); 739 } 740 #endif 741