1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_IOCTL_H__ 32 #define __T4_IOCTL_H__ 33 34 #include <sys/types.h> 35 #include <net/ethernet.h> 36 37 /* 38 * Ioctl commands specific to this driver. 39 */ 40 enum { 41 T4_GETREG = 0x40, /* read register */ 42 T4_SETREG, /* write register */ 43 T4_REGDUMP, /* dump of all registers */ 44 T4_GET_FILTER_MODE, /* get global filter mode */ 45 T4_SET_FILTER_MODE, /* set global filter mode */ 46 T4_GET_FILTER, /* get information about a filter */ 47 T4_SET_FILTER, /* program a filter */ 48 T4_DEL_FILTER, /* delete a filter */ 49 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 50 T4_LOAD_FW, /* flash firmware */ 51 T4_GET_MEM, /* read memory */ 52 T4_GET_I2C, /* read from i2c addressible device */ 53 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 54 T4_SET_OFLD_POLICY, /* Set offload policy */ 55 T4_SET_SCHED_CLASS, /* set sched class */ 56 T4_SET_SCHED_QUEUE, /* set queue class */ 57 T4_GET_TRACER, /* get information about a tracer */ 58 T4_SET_TRACER, /* program a tracer */ 59 T4_LOAD_CFG, /* copy a config file to card's flash */ 60 T4_LOAD_BOOT, /* flash boot rom */ 61 T4_LOAD_BOOTCFG, /* flash bootcfg */ 62 }; 63 64 struct t4_reg { 65 uint32_t addr; 66 uint32_t size; 67 uint64_t val; 68 }; 69 70 #define T4_REGDUMP_SIZE (160 * 1024) 71 #define T5_REGDUMP_SIZE (332 * 1024) 72 struct t4_regdump { 73 uint32_t version; 74 uint32_t len; /* bytes */ 75 uint32_t *data; 76 }; 77 78 struct t4_data { 79 uint32_t len; 80 uint8_t *data; 81 }; 82 83 struct t4_bootrom { 84 uint32_t pf_offset; 85 uint32_t pfidx_addr; 86 uint32_t len; 87 uint8_t *data; 88 }; 89 90 struct t4_i2c_data { 91 uint8_t port_id; 92 uint8_t dev_addr; 93 uint8_t offset; 94 uint8_t len; 95 uint8_t data[8]; 96 }; 97 98 /* 99 * A hardware filter is some valid combination of these. 100 */ 101 #define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 102 #define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 103 #define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 104 #define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 105 #define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 106 #define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 107 #define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 108 #define T4_FILTER_PORT 0x80 /* Physical ingress port */ 109 #define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 110 #define T4_FILTER_VLAN 0x200 /* VLAN ID */ 111 #define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 112 #define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 113 #define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 114 #define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 115 #define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 116 #define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 117 118 #define T4_FILTER_IC_VNIC 0x80000000 /* TP Ingress Config's F_VNIC 119 bit. It indicates whether 120 T4_FILTER_VNIC bit means VNIC 121 id (PF/VF) or outer VLAN. 122 0 = oVLAN, 1 = VNIC */ 123 124 /* Filter action */ 125 enum { 126 FILTER_PASS = 0, /* default */ 127 FILTER_DROP, 128 FILTER_SWITCH 129 }; 130 131 /* 802.1q manipulation on FILTER_SWITCH */ 132 enum { 133 VLAN_NOCHANGE = 0, /* default */ 134 VLAN_REMOVE, 135 VLAN_INSERT, 136 VLAN_REWRITE 137 }; 138 139 /* MPS match type */ 140 enum { 141 UCAST_EXACT = 0, /* exact unicast match */ 142 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 143 MCAST_EXACT = 2, /* exact multicast match */ 144 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 145 PROMISC = 4, /* no match but port is promiscuous */ 146 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 147 BCAST = 6, /* broadcast packet */ 148 }; 149 150 /* Rx steering */ 151 enum { 152 DST_MODE_QUEUE, /* queue is directly specified by filter */ 153 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 154 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 155 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 156 RSS subtable */ 157 }; 158 159 struct t4_filter_tuple { 160 /* 161 * These are always available. 162 */ 163 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 164 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 165 uint16_t sport; /* source port */ 166 uint16_t dport; /* destination port */ 167 168 /* 169 * A combination of these (up to 36 bits) is available. TP_VLAN_PRI_MAP 170 * is used to select the global mode and all filters are limited to the 171 * set of fields allowed by the global mode. 172 */ 173 uint16_t vnic; /* VNIC id (PF/VF) or outer VLAN tag */ 174 uint16_t vlan; /* VLAN tag */ 175 uint16_t ethtype; /* Ethernet type */ 176 uint8_t tos; /* TOS/Traffic Type */ 177 uint8_t proto; /* protocol type */ 178 uint32_t fcoe:1; /* FCoE packet */ 179 uint32_t iport:3; /* ingress port */ 180 uint32_t matchtype:3; /* MPS match type */ 181 uint32_t frag:1; /* fragmentation extension header */ 182 uint32_t macidx:9; /* exact match MAC index */ 183 uint32_t vlan_vld:1; /* VLAN valid */ 184 uint32_t ovlan_vld:1; /* outer VLAN tag valid, value in "vnic" */ 185 uint32_t pfvf_vld:1; /* VNIC id (PF/VF) valid, value in "vnic" */ 186 }; 187 188 struct t4_filter_specification { 189 uint32_t hitcnts:1; /* count filter hits in TCB */ 190 uint32_t prio:1; /* filter has priority over active/server */ 191 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 192 uint32_t action:2; /* drop, pass, switch */ 193 uint32_t rpttid:1; /* report TID in RSS hash field */ 194 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 195 uint32_t iq:10; /* ingress queue */ 196 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 197 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 198 /* 1 => TCB contains IQ ID */ 199 200 /* 201 * Switch proxy/rewrite fields. An ingress packet which matches a 202 * filter with "switch" set will be looped back out as an egress 203 * packet -- potentially with some Ethernet header rewriting. 204 */ 205 uint32_t eport:2; /* egress port to switch packet out */ 206 uint32_t newdmac:1; /* rewrite destination MAC address */ 207 uint32_t newsmac:1; /* rewrite source MAC address */ 208 uint32_t newvlan:2; /* rewrite VLAN Tag */ 209 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 210 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 211 uint16_t vlan; /* VLAN Tag to insert */ 212 213 /* 214 * Filter rule value/mask pairs. 215 */ 216 struct t4_filter_tuple val; 217 struct t4_filter_tuple mask; 218 }; 219 220 struct t4_filter { 221 uint32_t idx; 222 uint16_t l2tidx; 223 uint16_t smtidx; 224 uint64_t hits; 225 struct t4_filter_specification fs; 226 }; 227 228 /* Tx Scheduling Class parameters */ 229 struct t4_sched_class_params { 230 int8_t level; /* scheduler hierarchy level */ 231 int8_t mode; /* per-class or per-flow */ 232 int8_t rateunit; /* bit or packet rate */ 233 int8_t ratemode; /* %port relative or kbps absolute */ 234 int8_t channel; /* scheduler channel [0..N] */ 235 int8_t cl; /* scheduler class [0..N] */ 236 int32_t minrate; /* minimum rate */ 237 int32_t maxrate; /* maximum rate */ 238 int16_t weight; /* percent weight */ 239 int16_t pktsize; /* average packet size */ 240 }; 241 242 /* 243 * Support for "sched-class" command to allow a TX Scheduling Class to be 244 * programmed with various parameters. 245 */ 246 struct t4_sched_params { 247 int8_t subcmd; /* sub-command */ 248 int8_t type; /* packet or flow */ 249 union { 250 struct { /* sub-command SCHED_CLASS_CONFIG */ 251 int8_t minmax; /* minmax enable */ 252 } config; 253 struct t4_sched_class_params params; 254 uint8_t reserved[6 + 8 * 8]; 255 } u; 256 }; 257 258 enum { 259 SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */ 260 SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */ 261 }; 262 263 enum { 264 SCHED_CLASS_TYPE_PACKET, 265 }; 266 267 enum { 268 SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */ 269 SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */ 270 SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */ 271 }; 272 273 enum { 274 SCHED_CLASS_MODE_CLASS, /* per-class scheduling */ 275 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 276 }; 277 278 enum { 279 SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */ 280 SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */ 281 }; 282 283 enum { 284 SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */ 285 SCHED_CLASS_RATEMODE_ABS, /* Kb/s */ 286 }; 287 288 /* 289 * Support for "sched_queue" command to allow one or more NIC TX Queues to be 290 * bound to a TX Scheduling Class. 291 */ 292 struct t4_sched_queue { 293 uint8_t port; 294 int8_t queue; /* queue index; -1 => all queues */ 295 int8_t cl; /* class index; -1 => unbind */ 296 }; 297 298 #define T4_SGE_CONTEXT_SIZE 24 299 enum { 300 SGE_CONTEXT_EGRESS, 301 SGE_CONTEXT_INGRESS, 302 SGE_CONTEXT_FLM, 303 SGE_CONTEXT_CNM 304 }; 305 306 struct t4_sge_context { 307 uint32_t mem_id; 308 uint32_t cid; 309 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 310 }; 311 312 struct t4_mem_range { 313 uint32_t addr; 314 uint32_t len; 315 uint32_t *data; 316 }; 317 318 #define T4_TRACE_LEN 112 319 struct t4_trace_params { 320 uint32_t data[T4_TRACE_LEN / 4]; 321 uint32_t mask[T4_TRACE_LEN / 4]; 322 uint16_t snap_len; 323 uint16_t min_len; 324 uint8_t skip_ofst; 325 uint8_t skip_len; 326 uint8_t invert; 327 uint8_t port; 328 }; 329 330 struct t4_tracer { 331 uint8_t idx; 332 uint8_t enabled; 333 uint8_t valid; 334 struct t4_trace_params tp; 335 }; 336 337 #define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 338 #define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 339 #define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 340 #define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 341 #define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 342 #define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 343 #define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 344 #define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 345 #define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 346 struct t4_sge_context) 347 #define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 348 #define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 349 #define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 350 #define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 351 #define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \ 352 struct t4_sched_params) 353 #define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \ 354 struct t4_sched_queue) 355 #define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 356 #define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 357 #define CHELSIO_T4_LOAD_CFG _IOW('f', T4_LOAD_CFG, struct t4_data) 358 #define CHELSIO_T4_LOAD_BOOT _IOW('f', T4_LOAD_BOOT, struct t4_bootrom) 359 #define CHELSIO_T4_LOAD_BOOTCFG _IOW('f', T4_LOAD_BOOTCFG, struct t4_data) 360 #endif 361