1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ddb.h" 32 #include "opt_inet.h" 33 #include "opt_inet6.h" 34 #include "opt_rss.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/priv.h> 39 #include <sys/kernel.h> 40 #include <sys/bus.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/queue.h> 44 #include <sys/taskqueue.h> 45 #include <sys/pciio.h> 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pci_private.h> 49 #include <sys/firmware.h> 50 #include <sys/sbuf.h> 51 #include <sys/smp.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_types.h> 58 #include <net/if_dl.h> 59 #include <net/if_vlan_var.h> 60 #ifdef RSS 61 #include <net/rss_config.h> 62 #endif 63 #if defined(__i386__) || defined(__amd64__) 64 #include <vm/vm.h> 65 #include <vm/pmap.h> 66 #endif 67 #ifdef DDB 68 #include <ddb/ddb.h> 69 #include <ddb/db_lex.h> 70 #endif 71 72 #include "common/common.h" 73 #include "common/t4_msg.h" 74 #include "common/t4_regs.h" 75 #include "common/t4_regs_values.h" 76 #include "t4_ioctl.h" 77 #include "t4_l2t.h" 78 #include "t4_mp_ring.h" 79 #include "t4_if.h" 80 81 /* T4 bus driver interface */ 82 static int t4_probe(device_t); 83 static int t4_attach(device_t); 84 static int t4_detach(device_t); 85 static int t4_ready(device_t); 86 static int t4_read_port_device(device_t, int, device_t *); 87 static device_method_t t4_methods[] = { 88 DEVMETHOD(device_probe, t4_probe), 89 DEVMETHOD(device_attach, t4_attach), 90 DEVMETHOD(device_detach, t4_detach), 91 92 DEVMETHOD(t4_is_main_ready, t4_ready), 93 DEVMETHOD(t4_read_port_device, t4_read_port_device), 94 95 DEVMETHOD_END 96 }; 97 static driver_t t4_driver = { 98 "t4nex", 99 t4_methods, 100 sizeof(struct adapter) 101 }; 102 103 104 /* T4 port (cxgbe) interface */ 105 static int cxgbe_probe(device_t); 106 static int cxgbe_attach(device_t); 107 static int cxgbe_detach(device_t); 108 device_method_t cxgbe_methods[] = { 109 DEVMETHOD(device_probe, cxgbe_probe), 110 DEVMETHOD(device_attach, cxgbe_attach), 111 DEVMETHOD(device_detach, cxgbe_detach), 112 { 0, 0 } 113 }; 114 static driver_t cxgbe_driver = { 115 "cxgbe", 116 cxgbe_methods, 117 sizeof(struct port_info) 118 }; 119 120 /* T4 VI (vcxgbe) interface */ 121 static int vcxgbe_probe(device_t); 122 static int vcxgbe_attach(device_t); 123 static int vcxgbe_detach(device_t); 124 static device_method_t vcxgbe_methods[] = { 125 DEVMETHOD(device_probe, vcxgbe_probe), 126 DEVMETHOD(device_attach, vcxgbe_attach), 127 DEVMETHOD(device_detach, vcxgbe_detach), 128 { 0, 0 } 129 }; 130 static driver_t vcxgbe_driver = { 131 "vcxgbe", 132 vcxgbe_methods, 133 sizeof(struct vi_info) 134 }; 135 136 static d_ioctl_t t4_ioctl; 137 138 static struct cdevsw t4_cdevsw = { 139 .d_version = D_VERSION, 140 .d_ioctl = t4_ioctl, 141 .d_name = "t4nex", 142 }; 143 144 /* T5 bus driver interface */ 145 static int t5_probe(device_t); 146 static device_method_t t5_methods[] = { 147 DEVMETHOD(device_probe, t5_probe), 148 DEVMETHOD(device_attach, t4_attach), 149 DEVMETHOD(device_detach, t4_detach), 150 151 DEVMETHOD(t4_is_main_ready, t4_ready), 152 DEVMETHOD(t4_read_port_device, t4_read_port_device), 153 154 DEVMETHOD_END 155 }; 156 static driver_t t5_driver = { 157 "t5nex", 158 t5_methods, 159 sizeof(struct adapter) 160 }; 161 162 163 /* T5 port (cxl) interface */ 164 static driver_t cxl_driver = { 165 "cxl", 166 cxgbe_methods, 167 sizeof(struct port_info) 168 }; 169 170 /* T5 VI (vcxl) interface */ 171 static driver_t vcxl_driver = { 172 "vcxl", 173 vcxgbe_methods, 174 sizeof(struct vi_info) 175 }; 176 177 /* T6 bus driver interface */ 178 static int t6_probe(device_t); 179 static device_method_t t6_methods[] = { 180 DEVMETHOD(device_probe, t6_probe), 181 DEVMETHOD(device_attach, t4_attach), 182 DEVMETHOD(device_detach, t4_detach), 183 184 DEVMETHOD(t4_is_main_ready, t4_ready), 185 DEVMETHOD(t4_read_port_device, t4_read_port_device), 186 187 DEVMETHOD_END 188 }; 189 static driver_t t6_driver = { 190 "t6nex", 191 t6_methods, 192 sizeof(struct adapter) 193 }; 194 195 196 /* T6 port (cc) interface */ 197 static driver_t cc_driver = { 198 "cc", 199 cxgbe_methods, 200 sizeof(struct port_info) 201 }; 202 203 /* T6 VI (vcc) interface */ 204 static driver_t vcc_driver = { 205 "vcc", 206 vcxgbe_methods, 207 sizeof(struct vi_info) 208 }; 209 210 /* ifnet + media interface */ 211 static void cxgbe_init(void *); 212 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 213 static int cxgbe_transmit(struct ifnet *, struct mbuf *); 214 static void cxgbe_qflush(struct ifnet *); 215 static int cxgbe_media_change(struct ifnet *); 216 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 217 218 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 219 220 /* 221 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 222 * then ADAPTER_LOCK, then t4_uld_list_lock. 223 */ 224 static struct sx t4_list_lock; 225 SLIST_HEAD(, adapter) t4_list; 226 #ifdef TCP_OFFLOAD 227 static struct sx t4_uld_list_lock; 228 SLIST_HEAD(, uld_info) t4_uld_list; 229 #endif 230 231 /* 232 * Tunables. See tweak_tunables() too. 233 * 234 * Each tunable is set to a default value here if it's known at compile-time. 235 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 236 * provide a reasonable default (upto n) when the driver is loaded. 237 * 238 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 239 * T5 are under hw.cxl. 240 */ 241 242 /* 243 * Number of queues for tx and rx, 10G and 1G, NIC and offload. 244 */ 245 #define NTXQ_10G 16 246 int t4_ntxq10g = -NTXQ_10G; 247 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g); 248 249 #define NRXQ_10G 8 250 int t4_nrxq10g = -NRXQ_10G; 251 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g); 252 253 #define NTXQ_1G 4 254 int t4_ntxq1g = -NTXQ_1G; 255 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g); 256 257 #define NRXQ_1G 2 258 int t4_nrxq1g = -NRXQ_1G; 259 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g); 260 261 #define NTXQ_VI 1 262 static int t4_ntxq_vi = -NTXQ_VI; 263 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi); 264 265 #define NRXQ_VI 1 266 static int t4_nrxq_vi = -NRXQ_VI; 267 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi); 268 269 static int t4_rsrv_noflowq = 0; 270 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq); 271 272 #ifdef TCP_OFFLOAD 273 #define NOFLDTXQ_10G 8 274 static int t4_nofldtxq10g = -NOFLDTXQ_10G; 275 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g); 276 277 #define NOFLDRXQ_10G 2 278 static int t4_nofldrxq10g = -NOFLDRXQ_10G; 279 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g); 280 281 #define NOFLDTXQ_1G 2 282 static int t4_nofldtxq1g = -NOFLDTXQ_1G; 283 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g); 284 285 #define NOFLDRXQ_1G 1 286 static int t4_nofldrxq1g = -NOFLDRXQ_1G; 287 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g); 288 289 #define NOFLDTXQ_VI 1 290 static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 291 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi); 292 293 #define NOFLDRXQ_VI 1 294 static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 295 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi); 296 #endif 297 298 #ifdef DEV_NETMAP 299 #define NNMTXQ_VI 2 300 static int t4_nnmtxq_vi = -NNMTXQ_VI; 301 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi); 302 303 #define NNMRXQ_VI 2 304 static int t4_nnmrxq_vi = -NNMRXQ_VI; 305 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi); 306 #endif 307 308 /* 309 * Holdoff parameters for 10G and 1G ports. 310 */ 311 #define TMR_IDX_10G 1 312 int t4_tmr_idx_10g = TMR_IDX_10G; 313 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g); 314 315 #define PKTC_IDX_10G (-1) 316 int t4_pktc_idx_10g = PKTC_IDX_10G; 317 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g); 318 319 #define TMR_IDX_1G 1 320 int t4_tmr_idx_1g = TMR_IDX_1G; 321 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g); 322 323 #define PKTC_IDX_1G (-1) 324 int t4_pktc_idx_1g = PKTC_IDX_1G; 325 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g); 326 327 /* 328 * Size (# of entries) of each tx and rx queue. 329 */ 330 unsigned int t4_qsize_txq = TX_EQ_QSIZE; 331 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq); 332 333 unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 334 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq); 335 336 /* 337 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 338 */ 339 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 340 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); 341 342 /* 343 * Configuration file. 344 */ 345 #define DEFAULT_CF "default" 346 #define FLASH_CF "flash" 347 #define UWIRE_CF "uwire" 348 #define FPGA_CF "fpga" 349 static char t4_cfg_file[32] = DEFAULT_CF; 350 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); 351 352 /* 353 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively). 354 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 355 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 356 * mark or when signalled to do so, 0 to never emit PAUSE. 357 */ 358 static int t4_pause_settings = PAUSE_TX | PAUSE_RX; 359 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings); 360 361 /* 362 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS, 363 * FEC_RESERVED respectively). 364 * -1 to run with the firmware default. 365 * 0 to disable FEC. 366 */ 367 static int t4_fec = -1; 368 TUNABLE_INT("hw.cxgbe.fec", &t4_fec); 369 370 /* 371 * Link autonegotiation. 372 * -1 to run with the firmware default. 373 * 0 to disable. 374 * 1 to enable. 375 */ 376 static int t4_autoneg = -1; 377 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg); 378 379 /* 380 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 381 * encouraged respectively). 382 */ 383 static unsigned int t4_fw_install = 1; 384 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install); 385 386 /* 387 * ASIC features that will be used. Disable the ones you don't want so that the 388 * chip resources aren't wasted on features that will not be used. 389 */ 390 static int t4_nbmcaps_allowed = 0; 391 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed); 392 393 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 394 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed); 395 396 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 397 FW_CAPS_CONFIG_SWITCH_EGRESS; 398 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed); 399 400 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC; 401 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed); 402 403 static int t4_toecaps_allowed = -1; 404 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed); 405 406 static int t4_rdmacaps_allowed = -1; 407 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed); 408 409 static int t4_cryptocaps_allowed = 0; 410 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed); 411 412 static int t4_iscsicaps_allowed = -1; 413 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); 414 415 static int t4_fcoecaps_allowed = 0; 416 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); 417 418 static int t5_write_combine = 0; 419 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); 420 421 static int t4_num_vis = 1; 422 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis); 423 424 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */ 425 static int vi_mac_funcs[] = { 426 FW_VI_FUNC_OFLD, 427 FW_VI_FUNC_IWARP, 428 FW_VI_FUNC_OPENISCSI, 429 FW_VI_FUNC_OPENFCOE, 430 FW_VI_FUNC_FOISCSI, 431 FW_VI_FUNC_FOFCOE, 432 }; 433 434 struct intrs_and_queues { 435 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 436 uint16_t nirq; /* Total # of vectors */ 437 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */ 438 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */ 439 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */ 440 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */ 441 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */ 442 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */ 443 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */ 444 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */ 445 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */ 446 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */ 447 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */ 448 449 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 450 uint16_t ntxq_vi; /* # of NIC txq's */ 451 uint16_t nrxq_vi; /* # of NIC rxq's */ 452 uint16_t nofldtxq_vi; /* # of TOE txq's */ 453 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 454 uint16_t nnmtxq_vi; /* # of netmap txq's */ 455 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 456 }; 457 458 struct filter_entry { 459 uint32_t valid:1; /* filter allocated and valid */ 460 uint32_t locked:1; /* filter is administratively locked */ 461 uint32_t pending:1; /* filter action is pending firmware reply */ 462 uint32_t smtidx:8; /* Source MAC Table index for smac */ 463 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 464 465 struct t4_filter_specification fs; 466 }; 467 468 static void setup_memwin(struct adapter *); 469 static void position_memwin(struct adapter *, int, uint32_t); 470 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 471 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *, 472 int); 473 static inline int write_via_memwin(struct adapter *, int, uint32_t, 474 const uint32_t *, int); 475 static int validate_mem_range(struct adapter *, uint32_t, int); 476 static int fwmtype_to_hwmtype(int); 477 static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 478 uint32_t *); 479 static int fixup_devlog_params(struct adapter *); 480 static int cfg_itype_and_nqueues(struct adapter *, int, int, int, 481 struct intrs_and_queues *); 482 static int prep_firmware(struct adapter *); 483 static int partition_resources(struct adapter *, const struct firmware *, 484 const char *); 485 static int get_params__pre_init(struct adapter *); 486 static int get_params__post_init(struct adapter *); 487 static int set_params__post_init(struct adapter *); 488 static void t4_set_desc(struct adapter *); 489 static void build_medialist(struct port_info *, struct ifmedia *); 490 static int cxgbe_init_synchronized(struct vi_info *); 491 static int cxgbe_uninit_synchronized(struct vi_info *); 492 static void quiesce_txq(struct adapter *, struct sge_txq *); 493 static void quiesce_wrq(struct adapter *, struct sge_wrq *); 494 static void quiesce_iq(struct adapter *, struct sge_iq *); 495 static void quiesce_fl(struct adapter *, struct sge_fl *); 496 static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 497 driver_intr_t *, void *, char *); 498 static int t4_free_irq(struct adapter *, struct irq *); 499 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 500 static void vi_refresh_stats(struct adapter *, struct vi_info *); 501 static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 502 static void cxgbe_tick(void *); 503 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 504 static void cxgbe_sysctls(struct port_info *); 505 static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 506 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS); 507 static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 508 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 509 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 510 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 511 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 512 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 513 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 514 static int sysctl_fec(SYSCTL_HANDLER_ARGS); 515 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 516 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 517 static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 518 #ifdef SBUF_DRAIN 519 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 520 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 521 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 522 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 523 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 524 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 525 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 526 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 527 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 528 static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 529 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 530 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 531 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 532 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 533 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 534 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 535 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 536 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 537 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 538 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 539 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 540 static int sysctl_tids(SYSCTL_HANDLER_ARGS); 541 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 542 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 543 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 544 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 545 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 546 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 547 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 548 #endif 549 #ifdef TCP_OFFLOAD 550 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 551 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 552 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 553 #endif 554 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t); 555 static uint32_t mode_to_fconf(uint32_t); 556 static uint32_t mode_to_iconf(uint32_t); 557 static int check_fspec_against_fconf_iconf(struct adapter *, 558 struct t4_filter_specification *); 559 static int get_filter_mode(struct adapter *, uint32_t *); 560 static int set_filter_mode(struct adapter *, uint32_t); 561 static inline uint64_t get_filter_hits(struct adapter *, uint32_t); 562 static int get_filter(struct adapter *, struct t4_filter *); 563 static int set_filter(struct adapter *, struct t4_filter *); 564 static int del_filter(struct adapter *, struct t4_filter *); 565 static void clear_filter(struct filter_entry *); 566 static int set_filter_wr(struct adapter *, int); 567 static int del_filter_wr(struct adapter *, int); 568 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *, 569 struct mbuf *); 570 static int get_sge_context(struct adapter *, struct t4_sge_context *); 571 static int load_fw(struct adapter *, struct t4_data *); 572 static int load_cfg(struct adapter *, struct t4_data *); 573 static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 574 static int read_i2c(struct adapter *, struct t4_i2c_data *); 575 #ifdef TCP_OFFLOAD 576 static int toe_capability(struct vi_info *, int); 577 #endif 578 static int mod_event(module_t, int, void *); 579 static int notify_siblings(device_t, int); 580 581 struct { 582 uint16_t device; 583 char *desc; 584 } t4_pciids[] = { 585 {0xa000, "Chelsio Terminator 4 FPGA"}, 586 {0x4400, "Chelsio T440-dbg"}, 587 {0x4401, "Chelsio T420-CR"}, 588 {0x4402, "Chelsio T422-CR"}, 589 {0x4403, "Chelsio T440-CR"}, 590 {0x4404, "Chelsio T420-BCH"}, 591 {0x4405, "Chelsio T440-BCH"}, 592 {0x4406, "Chelsio T440-CH"}, 593 {0x4407, "Chelsio T420-SO"}, 594 {0x4408, "Chelsio T420-CX"}, 595 {0x4409, "Chelsio T420-BT"}, 596 {0x440a, "Chelsio T404-BT"}, 597 {0x440e, "Chelsio T440-LP-CR"}, 598 }, t5_pciids[] = { 599 {0xb000, "Chelsio Terminator 5 FPGA"}, 600 {0x5400, "Chelsio T580-dbg"}, 601 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 602 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 603 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 604 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 605 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 606 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 607 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 608 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 609 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 610 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 611 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 612 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 613 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 614 #ifdef notyet 615 {0x5404, "Chelsio T520-BCH"}, 616 {0x5405, "Chelsio T540-BCH"}, 617 {0x5406, "Chelsio T540-CH"}, 618 {0x5408, "Chelsio T520-CX"}, 619 {0x540b, "Chelsio B520-SR"}, 620 {0x540c, "Chelsio B504-BT"}, 621 {0x540f, "Chelsio Amsterdam"}, 622 {0x5413, "Chelsio T580-CHR"}, 623 #endif 624 }, t6_pciids[] = { 625 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 626 {0x6400, "Chelsio T6225-DBG"}, /* 2 x 10/25G, debug */ 627 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 628 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 629 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 630 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 631 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 632 {0x6410, "Chelsio T62100-DBG"}, /* 2 x 40/50/100G, debug */ 633 }; 634 635 #ifdef TCP_OFFLOAD 636 /* 637 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be 638 * exactly the same for both rxq and ofld_rxq. 639 */ 640 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 641 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 642 #endif 643 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 644 645 static int 646 t4_probe(device_t dev) 647 { 648 int i; 649 uint16_t v = pci_get_vendor(dev); 650 uint16_t d = pci_get_device(dev); 651 uint8_t f = pci_get_function(dev); 652 653 if (v != PCI_VENDOR_ID_CHELSIO) 654 return (ENXIO); 655 656 /* Attach only to PF0 of the FPGA */ 657 if (d == 0xa000 && f != 0) 658 return (ENXIO); 659 660 for (i = 0; i < nitems(t4_pciids); i++) { 661 if (d == t4_pciids[i].device) { 662 device_set_desc(dev, t4_pciids[i].desc); 663 return (BUS_PROBE_DEFAULT); 664 } 665 } 666 667 return (ENXIO); 668 } 669 670 static int 671 t5_probe(device_t dev) 672 { 673 int i; 674 uint16_t v = pci_get_vendor(dev); 675 uint16_t d = pci_get_device(dev); 676 uint8_t f = pci_get_function(dev); 677 678 if (v != PCI_VENDOR_ID_CHELSIO) 679 return (ENXIO); 680 681 /* Attach only to PF0 of the FPGA */ 682 if (d == 0xb000 && f != 0) 683 return (ENXIO); 684 685 for (i = 0; i < nitems(t5_pciids); i++) { 686 if (d == t5_pciids[i].device) { 687 device_set_desc(dev, t5_pciids[i].desc); 688 return (BUS_PROBE_DEFAULT); 689 } 690 } 691 692 return (ENXIO); 693 } 694 695 static int 696 t6_probe(device_t dev) 697 { 698 int i; 699 uint16_t v = pci_get_vendor(dev); 700 uint16_t d = pci_get_device(dev); 701 702 if (v != PCI_VENDOR_ID_CHELSIO) 703 return (ENXIO); 704 705 for (i = 0; i < nitems(t6_pciids); i++) { 706 if (d == t6_pciids[i].device) { 707 device_set_desc(dev, t6_pciids[i].desc); 708 return (BUS_PROBE_DEFAULT); 709 } 710 } 711 712 return (ENXIO); 713 } 714 715 static void 716 t5_attribute_workaround(device_t dev) 717 { 718 device_t root_port; 719 uint32_t v; 720 721 /* 722 * The T5 chips do not properly echo the No Snoop and Relaxed 723 * Ordering attributes when replying to a TLP from a Root 724 * Port. As a workaround, find the parent Root Port and 725 * disable No Snoop and Relaxed Ordering. Note that this 726 * affects all devices under this root port. 727 */ 728 root_port = pci_find_pcie_root_port(dev); 729 if (root_port == NULL) { 730 device_printf(dev, "Unable to find parent root port\n"); 731 return; 732 } 733 734 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 735 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 736 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 737 0) 738 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 739 device_get_nameunit(root_port)); 740 } 741 742 static const struct devnames devnames[] = { 743 { 744 .nexus_name = "t4nex", 745 .ifnet_name = "cxgbe", 746 .vi_ifnet_name = "vcxgbe", 747 .pf03_drv_name = "t4iov", 748 .vf_nexus_name = "t4vf", 749 .vf_ifnet_name = "cxgbev" 750 }, { 751 .nexus_name = "t5nex", 752 .ifnet_name = "cxl", 753 .vi_ifnet_name = "vcxl", 754 .pf03_drv_name = "t5iov", 755 .vf_nexus_name = "t5vf", 756 .vf_ifnet_name = "cxlv" 757 }, { 758 .nexus_name = "t6nex", 759 .ifnet_name = "cc", 760 .vi_ifnet_name = "vcc", 761 .pf03_drv_name = "t6iov", 762 .vf_nexus_name = "t6vf", 763 .vf_ifnet_name = "ccv" 764 } 765 }; 766 767 void 768 t4_init_devnames(struct adapter *sc) 769 { 770 int id; 771 772 id = chip_id(sc); 773 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 774 sc->names = &devnames[id - CHELSIO_T4]; 775 else { 776 device_printf(sc->dev, "chip id %d is not supported.\n", id); 777 sc->names = NULL; 778 } 779 } 780 781 static int 782 t4_attach(device_t dev) 783 { 784 struct adapter *sc; 785 int rc = 0, i, j, n10g, n1g, rqidx, tqidx; 786 struct make_dev_args mda; 787 struct intrs_and_queues iaq; 788 struct sge *s; 789 uint8_t *buf; 790 #ifdef TCP_OFFLOAD 791 int ofld_rqidx, ofld_tqidx; 792 #endif 793 #ifdef DEV_NETMAP 794 int nm_rqidx, nm_tqidx; 795 #endif 796 int num_vis; 797 798 sc = device_get_softc(dev); 799 sc->dev = dev; 800 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 801 802 if ((pci_get_device(dev) & 0xff00) == 0x5400) 803 t5_attribute_workaround(dev); 804 pci_enable_busmaster(dev); 805 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 806 uint32_t v; 807 808 pci_set_max_read_req(dev, 4096); 809 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 810 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 811 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 812 813 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 814 } 815 816 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 817 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 818 sc->traceq = -1; 819 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 820 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 821 device_get_nameunit(dev)); 822 823 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 824 device_get_nameunit(dev)); 825 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 826 t4_add_adapter(sc); 827 828 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 829 TAILQ_INIT(&sc->sfl); 830 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 831 832 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 833 834 rc = t4_map_bars_0_and_4(sc); 835 if (rc != 0) 836 goto done; /* error message displayed already */ 837 838 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 839 840 /* Prepare the adapter for operation. */ 841 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 842 rc = -t4_prep_adapter(sc, buf); 843 free(buf, M_CXGBE); 844 if (rc != 0) { 845 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 846 goto done; 847 } 848 849 /* 850 * This is the real PF# to which we're attaching. Works from within PCI 851 * passthrough environments too, where pci_get_function() could return a 852 * different PF# depending on the passthrough configuration. We need to 853 * use the real PF# in all our communication with the firmware. 854 */ 855 j = t4_read_reg(sc, A_PL_WHOAMI); 856 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 857 sc->mbox = sc->pf; 858 859 t4_init_devnames(sc); 860 if (sc->names == NULL) { 861 rc = ENOTSUP; 862 goto done; /* error message displayed already */ 863 } 864 865 /* 866 * Do this really early, with the memory windows set up even before the 867 * character device. The userland tool's register i/o and mem read 868 * will work even in "recovery mode". 869 */ 870 setup_memwin(sc); 871 if (t4_init_devlog_params(sc, 0) == 0) 872 fixup_devlog_params(sc); 873 make_dev_args_init(&mda); 874 mda.mda_devsw = &t4_cdevsw; 875 mda.mda_uid = UID_ROOT; 876 mda.mda_gid = GID_WHEEL; 877 mda.mda_mode = 0600; 878 mda.mda_si_drv1 = sc; 879 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 880 if (rc != 0) 881 device_printf(dev, "failed to create nexus char device: %d.\n", 882 rc); 883 884 /* Go no further if recovery mode has been requested. */ 885 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 886 device_printf(dev, "recovery mode.\n"); 887 goto done; 888 } 889 890 #if defined(__i386__) 891 if ((cpu_feature & CPUID_CX8) == 0) { 892 device_printf(dev, "64 bit atomics not available.\n"); 893 rc = ENOTSUP; 894 goto done; 895 } 896 #endif 897 898 /* Prepare the firmware for operation */ 899 rc = prep_firmware(sc); 900 if (rc != 0) 901 goto done; /* error message displayed already */ 902 903 rc = get_params__post_init(sc); 904 if (rc != 0) 905 goto done; /* error message displayed already */ 906 907 rc = set_params__post_init(sc); 908 if (rc != 0) 909 goto done; /* error message displayed already */ 910 911 rc = t4_map_bar_2(sc); 912 if (rc != 0) 913 goto done; /* error message displayed already */ 914 915 rc = t4_create_dma_tag(sc); 916 if (rc != 0) 917 goto done; /* error message displayed already */ 918 919 /* 920 * Number of VIs to create per-port. The first VI is the "main" regular 921 * VI for the port. The rest are additional virtual interfaces on the 922 * same physical port. Note that the main VI does not have native 923 * netmap support but the extra VIs do. 924 * 925 * Limit the number of VIs per port to the number of available 926 * MAC addresses per port. 927 */ 928 if (t4_num_vis >= 1) 929 num_vis = t4_num_vis; 930 else 931 num_vis = 1; 932 if (num_vis > nitems(vi_mac_funcs)) { 933 num_vis = nitems(vi_mac_funcs); 934 device_printf(dev, "Number of VIs limited to %d\n", num_vis); 935 } 936 937 /* 938 * First pass over all the ports - allocate VIs and initialize some 939 * basic parameters like mac address, port type, etc. We also figure 940 * out whether a port is 10G or 1G and use that information when 941 * calculating how many interrupts to attempt to allocate. 942 */ 943 n10g = n1g = 0; 944 for_each_port(sc, i) { 945 struct port_info *pi; 946 struct link_config *lc; 947 948 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 949 sc->port[i] = pi; 950 951 /* These must be set before t4_port_init */ 952 pi->adapter = sc; 953 pi->port_id = i; 954 /* 955 * XXX: vi[0] is special so we can't delay this allocation until 956 * pi->nvi's final value is known. 957 */ 958 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE, 959 M_ZERO | M_WAITOK); 960 961 /* 962 * Allocate the "main" VI and initialize parameters 963 * like mac addr. 964 */ 965 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 966 if (rc != 0) { 967 device_printf(dev, "unable to initialize port %d: %d\n", 968 i, rc); 969 free(pi->vi, M_CXGBE); 970 free(pi, M_CXGBE); 971 sc->port[i] = NULL; 972 goto done; 973 } 974 975 lc = &pi->link_cfg; 976 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 977 lc->requested_fc |= t4_pause_settings; 978 if (t4_fec != -1) { 979 lc->requested_fec = t4_fec & 980 G_FW_PORT_CAP_FEC(lc->supported); 981 } 982 if (lc->supported & FW_PORT_CAP_ANEG && t4_autoneg != -1) { 983 lc->autoneg = t4_autoneg ? AUTONEG_ENABLE : 984 AUTONEG_DISABLE; 985 } 986 987 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 988 if (rc != 0) { 989 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc); 990 free(pi->vi, M_CXGBE); 991 free(pi, M_CXGBE); 992 sc->port[i] = NULL; 993 goto done; 994 } 995 996 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 997 device_get_nameunit(dev), i); 998 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 999 sc->chan_map[pi->tx_chan] = i; 1000 1001 pi->tc = malloc(sizeof(struct tx_sched_class) * 1002 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK); 1003 1004 if (port_top_speed(pi) >= 10) { 1005 n10g++; 1006 } else { 1007 n1g++; 1008 } 1009 1010 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1); 1011 if (pi->dev == NULL) { 1012 device_printf(dev, 1013 "failed to add device for port %d.\n", i); 1014 rc = ENXIO; 1015 goto done; 1016 } 1017 pi->vi[0].dev = pi->dev; 1018 device_set_softc(pi->dev, pi); 1019 } 1020 1021 /* 1022 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1023 */ 1024 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq); 1025 if (rc != 0) 1026 goto done; /* error message displayed already */ 1027 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0) 1028 num_vis = 1; 1029 1030 sc->intr_type = iaq.intr_type; 1031 sc->intr_count = iaq.nirq; 1032 1033 s = &sc->sge; 1034 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g; 1035 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g; 1036 if (num_vis > 1) { 1037 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi; 1038 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi; 1039 } 1040 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1041 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 1042 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1043 #ifdef TCP_OFFLOAD 1044 if (is_offload(sc)) { 1045 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g; 1046 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g; 1047 if (num_vis > 1) { 1048 s->nofldrxq += (n10g + n1g) * (num_vis - 1) * 1049 iaq.nofldrxq_vi; 1050 s->nofldtxq += (n10g + n1g) * (num_vis - 1) * 1051 iaq.nofldtxq_vi; 1052 } 1053 s->neq += s->nofldtxq + s->nofldrxq; 1054 s->niq += s->nofldrxq; 1055 1056 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1057 M_CXGBE, M_ZERO | M_WAITOK); 1058 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1059 M_CXGBE, M_ZERO | M_WAITOK); 1060 } 1061 #endif 1062 #ifdef DEV_NETMAP 1063 if (num_vis > 1) { 1064 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi; 1065 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi; 1066 } 1067 s->neq += s->nnmtxq + s->nnmrxq; 1068 s->niq += s->nnmrxq; 1069 1070 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1071 M_CXGBE, M_ZERO | M_WAITOK); 1072 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1073 M_CXGBE, M_ZERO | M_WAITOK); 1074 #endif 1075 1076 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE, 1077 M_ZERO | M_WAITOK); 1078 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1079 M_ZERO | M_WAITOK); 1080 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1081 M_ZERO | M_WAITOK); 1082 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1083 M_ZERO | M_WAITOK); 1084 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1085 M_ZERO | M_WAITOK); 1086 1087 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1088 M_ZERO | M_WAITOK); 1089 1090 t4_init_l2t(sc, M_WAITOK); 1091 1092 /* 1093 * Second pass over the ports. This time we know the number of rx and 1094 * tx queues that each port should get. 1095 */ 1096 rqidx = tqidx = 0; 1097 #ifdef TCP_OFFLOAD 1098 ofld_rqidx = ofld_tqidx = 0; 1099 #endif 1100 #ifdef DEV_NETMAP 1101 nm_rqidx = nm_tqidx = 0; 1102 #endif 1103 for_each_port(sc, i) { 1104 struct port_info *pi = sc->port[i]; 1105 struct vi_info *vi; 1106 1107 if (pi == NULL) 1108 continue; 1109 1110 pi->nvi = num_vis; 1111 for_each_vi(pi, j, vi) { 1112 vi->pi = pi; 1113 vi->qsize_rxq = t4_qsize_rxq; 1114 vi->qsize_txq = t4_qsize_txq; 1115 1116 vi->first_rxq = rqidx; 1117 vi->first_txq = tqidx; 1118 if (port_top_speed(pi) >= 10) { 1119 vi->tmr_idx = t4_tmr_idx_10g; 1120 vi->pktc_idx = t4_pktc_idx_10g; 1121 vi->flags |= iaq.intr_flags_10g & INTR_RXQ; 1122 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi; 1123 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi; 1124 } else { 1125 vi->tmr_idx = t4_tmr_idx_1g; 1126 vi->pktc_idx = t4_pktc_idx_1g; 1127 vi->flags |= iaq.intr_flags_1g & INTR_RXQ; 1128 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi; 1129 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi; 1130 } 1131 rqidx += vi->nrxq; 1132 tqidx += vi->ntxq; 1133 1134 if (j == 0 && vi->ntxq > 1) 1135 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0; 1136 else 1137 vi->rsrv_noflowq = 0; 1138 1139 #ifdef TCP_OFFLOAD 1140 vi->first_ofld_rxq = ofld_rqidx; 1141 vi->first_ofld_txq = ofld_tqidx; 1142 if (port_top_speed(pi) >= 10) { 1143 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ; 1144 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g : 1145 iaq.nofldrxq_vi; 1146 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g : 1147 iaq.nofldtxq_vi; 1148 } else { 1149 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ; 1150 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g : 1151 iaq.nofldrxq_vi; 1152 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g : 1153 iaq.nofldtxq_vi; 1154 } 1155 ofld_rqidx += vi->nofldrxq; 1156 ofld_tqidx += vi->nofldtxq; 1157 #endif 1158 #ifdef DEV_NETMAP 1159 if (j > 0) { 1160 vi->first_nm_rxq = nm_rqidx; 1161 vi->first_nm_txq = nm_tqidx; 1162 vi->nnmrxq = iaq.nnmrxq_vi; 1163 vi->nnmtxq = iaq.nnmtxq_vi; 1164 nm_rqidx += vi->nnmrxq; 1165 nm_tqidx += vi->nnmtxq; 1166 } 1167 #endif 1168 } 1169 } 1170 1171 rc = t4_setup_intr_handlers(sc); 1172 if (rc != 0) { 1173 device_printf(dev, 1174 "failed to setup interrupt handlers: %d\n", rc); 1175 goto done; 1176 } 1177 1178 rc = bus_generic_attach(dev); 1179 if (rc != 0) { 1180 device_printf(dev, 1181 "failed to attach all child ports: %d\n", rc); 1182 goto done; 1183 } 1184 1185 device_printf(dev, 1186 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1187 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1188 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1189 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1190 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1191 1192 t4_set_desc(sc); 1193 1194 notify_siblings(dev, 0); 1195 1196 done: 1197 if (rc != 0 && sc->cdev) { 1198 /* cdev was created and so cxgbetool works; recover that way. */ 1199 device_printf(dev, 1200 "error during attach, adapter is now in recovery mode.\n"); 1201 rc = 0; 1202 } 1203 1204 if (rc != 0) 1205 t4_detach_common(dev); 1206 else 1207 t4_sysctls(sc); 1208 1209 return (rc); 1210 } 1211 1212 static int 1213 t4_ready(device_t dev) 1214 { 1215 struct adapter *sc; 1216 1217 sc = device_get_softc(dev); 1218 if (sc->flags & FW_OK) 1219 return (0); 1220 return (ENXIO); 1221 } 1222 1223 static int 1224 t4_read_port_device(device_t dev, int port, device_t *child) 1225 { 1226 struct adapter *sc; 1227 struct port_info *pi; 1228 1229 sc = device_get_softc(dev); 1230 if (port < 0 || port >= MAX_NPORTS) 1231 return (EINVAL); 1232 pi = sc->port[port]; 1233 if (pi == NULL || pi->dev == NULL) 1234 return (ENXIO); 1235 *child = pi->dev; 1236 return (0); 1237 } 1238 1239 static int 1240 notify_siblings(device_t dev, int detaching) 1241 { 1242 device_t sibling; 1243 int error, i; 1244 1245 error = 0; 1246 for (i = 0; i < PCI_FUNCMAX; i++) { 1247 if (i == pci_get_function(dev)) 1248 continue; 1249 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1250 pci_get_slot(dev), i); 1251 if (sibling == NULL || !device_is_attached(sibling)) 1252 continue; 1253 if (detaching) 1254 error = T4_DETACH_CHILD(sibling); 1255 else 1256 (void)T4_ATTACH_CHILD(sibling); 1257 if (error) 1258 break; 1259 } 1260 return (error); 1261 } 1262 1263 /* 1264 * Idempotent 1265 */ 1266 static int 1267 t4_detach(device_t dev) 1268 { 1269 struct adapter *sc; 1270 int rc; 1271 1272 sc = device_get_softc(dev); 1273 1274 rc = notify_siblings(dev, 1); 1275 if (rc) { 1276 device_printf(dev, 1277 "failed to detach sibling devices: %d\n", rc); 1278 return (rc); 1279 } 1280 1281 return (t4_detach_common(dev)); 1282 } 1283 1284 int 1285 t4_detach_common(device_t dev) 1286 { 1287 struct adapter *sc; 1288 struct port_info *pi; 1289 int i, rc; 1290 1291 sc = device_get_softc(dev); 1292 1293 if (sc->flags & FULL_INIT_DONE) { 1294 if (!(sc->flags & IS_VF)) 1295 t4_intr_disable(sc); 1296 } 1297 1298 if (sc->cdev) { 1299 destroy_dev(sc->cdev); 1300 sc->cdev = NULL; 1301 } 1302 1303 if (device_is_attached(dev)) { 1304 rc = bus_generic_detach(dev); 1305 if (rc) { 1306 device_printf(dev, 1307 "failed to detach child devices: %d\n", rc); 1308 return (rc); 1309 } 1310 } 1311 1312 for (i = 0; i < sc->intr_count; i++) 1313 t4_free_irq(sc, &sc->irq[i]); 1314 1315 for (i = 0; i < MAX_NPORTS; i++) { 1316 pi = sc->port[i]; 1317 if (pi) { 1318 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1319 if (pi->dev) 1320 device_delete_child(dev, pi->dev); 1321 1322 mtx_destroy(&pi->pi_lock); 1323 free(pi->vi, M_CXGBE); 1324 free(pi->tc, M_CXGBE); 1325 free(pi, M_CXGBE); 1326 } 1327 } 1328 1329 if (sc->flags & FULL_INIT_DONE) 1330 adapter_full_uninit(sc); 1331 1332 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1333 t4_fw_bye(sc, sc->mbox); 1334 1335 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1336 pci_release_msi(dev); 1337 1338 if (sc->regs_res) 1339 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1340 sc->regs_res); 1341 1342 if (sc->udbs_res) 1343 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1344 sc->udbs_res); 1345 1346 if (sc->msix_res) 1347 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1348 sc->msix_res); 1349 1350 if (sc->l2t) 1351 t4_free_l2t(sc->l2t); 1352 1353 #ifdef TCP_OFFLOAD 1354 free(sc->sge.ofld_rxq, M_CXGBE); 1355 free(sc->sge.ofld_txq, M_CXGBE); 1356 #endif 1357 #ifdef DEV_NETMAP 1358 free(sc->sge.nm_rxq, M_CXGBE); 1359 free(sc->sge.nm_txq, M_CXGBE); 1360 #endif 1361 free(sc->irq, M_CXGBE); 1362 free(sc->sge.rxq, M_CXGBE); 1363 free(sc->sge.txq, M_CXGBE); 1364 free(sc->sge.ctrlq, M_CXGBE); 1365 free(sc->sge.iqmap, M_CXGBE); 1366 free(sc->sge.eqmap, M_CXGBE); 1367 free(sc->tids.ftid_tab, M_CXGBE); 1368 t4_destroy_dma_tag(sc); 1369 if (mtx_initialized(&sc->sc_lock)) { 1370 sx_xlock(&t4_list_lock); 1371 SLIST_REMOVE(&t4_list, sc, adapter, link); 1372 sx_xunlock(&t4_list_lock); 1373 mtx_destroy(&sc->sc_lock); 1374 } 1375 1376 callout_drain(&sc->sfl_callout); 1377 if (mtx_initialized(&sc->tids.ftid_lock)) 1378 mtx_destroy(&sc->tids.ftid_lock); 1379 if (mtx_initialized(&sc->sfl_lock)) 1380 mtx_destroy(&sc->sfl_lock); 1381 if (mtx_initialized(&sc->ifp_lock)) 1382 mtx_destroy(&sc->ifp_lock); 1383 if (mtx_initialized(&sc->reg_lock)) 1384 mtx_destroy(&sc->reg_lock); 1385 1386 for (i = 0; i < NUM_MEMWIN; i++) { 1387 struct memwin *mw = &sc->memwin[i]; 1388 1389 if (rw_initialized(&mw->mw_lock)) 1390 rw_destroy(&mw->mw_lock); 1391 } 1392 1393 bzero(sc, sizeof(*sc)); 1394 1395 return (0); 1396 } 1397 1398 static int 1399 cxgbe_probe(device_t dev) 1400 { 1401 char buf[128]; 1402 struct port_info *pi = device_get_softc(dev); 1403 1404 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1405 device_set_desc_copy(dev, buf); 1406 1407 return (BUS_PROBE_DEFAULT); 1408 } 1409 1410 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1411 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1412 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1413 #define T4_CAP_ENABLE (T4_CAP) 1414 1415 static int 1416 cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1417 { 1418 struct ifnet *ifp; 1419 struct sbuf *sb; 1420 1421 vi->xact_addr_filt = -1; 1422 callout_init(&vi->tick, 1); 1423 1424 /* Allocate an ifnet and set it up */ 1425 ifp = if_alloc(IFT_ETHER); 1426 if (ifp == NULL) { 1427 device_printf(dev, "Cannot allocate ifnet\n"); 1428 return (ENOMEM); 1429 } 1430 vi->ifp = ifp; 1431 ifp->if_softc = vi; 1432 1433 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1434 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1435 1436 ifp->if_init = cxgbe_init; 1437 ifp->if_ioctl = cxgbe_ioctl; 1438 ifp->if_transmit = cxgbe_transmit; 1439 ifp->if_qflush = cxgbe_qflush; 1440 ifp->if_get_counter = cxgbe_get_counter; 1441 1442 ifp->if_capabilities = T4_CAP; 1443 #ifdef TCP_OFFLOAD 1444 if (vi->nofldrxq != 0) 1445 ifp->if_capabilities |= IFCAP_TOE; 1446 #endif 1447 #ifdef DEV_NETMAP 1448 if (vi->nnmrxq != 0) 1449 ifp->if_capabilities |= IFCAP_NETMAP; 1450 #endif 1451 ifp->if_capenable = T4_CAP_ENABLE; 1452 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1453 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1454 1455 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1456 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1457 ifp->if_hw_tsomaxsegsize = 65536; 1458 1459 /* Initialize ifmedia for this VI */ 1460 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change, 1461 cxgbe_media_status); 1462 build_medialist(vi->pi, &vi->media); 1463 1464 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1465 EVENTHANDLER_PRI_ANY); 1466 1467 ether_ifattach(ifp, vi->hw_addr); 1468 #ifdef DEV_NETMAP 1469 if (ifp->if_capabilities & IFCAP_NETMAP) 1470 cxgbe_nm_attach(vi); 1471 #endif 1472 sb = sbuf_new_auto(); 1473 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1474 #ifdef TCP_OFFLOAD 1475 if (ifp->if_capabilities & IFCAP_TOE) 1476 sbuf_printf(sb, "; %d txq, %d rxq (TOE)", 1477 vi->nofldtxq, vi->nofldrxq); 1478 #endif 1479 #ifdef DEV_NETMAP 1480 if (ifp->if_capabilities & IFCAP_NETMAP) 1481 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1482 vi->nnmtxq, vi->nnmrxq); 1483 #endif 1484 sbuf_finish(sb); 1485 device_printf(dev, "%s\n", sbuf_data(sb)); 1486 sbuf_delete(sb); 1487 1488 vi_sysctls(vi); 1489 1490 return (0); 1491 } 1492 1493 static int 1494 cxgbe_attach(device_t dev) 1495 { 1496 struct port_info *pi = device_get_softc(dev); 1497 struct adapter *sc = pi->adapter; 1498 struct vi_info *vi; 1499 int i, rc; 1500 1501 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1502 1503 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1504 if (rc) 1505 return (rc); 1506 1507 for_each_vi(pi, i, vi) { 1508 if (i == 0) 1509 continue; 1510 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1511 if (vi->dev == NULL) { 1512 device_printf(dev, "failed to add VI %d\n", i); 1513 continue; 1514 } 1515 device_set_softc(vi->dev, vi); 1516 } 1517 1518 cxgbe_sysctls(pi); 1519 1520 bus_generic_attach(dev); 1521 1522 return (0); 1523 } 1524 1525 static void 1526 cxgbe_vi_detach(struct vi_info *vi) 1527 { 1528 struct ifnet *ifp = vi->ifp; 1529 1530 ether_ifdetach(ifp); 1531 1532 if (vi->vlan_c) 1533 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c); 1534 1535 /* Let detach proceed even if these fail. */ 1536 #ifdef DEV_NETMAP 1537 if (ifp->if_capabilities & IFCAP_NETMAP) 1538 cxgbe_nm_detach(vi); 1539 #endif 1540 cxgbe_uninit_synchronized(vi); 1541 callout_drain(&vi->tick); 1542 vi_full_uninit(vi); 1543 1544 ifmedia_removeall(&vi->media); 1545 if_free(vi->ifp); 1546 vi->ifp = NULL; 1547 } 1548 1549 static int 1550 cxgbe_detach(device_t dev) 1551 { 1552 struct port_info *pi = device_get_softc(dev); 1553 struct adapter *sc = pi->adapter; 1554 int rc; 1555 1556 /* Detach the extra VIs first. */ 1557 rc = bus_generic_detach(dev); 1558 if (rc) 1559 return (rc); 1560 device_delete_children(dev); 1561 1562 doom_vi(sc, &pi->vi[0]); 1563 1564 if (pi->flags & HAS_TRACEQ) { 1565 sc->traceq = -1; /* cloner should not create ifnet */ 1566 t4_tracer_port_detach(sc); 1567 } 1568 1569 cxgbe_vi_detach(&pi->vi[0]); 1570 callout_drain(&pi->tick); 1571 1572 end_synchronized_op(sc, 0); 1573 1574 return (0); 1575 } 1576 1577 static void 1578 cxgbe_init(void *arg) 1579 { 1580 struct vi_info *vi = arg; 1581 struct adapter *sc = vi->pi->adapter; 1582 1583 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1584 return; 1585 cxgbe_init_synchronized(vi); 1586 end_synchronized_op(sc, 0); 1587 } 1588 1589 static int 1590 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1591 { 1592 int rc = 0, mtu, flags, can_sleep; 1593 struct vi_info *vi = ifp->if_softc; 1594 struct adapter *sc = vi->pi->adapter; 1595 struct ifreq *ifr = (struct ifreq *)data; 1596 uint32_t mask; 1597 1598 switch (cmd) { 1599 case SIOCSIFMTU: 1600 mtu = ifr->ifr_mtu; 1601 if (mtu < ETHERMIN || mtu > MAX_MTU) 1602 return (EINVAL); 1603 1604 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1605 if (rc) 1606 return (rc); 1607 ifp->if_mtu = mtu; 1608 if (vi->flags & VI_INIT_DONE) { 1609 t4_update_fl_bufsize(ifp); 1610 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1611 rc = update_mac_settings(ifp, XGMAC_MTU); 1612 } 1613 end_synchronized_op(sc, 0); 1614 break; 1615 1616 case SIOCSIFFLAGS: 1617 can_sleep = 0; 1618 redo_sifflags: 1619 rc = begin_synchronized_op(sc, vi, 1620 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); 1621 if (rc) 1622 return (rc); 1623 1624 if (ifp->if_flags & IFF_UP) { 1625 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1626 flags = vi->if_flags; 1627 if ((ifp->if_flags ^ flags) & 1628 (IFF_PROMISC | IFF_ALLMULTI)) { 1629 if (can_sleep == 1) { 1630 end_synchronized_op(sc, 0); 1631 can_sleep = 0; 1632 goto redo_sifflags; 1633 } 1634 rc = update_mac_settings(ifp, 1635 XGMAC_PROMISC | XGMAC_ALLMULTI); 1636 } 1637 } else { 1638 if (can_sleep == 0) { 1639 end_synchronized_op(sc, LOCK_HELD); 1640 can_sleep = 1; 1641 goto redo_sifflags; 1642 } 1643 rc = cxgbe_init_synchronized(vi); 1644 } 1645 vi->if_flags = ifp->if_flags; 1646 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1647 if (can_sleep == 0) { 1648 end_synchronized_op(sc, LOCK_HELD); 1649 can_sleep = 1; 1650 goto redo_sifflags; 1651 } 1652 rc = cxgbe_uninit_synchronized(vi); 1653 } 1654 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); 1655 break; 1656 1657 case SIOCADDMULTI: 1658 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1659 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); 1660 if (rc) 1661 return (rc); 1662 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1663 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1664 end_synchronized_op(sc, LOCK_HELD); 1665 break; 1666 1667 case SIOCSIFCAP: 1668 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1669 if (rc) 1670 return (rc); 1671 1672 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1673 if (mask & IFCAP_TXCSUM) { 1674 ifp->if_capenable ^= IFCAP_TXCSUM; 1675 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1676 1677 if (IFCAP_TSO4 & ifp->if_capenable && 1678 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1679 ifp->if_capenable &= ~IFCAP_TSO4; 1680 if_printf(ifp, 1681 "tso4 disabled due to -txcsum.\n"); 1682 } 1683 } 1684 if (mask & IFCAP_TXCSUM_IPV6) { 1685 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1686 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1687 1688 if (IFCAP_TSO6 & ifp->if_capenable && 1689 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1690 ifp->if_capenable &= ~IFCAP_TSO6; 1691 if_printf(ifp, 1692 "tso6 disabled due to -txcsum6.\n"); 1693 } 1694 } 1695 if (mask & IFCAP_RXCSUM) 1696 ifp->if_capenable ^= IFCAP_RXCSUM; 1697 if (mask & IFCAP_RXCSUM_IPV6) 1698 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1699 1700 /* 1701 * Note that we leave CSUM_TSO alone (it is always set). The 1702 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1703 * sending a TSO request our way, so it's sufficient to toggle 1704 * IFCAP_TSOx only. 1705 */ 1706 if (mask & IFCAP_TSO4) { 1707 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1708 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1709 if_printf(ifp, "enable txcsum first.\n"); 1710 rc = EAGAIN; 1711 goto fail; 1712 } 1713 ifp->if_capenable ^= IFCAP_TSO4; 1714 } 1715 if (mask & IFCAP_TSO6) { 1716 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1717 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1718 if_printf(ifp, "enable txcsum6 first.\n"); 1719 rc = EAGAIN; 1720 goto fail; 1721 } 1722 ifp->if_capenable ^= IFCAP_TSO6; 1723 } 1724 if (mask & IFCAP_LRO) { 1725 #if defined(INET) || defined(INET6) 1726 int i; 1727 struct sge_rxq *rxq; 1728 1729 ifp->if_capenable ^= IFCAP_LRO; 1730 for_each_rxq(vi, i, rxq) { 1731 if (ifp->if_capenable & IFCAP_LRO) 1732 rxq->iq.flags |= IQ_LRO_ENABLED; 1733 else 1734 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1735 } 1736 #endif 1737 } 1738 #ifdef TCP_OFFLOAD 1739 if (mask & IFCAP_TOE) { 1740 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1741 1742 rc = toe_capability(vi, enable); 1743 if (rc != 0) 1744 goto fail; 1745 1746 ifp->if_capenable ^= mask; 1747 } 1748 #endif 1749 if (mask & IFCAP_VLAN_HWTAGGING) { 1750 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1751 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1752 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1753 } 1754 if (mask & IFCAP_VLAN_MTU) { 1755 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1756 1757 /* Need to find out how to disable auto-mtu-inflation */ 1758 } 1759 if (mask & IFCAP_VLAN_HWTSO) 1760 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1761 if (mask & IFCAP_VLAN_HWCSUM) 1762 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1763 1764 #ifdef VLAN_CAPABILITIES 1765 VLAN_CAPABILITIES(ifp); 1766 #endif 1767 fail: 1768 end_synchronized_op(sc, 0); 1769 break; 1770 1771 case SIOCSIFMEDIA: 1772 case SIOCGIFMEDIA: 1773 case SIOCGIFXMEDIA: 1774 ifmedia_ioctl(ifp, ifr, &vi->media, cmd); 1775 break; 1776 1777 case SIOCGI2C: { 1778 struct ifi2creq i2c; 1779 1780 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 1781 if (rc != 0) 1782 break; 1783 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1784 rc = EPERM; 1785 break; 1786 } 1787 if (i2c.len > sizeof(i2c.data)) { 1788 rc = EINVAL; 1789 break; 1790 } 1791 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1792 if (rc) 1793 return (rc); 1794 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr, 1795 i2c.offset, i2c.len, &i2c.data[0]); 1796 end_synchronized_op(sc, 0); 1797 if (rc == 0) 1798 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 1799 break; 1800 } 1801 1802 default: 1803 rc = ether_ioctl(ifp, cmd, data); 1804 } 1805 1806 return (rc); 1807 } 1808 1809 static int 1810 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1811 { 1812 struct vi_info *vi = ifp->if_softc; 1813 struct port_info *pi = vi->pi; 1814 struct adapter *sc = pi->adapter; 1815 struct sge_txq *txq; 1816 void *items[1]; 1817 int rc; 1818 1819 M_ASSERTPKTHDR(m); 1820 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1821 1822 if (__predict_false(pi->link_cfg.link_ok == 0)) { 1823 m_freem(m); 1824 return (ENETDOWN); 1825 } 1826 1827 rc = parse_pkt(sc, &m); 1828 if (__predict_false(rc != 0)) { 1829 MPASS(m == NULL); /* was freed already */ 1830 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 1831 return (rc); 1832 } 1833 1834 /* Select a txq. */ 1835 txq = &sc->sge.txq[vi->first_txq]; 1836 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 1837 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 1838 vi->rsrv_noflowq); 1839 1840 items[0] = m; 1841 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 1842 if (__predict_false(rc != 0)) 1843 m_freem(m); 1844 1845 return (rc); 1846 } 1847 1848 static void 1849 cxgbe_qflush(struct ifnet *ifp) 1850 { 1851 struct vi_info *vi = ifp->if_softc; 1852 struct sge_txq *txq; 1853 int i; 1854 1855 /* queues do not exist if !VI_INIT_DONE. */ 1856 if (vi->flags & VI_INIT_DONE) { 1857 for_each_txq(vi, i, txq) { 1858 TXQ_LOCK(txq); 1859 txq->eq.flags &= ~EQ_ENABLED; 1860 TXQ_UNLOCK(txq); 1861 while (!mp_ring_is_idle(txq->r)) { 1862 mp_ring_check_drainage(txq->r, 0); 1863 pause("qflush", 1); 1864 } 1865 } 1866 } 1867 if_qflush(ifp); 1868 } 1869 1870 static uint64_t 1871 vi_get_counter(struct ifnet *ifp, ift_counter c) 1872 { 1873 struct vi_info *vi = ifp->if_softc; 1874 struct fw_vi_stats_vf *s = &vi->stats; 1875 1876 vi_refresh_stats(vi->pi->adapter, vi); 1877 1878 switch (c) { 1879 case IFCOUNTER_IPACKETS: 1880 return (s->rx_bcast_frames + s->rx_mcast_frames + 1881 s->rx_ucast_frames); 1882 case IFCOUNTER_IERRORS: 1883 return (s->rx_err_frames); 1884 case IFCOUNTER_OPACKETS: 1885 return (s->tx_bcast_frames + s->tx_mcast_frames + 1886 s->tx_ucast_frames + s->tx_offload_frames); 1887 case IFCOUNTER_OERRORS: 1888 return (s->tx_drop_frames); 1889 case IFCOUNTER_IBYTES: 1890 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 1891 s->rx_ucast_bytes); 1892 case IFCOUNTER_OBYTES: 1893 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 1894 s->tx_ucast_bytes + s->tx_offload_bytes); 1895 case IFCOUNTER_IMCASTS: 1896 return (s->rx_mcast_frames); 1897 case IFCOUNTER_OMCASTS: 1898 return (s->tx_mcast_frames); 1899 case IFCOUNTER_OQDROPS: { 1900 uint64_t drops; 1901 1902 drops = 0; 1903 if (vi->flags & VI_INIT_DONE) { 1904 int i; 1905 struct sge_txq *txq; 1906 1907 for_each_txq(vi, i, txq) 1908 drops += counter_u64_fetch(txq->r->drops); 1909 } 1910 1911 return (drops); 1912 1913 } 1914 1915 default: 1916 return (if_get_counter_default(ifp, c)); 1917 } 1918 } 1919 1920 uint64_t 1921 cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 1922 { 1923 struct vi_info *vi = ifp->if_softc; 1924 struct port_info *pi = vi->pi; 1925 struct adapter *sc = pi->adapter; 1926 struct port_stats *s = &pi->stats; 1927 1928 if (pi->nvi > 1 || sc->flags & IS_VF) 1929 return (vi_get_counter(ifp, c)); 1930 1931 cxgbe_refresh_stats(sc, pi); 1932 1933 switch (c) { 1934 case IFCOUNTER_IPACKETS: 1935 return (s->rx_frames); 1936 1937 case IFCOUNTER_IERRORS: 1938 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 1939 s->rx_fcs_err + s->rx_len_err); 1940 1941 case IFCOUNTER_OPACKETS: 1942 return (s->tx_frames); 1943 1944 case IFCOUNTER_OERRORS: 1945 return (s->tx_error_frames); 1946 1947 case IFCOUNTER_IBYTES: 1948 return (s->rx_octets); 1949 1950 case IFCOUNTER_OBYTES: 1951 return (s->tx_octets); 1952 1953 case IFCOUNTER_IMCASTS: 1954 return (s->rx_mcast_frames); 1955 1956 case IFCOUNTER_OMCASTS: 1957 return (s->tx_mcast_frames); 1958 1959 case IFCOUNTER_IQDROPS: 1960 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 1961 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 1962 s->rx_trunc3 + pi->tnl_cong_drops); 1963 1964 case IFCOUNTER_OQDROPS: { 1965 uint64_t drops; 1966 1967 drops = s->tx_drop; 1968 if (vi->flags & VI_INIT_DONE) { 1969 int i; 1970 struct sge_txq *txq; 1971 1972 for_each_txq(vi, i, txq) 1973 drops += counter_u64_fetch(txq->r->drops); 1974 } 1975 1976 return (drops); 1977 1978 } 1979 1980 default: 1981 return (if_get_counter_default(ifp, c)); 1982 } 1983 } 1984 1985 static int 1986 cxgbe_media_change(struct ifnet *ifp) 1987 { 1988 struct vi_info *vi = ifp->if_softc; 1989 1990 device_printf(vi->dev, "%s unimplemented.\n", __func__); 1991 1992 return (EOPNOTSUPP); 1993 } 1994 1995 static void 1996 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1997 { 1998 struct vi_info *vi = ifp->if_softc; 1999 struct port_info *pi = vi->pi; 2000 struct ifmedia_entry *cur; 2001 int speed = pi->link_cfg.speed; 2002 2003 cur = vi->media.ifm_cur; 2004 2005 ifmr->ifm_status = IFM_AVALID; 2006 if (!pi->link_cfg.link_ok) 2007 return; 2008 2009 ifmr->ifm_status |= IFM_ACTIVE; 2010 2011 /* active and current will differ iff current media is autoselect. */ 2012 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 2013 return; 2014 2015 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2016 if (speed == 10000) 2017 ifmr->ifm_active |= IFM_10G_T; 2018 else if (speed == 1000) 2019 ifmr->ifm_active |= IFM_1000_T; 2020 else if (speed == 100) 2021 ifmr->ifm_active |= IFM_100_TX; 2022 else if (speed == 10) 2023 ifmr->ifm_active |= IFM_10_T; 2024 else 2025 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, 2026 speed)); 2027 } 2028 2029 static int 2030 vcxgbe_probe(device_t dev) 2031 { 2032 char buf[128]; 2033 struct vi_info *vi = device_get_softc(dev); 2034 2035 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2036 vi - vi->pi->vi); 2037 device_set_desc_copy(dev, buf); 2038 2039 return (BUS_PROBE_DEFAULT); 2040 } 2041 2042 static int 2043 vcxgbe_attach(device_t dev) 2044 { 2045 struct vi_info *vi; 2046 struct port_info *pi; 2047 struct adapter *sc; 2048 int func, index, rc; 2049 u32 param, val; 2050 2051 vi = device_get_softc(dev); 2052 pi = vi->pi; 2053 sc = pi->adapter; 2054 2055 index = vi - pi->vi; 2056 KASSERT(index < nitems(vi_mac_funcs), 2057 ("%s: VI %s doesn't have a MAC func", __func__, 2058 device_get_nameunit(dev))); 2059 func = vi_mac_funcs[index]; 2060 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2061 vi->hw_addr, &vi->rss_size, func, 0); 2062 if (rc < 0) { 2063 device_printf(dev, "Failed to allocate virtual interface " 2064 "for port %d: %d\n", pi->port_id, -rc); 2065 return (-rc); 2066 } 2067 vi->viid = rc; 2068 if (chip_id(sc) <= CHELSIO_T5) 2069 vi->smt_idx = (rc & 0x7f) << 1; 2070 else 2071 vi->smt_idx = (rc & 0x7f); 2072 2073 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2074 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2075 V_FW_PARAMS_PARAM_YZ(vi->viid); 2076 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2077 if (rc) 2078 vi->rss_base = 0xffff; 2079 else { 2080 /* MPASS((val >> 16) == rss_size); */ 2081 vi->rss_base = val & 0xffff; 2082 } 2083 2084 rc = cxgbe_vi_attach(dev, vi); 2085 if (rc) { 2086 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2087 return (rc); 2088 } 2089 return (0); 2090 } 2091 2092 static int 2093 vcxgbe_detach(device_t dev) 2094 { 2095 struct vi_info *vi; 2096 struct adapter *sc; 2097 2098 vi = device_get_softc(dev); 2099 sc = vi->pi->adapter; 2100 2101 doom_vi(sc, vi); 2102 2103 cxgbe_vi_detach(vi); 2104 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2105 2106 end_synchronized_op(sc, 0); 2107 2108 return (0); 2109 } 2110 2111 void 2112 t4_fatal_err(struct adapter *sc) 2113 { 2114 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2115 t4_intr_disable(sc); 2116 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 2117 device_get_nameunit(sc->dev)); 2118 } 2119 2120 void 2121 t4_add_adapter(struct adapter *sc) 2122 { 2123 sx_xlock(&t4_list_lock); 2124 SLIST_INSERT_HEAD(&t4_list, sc, link); 2125 sx_xunlock(&t4_list_lock); 2126 } 2127 2128 int 2129 t4_map_bars_0_and_4(struct adapter *sc) 2130 { 2131 sc->regs_rid = PCIR_BAR(0); 2132 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2133 &sc->regs_rid, RF_ACTIVE); 2134 if (sc->regs_res == NULL) { 2135 device_printf(sc->dev, "cannot map registers.\n"); 2136 return (ENXIO); 2137 } 2138 sc->bt = rman_get_bustag(sc->regs_res); 2139 sc->bh = rman_get_bushandle(sc->regs_res); 2140 sc->mmio_len = rman_get_size(sc->regs_res); 2141 setbit(&sc->doorbells, DOORBELL_KDB); 2142 2143 sc->msix_rid = PCIR_BAR(4); 2144 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2145 &sc->msix_rid, RF_ACTIVE); 2146 if (sc->msix_res == NULL) { 2147 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2148 return (ENXIO); 2149 } 2150 2151 return (0); 2152 } 2153 2154 int 2155 t4_map_bar_2(struct adapter *sc) 2156 { 2157 2158 /* 2159 * T4: only iWARP driver uses the userspace doorbells. There is no need 2160 * to map it if RDMA is disabled. 2161 */ 2162 if (is_t4(sc) && sc->rdmacaps == 0) 2163 return (0); 2164 2165 sc->udbs_rid = PCIR_BAR(2); 2166 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2167 &sc->udbs_rid, RF_ACTIVE); 2168 if (sc->udbs_res == NULL) { 2169 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2170 return (ENXIO); 2171 } 2172 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2173 2174 if (chip_id(sc) >= CHELSIO_T5) { 2175 setbit(&sc->doorbells, DOORBELL_UDB); 2176 #if defined(__i386__) || defined(__amd64__) 2177 if (t5_write_combine) { 2178 int rc, mode; 2179 2180 /* 2181 * Enable write combining on BAR2. This is the 2182 * userspace doorbell BAR and is split into 128B 2183 * (UDBS_SEG_SIZE) doorbell regions, each associated 2184 * with an egress queue. The first 64B has the doorbell 2185 * and the second 64B can be used to submit a tx work 2186 * request with an implicit doorbell. 2187 */ 2188 2189 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2190 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2191 if (rc == 0) { 2192 clrbit(&sc->doorbells, DOORBELL_UDB); 2193 setbit(&sc->doorbells, DOORBELL_WCWR); 2194 setbit(&sc->doorbells, DOORBELL_UDBWC); 2195 } else { 2196 device_printf(sc->dev, 2197 "couldn't enable write combining: %d\n", 2198 rc); 2199 } 2200 2201 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2202 t4_write_reg(sc, A_SGE_STAT_CFG, 2203 V_STATSOURCE_T5(7) | mode); 2204 } 2205 #endif 2206 } 2207 2208 return (0); 2209 } 2210 2211 struct memwin_init { 2212 uint32_t base; 2213 uint32_t aperture; 2214 }; 2215 2216 static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2217 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2218 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2219 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2220 }; 2221 2222 static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2223 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2224 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2225 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2226 }; 2227 2228 static void 2229 setup_memwin(struct adapter *sc) 2230 { 2231 const struct memwin_init *mw_init; 2232 struct memwin *mw; 2233 int i; 2234 uint32_t bar0; 2235 2236 if (is_t4(sc)) { 2237 /* 2238 * Read low 32b of bar0 indirectly via the hardware backdoor 2239 * mechanism. Works from within PCI passthrough environments 2240 * too, where rman_get_start() can return a different value. We 2241 * need to program the T4 memory window decoders with the actual 2242 * addresses that will be coming across the PCIe link. 2243 */ 2244 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2245 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2246 2247 mw_init = &t4_memwin[0]; 2248 } else { 2249 /* T5+ use the relative offset inside the PCIe BAR */ 2250 bar0 = 0; 2251 2252 mw_init = &t5_memwin[0]; 2253 } 2254 2255 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2256 rw_init(&mw->mw_lock, "memory window access"); 2257 mw->mw_base = mw_init->base; 2258 mw->mw_aperture = mw_init->aperture; 2259 mw->mw_curpos = 0; 2260 t4_write_reg(sc, 2261 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2262 (mw->mw_base + bar0) | V_BIR(0) | 2263 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2264 rw_wlock(&mw->mw_lock); 2265 position_memwin(sc, i, 0); 2266 rw_wunlock(&mw->mw_lock); 2267 } 2268 2269 /* flush */ 2270 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2271 } 2272 2273 /* 2274 * Positions the memory window at the given address in the card's address space. 2275 * There are some alignment requirements and the actual position may be at an 2276 * address prior to the requested address. mw->mw_curpos always has the actual 2277 * position of the window. 2278 */ 2279 static void 2280 position_memwin(struct adapter *sc, int idx, uint32_t addr) 2281 { 2282 struct memwin *mw; 2283 uint32_t pf; 2284 uint32_t reg; 2285 2286 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2287 mw = &sc->memwin[idx]; 2288 rw_assert(&mw->mw_lock, RA_WLOCKED); 2289 2290 if (is_t4(sc)) { 2291 pf = 0; 2292 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2293 } else { 2294 pf = V_PFNUM(sc->pf); 2295 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2296 } 2297 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2298 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2299 t4_read_reg(sc, reg); /* flush */ 2300 } 2301 2302 static int 2303 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2304 int len, int rw) 2305 { 2306 struct memwin *mw; 2307 uint32_t mw_end, v; 2308 2309 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2310 2311 /* Memory can only be accessed in naturally aligned 4 byte units */ 2312 if (addr & 3 || len & 3 || len <= 0) 2313 return (EINVAL); 2314 2315 mw = &sc->memwin[idx]; 2316 while (len > 0) { 2317 rw_rlock(&mw->mw_lock); 2318 mw_end = mw->mw_curpos + mw->mw_aperture; 2319 if (addr >= mw_end || addr < mw->mw_curpos) { 2320 /* Will need to reposition the window */ 2321 if (!rw_try_upgrade(&mw->mw_lock)) { 2322 rw_runlock(&mw->mw_lock); 2323 rw_wlock(&mw->mw_lock); 2324 } 2325 rw_assert(&mw->mw_lock, RA_WLOCKED); 2326 position_memwin(sc, idx, addr); 2327 rw_downgrade(&mw->mw_lock); 2328 mw_end = mw->mw_curpos + mw->mw_aperture; 2329 } 2330 rw_assert(&mw->mw_lock, RA_RLOCKED); 2331 while (addr < mw_end && len > 0) { 2332 if (rw == 0) { 2333 v = t4_read_reg(sc, mw->mw_base + addr - 2334 mw->mw_curpos); 2335 *val++ = le32toh(v); 2336 } else { 2337 v = *val++; 2338 t4_write_reg(sc, mw->mw_base + addr - 2339 mw->mw_curpos, htole32(v)); 2340 } 2341 addr += 4; 2342 len -= 4; 2343 } 2344 rw_runlock(&mw->mw_lock); 2345 } 2346 2347 return (0); 2348 } 2349 2350 static inline int 2351 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2352 int len) 2353 { 2354 2355 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 2356 } 2357 2358 static inline int 2359 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 2360 const uint32_t *val, int len) 2361 { 2362 2363 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 2364 } 2365 2366 static int 2367 t4_range_cmp(const void *a, const void *b) 2368 { 2369 return ((const struct t4_range *)a)->start - 2370 ((const struct t4_range *)b)->start; 2371 } 2372 2373 /* 2374 * Verify that the memory range specified by the addr/len pair is valid within 2375 * the card's address space. 2376 */ 2377 static int 2378 validate_mem_range(struct adapter *sc, uint32_t addr, int len) 2379 { 2380 struct t4_range mem_ranges[4], *r, *next; 2381 uint32_t em, addr_len; 2382 int i, n, remaining; 2383 2384 /* Memory can only be accessed in naturally aligned 4 byte units */ 2385 if (addr & 3 || len & 3 || len <= 0) 2386 return (EINVAL); 2387 2388 /* Enabled memories */ 2389 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2390 2391 r = &mem_ranges[0]; 2392 n = 0; 2393 bzero(r, sizeof(mem_ranges)); 2394 if (em & F_EDRAM0_ENABLE) { 2395 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2396 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2397 if (r->size > 0) { 2398 r->start = G_EDRAM0_BASE(addr_len) << 20; 2399 if (addr >= r->start && 2400 addr + len <= r->start + r->size) 2401 return (0); 2402 r++; 2403 n++; 2404 } 2405 } 2406 if (em & F_EDRAM1_ENABLE) { 2407 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2408 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2409 if (r->size > 0) { 2410 r->start = G_EDRAM1_BASE(addr_len) << 20; 2411 if (addr >= r->start && 2412 addr + len <= r->start + r->size) 2413 return (0); 2414 r++; 2415 n++; 2416 } 2417 } 2418 if (em & F_EXT_MEM_ENABLE) { 2419 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2420 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2421 if (r->size > 0) { 2422 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2423 if (addr >= r->start && 2424 addr + len <= r->start + r->size) 2425 return (0); 2426 r++; 2427 n++; 2428 } 2429 } 2430 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2431 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2432 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2433 if (r->size > 0) { 2434 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2435 if (addr >= r->start && 2436 addr + len <= r->start + r->size) 2437 return (0); 2438 r++; 2439 n++; 2440 } 2441 } 2442 MPASS(n <= nitems(mem_ranges)); 2443 2444 if (n > 1) { 2445 /* Sort and merge the ranges. */ 2446 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2447 2448 /* Start from index 0 and examine the next n - 1 entries. */ 2449 r = &mem_ranges[0]; 2450 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2451 2452 MPASS(r->size > 0); /* r is a valid entry. */ 2453 next = r + 1; 2454 MPASS(next->size > 0); /* and so is the next one. */ 2455 2456 while (r->start + r->size >= next->start) { 2457 /* Merge the next one into the current entry. */ 2458 r->size = max(r->start + r->size, 2459 next->start + next->size) - r->start; 2460 n--; /* One fewer entry in total. */ 2461 if (--remaining == 0) 2462 goto done; /* short circuit */ 2463 next++; 2464 } 2465 if (next != r + 1) { 2466 /* 2467 * Some entries were merged into r and next 2468 * points to the first valid entry that couldn't 2469 * be merged. 2470 */ 2471 MPASS(next->size > 0); /* must be valid */ 2472 memcpy(r + 1, next, remaining * sizeof(*r)); 2473 #ifdef INVARIANTS 2474 /* 2475 * This so that the foo->size assertion in the 2476 * next iteration of the loop do the right 2477 * thing for entries that were pulled up and are 2478 * no longer valid. 2479 */ 2480 MPASS(n < nitems(mem_ranges)); 2481 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2482 sizeof(struct t4_range)); 2483 #endif 2484 } 2485 } 2486 done: 2487 /* Done merging the ranges. */ 2488 MPASS(n > 0); 2489 r = &mem_ranges[0]; 2490 for (i = 0; i < n; i++, r++) { 2491 if (addr >= r->start && 2492 addr + len <= r->start + r->size) 2493 return (0); 2494 } 2495 } 2496 2497 return (EFAULT); 2498 } 2499 2500 static int 2501 fwmtype_to_hwmtype(int mtype) 2502 { 2503 2504 switch (mtype) { 2505 case FW_MEMTYPE_EDC0: 2506 return (MEM_EDC0); 2507 case FW_MEMTYPE_EDC1: 2508 return (MEM_EDC1); 2509 case FW_MEMTYPE_EXTMEM: 2510 return (MEM_MC0); 2511 case FW_MEMTYPE_EXTMEM1: 2512 return (MEM_MC1); 2513 default: 2514 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2515 } 2516 } 2517 2518 /* 2519 * Verify that the memory range specified by the memtype/offset/len pair is 2520 * valid and lies entirely within the memtype specified. The global address of 2521 * the start of the range is returned in addr. 2522 */ 2523 static int 2524 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 2525 uint32_t *addr) 2526 { 2527 uint32_t em, addr_len, maddr; 2528 2529 /* Memory can only be accessed in naturally aligned 4 byte units */ 2530 if (off & 3 || len & 3 || len == 0) 2531 return (EINVAL); 2532 2533 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2534 switch (fwmtype_to_hwmtype(mtype)) { 2535 case MEM_EDC0: 2536 if (!(em & F_EDRAM0_ENABLE)) 2537 return (EINVAL); 2538 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2539 maddr = G_EDRAM0_BASE(addr_len) << 20; 2540 break; 2541 case MEM_EDC1: 2542 if (!(em & F_EDRAM1_ENABLE)) 2543 return (EINVAL); 2544 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2545 maddr = G_EDRAM1_BASE(addr_len) << 20; 2546 break; 2547 case MEM_MC: 2548 if (!(em & F_EXT_MEM_ENABLE)) 2549 return (EINVAL); 2550 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2551 maddr = G_EXT_MEM_BASE(addr_len) << 20; 2552 break; 2553 case MEM_MC1: 2554 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 2555 return (EINVAL); 2556 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2557 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 2558 break; 2559 default: 2560 return (EINVAL); 2561 } 2562 2563 *addr = maddr + off; /* global address */ 2564 return (validate_mem_range(sc, *addr, len)); 2565 } 2566 2567 static int 2568 fixup_devlog_params(struct adapter *sc) 2569 { 2570 struct devlog_params *dparams = &sc->params.devlog; 2571 int rc; 2572 2573 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 2574 dparams->size, &dparams->addr); 2575 2576 return (rc); 2577 } 2578 2579 static int 2580 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis, 2581 struct intrs_and_queues *iaq) 2582 { 2583 int rc, itype, navail, nrxq10g, nrxq1g, n; 2584 int nofldrxq10g = 0, nofldrxq1g = 0; 2585 2586 bzero(iaq, sizeof(*iaq)); 2587 2588 iaq->ntxq10g = t4_ntxq10g; 2589 iaq->ntxq1g = t4_ntxq1g; 2590 iaq->ntxq_vi = t4_ntxq_vi; 2591 iaq->nrxq10g = nrxq10g = t4_nrxq10g; 2592 iaq->nrxq1g = nrxq1g = t4_nrxq1g; 2593 iaq->nrxq_vi = t4_nrxq_vi; 2594 iaq->rsrv_noflowq = t4_rsrv_noflowq; 2595 #ifdef TCP_OFFLOAD 2596 if (is_offload(sc)) { 2597 iaq->nofldtxq10g = t4_nofldtxq10g; 2598 iaq->nofldtxq1g = t4_nofldtxq1g; 2599 iaq->nofldtxq_vi = t4_nofldtxq_vi; 2600 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g; 2601 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g; 2602 iaq->nofldrxq_vi = t4_nofldrxq_vi; 2603 } 2604 #endif 2605 #ifdef DEV_NETMAP 2606 iaq->nnmtxq_vi = t4_nnmtxq_vi; 2607 iaq->nnmrxq_vi = t4_nnmrxq_vi; 2608 #endif 2609 2610 for (itype = INTR_MSIX; itype; itype >>= 1) { 2611 2612 if ((itype & t4_intr_types) == 0) 2613 continue; /* not allowed */ 2614 2615 if (itype == INTR_MSIX) 2616 navail = pci_msix_count(sc->dev); 2617 else if (itype == INTR_MSI) 2618 navail = pci_msi_count(sc->dev); 2619 else 2620 navail = 1; 2621 restart: 2622 if (navail == 0) 2623 continue; 2624 2625 iaq->intr_type = itype; 2626 iaq->intr_flags_10g = 0; 2627 iaq->intr_flags_1g = 0; 2628 2629 /* 2630 * Best option: an interrupt vector for errors, one for the 2631 * firmware event queue, and one for every rxq (NIC and TOE) of 2632 * every VI. The VIs that support netmap use the same 2633 * interrupts for the NIC rx queues and the netmap rx queues 2634 * because only one set of queues is active at a time. 2635 */ 2636 iaq->nirq = T4_EXTRA_INTR; 2637 iaq->nirq += n10g * (nrxq10g + nofldrxq10g); 2638 iaq->nirq += n1g * (nrxq1g + nofldrxq1g); 2639 iaq->nirq += (n10g + n1g) * (num_vis - 1) * 2640 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */ 2641 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi; 2642 if (iaq->nirq <= navail && 2643 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2644 iaq->intr_flags_10g = INTR_ALL; 2645 iaq->intr_flags_1g = INTR_ALL; 2646 goto allocate; 2647 } 2648 2649 /* Disable the VIs (and netmap) if there aren't enough intrs */ 2650 if (num_vis > 1) { 2651 device_printf(sc->dev, "virtual interfaces disabled " 2652 "because num_vis=%u with current settings " 2653 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, " 2654 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, " 2655 "nnmrxq_vi=%u) would need %u interrupts but " 2656 "only %u are available.\n", num_vis, nrxq10g, 2657 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi, 2658 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq, 2659 navail); 2660 num_vis = 1; 2661 iaq->ntxq_vi = iaq->nrxq_vi = 0; 2662 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 2663 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 2664 goto restart; 2665 } 2666 2667 /* 2668 * Second best option: a vector for errors, one for the firmware 2669 * event queue, and vectors for either all the NIC rx queues or 2670 * all the TOE rx queues. The queues that don't get vectors 2671 * will forward their interrupts to those that do. 2672 */ 2673 iaq->nirq = T4_EXTRA_INTR; 2674 if (nrxq10g >= nofldrxq10g) { 2675 iaq->intr_flags_10g = INTR_RXQ; 2676 iaq->nirq += n10g * nrxq10g; 2677 } else { 2678 iaq->intr_flags_10g = INTR_OFLD_RXQ; 2679 iaq->nirq += n10g * nofldrxq10g; 2680 } 2681 if (nrxq1g >= nofldrxq1g) { 2682 iaq->intr_flags_1g = INTR_RXQ; 2683 iaq->nirq += n1g * nrxq1g; 2684 } else { 2685 iaq->intr_flags_1g = INTR_OFLD_RXQ; 2686 iaq->nirq += n1g * nofldrxq1g; 2687 } 2688 if (iaq->nirq <= navail && 2689 (itype != INTR_MSI || powerof2(iaq->nirq))) 2690 goto allocate; 2691 2692 /* 2693 * Next best option: an interrupt vector for errors, one for the 2694 * firmware event queue, and at least one per main-VI. At this 2695 * point we know we'll have to downsize nrxq and/or nofldrxq to 2696 * fit what's available to us. 2697 */ 2698 iaq->nirq = T4_EXTRA_INTR; 2699 iaq->nirq += n10g + n1g; 2700 if (iaq->nirq <= navail) { 2701 int leftover = navail - iaq->nirq; 2702 2703 if (n10g > 0) { 2704 int target = max(nrxq10g, nofldrxq10g); 2705 2706 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ? 2707 INTR_RXQ : INTR_OFLD_RXQ; 2708 2709 n = 1; 2710 while (n < target && leftover >= n10g) { 2711 leftover -= n10g; 2712 iaq->nirq += n10g; 2713 n++; 2714 } 2715 iaq->nrxq10g = min(n, nrxq10g); 2716 #ifdef TCP_OFFLOAD 2717 iaq->nofldrxq10g = min(n, nofldrxq10g); 2718 #endif 2719 } 2720 2721 if (n1g > 0) { 2722 int target = max(nrxq1g, nofldrxq1g); 2723 2724 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ? 2725 INTR_RXQ : INTR_OFLD_RXQ; 2726 2727 n = 1; 2728 while (n < target && leftover >= n1g) { 2729 leftover -= n1g; 2730 iaq->nirq += n1g; 2731 n++; 2732 } 2733 iaq->nrxq1g = min(n, nrxq1g); 2734 #ifdef TCP_OFFLOAD 2735 iaq->nofldrxq1g = min(n, nofldrxq1g); 2736 #endif 2737 } 2738 2739 if (itype != INTR_MSI || powerof2(iaq->nirq)) 2740 goto allocate; 2741 } 2742 2743 /* 2744 * Least desirable option: one interrupt vector for everything. 2745 */ 2746 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1; 2747 iaq->intr_flags_10g = iaq->intr_flags_1g = 0; 2748 #ifdef TCP_OFFLOAD 2749 if (is_offload(sc)) 2750 iaq->nofldrxq10g = iaq->nofldrxq1g = 1; 2751 #endif 2752 allocate: 2753 navail = iaq->nirq; 2754 rc = 0; 2755 if (itype == INTR_MSIX) 2756 rc = pci_alloc_msix(sc->dev, &navail); 2757 else if (itype == INTR_MSI) 2758 rc = pci_alloc_msi(sc->dev, &navail); 2759 2760 if (rc == 0) { 2761 if (navail == iaq->nirq) 2762 return (0); 2763 2764 /* 2765 * Didn't get the number requested. Use whatever number 2766 * the kernel is willing to allocate (it's in navail). 2767 */ 2768 device_printf(sc->dev, "fewer vectors than requested, " 2769 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 2770 itype, iaq->nirq, navail); 2771 pci_release_msi(sc->dev); 2772 goto restart; 2773 } 2774 2775 device_printf(sc->dev, 2776 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 2777 itype, rc, iaq->nirq, navail); 2778 } 2779 2780 device_printf(sc->dev, 2781 "failed to find a usable interrupt type. " 2782 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 2783 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 2784 2785 return (ENXIO); 2786 } 2787 2788 #define FW_VERSION(chip) ( \ 2789 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 2790 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 2791 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 2792 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 2793 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 2794 2795 struct fw_info { 2796 uint8_t chip; 2797 char *kld_name; 2798 char *fw_mod_name; 2799 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 2800 } fw_info[] = { 2801 { 2802 .chip = CHELSIO_T4, 2803 .kld_name = "t4fw_cfg", 2804 .fw_mod_name = "t4fw", 2805 .fw_hdr = { 2806 .chip = FW_HDR_CHIP_T4, 2807 .fw_ver = htobe32_const(FW_VERSION(T4)), 2808 .intfver_nic = FW_INTFVER(T4, NIC), 2809 .intfver_vnic = FW_INTFVER(T4, VNIC), 2810 .intfver_ofld = FW_INTFVER(T4, OFLD), 2811 .intfver_ri = FW_INTFVER(T4, RI), 2812 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 2813 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 2814 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 2815 .intfver_fcoe = FW_INTFVER(T4, FCOE), 2816 }, 2817 }, { 2818 .chip = CHELSIO_T5, 2819 .kld_name = "t5fw_cfg", 2820 .fw_mod_name = "t5fw", 2821 .fw_hdr = { 2822 .chip = FW_HDR_CHIP_T5, 2823 .fw_ver = htobe32_const(FW_VERSION(T5)), 2824 .intfver_nic = FW_INTFVER(T5, NIC), 2825 .intfver_vnic = FW_INTFVER(T5, VNIC), 2826 .intfver_ofld = FW_INTFVER(T5, OFLD), 2827 .intfver_ri = FW_INTFVER(T5, RI), 2828 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 2829 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 2830 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 2831 .intfver_fcoe = FW_INTFVER(T5, FCOE), 2832 }, 2833 }, { 2834 .chip = CHELSIO_T6, 2835 .kld_name = "t6fw_cfg", 2836 .fw_mod_name = "t6fw", 2837 .fw_hdr = { 2838 .chip = FW_HDR_CHIP_T6, 2839 .fw_ver = htobe32_const(FW_VERSION(T6)), 2840 .intfver_nic = FW_INTFVER(T6, NIC), 2841 .intfver_vnic = FW_INTFVER(T6, VNIC), 2842 .intfver_ofld = FW_INTFVER(T6, OFLD), 2843 .intfver_ri = FW_INTFVER(T6, RI), 2844 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 2845 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 2846 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 2847 .intfver_fcoe = FW_INTFVER(T6, FCOE), 2848 }, 2849 } 2850 }; 2851 2852 static struct fw_info * 2853 find_fw_info(int chip) 2854 { 2855 int i; 2856 2857 for (i = 0; i < nitems(fw_info); i++) { 2858 if (fw_info[i].chip == chip) 2859 return (&fw_info[i]); 2860 } 2861 return (NULL); 2862 } 2863 2864 /* 2865 * Is the given firmware API compatible with the one the driver was compiled 2866 * with? 2867 */ 2868 static int 2869 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 2870 { 2871 2872 /* short circuit if it's the exact same firmware version */ 2873 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 2874 return (1); 2875 2876 /* 2877 * XXX: Is this too conservative? Perhaps I should limit this to the 2878 * features that are supported in the driver. 2879 */ 2880 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 2881 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 2882 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 2883 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 2884 return (1); 2885 #undef SAME_INTF 2886 2887 return (0); 2888 } 2889 2890 /* 2891 * The firmware in the KLD is usable, but should it be installed? This routine 2892 * explains itself in detail if it indicates the KLD firmware should be 2893 * installed. 2894 */ 2895 static int 2896 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 2897 { 2898 const char *reason; 2899 2900 if (!card_fw_usable) { 2901 reason = "incompatible or unusable"; 2902 goto install; 2903 } 2904 2905 if (k > c) { 2906 reason = "older than the version bundled with this driver"; 2907 goto install; 2908 } 2909 2910 if (t4_fw_install == 2 && k != c) { 2911 reason = "different than the version bundled with this driver"; 2912 goto install; 2913 } 2914 2915 return (0); 2916 2917 install: 2918 if (t4_fw_install == 0) { 2919 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2920 "but the driver is prohibited from installing a different " 2921 "firmware on the card.\n", 2922 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2923 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 2924 2925 return (0); 2926 } 2927 2928 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2929 "installing firmware %u.%u.%u.%u on card.\n", 2930 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2931 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 2932 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 2933 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 2934 2935 return (1); 2936 } 2937 /* 2938 * Establish contact with the firmware and determine if we are the master driver 2939 * or not, and whether we are responsible for chip initialization. 2940 */ 2941 static int 2942 prep_firmware(struct adapter *sc) 2943 { 2944 const struct firmware *fw = NULL, *default_cfg; 2945 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 2946 enum dev_state state; 2947 struct fw_info *fw_info; 2948 struct fw_hdr *card_fw; /* fw on the card */ 2949 const struct fw_hdr *kld_fw; /* fw in the KLD */ 2950 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 2951 against */ 2952 2953 /* Contact firmware. */ 2954 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 2955 if (rc < 0 || state == DEV_STATE_ERR) { 2956 rc = -rc; 2957 device_printf(sc->dev, 2958 "failed to connect to the firmware: %d, %d.\n", rc, state); 2959 return (rc); 2960 } 2961 pf = rc; 2962 if (pf == sc->mbox) 2963 sc->flags |= MASTER_PF; 2964 else if (state == DEV_STATE_UNINIT) { 2965 /* 2966 * We didn't get to be the master so we definitely won't be 2967 * configuring the chip. It's a bug if someone else hasn't 2968 * configured it already. 2969 */ 2970 device_printf(sc->dev, "couldn't be master(%d), " 2971 "device not already initialized either(%d).\n", rc, state); 2972 return (EDOOFUS); 2973 } 2974 2975 /* This is the firmware whose headers the driver was compiled against */ 2976 fw_info = find_fw_info(chip_id(sc)); 2977 if (fw_info == NULL) { 2978 device_printf(sc->dev, 2979 "unable to look up firmware information for chip %d.\n", 2980 chip_id(sc)); 2981 return (EINVAL); 2982 } 2983 drv_fw = &fw_info->fw_hdr; 2984 2985 /* 2986 * The firmware KLD contains many modules. The KLD name is also the 2987 * name of the module that contains the default config file. 2988 */ 2989 default_cfg = firmware_get(fw_info->kld_name); 2990 2991 /* Read the header of the firmware on the card */ 2992 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 2993 rc = -t4_read_flash(sc, FLASH_FW_START, 2994 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 2995 if (rc == 0) 2996 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 2997 else { 2998 device_printf(sc->dev, 2999 "Unable to read card's firmware header: %d\n", rc); 3000 card_fw_usable = 0; 3001 } 3002 3003 /* This is the firmware in the KLD */ 3004 fw = firmware_get(fw_info->fw_mod_name); 3005 if (fw != NULL) { 3006 kld_fw = (const void *)fw->data; 3007 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 3008 } else { 3009 kld_fw = NULL; 3010 kld_fw_usable = 0; 3011 } 3012 3013 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 3014 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 3015 /* 3016 * Common case: the firmware on the card is an exact match and 3017 * the KLD is an exact match too, or the KLD is 3018 * absent/incompatible. Note that t4_fw_install = 2 is ignored 3019 * here -- use cxgbetool loadfw if you want to reinstall the 3020 * same firmware as the one on the card. 3021 */ 3022 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 3023 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 3024 be32toh(card_fw->fw_ver))) { 3025 3026 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3027 if (rc != 0) { 3028 device_printf(sc->dev, 3029 "failed to install firmware: %d\n", rc); 3030 goto done; 3031 } 3032 3033 /* Installed successfully, update the cached header too. */ 3034 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3035 card_fw_usable = 1; 3036 need_fw_reset = 0; /* already reset as part of load_fw */ 3037 } 3038 3039 if (!card_fw_usable) { 3040 uint32_t d, c, k; 3041 3042 d = ntohl(drv_fw->fw_ver); 3043 c = ntohl(card_fw->fw_ver); 3044 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 3045 3046 device_printf(sc->dev, "Cannot find a usable firmware: " 3047 "fw_install %d, chip state %d, " 3048 "driver compiled with %d.%d.%d.%d, " 3049 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 3050 t4_fw_install, state, 3051 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3052 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 3053 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3054 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 3055 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3056 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3057 rc = EINVAL; 3058 goto done; 3059 } 3060 3061 /* Reset device */ 3062 if (need_fw_reset && 3063 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 3064 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3065 if (rc != ETIMEDOUT && rc != EIO) 3066 t4_fw_bye(sc, sc->mbox); 3067 goto done; 3068 } 3069 sc->flags |= FW_OK; 3070 3071 rc = get_params__pre_init(sc); 3072 if (rc != 0) 3073 goto done; /* error message displayed already */ 3074 3075 /* Partition adapter resources as specified in the config file. */ 3076 if (state == DEV_STATE_UNINIT) { 3077 3078 KASSERT(sc->flags & MASTER_PF, 3079 ("%s: trying to change chip settings when not master.", 3080 __func__)); 3081 3082 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 3083 if (rc != 0) 3084 goto done; /* error message displayed already */ 3085 3086 t4_tweak_chip_settings(sc); 3087 3088 /* get basic stuff going */ 3089 rc = -t4_fw_initialize(sc, sc->mbox); 3090 if (rc != 0) { 3091 device_printf(sc->dev, "fw init failed: %d.\n", rc); 3092 goto done; 3093 } 3094 } else { 3095 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 3096 sc->cfcsum = 0; 3097 } 3098 3099 done: 3100 free(card_fw, M_CXGBE); 3101 if (fw != NULL) 3102 firmware_put(fw, FIRMWARE_UNLOAD); 3103 if (default_cfg != NULL) 3104 firmware_put(default_cfg, FIRMWARE_UNLOAD); 3105 3106 return (rc); 3107 } 3108 3109 #define FW_PARAM_DEV(param) \ 3110 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3111 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3112 #define FW_PARAM_PFVF(param) \ 3113 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3114 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3115 3116 /* 3117 * Partition chip resources for use between various PFs, VFs, etc. 3118 */ 3119 static int 3120 partition_resources(struct adapter *sc, const struct firmware *default_cfg, 3121 const char *name_prefix) 3122 { 3123 const struct firmware *cfg = NULL; 3124 int rc = 0; 3125 struct fw_caps_config_cmd caps; 3126 uint32_t mtype, moff, finicsum, cfcsum; 3127 3128 /* 3129 * Figure out what configuration file to use. Pick the default config 3130 * file for the card if the user hasn't specified one explicitly. 3131 */ 3132 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 3133 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3134 /* Card specific overrides go here. */ 3135 if (pci_get_device(sc->dev) == 0x440a) 3136 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 3137 if (is_fpga(sc)) 3138 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 3139 } 3140 3141 /* 3142 * We need to load another module if the profile is anything except 3143 * "default" or "flash". 3144 */ 3145 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 3146 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3147 char s[32]; 3148 3149 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 3150 cfg = firmware_get(s); 3151 if (cfg == NULL) { 3152 if (default_cfg != NULL) { 3153 device_printf(sc->dev, 3154 "unable to load module \"%s\" for " 3155 "configuration profile \"%s\", will use " 3156 "the default config file instead.\n", 3157 s, sc->cfg_file); 3158 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3159 "%s", DEFAULT_CF); 3160 } else { 3161 device_printf(sc->dev, 3162 "unable to load module \"%s\" for " 3163 "configuration profile \"%s\", will use " 3164 "the config file on the card's flash " 3165 "instead.\n", s, sc->cfg_file); 3166 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3167 "%s", FLASH_CF); 3168 } 3169 } 3170 } 3171 3172 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3173 default_cfg == NULL) { 3174 device_printf(sc->dev, 3175 "default config file not available, will use the config " 3176 "file on the card's flash instead.\n"); 3177 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3178 } 3179 3180 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3181 u_int cflen; 3182 const uint32_t *cfdata; 3183 uint32_t param, val, addr; 3184 3185 KASSERT(cfg != NULL || default_cfg != NULL, 3186 ("%s: no config to upload", __func__)); 3187 3188 /* 3189 * Ask the firmware where it wants us to upload the config file. 3190 */ 3191 param = FW_PARAM_DEV(CF); 3192 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3193 if (rc != 0) { 3194 /* No support for config file? Shouldn't happen. */ 3195 device_printf(sc->dev, 3196 "failed to query config file location: %d.\n", rc); 3197 goto done; 3198 } 3199 mtype = G_FW_PARAMS_PARAM_Y(val); 3200 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3201 3202 /* 3203 * XXX: sheer laziness. We deliberately added 4 bytes of 3204 * useless stuffing/comments at the end of the config file so 3205 * it's ok to simply throw away the last remaining bytes when 3206 * the config file is not an exact multiple of 4. This also 3207 * helps with the validate_mt_off_len check. 3208 */ 3209 if (cfg != NULL) { 3210 cflen = cfg->datasize & ~3; 3211 cfdata = cfg->data; 3212 } else { 3213 cflen = default_cfg->datasize & ~3; 3214 cfdata = default_cfg->data; 3215 } 3216 3217 if (cflen > FLASH_CFG_MAX_SIZE) { 3218 device_printf(sc->dev, 3219 "config file too long (%d, max allowed is %d). " 3220 "Will try to use the config on the card, if any.\n", 3221 cflen, FLASH_CFG_MAX_SIZE); 3222 goto use_config_on_flash; 3223 } 3224 3225 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3226 if (rc != 0) { 3227 device_printf(sc->dev, 3228 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3229 "Will try to use the config on the card, if any.\n", 3230 __func__, mtype, moff, cflen, rc); 3231 goto use_config_on_flash; 3232 } 3233 write_via_memwin(sc, 2, addr, cfdata, cflen); 3234 } else { 3235 use_config_on_flash: 3236 mtype = FW_MEMTYPE_FLASH; 3237 moff = t4_flash_cfg_addr(sc); 3238 } 3239 3240 bzero(&caps, sizeof(caps)); 3241 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3242 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3243 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3244 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3245 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3246 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3247 if (rc != 0) { 3248 device_printf(sc->dev, 3249 "failed to pre-process config file: %d " 3250 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3251 goto done; 3252 } 3253 3254 finicsum = be32toh(caps.finicsum); 3255 cfcsum = be32toh(caps.cfcsum); 3256 if (finicsum != cfcsum) { 3257 device_printf(sc->dev, 3258 "WARNING: config file checksum mismatch: %08x %08x\n", 3259 finicsum, cfcsum); 3260 } 3261 sc->cfcsum = cfcsum; 3262 3263 #define LIMIT_CAPS(x) do { \ 3264 caps.x &= htobe16(t4_##x##_allowed); \ 3265 } while (0) 3266 3267 /* 3268 * Let the firmware know what features will (not) be used so it can tune 3269 * things accordingly. 3270 */ 3271 LIMIT_CAPS(nbmcaps); 3272 LIMIT_CAPS(linkcaps); 3273 LIMIT_CAPS(switchcaps); 3274 LIMIT_CAPS(niccaps); 3275 LIMIT_CAPS(toecaps); 3276 LIMIT_CAPS(rdmacaps); 3277 LIMIT_CAPS(cryptocaps); 3278 LIMIT_CAPS(iscsicaps); 3279 LIMIT_CAPS(fcoecaps); 3280 #undef LIMIT_CAPS 3281 3282 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3283 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3284 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3285 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3286 if (rc != 0) { 3287 device_printf(sc->dev, 3288 "failed to process config file: %d.\n", rc); 3289 } 3290 done: 3291 if (cfg != NULL) 3292 firmware_put(cfg, FIRMWARE_UNLOAD); 3293 return (rc); 3294 } 3295 3296 /* 3297 * Retrieve parameters that are needed (or nice to have) very early. 3298 */ 3299 static int 3300 get_params__pre_init(struct adapter *sc) 3301 { 3302 int rc; 3303 uint32_t param[2], val[2]; 3304 3305 t4_get_version_info(sc); 3306 3307 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3308 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3309 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3310 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3311 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3312 3313 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3314 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3315 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3316 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3317 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3318 3319 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3320 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3321 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3322 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3323 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3324 3325 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3326 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3327 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3328 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3329 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3330 3331 param[0] = FW_PARAM_DEV(PORTVEC); 3332 param[1] = FW_PARAM_DEV(CCLK); 3333 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3334 if (rc != 0) { 3335 device_printf(sc->dev, 3336 "failed to query parameters (pre_init): %d.\n", rc); 3337 return (rc); 3338 } 3339 3340 sc->params.portvec = val[0]; 3341 sc->params.nports = bitcount32(val[0]); 3342 sc->params.vpd.cclk = val[1]; 3343 3344 /* Read device log parameters. */ 3345 rc = -t4_init_devlog_params(sc, 1); 3346 if (rc == 0) 3347 fixup_devlog_params(sc); 3348 else { 3349 device_printf(sc->dev, 3350 "failed to get devlog parameters: %d.\n", rc); 3351 rc = 0; /* devlog isn't critical for device operation */ 3352 } 3353 3354 return (rc); 3355 } 3356 3357 /* 3358 * Retrieve various parameters that are of interest to the driver. The device 3359 * has been initialized by the firmware at this point. 3360 */ 3361 static int 3362 get_params__post_init(struct adapter *sc) 3363 { 3364 int rc; 3365 uint32_t param[7], val[7]; 3366 struct fw_caps_config_cmd caps; 3367 3368 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3369 param[1] = FW_PARAM_PFVF(EQ_START); 3370 param[2] = FW_PARAM_PFVF(FILTER_START); 3371 param[3] = FW_PARAM_PFVF(FILTER_END); 3372 param[4] = FW_PARAM_PFVF(L2T_START); 3373 param[5] = FW_PARAM_PFVF(L2T_END); 3374 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3375 if (rc != 0) { 3376 device_printf(sc->dev, 3377 "failed to query parameters (post_init): %d.\n", rc); 3378 return (rc); 3379 } 3380 3381 sc->sge.iq_start = val[0]; 3382 sc->sge.eq_start = val[1]; 3383 sc->tids.ftid_base = val[2]; 3384 sc->tids.nftids = val[3] - val[2] + 1; 3385 sc->params.ftid_min = val[2]; 3386 sc->params.ftid_max = val[3]; 3387 sc->vres.l2t.start = val[4]; 3388 sc->vres.l2t.size = val[5] - val[4] + 1; 3389 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3390 ("%s: L2 table size (%u) larger than expected (%u)", 3391 __func__, sc->vres.l2t.size, L2T_SIZE)); 3392 3393 /* get capabilites */ 3394 bzero(&caps, sizeof(caps)); 3395 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3396 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3397 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3398 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3399 if (rc != 0) { 3400 device_printf(sc->dev, 3401 "failed to get card capabilities: %d.\n", rc); 3402 return (rc); 3403 } 3404 3405 #define READ_CAPS(x) do { \ 3406 sc->x = htobe16(caps.x); \ 3407 } while (0) 3408 READ_CAPS(nbmcaps); 3409 READ_CAPS(linkcaps); 3410 READ_CAPS(switchcaps); 3411 READ_CAPS(niccaps); 3412 READ_CAPS(toecaps); 3413 READ_CAPS(rdmacaps); 3414 READ_CAPS(cryptocaps); 3415 READ_CAPS(iscsicaps); 3416 READ_CAPS(fcoecaps); 3417 3418 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 3419 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 3420 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 3421 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3422 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 3423 if (rc != 0) { 3424 device_printf(sc->dev, 3425 "failed to query NIC parameters: %d.\n", rc); 3426 return (rc); 3427 } 3428 sc->tids.etid_base = val[0]; 3429 sc->params.etid_min = val[0]; 3430 sc->tids.netids = val[1] - val[0] + 1; 3431 sc->params.netids = sc->tids.netids; 3432 sc->params.eo_wr_cred = val[2]; 3433 sc->params.ethoffload = 1; 3434 } 3435 3436 if (sc->toecaps) { 3437 /* query offload-related parameters */ 3438 param[0] = FW_PARAM_DEV(NTID); 3439 param[1] = FW_PARAM_PFVF(SERVER_START); 3440 param[2] = FW_PARAM_PFVF(SERVER_END); 3441 param[3] = FW_PARAM_PFVF(TDDP_START); 3442 param[4] = FW_PARAM_PFVF(TDDP_END); 3443 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3444 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3445 if (rc != 0) { 3446 device_printf(sc->dev, 3447 "failed to query TOE parameters: %d.\n", rc); 3448 return (rc); 3449 } 3450 sc->tids.ntids = val[0]; 3451 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3452 sc->tids.stid_base = val[1]; 3453 sc->tids.nstids = val[2] - val[1] + 1; 3454 sc->vres.ddp.start = val[3]; 3455 sc->vres.ddp.size = val[4] - val[3] + 1; 3456 sc->params.ofldq_wr_cred = val[5]; 3457 sc->params.offload = 1; 3458 } 3459 if (sc->rdmacaps) { 3460 param[0] = FW_PARAM_PFVF(STAG_START); 3461 param[1] = FW_PARAM_PFVF(STAG_END); 3462 param[2] = FW_PARAM_PFVF(RQ_START); 3463 param[3] = FW_PARAM_PFVF(RQ_END); 3464 param[4] = FW_PARAM_PFVF(PBL_START); 3465 param[5] = FW_PARAM_PFVF(PBL_END); 3466 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3467 if (rc != 0) { 3468 device_printf(sc->dev, 3469 "failed to query RDMA parameters(1): %d.\n", rc); 3470 return (rc); 3471 } 3472 sc->vres.stag.start = val[0]; 3473 sc->vres.stag.size = val[1] - val[0] + 1; 3474 sc->vres.rq.start = val[2]; 3475 sc->vres.rq.size = val[3] - val[2] + 1; 3476 sc->vres.pbl.start = val[4]; 3477 sc->vres.pbl.size = val[5] - val[4] + 1; 3478 3479 param[0] = FW_PARAM_PFVF(SQRQ_START); 3480 param[1] = FW_PARAM_PFVF(SQRQ_END); 3481 param[2] = FW_PARAM_PFVF(CQ_START); 3482 param[3] = FW_PARAM_PFVF(CQ_END); 3483 param[4] = FW_PARAM_PFVF(OCQ_START); 3484 param[5] = FW_PARAM_PFVF(OCQ_END); 3485 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3486 if (rc != 0) { 3487 device_printf(sc->dev, 3488 "failed to query RDMA parameters(2): %d.\n", rc); 3489 return (rc); 3490 } 3491 sc->vres.qp.start = val[0]; 3492 sc->vres.qp.size = val[1] - val[0] + 1; 3493 sc->vres.cq.start = val[2]; 3494 sc->vres.cq.size = val[3] - val[2] + 1; 3495 sc->vres.ocq.start = val[4]; 3496 sc->vres.ocq.size = val[5] - val[4] + 1; 3497 } 3498 if (sc->iscsicaps) { 3499 param[0] = FW_PARAM_PFVF(ISCSI_START); 3500 param[1] = FW_PARAM_PFVF(ISCSI_END); 3501 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3502 if (rc != 0) { 3503 device_printf(sc->dev, 3504 "failed to query iSCSI parameters: %d.\n", rc); 3505 return (rc); 3506 } 3507 sc->vres.iscsi.start = val[0]; 3508 sc->vres.iscsi.size = val[1] - val[0] + 1; 3509 } 3510 3511 t4_init_sge_params(sc); 3512 3513 /* 3514 * We've got the params we wanted to query via the firmware. Now grab 3515 * some others directly from the chip. 3516 */ 3517 rc = t4_read_chip_settings(sc); 3518 3519 return (rc); 3520 } 3521 3522 static int 3523 set_params__post_init(struct adapter *sc) 3524 { 3525 uint32_t param, val; 3526 3527 /* ask for encapsulated CPLs */ 3528 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3529 val = 1; 3530 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3531 3532 return (0); 3533 } 3534 3535 #undef FW_PARAM_PFVF 3536 #undef FW_PARAM_DEV 3537 3538 static void 3539 t4_set_desc(struct adapter *sc) 3540 { 3541 char buf[128]; 3542 struct adapter_params *p = &sc->params; 3543 3544 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 3545 3546 device_set_desc_copy(sc->dev, buf); 3547 } 3548 3549 static void 3550 build_medialist(struct port_info *pi, struct ifmedia *media) 3551 { 3552 int m; 3553 3554 PORT_LOCK(pi); 3555 3556 ifmedia_removeall(media); 3557 3558 m = IFM_ETHER | IFM_FDX; 3559 3560 switch(pi->port_type) { 3561 case FW_PORT_TYPE_BT_XFI: 3562 case FW_PORT_TYPE_BT_XAUI: 3563 ifmedia_add(media, m | IFM_10G_T, 0, NULL); 3564 /* fall through */ 3565 3566 case FW_PORT_TYPE_BT_SGMII: 3567 ifmedia_add(media, m | IFM_1000_T, 0, NULL); 3568 ifmedia_add(media, m | IFM_100_TX, 0, NULL); 3569 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL); 3570 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 3571 break; 3572 3573 case FW_PORT_TYPE_CX4: 3574 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL); 3575 ifmedia_set(media, m | IFM_10G_CX4); 3576 break; 3577 3578 case FW_PORT_TYPE_QSFP_10G: 3579 case FW_PORT_TYPE_SFP: 3580 case FW_PORT_TYPE_FIBER_XFI: 3581 case FW_PORT_TYPE_FIBER_XAUI: 3582 switch (pi->mod_type) { 3583 3584 case FW_PORT_MOD_TYPE_LR: 3585 ifmedia_add(media, m | IFM_10G_LR, 0, NULL); 3586 ifmedia_set(media, m | IFM_10G_LR); 3587 break; 3588 3589 case FW_PORT_MOD_TYPE_SR: 3590 ifmedia_add(media, m | IFM_10G_SR, 0, NULL); 3591 ifmedia_set(media, m | IFM_10G_SR); 3592 break; 3593 3594 case FW_PORT_MOD_TYPE_LRM: 3595 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL); 3596 ifmedia_set(media, m | IFM_10G_LRM); 3597 break; 3598 3599 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3600 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3601 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL); 3602 ifmedia_set(media, m | IFM_10G_TWINAX); 3603 break; 3604 3605 case FW_PORT_MOD_TYPE_NONE: 3606 m &= ~IFM_FDX; 3607 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3608 ifmedia_set(media, m | IFM_NONE); 3609 break; 3610 3611 case FW_PORT_MOD_TYPE_NA: 3612 case FW_PORT_MOD_TYPE_ER: 3613 default: 3614 device_printf(pi->dev, 3615 "unknown port_type (%d), mod_type (%d)\n", 3616 pi->port_type, pi->mod_type); 3617 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3618 ifmedia_set(media, m | IFM_UNKNOWN); 3619 break; 3620 } 3621 break; 3622 3623 case FW_PORT_TYPE_CR_QSFP: 3624 case FW_PORT_TYPE_SFP28: 3625 case FW_PORT_TYPE_KR_SFP28: 3626 switch (pi->mod_type) { 3627 3628 case FW_PORT_MOD_TYPE_SR: 3629 ifmedia_add(media, m | IFM_25G_SR, 0, NULL); 3630 ifmedia_set(media, m | IFM_25G_SR); 3631 break; 3632 3633 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3634 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3635 ifmedia_add(media, m | IFM_25G_CR, 0, NULL); 3636 ifmedia_set(media, m | IFM_25G_CR); 3637 break; 3638 3639 case FW_PORT_MOD_TYPE_NONE: 3640 m &= ~IFM_FDX; 3641 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3642 ifmedia_set(media, m | IFM_NONE); 3643 break; 3644 3645 default: 3646 device_printf(pi->dev, 3647 "unknown port_type (%d), mod_type (%d)\n", 3648 pi->port_type, pi->mod_type); 3649 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3650 ifmedia_set(media, m | IFM_UNKNOWN); 3651 break; 3652 } 3653 break; 3654 3655 case FW_PORT_TYPE_QSFP: 3656 switch (pi->mod_type) { 3657 3658 case FW_PORT_MOD_TYPE_LR: 3659 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL); 3660 ifmedia_set(media, m | IFM_40G_LR4); 3661 break; 3662 3663 case FW_PORT_MOD_TYPE_SR: 3664 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL); 3665 ifmedia_set(media, m | IFM_40G_SR4); 3666 break; 3667 3668 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3669 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3670 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL); 3671 ifmedia_set(media, m | IFM_40G_CR4); 3672 break; 3673 3674 case FW_PORT_MOD_TYPE_NONE: 3675 m &= ~IFM_FDX; 3676 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3677 ifmedia_set(media, m | IFM_NONE); 3678 break; 3679 3680 default: 3681 device_printf(pi->dev, 3682 "unknown port_type (%d), mod_type (%d)\n", 3683 pi->port_type, pi->mod_type); 3684 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3685 ifmedia_set(media, m | IFM_UNKNOWN); 3686 break; 3687 } 3688 break; 3689 3690 case FW_PORT_TYPE_KR4_100G: 3691 case FW_PORT_TYPE_CR4_QSFP: 3692 switch (pi->mod_type) { 3693 3694 case FW_PORT_MOD_TYPE_LR: 3695 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL); 3696 ifmedia_set(media, m | IFM_100G_LR4); 3697 break; 3698 3699 case FW_PORT_MOD_TYPE_SR: 3700 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL); 3701 ifmedia_set(media, m | IFM_100G_SR4); 3702 break; 3703 3704 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3705 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3706 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL); 3707 ifmedia_set(media, m | IFM_100G_CR4); 3708 break; 3709 3710 case FW_PORT_MOD_TYPE_NONE: 3711 m &= ~IFM_FDX; 3712 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3713 ifmedia_set(media, m | IFM_NONE); 3714 break; 3715 3716 default: 3717 device_printf(pi->dev, 3718 "unknown port_type (%d), mod_type (%d)\n", 3719 pi->port_type, pi->mod_type); 3720 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3721 ifmedia_set(media, m | IFM_UNKNOWN); 3722 break; 3723 } 3724 break; 3725 3726 default: 3727 device_printf(pi->dev, 3728 "unknown port_type (%d), mod_type (%d)\n", pi->port_type, 3729 pi->mod_type); 3730 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3731 ifmedia_set(media, m | IFM_UNKNOWN); 3732 break; 3733 } 3734 3735 PORT_UNLOCK(pi); 3736 } 3737 3738 #define FW_MAC_EXACT_CHUNK 7 3739 3740 /* 3741 * Program the port's XGMAC based on parameters in ifnet. The caller also 3742 * indicates which parameters should be programmed (the rest are left alone). 3743 */ 3744 int 3745 update_mac_settings(struct ifnet *ifp, int flags) 3746 { 3747 int rc = 0; 3748 struct vi_info *vi = ifp->if_softc; 3749 struct port_info *pi = vi->pi; 3750 struct adapter *sc = pi->adapter; 3751 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 3752 3753 ASSERT_SYNCHRONIZED_OP(sc); 3754 KASSERT(flags, ("%s: not told what to update.", __func__)); 3755 3756 if (flags & XGMAC_MTU) 3757 mtu = ifp->if_mtu; 3758 3759 if (flags & XGMAC_PROMISC) 3760 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 3761 3762 if (flags & XGMAC_ALLMULTI) 3763 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 3764 3765 if (flags & XGMAC_VLANEX) 3766 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 3767 3768 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 3769 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 3770 allmulti, 1, vlanex, false); 3771 if (rc) { 3772 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 3773 rc); 3774 return (rc); 3775 } 3776 } 3777 3778 if (flags & XGMAC_UCADDR) { 3779 uint8_t ucaddr[ETHER_ADDR_LEN]; 3780 3781 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 3782 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 3783 ucaddr, true, true); 3784 if (rc < 0) { 3785 rc = -rc; 3786 if_printf(ifp, "change_mac failed: %d\n", rc); 3787 return (rc); 3788 } else { 3789 vi->xact_addr_filt = rc; 3790 rc = 0; 3791 } 3792 } 3793 3794 if (flags & XGMAC_MCADDRS) { 3795 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 3796 int del = 1; 3797 uint64_t hash = 0; 3798 struct ifmultiaddr *ifma; 3799 int i = 0, j; 3800 3801 if_maddr_rlock(ifp); 3802 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 3803 if (ifma->ifma_addr->sa_family != AF_LINK) 3804 continue; 3805 mcaddr[i] = 3806 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 3807 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 3808 i++; 3809 3810 if (i == FW_MAC_EXACT_CHUNK) { 3811 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 3812 del, i, mcaddr, NULL, &hash, 0); 3813 if (rc < 0) { 3814 rc = -rc; 3815 for (j = 0; j < i; j++) { 3816 if_printf(ifp, 3817 "failed to add mc address" 3818 " %02x:%02x:%02x:" 3819 "%02x:%02x:%02x rc=%d\n", 3820 mcaddr[j][0], mcaddr[j][1], 3821 mcaddr[j][2], mcaddr[j][3], 3822 mcaddr[j][4], mcaddr[j][5], 3823 rc); 3824 } 3825 goto mcfail; 3826 } 3827 del = 0; 3828 i = 0; 3829 } 3830 } 3831 if (i > 0) { 3832 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 3833 mcaddr, NULL, &hash, 0); 3834 if (rc < 0) { 3835 rc = -rc; 3836 for (j = 0; j < i; j++) { 3837 if_printf(ifp, 3838 "failed to add mc address" 3839 " %02x:%02x:%02x:" 3840 "%02x:%02x:%02x rc=%d\n", 3841 mcaddr[j][0], mcaddr[j][1], 3842 mcaddr[j][2], mcaddr[j][3], 3843 mcaddr[j][4], mcaddr[j][5], 3844 rc); 3845 } 3846 goto mcfail; 3847 } 3848 } 3849 3850 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 3851 if (rc != 0) 3852 if_printf(ifp, "failed to set mc address hash: %d", rc); 3853 mcfail: 3854 if_maddr_runlock(ifp); 3855 } 3856 3857 return (rc); 3858 } 3859 3860 /* 3861 * {begin|end}_synchronized_op must be called from the same thread. 3862 */ 3863 int 3864 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 3865 char *wmesg) 3866 { 3867 int rc, pri; 3868 3869 #ifdef WITNESS 3870 /* the caller thinks it's ok to sleep, but is it really? */ 3871 if (flags & SLEEP_OK) 3872 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 3873 "begin_synchronized_op"); 3874 #endif 3875 3876 if (INTR_OK) 3877 pri = PCATCH; 3878 else 3879 pri = 0; 3880 3881 ADAPTER_LOCK(sc); 3882 for (;;) { 3883 3884 if (vi && IS_DOOMED(vi)) { 3885 rc = ENXIO; 3886 goto done; 3887 } 3888 3889 if (!IS_BUSY(sc)) { 3890 rc = 0; 3891 break; 3892 } 3893 3894 if (!(flags & SLEEP_OK)) { 3895 rc = EBUSY; 3896 goto done; 3897 } 3898 3899 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 3900 rc = EINTR; 3901 goto done; 3902 } 3903 } 3904 3905 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 3906 SET_BUSY(sc); 3907 #ifdef INVARIANTS 3908 sc->last_op = wmesg; 3909 sc->last_op_thr = curthread; 3910 sc->last_op_flags = flags; 3911 #endif 3912 3913 done: 3914 if (!(flags & HOLD_LOCK) || rc) 3915 ADAPTER_UNLOCK(sc); 3916 3917 return (rc); 3918 } 3919 3920 /* 3921 * Tell if_ioctl and if_init that the VI is going away. This is 3922 * special variant of begin_synchronized_op and must be paired with a 3923 * call to end_synchronized_op. 3924 */ 3925 void 3926 doom_vi(struct adapter *sc, struct vi_info *vi) 3927 { 3928 3929 ADAPTER_LOCK(sc); 3930 SET_DOOMED(vi); 3931 wakeup(&sc->flags); 3932 while (IS_BUSY(sc)) 3933 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 3934 SET_BUSY(sc); 3935 #ifdef INVARIANTS 3936 sc->last_op = "t4detach"; 3937 sc->last_op_thr = curthread; 3938 sc->last_op_flags = 0; 3939 #endif 3940 ADAPTER_UNLOCK(sc); 3941 } 3942 3943 /* 3944 * {begin|end}_synchronized_op must be called from the same thread. 3945 */ 3946 void 3947 end_synchronized_op(struct adapter *sc, int flags) 3948 { 3949 3950 if (flags & LOCK_HELD) 3951 ADAPTER_LOCK_ASSERT_OWNED(sc); 3952 else 3953 ADAPTER_LOCK(sc); 3954 3955 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 3956 CLR_BUSY(sc); 3957 wakeup(&sc->flags); 3958 ADAPTER_UNLOCK(sc); 3959 } 3960 3961 static int 3962 cxgbe_init_synchronized(struct vi_info *vi) 3963 { 3964 struct port_info *pi = vi->pi; 3965 struct adapter *sc = pi->adapter; 3966 struct ifnet *ifp = vi->ifp; 3967 int rc = 0, i; 3968 struct sge_txq *txq; 3969 3970 ASSERT_SYNCHRONIZED_OP(sc); 3971 3972 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3973 return (0); /* already running */ 3974 3975 if (!(sc->flags & FULL_INIT_DONE) && 3976 ((rc = adapter_full_init(sc)) != 0)) 3977 return (rc); /* error message displayed already */ 3978 3979 if (!(vi->flags & VI_INIT_DONE) && 3980 ((rc = vi_full_init(vi)) != 0)) 3981 return (rc); /* error message displayed already */ 3982 3983 rc = update_mac_settings(ifp, XGMAC_ALL); 3984 if (rc) 3985 goto done; /* error message displayed already */ 3986 3987 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 3988 if (rc != 0) { 3989 if_printf(ifp, "enable_vi failed: %d\n", rc); 3990 goto done; 3991 } 3992 3993 /* 3994 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 3995 * if this changes. 3996 */ 3997 3998 for_each_txq(vi, i, txq) { 3999 TXQ_LOCK(txq); 4000 txq->eq.flags |= EQ_ENABLED; 4001 TXQ_UNLOCK(txq); 4002 } 4003 4004 /* 4005 * The first iq of the first port to come up is used for tracing. 4006 */ 4007 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 4008 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 4009 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 4010 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 4011 V_QUEUENUMBER(sc->traceq)); 4012 pi->flags |= HAS_TRACEQ; 4013 } 4014 4015 /* all ok */ 4016 PORT_LOCK(pi); 4017 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4018 pi->up_vis++; 4019 4020 if (pi->nvi > 1 || sc->flags & IS_VF) 4021 callout_reset(&vi->tick, hz, vi_tick, vi); 4022 else 4023 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 4024 PORT_UNLOCK(pi); 4025 done: 4026 if (rc != 0) 4027 cxgbe_uninit_synchronized(vi); 4028 4029 return (rc); 4030 } 4031 4032 /* 4033 * Idempotent. 4034 */ 4035 static int 4036 cxgbe_uninit_synchronized(struct vi_info *vi) 4037 { 4038 struct port_info *pi = vi->pi; 4039 struct adapter *sc = pi->adapter; 4040 struct ifnet *ifp = vi->ifp; 4041 int rc, i; 4042 struct sge_txq *txq; 4043 4044 ASSERT_SYNCHRONIZED_OP(sc); 4045 4046 if (!(vi->flags & VI_INIT_DONE)) { 4047 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING), 4048 ("uninited VI is running")); 4049 return (0); 4050 } 4051 4052 /* 4053 * Disable the VI so that all its data in either direction is discarded 4054 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 4055 * tick) intact as the TP can deliver negative advice or data that it's 4056 * holding in its RAM (for an offloaded connection) even after the VI is 4057 * disabled. 4058 */ 4059 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 4060 if (rc) { 4061 if_printf(ifp, "disable_vi failed: %d\n", rc); 4062 return (rc); 4063 } 4064 4065 for_each_txq(vi, i, txq) { 4066 TXQ_LOCK(txq); 4067 txq->eq.flags &= ~EQ_ENABLED; 4068 TXQ_UNLOCK(txq); 4069 } 4070 4071 PORT_LOCK(pi); 4072 if (pi->nvi > 1 || sc->flags & IS_VF) 4073 callout_stop(&vi->tick); 4074 else 4075 callout_stop(&pi->tick); 4076 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4077 PORT_UNLOCK(pi); 4078 return (0); 4079 } 4080 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4081 pi->up_vis--; 4082 if (pi->up_vis > 0) { 4083 PORT_UNLOCK(pi); 4084 return (0); 4085 } 4086 PORT_UNLOCK(pi); 4087 4088 pi->link_cfg.link_ok = 0; 4089 pi->link_cfg.speed = 0; 4090 pi->link_cfg.link_down_rc = 255; 4091 t4_os_link_changed(sc, pi->port_id, 0); 4092 4093 return (0); 4094 } 4095 4096 /* 4097 * It is ok for this function to fail midway and return right away. t4_detach 4098 * will walk the entire sc->irq list and clean up whatever is valid. 4099 */ 4100 int 4101 t4_setup_intr_handlers(struct adapter *sc) 4102 { 4103 int rc, rid, p, q, v; 4104 char s[8]; 4105 struct irq *irq; 4106 struct port_info *pi; 4107 struct vi_info *vi; 4108 struct sge *sge = &sc->sge; 4109 struct sge_rxq *rxq; 4110 #ifdef TCP_OFFLOAD 4111 struct sge_ofld_rxq *ofld_rxq; 4112 #endif 4113 #ifdef DEV_NETMAP 4114 struct sge_nm_rxq *nm_rxq; 4115 #endif 4116 #ifdef RSS 4117 int nbuckets = rss_getnumbuckets(); 4118 #endif 4119 4120 /* 4121 * Setup interrupts. 4122 */ 4123 irq = &sc->irq[0]; 4124 rid = sc->intr_type == INTR_INTX ? 0 : 1; 4125 if (sc->intr_count == 1) 4126 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 4127 4128 /* Multiple interrupts. */ 4129 if (sc->flags & IS_VF) 4130 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 4131 ("%s: too few intr.", __func__)); 4132 else 4133 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 4134 ("%s: too few intr.", __func__)); 4135 4136 /* The first one is always error intr on PFs */ 4137 if (!(sc->flags & IS_VF)) { 4138 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4139 if (rc != 0) 4140 return (rc); 4141 irq++; 4142 rid++; 4143 } 4144 4145 /* The second one is always the firmware event queue (first on VFs) */ 4146 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4147 if (rc != 0) 4148 return (rc); 4149 irq++; 4150 rid++; 4151 4152 for_each_port(sc, p) { 4153 pi = sc->port[p]; 4154 for_each_vi(pi, v, vi) { 4155 vi->first_intr = rid - 1; 4156 4157 if (vi->nnmrxq > 0) { 4158 int n = max(vi->nrxq, vi->nnmrxq); 4159 4160 MPASS(vi->flags & INTR_RXQ); 4161 4162 rxq = &sge->rxq[vi->first_rxq]; 4163 #ifdef DEV_NETMAP 4164 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4165 #endif 4166 for (q = 0; q < n; q++) { 4167 snprintf(s, sizeof(s), "%x%c%x", p, 4168 'a' + v, q); 4169 if (q < vi->nrxq) 4170 irq->rxq = rxq++; 4171 #ifdef DEV_NETMAP 4172 if (q < vi->nnmrxq) 4173 irq->nm_rxq = nm_rxq++; 4174 #endif 4175 rc = t4_alloc_irq(sc, irq, rid, 4176 t4_vi_intr, irq, s); 4177 if (rc != 0) 4178 return (rc); 4179 irq++; 4180 rid++; 4181 vi->nintr++; 4182 } 4183 } else if (vi->flags & INTR_RXQ) { 4184 for_each_rxq(vi, q, rxq) { 4185 snprintf(s, sizeof(s), "%x%c%x", p, 4186 'a' + v, q); 4187 rc = t4_alloc_irq(sc, irq, rid, 4188 t4_intr, rxq, s); 4189 if (rc != 0) 4190 return (rc); 4191 #ifdef RSS 4192 bus_bind_intr(sc->dev, irq->res, 4193 rss_getcpu(q % nbuckets)); 4194 #endif 4195 irq++; 4196 rid++; 4197 vi->nintr++; 4198 } 4199 } 4200 #ifdef TCP_OFFLOAD 4201 if (vi->flags & INTR_OFLD_RXQ) { 4202 for_each_ofld_rxq(vi, q, ofld_rxq) { 4203 snprintf(s, sizeof(s), "%x%c%x", p, 4204 'A' + v, q); 4205 rc = t4_alloc_irq(sc, irq, rid, 4206 t4_intr, ofld_rxq, s); 4207 if (rc != 0) 4208 return (rc); 4209 irq++; 4210 rid++; 4211 vi->nintr++; 4212 } 4213 } 4214 #endif 4215 } 4216 } 4217 MPASS(irq == &sc->irq[sc->intr_count]); 4218 4219 return (0); 4220 } 4221 4222 int 4223 adapter_full_init(struct adapter *sc) 4224 { 4225 int rc, i; 4226 #ifdef RSS 4227 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4228 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4229 #endif 4230 4231 ASSERT_SYNCHRONIZED_OP(sc); 4232 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4233 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 4234 ("%s: FULL_INIT_DONE already", __func__)); 4235 4236 /* 4237 * queues that belong to the adapter (not any particular port). 4238 */ 4239 rc = t4_setup_adapter_queues(sc); 4240 if (rc != 0) 4241 goto done; 4242 4243 for (i = 0; i < nitems(sc->tq); i++) { 4244 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 4245 taskqueue_thread_enqueue, &sc->tq[i]); 4246 if (sc->tq[i] == NULL) { 4247 device_printf(sc->dev, 4248 "failed to allocate task queue %d\n", i); 4249 rc = ENOMEM; 4250 goto done; 4251 } 4252 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 4253 device_get_nameunit(sc->dev), i); 4254 } 4255 #ifdef RSS 4256 MPASS(RSS_KEYSIZE == 40); 4257 rss_getkey((void *)&raw_rss_key[0]); 4258 for (i = 0; i < nitems(rss_key); i++) { 4259 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 4260 } 4261 t4_write_rss_key(sc, &rss_key[0], -1); 4262 #endif 4263 4264 if (!(sc->flags & IS_VF)) 4265 t4_intr_enable(sc); 4266 sc->flags |= FULL_INIT_DONE; 4267 done: 4268 if (rc != 0) 4269 adapter_full_uninit(sc); 4270 4271 return (rc); 4272 } 4273 4274 int 4275 adapter_full_uninit(struct adapter *sc) 4276 { 4277 int i; 4278 4279 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4280 4281 t4_teardown_adapter_queues(sc); 4282 4283 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 4284 taskqueue_free(sc->tq[i]); 4285 sc->tq[i] = NULL; 4286 } 4287 4288 sc->flags &= ~FULL_INIT_DONE; 4289 4290 return (0); 4291 } 4292 4293 #ifdef RSS 4294 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 4295 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 4296 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 4297 RSS_HASHTYPE_RSS_UDP_IPV6) 4298 4299 /* Translates kernel hash types to hardware. */ 4300 static int 4301 hashconfig_to_hashen(int hashconfig) 4302 { 4303 int hashen = 0; 4304 4305 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 4306 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 4307 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 4308 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 4309 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 4310 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4311 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4312 } 4313 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 4314 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4315 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4316 } 4317 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 4318 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4319 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 4320 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4321 4322 return (hashen); 4323 } 4324 4325 /* Translates hardware hash types to kernel. */ 4326 static int 4327 hashen_to_hashconfig(int hashen) 4328 { 4329 int hashconfig = 0; 4330 4331 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 4332 /* 4333 * If UDP hashing was enabled it must have been enabled for 4334 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 4335 * enabling any 4-tuple hash is nonsense configuration. 4336 */ 4337 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4338 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 4339 4340 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4341 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 4342 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4343 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 4344 } 4345 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4346 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 4347 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4348 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 4349 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 4350 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 4351 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 4352 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 4353 4354 return (hashconfig); 4355 } 4356 #endif 4357 4358 int 4359 vi_full_init(struct vi_info *vi) 4360 { 4361 struct adapter *sc = vi->pi->adapter; 4362 struct ifnet *ifp = vi->ifp; 4363 uint16_t *rss; 4364 struct sge_rxq *rxq; 4365 int rc, i, j, hashen; 4366 #ifdef RSS 4367 int nbuckets = rss_getnumbuckets(); 4368 int hashconfig = rss_gethashconfig(); 4369 int extra; 4370 #endif 4371 4372 ASSERT_SYNCHRONIZED_OP(sc); 4373 KASSERT((vi->flags & VI_INIT_DONE) == 0, 4374 ("%s: VI_INIT_DONE already", __func__)); 4375 4376 sysctl_ctx_init(&vi->ctx); 4377 vi->flags |= VI_SYSCTL_CTX; 4378 4379 /* 4380 * Allocate tx/rx/fl queues for this VI. 4381 */ 4382 rc = t4_setup_vi_queues(vi); 4383 if (rc != 0) 4384 goto done; /* error message displayed already */ 4385 4386 /* 4387 * Setup RSS for this VI. Save a copy of the RSS table for later use. 4388 */ 4389 if (vi->nrxq > vi->rss_size) { 4390 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 4391 "some queues will never receive traffic.\n", vi->nrxq, 4392 vi->rss_size); 4393 } else if (vi->rss_size % vi->nrxq) { 4394 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 4395 "expect uneven traffic distribution.\n", vi->nrxq, 4396 vi->rss_size); 4397 } 4398 #ifdef RSS 4399 if (vi->nrxq != nbuckets) { 4400 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 4401 "performance will be impacted.\n", vi->nrxq, nbuckets); 4402 } 4403 #endif 4404 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 4405 for (i = 0; i < vi->rss_size;) { 4406 #ifdef RSS 4407 j = rss_get_indirection_to_bucket(i); 4408 j %= vi->nrxq; 4409 rxq = &sc->sge.rxq[vi->first_rxq + j]; 4410 rss[i++] = rxq->iq.abs_id; 4411 #else 4412 for_each_rxq(vi, j, rxq) { 4413 rss[i++] = rxq->iq.abs_id; 4414 if (i == vi->rss_size) 4415 break; 4416 } 4417 #endif 4418 } 4419 4420 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 4421 vi->rss_size); 4422 if (rc != 0) { 4423 if_printf(ifp, "rss_config failed: %d\n", rc); 4424 goto done; 4425 } 4426 4427 #ifdef RSS 4428 hashen = hashconfig_to_hashen(hashconfig); 4429 4430 /* 4431 * We may have had to enable some hashes even though the global config 4432 * wants them disabled. This is a potential problem that must be 4433 * reported to the user. 4434 */ 4435 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 4436 4437 /* 4438 * If we consider only the supported hash types, then the enabled hashes 4439 * are a superset of the requested hashes. In other words, there cannot 4440 * be any supported hash that was requested but not enabled, but there 4441 * can be hashes that were not requested but had to be enabled. 4442 */ 4443 extra &= SUPPORTED_RSS_HASHTYPES; 4444 MPASS((extra & hashconfig) == 0); 4445 4446 if (extra) { 4447 if_printf(ifp, 4448 "global RSS config (0x%x) cannot be accommodated.\n", 4449 hashconfig); 4450 } 4451 if (extra & RSS_HASHTYPE_RSS_IPV4) 4452 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 4453 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 4454 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 4455 if (extra & RSS_HASHTYPE_RSS_IPV6) 4456 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 4457 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 4458 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 4459 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 4460 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 4461 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 4462 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 4463 #else 4464 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 4465 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 4466 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4467 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 4468 #endif 4469 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0); 4470 if (rc != 0) { 4471 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 4472 goto done; 4473 } 4474 4475 vi->rss = rss; 4476 vi->flags |= VI_INIT_DONE; 4477 done: 4478 if (rc != 0) 4479 vi_full_uninit(vi); 4480 4481 return (rc); 4482 } 4483 4484 /* 4485 * Idempotent. 4486 */ 4487 int 4488 vi_full_uninit(struct vi_info *vi) 4489 { 4490 struct port_info *pi = vi->pi; 4491 struct adapter *sc = pi->adapter; 4492 int i; 4493 struct sge_rxq *rxq; 4494 struct sge_txq *txq; 4495 #ifdef TCP_OFFLOAD 4496 struct sge_ofld_rxq *ofld_rxq; 4497 struct sge_wrq *ofld_txq; 4498 #endif 4499 4500 if (vi->flags & VI_INIT_DONE) { 4501 4502 /* Need to quiesce queues. */ 4503 4504 /* XXX: Only for the first VI? */ 4505 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 4506 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 4507 4508 for_each_txq(vi, i, txq) { 4509 quiesce_txq(sc, txq); 4510 } 4511 4512 #ifdef TCP_OFFLOAD 4513 for_each_ofld_txq(vi, i, ofld_txq) { 4514 quiesce_wrq(sc, ofld_txq); 4515 } 4516 #endif 4517 4518 for_each_rxq(vi, i, rxq) { 4519 quiesce_iq(sc, &rxq->iq); 4520 quiesce_fl(sc, &rxq->fl); 4521 } 4522 4523 #ifdef TCP_OFFLOAD 4524 for_each_ofld_rxq(vi, i, ofld_rxq) { 4525 quiesce_iq(sc, &ofld_rxq->iq); 4526 quiesce_fl(sc, &ofld_rxq->fl); 4527 } 4528 #endif 4529 free(vi->rss, M_CXGBE); 4530 free(vi->nm_rss, M_CXGBE); 4531 } 4532 4533 t4_teardown_vi_queues(vi); 4534 vi->flags &= ~VI_INIT_DONE; 4535 4536 return (0); 4537 } 4538 4539 static void 4540 quiesce_txq(struct adapter *sc, struct sge_txq *txq) 4541 { 4542 struct sge_eq *eq = &txq->eq; 4543 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4544 4545 (void) sc; /* unused */ 4546 4547 #ifdef INVARIANTS 4548 TXQ_LOCK(txq); 4549 MPASS((eq->flags & EQ_ENABLED) == 0); 4550 TXQ_UNLOCK(txq); 4551 #endif 4552 4553 /* Wait for the mp_ring to empty. */ 4554 while (!mp_ring_is_idle(txq->r)) { 4555 mp_ring_check_drainage(txq->r, 0); 4556 pause("rquiesce", 1); 4557 } 4558 4559 /* Then wait for the hardware to finish. */ 4560 while (spg->cidx != htobe16(eq->pidx)) 4561 pause("equiesce", 1); 4562 4563 /* Finally, wait for the driver to reclaim all descriptors. */ 4564 while (eq->cidx != eq->pidx) 4565 pause("dquiesce", 1); 4566 } 4567 4568 static void 4569 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 4570 { 4571 4572 /* XXXTX */ 4573 } 4574 4575 static void 4576 quiesce_iq(struct adapter *sc, struct sge_iq *iq) 4577 { 4578 (void) sc; /* unused */ 4579 4580 /* Synchronize with the interrupt handler */ 4581 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 4582 pause("iqfree", 1); 4583 } 4584 4585 static void 4586 quiesce_fl(struct adapter *sc, struct sge_fl *fl) 4587 { 4588 mtx_lock(&sc->sfl_lock); 4589 FL_LOCK(fl); 4590 fl->flags |= FL_DOOMED; 4591 FL_UNLOCK(fl); 4592 callout_stop(&sc->sfl_callout); 4593 mtx_unlock(&sc->sfl_lock); 4594 4595 KASSERT((fl->flags & FL_STARVING) == 0, 4596 ("%s: still starving", __func__)); 4597 } 4598 4599 static int 4600 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 4601 driver_intr_t *handler, void *arg, char *name) 4602 { 4603 int rc; 4604 4605 irq->rid = rid; 4606 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 4607 RF_SHAREABLE | RF_ACTIVE); 4608 if (irq->res == NULL) { 4609 device_printf(sc->dev, 4610 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 4611 return (ENOMEM); 4612 } 4613 4614 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 4615 NULL, handler, arg, &irq->tag); 4616 if (rc != 0) { 4617 device_printf(sc->dev, 4618 "failed to setup interrupt for rid %d, name %s: %d\n", 4619 rid, name, rc); 4620 } else if (name) 4621 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 4622 4623 return (rc); 4624 } 4625 4626 static int 4627 t4_free_irq(struct adapter *sc, struct irq *irq) 4628 { 4629 if (irq->tag) 4630 bus_teardown_intr(sc->dev, irq->res, irq->tag); 4631 if (irq->res) 4632 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 4633 4634 bzero(irq, sizeof(*irq)); 4635 4636 return (0); 4637 } 4638 4639 static void 4640 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 4641 { 4642 4643 regs->version = chip_id(sc) | chip_rev(sc) << 10; 4644 t4_get_regs(sc, buf, regs->len); 4645 } 4646 4647 #define A_PL_INDIR_CMD 0x1f8 4648 4649 #define S_PL_AUTOINC 31 4650 #define M_PL_AUTOINC 0x1U 4651 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 4652 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 4653 4654 #define S_PL_VFID 20 4655 #define M_PL_VFID 0xffU 4656 #define V_PL_VFID(x) ((x) << S_PL_VFID) 4657 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 4658 4659 #define S_PL_ADDR 0 4660 #define M_PL_ADDR 0xfffffU 4661 #define V_PL_ADDR(x) ((x) << S_PL_ADDR) 4662 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 4663 4664 #define A_PL_INDIR_DATA 0x1fc 4665 4666 static uint64_t 4667 read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 4668 { 4669 u32 stats[2]; 4670 4671 mtx_assert(&sc->reg_lock, MA_OWNED); 4672 if (sc->flags & IS_VF) { 4673 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 4674 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 4675 } else { 4676 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4677 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4678 V_PL_ADDR(VF_MPS_REG(reg))); 4679 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 4680 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 4681 } 4682 return (((uint64_t)stats[1]) << 32 | stats[0]); 4683 } 4684 4685 static void 4686 t4_get_vi_stats(struct adapter *sc, unsigned int viid, 4687 struct fw_vi_stats_vf *stats) 4688 { 4689 4690 #define GET_STAT(name) \ 4691 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 4692 4693 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 4694 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 4695 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 4696 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 4697 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 4698 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 4699 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 4700 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 4701 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 4702 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 4703 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 4704 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 4705 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 4706 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 4707 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 4708 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 4709 4710 #undef GET_STAT 4711 } 4712 4713 static void 4714 t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 4715 { 4716 int reg; 4717 4718 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4719 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4720 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 4721 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 4722 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 4723 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 4724 } 4725 4726 static void 4727 vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 4728 { 4729 struct timeval tv; 4730 const struct timeval interval = {0, 250000}; /* 250ms */ 4731 4732 if (!(vi->flags & VI_INIT_DONE)) 4733 return; 4734 4735 getmicrotime(&tv); 4736 timevalsub(&tv, &interval); 4737 if (timevalcmp(&tv, &vi->last_refreshed, <)) 4738 return; 4739 4740 mtx_lock(&sc->reg_lock); 4741 t4_get_vi_stats(sc, vi->viid, &vi->stats); 4742 getmicrotime(&vi->last_refreshed); 4743 mtx_unlock(&sc->reg_lock); 4744 } 4745 4746 static void 4747 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 4748 { 4749 int i; 4750 u_int v, tnl_cong_drops; 4751 struct timeval tv; 4752 const struct timeval interval = {0, 250000}; /* 250ms */ 4753 4754 getmicrotime(&tv); 4755 timevalsub(&tv, &interval); 4756 if (timevalcmp(&tv, &pi->last_refreshed, <)) 4757 return; 4758 4759 tnl_cong_drops = 0; 4760 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 4761 for (i = 0; i < sc->chip_params->nchan; i++) { 4762 if (pi->rx_chan_map & (1 << i)) { 4763 mtx_lock(&sc->reg_lock); 4764 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 4765 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 4766 mtx_unlock(&sc->reg_lock); 4767 tnl_cong_drops += v; 4768 } 4769 } 4770 pi->tnl_cong_drops = tnl_cong_drops; 4771 getmicrotime(&pi->last_refreshed); 4772 } 4773 4774 static void 4775 cxgbe_tick(void *arg) 4776 { 4777 struct port_info *pi = arg; 4778 struct adapter *sc = pi->adapter; 4779 4780 PORT_LOCK_ASSERT_OWNED(pi); 4781 cxgbe_refresh_stats(sc, pi); 4782 4783 callout_schedule(&pi->tick, hz); 4784 } 4785 4786 void 4787 vi_tick(void *arg) 4788 { 4789 struct vi_info *vi = arg; 4790 struct adapter *sc = vi->pi->adapter; 4791 4792 vi_refresh_stats(sc, vi); 4793 4794 callout_schedule(&vi->tick, hz); 4795 } 4796 4797 static void 4798 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 4799 { 4800 struct ifnet *vlan; 4801 4802 if (arg != ifp || ifp->if_type != IFT_ETHER) 4803 return; 4804 4805 vlan = VLAN_DEVAT(ifp, vid); 4806 VLAN_SETCOOKIE(vlan, ifp); 4807 } 4808 4809 /* 4810 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 4811 */ 4812 static char *caps_decoder[] = { 4813 "\20\001IPMI\002NCSI", /* 0: NBM */ 4814 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 4815 "\20\001INGRESS\002EGRESS", /* 2: switch */ 4816 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 4817 "\006HASHFILTER\007ETHOFLD", 4818 "\20\001TOE", /* 4: TOE */ 4819 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 4820 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 4821 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 4822 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 4823 "\007T10DIF" 4824 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 4825 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 4826 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 4827 "\004PO_INITIATOR\005PO_TARGET", 4828 }; 4829 4830 void 4831 t4_sysctls(struct adapter *sc) 4832 { 4833 struct sysctl_ctx_list *ctx; 4834 struct sysctl_oid *oid; 4835 struct sysctl_oid_list *children, *c0; 4836 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 4837 4838 ctx = device_get_sysctl_ctx(sc->dev); 4839 4840 /* 4841 * dev.t4nex.X. 4842 */ 4843 oid = device_get_sysctl_tree(sc->dev); 4844 c0 = children = SYSCTL_CHILDREN(oid); 4845 4846 sc->sc_do_rxcopy = 1; 4847 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 4848 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 4849 4850 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 4851 sc->params.nports, "# of ports"); 4852 4853 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 4854 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, 4855 sysctl_bitfield, "A", "available doorbells"); 4856 4857 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 4858 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 4859 4860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 4861 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 4862 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 4863 "interrupt holdoff timer values (us)"); 4864 4865 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 4866 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 4867 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 4868 "interrupt holdoff packet counter values"); 4869 4870 t4_sge_sysctls(sc, ctx, children); 4871 4872 sc->lro_timeout = 100; 4873 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 4874 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 4875 4876 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 4877 &sc->debug_flags, 0, "flags to enable runtime debugging"); 4878 4879 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 4880 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 4881 4882 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 4883 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 4884 4885 if (sc->flags & IS_VF) 4886 return; 4887 4888 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 4889 NULL, chip_rev(sc), "chip hardware revision"); 4890 4891 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 4892 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 4893 4894 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 4895 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 4896 4897 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 4898 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 4899 4900 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 4901 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 4902 4903 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 4904 sc->er_version, 0, "expansion ROM version"); 4905 4906 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 4907 sc->bs_version, 0, "bootstrap firmware version"); 4908 4909 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 4910 NULL, sc->params.scfg_vers, "serial config version"); 4911 4912 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 4913 NULL, sc->params.vpd_vers, "VPD version"); 4914 4915 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 4916 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 4917 4918 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 4919 sc->cfcsum, "config file checksum"); 4920 4921 #define SYSCTL_CAP(name, n, text) \ 4922 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 4923 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \ 4924 sysctl_bitfield, "A", "available " text " capabilities") 4925 4926 SYSCTL_CAP(nbmcaps, 0, "NBM"); 4927 SYSCTL_CAP(linkcaps, 1, "link"); 4928 SYSCTL_CAP(switchcaps, 2, "switch"); 4929 SYSCTL_CAP(niccaps, 3, "NIC"); 4930 SYSCTL_CAP(toecaps, 4, "TCP offload"); 4931 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 4932 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 4933 SYSCTL_CAP(cryptocaps, 7, "crypto"); 4934 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 4935 #undef SYSCTL_CAP 4936 4937 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 4938 NULL, sc->tids.nftids, "number of filters"); 4939 4940 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 4941 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 4942 "chip temperature (in Celsius)"); 4943 4944 #ifdef SBUF_DRAIN 4945 /* 4946 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 4947 */ 4948 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 4949 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 4950 "logs and miscellaneous information"); 4951 children = SYSCTL_CHILDREN(oid); 4952 4953 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 4954 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4955 sysctl_cctrl, "A", "congestion control"); 4956 4957 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 4958 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4959 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 4960 4961 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 4962 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 4963 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 4964 4965 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 4966 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 4967 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 4968 4969 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 4970 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 4971 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 4972 4973 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 4974 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 4975 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 4976 4977 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 4978 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 4979 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 4980 4981 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 4982 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4983 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 4984 "A", "CIM logic analyzer"); 4985 4986 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 4987 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4988 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 4989 4990 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 4991 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 4992 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 4993 4994 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 4995 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 4996 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 4997 4998 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 4999 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 5000 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 5001 5002 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 5003 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 5004 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 5005 5006 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 5007 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 5008 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 5009 5010 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 5011 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 5012 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 5013 5014 if (chip_id(sc) > CHELSIO_T4) { 5015 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 5016 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 5017 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 5018 5019 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 5020 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 5021 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 5022 } 5023 5024 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 5025 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5026 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 5027 5028 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 5029 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5030 sysctl_cim_qcfg, "A", "CIM queue configuration"); 5031 5032 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 5033 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5034 sysctl_cpl_stats, "A", "CPL statistics"); 5035 5036 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 5037 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5038 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 5039 5040 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 5041 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5042 sysctl_devlog, "A", "firmware's device log"); 5043 5044 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 5045 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5046 sysctl_fcoe_stats, "A", "FCoE statistics"); 5047 5048 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 5049 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5050 sysctl_hw_sched, "A", "hardware scheduler "); 5051 5052 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 5053 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5054 sysctl_l2t, "A", "hardware L2 table"); 5055 5056 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 5057 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5058 sysctl_lb_stats, "A", "loopback statistics"); 5059 5060 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 5061 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5062 sysctl_meminfo, "A", "memory regions"); 5063 5064 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 5065 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5066 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 5067 "A", "MPS TCAM entries"); 5068 5069 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 5070 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5071 sysctl_path_mtus, "A", "path MTUs"); 5072 5073 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 5074 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5075 sysctl_pm_stats, "A", "PM statistics"); 5076 5077 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 5078 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5079 sysctl_rdma_stats, "A", "RDMA statistics"); 5080 5081 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 5082 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5083 sysctl_tcp_stats, "A", "TCP statistics"); 5084 5085 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 5086 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5087 sysctl_tids, "A", "TID information"); 5088 5089 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 5090 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5091 sysctl_tp_err_stats, "A", "TP error statistics"); 5092 5093 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 5094 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 5095 "TP logic analyzer event capture mask"); 5096 5097 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 5098 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5099 sysctl_tp_la, "A", "TP logic analyzer"); 5100 5101 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 5102 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5103 sysctl_tx_rate, "A", "Tx rate"); 5104 5105 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 5106 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5107 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 5108 5109 if (chip_id(sc) >= CHELSIO_T5) { 5110 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 5111 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5112 sysctl_wcwr_stats, "A", "write combined work requests"); 5113 } 5114 #endif 5115 5116 #ifdef TCP_OFFLOAD 5117 if (is_offload(sc)) { 5118 /* 5119 * dev.t4nex.X.toe. 5120 */ 5121 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 5122 NULL, "TOE parameters"); 5123 children = SYSCTL_CHILDREN(oid); 5124 5125 sc->tt.sndbuf = 256 * 1024; 5126 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 5127 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 5128 5129 sc->tt.ddp = 0; 5130 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 5131 &sc->tt.ddp, 0, "DDP allowed"); 5132 5133 sc->tt.rx_coalesce = 1; 5134 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 5135 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 5136 5137 sc->tt.tx_align = 1; 5138 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 5139 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 5140 5141 sc->tt.tx_zcopy = 0; 5142 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 5143 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 5144 "Enable zero-copy aio_write(2)"); 5145 5146 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 5147 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 5148 "TP timer tick (us)"); 5149 5150 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 5151 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 5152 "TCP timestamp tick (us)"); 5153 5154 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 5155 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 5156 "DACK tick (us)"); 5157 5158 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 5159 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 5160 "IU", "DACK timer (us)"); 5161 5162 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 5163 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 5164 sysctl_tp_timer, "LU", "Retransmit min (us)"); 5165 5166 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 5167 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 5168 sysctl_tp_timer, "LU", "Retransmit max (us)"); 5169 5170 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 5171 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 5172 sysctl_tp_timer, "LU", "Persist timer min (us)"); 5173 5174 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 5175 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 5176 sysctl_tp_timer, "LU", "Persist timer max (us)"); 5177 5178 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 5179 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 5180 sysctl_tp_timer, "LU", "Keepidle idle timer (us)"); 5181 5182 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl", 5183 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 5184 sysctl_tp_timer, "LU", "Keepidle interval (us)"); 5185 5186 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 5187 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 5188 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 5189 5190 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 5191 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 5192 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 5193 } 5194 #endif 5195 } 5196 5197 void 5198 vi_sysctls(struct vi_info *vi) 5199 { 5200 struct sysctl_ctx_list *ctx; 5201 struct sysctl_oid *oid; 5202 struct sysctl_oid_list *children; 5203 5204 ctx = device_get_sysctl_ctx(vi->dev); 5205 5206 /* 5207 * dev.v?(cxgbe|cxl).X. 5208 */ 5209 oid = device_get_sysctl_tree(vi->dev); 5210 children = SYSCTL_CHILDREN(oid); 5211 5212 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 5213 vi->viid, "VI identifer"); 5214 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 5215 &vi->nrxq, 0, "# of rx queues"); 5216 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 5217 &vi->ntxq, 0, "# of tx queues"); 5218 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 5219 &vi->first_rxq, 0, "index of first rx queue"); 5220 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 5221 &vi->first_txq, 0, "index of first tx queue"); 5222 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 5223 vi->rss_size, "size of RSS indirection table"); 5224 5225 if (IS_MAIN_VI(vi)) { 5226 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 5227 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 5228 "Reserve queue 0 for non-flowid packets"); 5229 } 5230 5231 #ifdef TCP_OFFLOAD 5232 if (vi->nofldrxq != 0) { 5233 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 5234 &vi->nofldrxq, 0, 5235 "# of rx queues for offloaded TCP connections"); 5236 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 5237 &vi->nofldtxq, 0, 5238 "# of tx queues for offloaded TCP connections"); 5239 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 5240 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 5241 "index of first TOE rx queue"); 5242 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 5243 CTLFLAG_RD, &vi->first_ofld_txq, 0, 5244 "index of first TOE tx queue"); 5245 } 5246 #endif 5247 #ifdef DEV_NETMAP 5248 if (vi->nnmrxq != 0) { 5249 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 5250 &vi->nnmrxq, 0, "# of netmap rx queues"); 5251 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 5252 &vi->nnmtxq, 0, "# of netmap tx queues"); 5253 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 5254 CTLFLAG_RD, &vi->first_nm_rxq, 0, 5255 "index of first netmap rx queue"); 5256 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 5257 CTLFLAG_RD, &vi->first_nm_txq, 0, 5258 "index of first netmap tx queue"); 5259 } 5260 #endif 5261 5262 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 5263 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 5264 "holdoff timer index"); 5265 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 5266 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 5267 "holdoff packet counter index"); 5268 5269 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 5270 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 5271 "rx queue size"); 5272 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 5273 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 5274 "tx queue size"); 5275 } 5276 5277 static void 5278 cxgbe_sysctls(struct port_info *pi) 5279 { 5280 struct sysctl_ctx_list *ctx; 5281 struct sysctl_oid *oid; 5282 struct sysctl_oid_list *children, *children2; 5283 struct adapter *sc = pi->adapter; 5284 int i; 5285 char name[16]; 5286 5287 ctx = device_get_sysctl_ctx(pi->dev); 5288 5289 /* 5290 * dev.cxgbe.X. 5291 */ 5292 oid = device_get_sysctl_tree(pi->dev); 5293 children = SYSCTL_CHILDREN(oid); 5294 5295 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 5296 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 5297 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 5298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 5299 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 5300 "PHY temperature (in Celsius)"); 5301 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 5302 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 5303 "PHY firmware version"); 5304 } 5305 5306 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 5307 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 5308 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)"); 5309 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 5310 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 5311 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 5312 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 5313 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 5314 "autonegotiation (-1 = not supported)"); 5315 5316 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 5317 port_top_speed(pi), "max speed (in Gbps)"); 5318 5319 if (sc->flags & IS_VF) 5320 return; 5321 5322 /* 5323 * dev.(cxgbe|cxl).X.tc. 5324 */ 5325 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 5326 "Tx scheduler traffic classes"); 5327 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 5328 struct tx_sched_class *tc = &pi->tc[i]; 5329 5330 snprintf(name, sizeof(name), "%d", i); 5331 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 5332 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 5333 "traffic class")); 5334 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD, 5335 &tc->flags, 0, "flags"); 5336 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 5337 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 5338 #ifdef SBUF_DRAIN 5339 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 5340 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 5341 sysctl_tc_params, "A", "traffic class parameters"); 5342 #endif 5343 } 5344 5345 /* 5346 * dev.cxgbe.X.stats. 5347 */ 5348 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 5349 NULL, "port statistics"); 5350 children = SYSCTL_CHILDREN(oid); 5351 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 5352 &pi->tx_parse_error, 0, 5353 "# of tx packets with invalid length or # of segments"); 5354 5355 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 5356 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 5357 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 5358 sysctl_handle_t4_reg64, "QU", desc) 5359 5360 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 5361 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 5362 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 5363 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 5364 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 5365 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 5366 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 5367 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 5368 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 5369 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 5370 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 5371 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 5372 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 5373 "# of tx frames in this range", 5374 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 5375 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 5376 "# of tx frames in this range", 5377 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 5378 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 5379 "# of tx frames in this range", 5380 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 5381 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 5382 "# of tx frames in this range", 5383 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 5384 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 5385 "# of tx frames in this range", 5386 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 5387 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 5388 "# of tx frames in this range", 5389 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 5390 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 5391 "# of tx frames in this range", 5392 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 5393 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 5394 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 5395 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 5396 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 5397 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 5398 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 5399 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 5400 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 5401 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 5402 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 5403 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 5404 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 5405 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 5406 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 5407 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 5408 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 5409 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 5410 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 5411 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 5412 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 5413 5414 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 5415 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 5416 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 5417 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 5418 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 5419 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 5420 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 5421 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 5422 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 5423 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 5424 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 5425 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 5426 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 5427 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 5428 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 5429 "# of frames received with bad FCS", 5430 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 5431 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 5432 "# of frames received with length error", 5433 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 5434 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 5435 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 5436 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 5437 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 5438 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 5439 "# of rx frames in this range", 5440 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 5441 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 5442 "# of rx frames in this range", 5443 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 5444 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 5445 "# of rx frames in this range", 5446 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 5447 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 5448 "# of rx frames in this range", 5449 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 5450 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 5451 "# of rx frames in this range", 5452 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 5453 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 5454 "# of rx frames in this range", 5455 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 5456 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 5457 "# of rx frames in this range", 5458 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 5459 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 5460 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 5461 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 5462 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 5463 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 5464 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 5465 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 5466 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 5467 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 5468 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 5469 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 5470 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 5471 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 5472 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 5473 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 5474 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 5475 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 5476 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 5477 5478 #undef SYSCTL_ADD_T4_REG64 5479 5480 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 5481 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 5482 &pi->stats.name, desc) 5483 5484 /* We get these from port_stats and they may be stale by up to 1s */ 5485 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 5486 "# drops due to buffer-group 0 overflows"); 5487 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 5488 "# drops due to buffer-group 1 overflows"); 5489 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 5490 "# drops due to buffer-group 2 overflows"); 5491 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 5492 "# drops due to buffer-group 3 overflows"); 5493 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 5494 "# of buffer-group 0 truncated packets"); 5495 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 5496 "# of buffer-group 1 truncated packets"); 5497 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 5498 "# of buffer-group 2 truncated packets"); 5499 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 5500 "# of buffer-group 3 truncated packets"); 5501 5502 #undef SYSCTL_ADD_T4_PORTSTAT 5503 } 5504 5505 static int 5506 sysctl_int_array(SYSCTL_HANDLER_ARGS) 5507 { 5508 int rc, *i, space = 0; 5509 struct sbuf sb; 5510 5511 sbuf_new_for_sysctl(&sb, NULL, 64, req); 5512 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 5513 if (space) 5514 sbuf_printf(&sb, " "); 5515 sbuf_printf(&sb, "%d", *i); 5516 space = 1; 5517 } 5518 rc = sbuf_finish(&sb); 5519 sbuf_delete(&sb); 5520 return (rc); 5521 } 5522 5523 static int 5524 sysctl_bitfield(SYSCTL_HANDLER_ARGS) 5525 { 5526 int rc; 5527 struct sbuf *sb; 5528 5529 rc = sysctl_wire_old_buffer(req, 0); 5530 if (rc != 0) 5531 return(rc); 5532 5533 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5534 if (sb == NULL) 5535 return (ENOMEM); 5536 5537 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1); 5538 rc = sbuf_finish(sb); 5539 sbuf_delete(sb); 5540 5541 return (rc); 5542 } 5543 5544 static int 5545 sysctl_btphy(SYSCTL_HANDLER_ARGS) 5546 { 5547 struct port_info *pi = arg1; 5548 int op = arg2; 5549 struct adapter *sc = pi->adapter; 5550 u_int v; 5551 int rc; 5552 5553 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 5554 if (rc) 5555 return (rc); 5556 /* XXX: magic numbers */ 5557 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 5558 &v); 5559 end_synchronized_op(sc, 0); 5560 if (rc) 5561 return (rc); 5562 if (op == 0) 5563 v /= 256; 5564 5565 rc = sysctl_handle_int(oidp, &v, 0, req); 5566 return (rc); 5567 } 5568 5569 static int 5570 sysctl_noflowq(SYSCTL_HANDLER_ARGS) 5571 { 5572 struct vi_info *vi = arg1; 5573 int rc, val; 5574 5575 val = vi->rsrv_noflowq; 5576 rc = sysctl_handle_int(oidp, &val, 0, req); 5577 if (rc != 0 || req->newptr == NULL) 5578 return (rc); 5579 5580 if ((val >= 1) && (vi->ntxq > 1)) 5581 vi->rsrv_noflowq = 1; 5582 else 5583 vi->rsrv_noflowq = 0; 5584 5585 return (rc); 5586 } 5587 5588 static int 5589 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 5590 { 5591 struct vi_info *vi = arg1; 5592 struct adapter *sc = vi->pi->adapter; 5593 int idx, rc, i; 5594 struct sge_rxq *rxq; 5595 #ifdef TCP_OFFLOAD 5596 struct sge_ofld_rxq *ofld_rxq; 5597 #endif 5598 uint8_t v; 5599 5600 idx = vi->tmr_idx; 5601 5602 rc = sysctl_handle_int(oidp, &idx, 0, req); 5603 if (rc != 0 || req->newptr == NULL) 5604 return (rc); 5605 5606 if (idx < 0 || idx >= SGE_NTIMERS) 5607 return (EINVAL); 5608 5609 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5610 "t4tmr"); 5611 if (rc) 5612 return (rc); 5613 5614 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 5615 for_each_rxq(vi, i, rxq) { 5616 #ifdef atomic_store_rel_8 5617 atomic_store_rel_8(&rxq->iq.intr_params, v); 5618 #else 5619 rxq->iq.intr_params = v; 5620 #endif 5621 } 5622 #ifdef TCP_OFFLOAD 5623 for_each_ofld_rxq(vi, i, ofld_rxq) { 5624 #ifdef atomic_store_rel_8 5625 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 5626 #else 5627 ofld_rxq->iq.intr_params = v; 5628 #endif 5629 } 5630 #endif 5631 vi->tmr_idx = idx; 5632 5633 end_synchronized_op(sc, LOCK_HELD); 5634 return (0); 5635 } 5636 5637 static int 5638 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 5639 { 5640 struct vi_info *vi = arg1; 5641 struct adapter *sc = vi->pi->adapter; 5642 int idx, rc; 5643 5644 idx = vi->pktc_idx; 5645 5646 rc = sysctl_handle_int(oidp, &idx, 0, req); 5647 if (rc != 0 || req->newptr == NULL) 5648 return (rc); 5649 5650 if (idx < -1 || idx >= SGE_NCOUNTERS) 5651 return (EINVAL); 5652 5653 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5654 "t4pktc"); 5655 if (rc) 5656 return (rc); 5657 5658 if (vi->flags & VI_INIT_DONE) 5659 rc = EBUSY; /* cannot be changed once the queues are created */ 5660 else 5661 vi->pktc_idx = idx; 5662 5663 end_synchronized_op(sc, LOCK_HELD); 5664 return (rc); 5665 } 5666 5667 static int 5668 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 5669 { 5670 struct vi_info *vi = arg1; 5671 struct adapter *sc = vi->pi->adapter; 5672 int qsize, rc; 5673 5674 qsize = vi->qsize_rxq; 5675 5676 rc = sysctl_handle_int(oidp, &qsize, 0, req); 5677 if (rc != 0 || req->newptr == NULL) 5678 return (rc); 5679 5680 if (qsize < 128 || (qsize & 7)) 5681 return (EINVAL); 5682 5683 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5684 "t4rxqs"); 5685 if (rc) 5686 return (rc); 5687 5688 if (vi->flags & VI_INIT_DONE) 5689 rc = EBUSY; /* cannot be changed once the queues are created */ 5690 else 5691 vi->qsize_rxq = qsize; 5692 5693 end_synchronized_op(sc, LOCK_HELD); 5694 return (rc); 5695 } 5696 5697 static int 5698 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 5699 { 5700 struct vi_info *vi = arg1; 5701 struct adapter *sc = vi->pi->adapter; 5702 int qsize, rc; 5703 5704 qsize = vi->qsize_txq; 5705 5706 rc = sysctl_handle_int(oidp, &qsize, 0, req); 5707 if (rc != 0 || req->newptr == NULL) 5708 return (rc); 5709 5710 if (qsize < 128 || qsize > 65536) 5711 return (EINVAL); 5712 5713 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5714 "t4txqs"); 5715 if (rc) 5716 return (rc); 5717 5718 if (vi->flags & VI_INIT_DONE) 5719 rc = EBUSY; /* cannot be changed once the queues are created */ 5720 else 5721 vi->qsize_txq = qsize; 5722 5723 end_synchronized_op(sc, LOCK_HELD); 5724 return (rc); 5725 } 5726 5727 static int 5728 sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 5729 { 5730 struct port_info *pi = arg1; 5731 struct adapter *sc = pi->adapter; 5732 struct link_config *lc = &pi->link_cfg; 5733 int rc; 5734 5735 if (req->newptr == NULL) { 5736 struct sbuf *sb; 5737 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX"; 5738 5739 rc = sysctl_wire_old_buffer(req, 0); 5740 if (rc != 0) 5741 return(rc); 5742 5743 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5744 if (sb == NULL) 5745 return (ENOMEM); 5746 5747 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits); 5748 rc = sbuf_finish(sb); 5749 sbuf_delete(sb); 5750 } else { 5751 char s[2]; 5752 int n; 5753 5754 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX)); 5755 s[1] = 0; 5756 5757 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 5758 if (rc != 0) 5759 return(rc); 5760 5761 if (s[1] != 0) 5762 return (EINVAL); 5763 if (s[0] < '0' || s[0] > '9') 5764 return (EINVAL); /* not a number */ 5765 n = s[0] - '0'; 5766 if (n & ~(PAUSE_TX | PAUSE_RX)) 5767 return (EINVAL); /* some other bit is set too */ 5768 5769 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 5770 "t4PAUSE"); 5771 if (rc) 5772 return (rc); 5773 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) { 5774 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 5775 lc->requested_fc |= n; 5776 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 5777 } 5778 end_synchronized_op(sc, 0); 5779 } 5780 5781 return (rc); 5782 } 5783 5784 static int 5785 sysctl_fec(SYSCTL_HANDLER_ARGS) 5786 { 5787 struct port_info *pi = arg1; 5788 struct adapter *sc = pi->adapter; 5789 struct link_config *lc = &pi->link_cfg; 5790 int rc; 5791 5792 if (req->newptr == NULL) { 5793 struct sbuf *sb; 5794 static char *bits = "\20\1RS\2BASER_RS\3RESERVED"; 5795 5796 rc = sysctl_wire_old_buffer(req, 0); 5797 if (rc != 0) 5798 return(rc); 5799 5800 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5801 if (sb == NULL) 5802 return (ENOMEM); 5803 5804 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits); 5805 rc = sbuf_finish(sb); 5806 sbuf_delete(sb); 5807 } else { 5808 char s[2]; 5809 int n; 5810 5811 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC); 5812 s[1] = 0; 5813 5814 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 5815 if (rc != 0) 5816 return(rc); 5817 5818 if (s[1] != 0) 5819 return (EINVAL); 5820 if (s[0] < '0' || s[0] > '9') 5821 return (EINVAL); /* not a number */ 5822 n = s[0] - '0'; 5823 if (n & ~M_FW_PORT_CAP_FEC) 5824 return (EINVAL); /* some other bit is set too */ 5825 5826 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 5827 "t4fec"); 5828 if (rc) 5829 return (rc); 5830 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) { 5831 lc->requested_fec = n & 5832 G_FW_PORT_CAP_FEC(lc->supported); 5833 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 5834 } 5835 end_synchronized_op(sc, 0); 5836 } 5837 5838 return (rc); 5839 } 5840 5841 static int 5842 sysctl_autoneg(SYSCTL_HANDLER_ARGS) 5843 { 5844 struct port_info *pi = arg1; 5845 struct adapter *sc = pi->adapter; 5846 struct link_config *lc = &pi->link_cfg; 5847 int rc, val, old; 5848 5849 if (lc->supported & FW_PORT_CAP_ANEG) 5850 val = lc->autoneg == AUTONEG_ENABLE ? 1 : 0; 5851 else 5852 val = -1; 5853 rc = sysctl_handle_int(oidp, &val, 0, req); 5854 if (rc != 0 || req->newptr == NULL) 5855 return (rc); 5856 if ((lc->supported & FW_PORT_CAP_ANEG) == 0) 5857 return (ENOTSUP); 5858 5859 val = val ? AUTONEG_ENABLE : AUTONEG_DISABLE; 5860 if (lc->autoneg == val) 5861 return (0); /* no change */ 5862 5863 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 5864 "t4aneg"); 5865 if (rc) 5866 return (rc); 5867 old = lc->autoneg; 5868 lc->autoneg = val; 5869 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 5870 if (rc != 0) 5871 lc->autoneg = old; 5872 return (rc); 5873 } 5874 5875 static int 5876 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 5877 { 5878 struct adapter *sc = arg1; 5879 int reg = arg2; 5880 uint64_t val; 5881 5882 val = t4_read_reg64(sc, reg); 5883 5884 return (sysctl_handle_64(oidp, &val, 0, req)); 5885 } 5886 5887 static int 5888 sysctl_temperature(SYSCTL_HANDLER_ARGS) 5889 { 5890 struct adapter *sc = arg1; 5891 int rc, t; 5892 uint32_t param, val; 5893 5894 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 5895 if (rc) 5896 return (rc); 5897 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5898 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5899 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 5900 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5901 end_synchronized_op(sc, 0); 5902 if (rc) 5903 return (rc); 5904 5905 /* unknown is returned as 0 but we display -1 in that case */ 5906 t = val == 0 ? -1 : val; 5907 5908 rc = sysctl_handle_int(oidp, &t, 0, req); 5909 return (rc); 5910 } 5911 5912 #ifdef SBUF_DRAIN 5913 static int 5914 sysctl_cctrl(SYSCTL_HANDLER_ARGS) 5915 { 5916 struct adapter *sc = arg1; 5917 struct sbuf *sb; 5918 int rc, i; 5919 uint16_t incr[NMTUS][NCCTRL_WIN]; 5920 static const char *dec_fac[] = { 5921 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 5922 "0.9375" 5923 }; 5924 5925 rc = sysctl_wire_old_buffer(req, 0); 5926 if (rc != 0) 5927 return (rc); 5928 5929 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5930 if (sb == NULL) 5931 return (ENOMEM); 5932 5933 t4_read_cong_tbl(sc, incr); 5934 5935 for (i = 0; i < NCCTRL_WIN; ++i) { 5936 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 5937 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 5938 incr[5][i], incr[6][i], incr[7][i]); 5939 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 5940 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 5941 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 5942 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 5943 } 5944 5945 rc = sbuf_finish(sb); 5946 sbuf_delete(sb); 5947 5948 return (rc); 5949 } 5950 5951 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 5952 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 5953 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 5954 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 5955 }; 5956 5957 static int 5958 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 5959 { 5960 struct adapter *sc = arg1; 5961 struct sbuf *sb; 5962 int rc, i, n, qid = arg2; 5963 uint32_t *buf, *p; 5964 char *qtype; 5965 u_int cim_num_obq = sc->chip_params->cim_num_obq; 5966 5967 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 5968 ("%s: bad qid %d\n", __func__, qid)); 5969 5970 if (qid < CIM_NUM_IBQ) { 5971 /* inbound queue */ 5972 qtype = "IBQ"; 5973 n = 4 * CIM_IBQ_SIZE; 5974 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 5975 rc = t4_read_cim_ibq(sc, qid, buf, n); 5976 } else { 5977 /* outbound queue */ 5978 qtype = "OBQ"; 5979 qid -= CIM_NUM_IBQ; 5980 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 5981 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 5982 rc = t4_read_cim_obq(sc, qid, buf, n); 5983 } 5984 5985 if (rc < 0) { 5986 rc = -rc; 5987 goto done; 5988 } 5989 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 5990 5991 rc = sysctl_wire_old_buffer(req, 0); 5992 if (rc != 0) 5993 goto done; 5994 5995 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 5996 if (sb == NULL) { 5997 rc = ENOMEM; 5998 goto done; 5999 } 6000 6001 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 6002 for (i = 0, p = buf; i < n; i += 16, p += 4) 6003 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 6004 p[2], p[3]); 6005 6006 rc = sbuf_finish(sb); 6007 sbuf_delete(sb); 6008 done: 6009 free(buf, M_CXGBE); 6010 return (rc); 6011 } 6012 6013 static int 6014 sysctl_cim_la(SYSCTL_HANDLER_ARGS) 6015 { 6016 struct adapter *sc = arg1; 6017 u_int cfg; 6018 struct sbuf *sb; 6019 uint32_t *buf, *p; 6020 int rc; 6021 6022 MPASS(chip_id(sc) <= CHELSIO_T5); 6023 6024 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6025 if (rc != 0) 6026 return (rc); 6027 6028 rc = sysctl_wire_old_buffer(req, 0); 6029 if (rc != 0) 6030 return (rc); 6031 6032 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6033 if (sb == NULL) 6034 return (ENOMEM); 6035 6036 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6037 M_ZERO | M_WAITOK); 6038 6039 rc = -t4_cim_read_la(sc, buf, NULL); 6040 if (rc != 0) 6041 goto done; 6042 6043 sbuf_printf(sb, "Status Data PC%s", 6044 cfg & F_UPDBGLACAPTPCONLY ? "" : 6045 " LS0Stat LS0Addr LS0Data"); 6046 6047 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 6048 if (cfg & F_UPDBGLACAPTPCONLY) { 6049 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 6050 p[6], p[7]); 6051 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 6052 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 6053 p[4] & 0xff, p[5] >> 8); 6054 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 6055 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6056 p[1] & 0xf, p[2] >> 4); 6057 } else { 6058 sbuf_printf(sb, 6059 "\n %02x %x%07x %x%07x %08x %08x " 6060 "%08x%08x%08x%08x", 6061 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6062 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 6063 p[6], p[7]); 6064 } 6065 } 6066 6067 rc = sbuf_finish(sb); 6068 sbuf_delete(sb); 6069 done: 6070 free(buf, M_CXGBE); 6071 return (rc); 6072 } 6073 6074 static int 6075 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 6076 { 6077 struct adapter *sc = arg1; 6078 u_int cfg; 6079 struct sbuf *sb; 6080 uint32_t *buf, *p; 6081 int rc; 6082 6083 MPASS(chip_id(sc) > CHELSIO_T5); 6084 6085 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6086 if (rc != 0) 6087 return (rc); 6088 6089 rc = sysctl_wire_old_buffer(req, 0); 6090 if (rc != 0) 6091 return (rc); 6092 6093 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6094 if (sb == NULL) 6095 return (ENOMEM); 6096 6097 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6098 M_ZERO | M_WAITOK); 6099 6100 rc = -t4_cim_read_la(sc, buf, NULL); 6101 if (rc != 0) 6102 goto done; 6103 6104 sbuf_printf(sb, "Status Inst Data PC%s", 6105 cfg & F_UPDBGLACAPTPCONLY ? "" : 6106 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 6107 6108 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 6109 if (cfg & F_UPDBGLACAPTPCONLY) { 6110 sbuf_printf(sb, "\n %02x %08x %08x %08x", 6111 p[3] & 0xff, p[2], p[1], p[0]); 6112 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 6113 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 6114 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 6115 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 6116 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 6117 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 6118 p[6] >> 16); 6119 } else { 6120 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 6121 "%08x %08x %08x %08x %08x %08x", 6122 (p[9] >> 16) & 0xff, 6123 p[9] & 0xffff, p[8] >> 16, 6124 p[8] & 0xffff, p[7] >> 16, 6125 p[7] & 0xffff, p[6] >> 16, 6126 p[2], p[1], p[0], p[5], p[4], p[3]); 6127 } 6128 } 6129 6130 rc = sbuf_finish(sb); 6131 sbuf_delete(sb); 6132 done: 6133 free(buf, M_CXGBE); 6134 return (rc); 6135 } 6136 6137 static int 6138 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 6139 { 6140 struct adapter *sc = arg1; 6141 u_int i; 6142 struct sbuf *sb; 6143 uint32_t *buf, *p; 6144 int rc; 6145 6146 rc = sysctl_wire_old_buffer(req, 0); 6147 if (rc != 0) 6148 return (rc); 6149 6150 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6151 if (sb == NULL) 6152 return (ENOMEM); 6153 6154 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 6155 M_ZERO | M_WAITOK); 6156 6157 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 6158 p = buf; 6159 6160 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6161 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 6162 p[1], p[0]); 6163 } 6164 6165 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 6166 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6167 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 6168 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 6169 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 6170 (p[1] >> 2) | ((p[2] & 3) << 30), 6171 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 6172 p[0] & 1); 6173 } 6174 6175 rc = sbuf_finish(sb); 6176 sbuf_delete(sb); 6177 free(buf, M_CXGBE); 6178 return (rc); 6179 } 6180 6181 static int 6182 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 6183 { 6184 struct adapter *sc = arg1; 6185 u_int i; 6186 struct sbuf *sb; 6187 uint32_t *buf, *p; 6188 int rc; 6189 6190 rc = sysctl_wire_old_buffer(req, 0); 6191 if (rc != 0) 6192 return (rc); 6193 6194 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6195 if (sb == NULL) 6196 return (ENOMEM); 6197 6198 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 6199 M_ZERO | M_WAITOK); 6200 6201 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 6202 p = buf; 6203 6204 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 6205 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6206 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 6207 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 6208 p[4], p[3], p[2], p[1], p[0]); 6209 } 6210 6211 sbuf_printf(sb, "\n\nCntl ID Data"); 6212 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6213 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 6214 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 6215 } 6216 6217 rc = sbuf_finish(sb); 6218 sbuf_delete(sb); 6219 free(buf, M_CXGBE); 6220 return (rc); 6221 } 6222 6223 static int 6224 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 6225 { 6226 struct adapter *sc = arg1; 6227 struct sbuf *sb; 6228 int rc, i; 6229 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6230 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6231 uint16_t thres[CIM_NUM_IBQ]; 6232 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 6233 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 6234 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 6235 6236 cim_num_obq = sc->chip_params->cim_num_obq; 6237 if (is_t4(sc)) { 6238 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 6239 obq_rdaddr = A_UP_OBQ_0_REALADDR; 6240 } else { 6241 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 6242 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 6243 } 6244 nq = CIM_NUM_IBQ + cim_num_obq; 6245 6246 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 6247 if (rc == 0) 6248 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 6249 if (rc != 0) 6250 return (rc); 6251 6252 t4_read_cimq_cfg(sc, base, size, thres); 6253 6254 rc = sysctl_wire_old_buffer(req, 0); 6255 if (rc != 0) 6256 return (rc); 6257 6258 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6259 if (sb == NULL) 6260 return (ENOMEM); 6261 6262 sbuf_printf(sb, 6263 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 6264 6265 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 6266 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 6267 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 6268 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6269 G_QUEREMFLITS(p[2]) * 16); 6270 for ( ; i < nq; i++, p += 4, wr += 2) 6271 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 6272 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 6273 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6274 G_QUEREMFLITS(p[2]) * 16); 6275 6276 rc = sbuf_finish(sb); 6277 sbuf_delete(sb); 6278 6279 return (rc); 6280 } 6281 6282 static int 6283 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 6284 { 6285 struct adapter *sc = arg1; 6286 struct sbuf *sb; 6287 int rc; 6288 struct tp_cpl_stats stats; 6289 6290 rc = sysctl_wire_old_buffer(req, 0); 6291 if (rc != 0) 6292 return (rc); 6293 6294 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6295 if (sb == NULL) 6296 return (ENOMEM); 6297 6298 mtx_lock(&sc->reg_lock); 6299 t4_tp_get_cpl_stats(sc, &stats); 6300 mtx_unlock(&sc->reg_lock); 6301 6302 if (sc->chip_params->nchan > 2) { 6303 sbuf_printf(sb, " channel 0 channel 1" 6304 " channel 2 channel 3"); 6305 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 6306 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 6307 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 6308 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 6309 } else { 6310 sbuf_printf(sb, " channel 0 channel 1"); 6311 sbuf_printf(sb, "\nCPL requests: %10u %10u", 6312 stats.req[0], stats.req[1]); 6313 sbuf_printf(sb, "\nCPL responses: %10u %10u", 6314 stats.rsp[0], stats.rsp[1]); 6315 } 6316 6317 rc = sbuf_finish(sb); 6318 sbuf_delete(sb); 6319 6320 return (rc); 6321 } 6322 6323 static int 6324 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 6325 { 6326 struct adapter *sc = arg1; 6327 struct sbuf *sb; 6328 int rc; 6329 struct tp_usm_stats stats; 6330 6331 rc = sysctl_wire_old_buffer(req, 0); 6332 if (rc != 0) 6333 return(rc); 6334 6335 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6336 if (sb == NULL) 6337 return (ENOMEM); 6338 6339 t4_get_usm_stats(sc, &stats); 6340 6341 sbuf_printf(sb, "Frames: %u\n", stats.frames); 6342 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 6343 sbuf_printf(sb, "Drops: %u", stats.drops); 6344 6345 rc = sbuf_finish(sb); 6346 sbuf_delete(sb); 6347 6348 return (rc); 6349 } 6350 6351 static const char * const devlog_level_strings[] = { 6352 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 6353 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 6354 [FW_DEVLOG_LEVEL_ERR] = "ERR", 6355 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 6356 [FW_DEVLOG_LEVEL_INFO] = "INFO", 6357 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 6358 }; 6359 6360 static const char * const devlog_facility_strings[] = { 6361 [FW_DEVLOG_FACILITY_CORE] = "CORE", 6362 [FW_DEVLOG_FACILITY_CF] = "CF", 6363 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 6364 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 6365 [FW_DEVLOG_FACILITY_RES] = "RES", 6366 [FW_DEVLOG_FACILITY_HW] = "HW", 6367 [FW_DEVLOG_FACILITY_FLR] = "FLR", 6368 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 6369 [FW_DEVLOG_FACILITY_PHY] = "PHY", 6370 [FW_DEVLOG_FACILITY_MAC] = "MAC", 6371 [FW_DEVLOG_FACILITY_PORT] = "PORT", 6372 [FW_DEVLOG_FACILITY_VI] = "VI", 6373 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 6374 [FW_DEVLOG_FACILITY_ACL] = "ACL", 6375 [FW_DEVLOG_FACILITY_TM] = "TM", 6376 [FW_DEVLOG_FACILITY_QFC] = "QFC", 6377 [FW_DEVLOG_FACILITY_DCB] = "DCB", 6378 [FW_DEVLOG_FACILITY_ETH] = "ETH", 6379 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 6380 [FW_DEVLOG_FACILITY_RI] = "RI", 6381 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 6382 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 6383 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 6384 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 6385 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 6386 }; 6387 6388 static int 6389 sysctl_devlog(SYSCTL_HANDLER_ARGS) 6390 { 6391 struct adapter *sc = arg1; 6392 struct devlog_params *dparams = &sc->params.devlog; 6393 struct fw_devlog_e *buf, *e; 6394 int i, j, rc, nentries, first = 0; 6395 struct sbuf *sb; 6396 uint64_t ftstamp = UINT64_MAX; 6397 6398 if (dparams->addr == 0) 6399 return (ENXIO); 6400 6401 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 6402 if (buf == NULL) 6403 return (ENOMEM); 6404 6405 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 6406 if (rc != 0) 6407 goto done; 6408 6409 nentries = dparams->size / sizeof(struct fw_devlog_e); 6410 for (i = 0; i < nentries; i++) { 6411 e = &buf[i]; 6412 6413 if (e->timestamp == 0) 6414 break; /* end */ 6415 6416 e->timestamp = be64toh(e->timestamp); 6417 e->seqno = be32toh(e->seqno); 6418 for (j = 0; j < 8; j++) 6419 e->params[j] = be32toh(e->params[j]); 6420 6421 if (e->timestamp < ftstamp) { 6422 ftstamp = e->timestamp; 6423 first = i; 6424 } 6425 } 6426 6427 if (buf[first].timestamp == 0) 6428 goto done; /* nothing in the log */ 6429 6430 rc = sysctl_wire_old_buffer(req, 0); 6431 if (rc != 0) 6432 goto done; 6433 6434 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6435 if (sb == NULL) { 6436 rc = ENOMEM; 6437 goto done; 6438 } 6439 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 6440 "Seq#", "Tstamp", "Level", "Facility", "Message"); 6441 6442 i = first; 6443 do { 6444 e = &buf[i]; 6445 if (e->timestamp == 0) 6446 break; /* end */ 6447 6448 sbuf_printf(sb, "%10d %15ju %8s %8s ", 6449 e->seqno, e->timestamp, 6450 (e->level < nitems(devlog_level_strings) ? 6451 devlog_level_strings[e->level] : "UNKNOWN"), 6452 (e->facility < nitems(devlog_facility_strings) ? 6453 devlog_facility_strings[e->facility] : "UNKNOWN")); 6454 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 6455 e->params[2], e->params[3], e->params[4], 6456 e->params[5], e->params[6], e->params[7]); 6457 6458 if (++i == nentries) 6459 i = 0; 6460 } while (i != first); 6461 6462 rc = sbuf_finish(sb); 6463 sbuf_delete(sb); 6464 done: 6465 free(buf, M_CXGBE); 6466 return (rc); 6467 } 6468 6469 static int 6470 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 6471 { 6472 struct adapter *sc = arg1; 6473 struct sbuf *sb; 6474 int rc; 6475 struct tp_fcoe_stats stats[MAX_NCHAN]; 6476 int i, nchan = sc->chip_params->nchan; 6477 6478 rc = sysctl_wire_old_buffer(req, 0); 6479 if (rc != 0) 6480 return (rc); 6481 6482 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6483 if (sb == NULL) 6484 return (ENOMEM); 6485 6486 for (i = 0; i < nchan; i++) 6487 t4_get_fcoe_stats(sc, i, &stats[i]); 6488 6489 if (nchan > 2) { 6490 sbuf_printf(sb, " channel 0 channel 1" 6491 " channel 2 channel 3"); 6492 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 6493 stats[0].octets_ddp, stats[1].octets_ddp, 6494 stats[2].octets_ddp, stats[3].octets_ddp); 6495 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 6496 stats[0].frames_ddp, stats[1].frames_ddp, 6497 stats[2].frames_ddp, stats[3].frames_ddp); 6498 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 6499 stats[0].frames_drop, stats[1].frames_drop, 6500 stats[2].frames_drop, stats[3].frames_drop); 6501 } else { 6502 sbuf_printf(sb, " channel 0 channel 1"); 6503 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 6504 stats[0].octets_ddp, stats[1].octets_ddp); 6505 sbuf_printf(sb, "\nframesDDP: %16u %16u", 6506 stats[0].frames_ddp, stats[1].frames_ddp); 6507 sbuf_printf(sb, "\nframesDrop: %16u %16u", 6508 stats[0].frames_drop, stats[1].frames_drop); 6509 } 6510 6511 rc = sbuf_finish(sb); 6512 sbuf_delete(sb); 6513 6514 return (rc); 6515 } 6516 6517 static int 6518 sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 6519 { 6520 struct adapter *sc = arg1; 6521 struct sbuf *sb; 6522 int rc, i; 6523 unsigned int map, kbps, ipg, mode; 6524 unsigned int pace_tab[NTX_SCHED]; 6525 6526 rc = sysctl_wire_old_buffer(req, 0); 6527 if (rc != 0) 6528 return (rc); 6529 6530 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6531 if (sb == NULL) 6532 return (ENOMEM); 6533 6534 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 6535 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 6536 t4_read_pace_tbl(sc, pace_tab); 6537 6538 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 6539 "Class IPG (0.1 ns) Flow IPG (us)"); 6540 6541 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 6542 t4_get_tx_sched(sc, i, &kbps, &ipg); 6543 sbuf_printf(sb, "\n %u %-5s %u ", i, 6544 (mode & (1 << i)) ? "flow" : "class", map & 3); 6545 if (kbps) 6546 sbuf_printf(sb, "%9u ", kbps); 6547 else 6548 sbuf_printf(sb, " disabled "); 6549 6550 if (ipg) 6551 sbuf_printf(sb, "%13u ", ipg); 6552 else 6553 sbuf_printf(sb, " disabled "); 6554 6555 if (pace_tab[i]) 6556 sbuf_printf(sb, "%10u", pace_tab[i]); 6557 else 6558 sbuf_printf(sb, " disabled"); 6559 } 6560 6561 rc = sbuf_finish(sb); 6562 sbuf_delete(sb); 6563 6564 return (rc); 6565 } 6566 6567 static int 6568 sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 6569 { 6570 struct adapter *sc = arg1; 6571 struct sbuf *sb; 6572 int rc, i, j; 6573 uint64_t *p0, *p1; 6574 struct lb_port_stats s[2]; 6575 static const char *stat_name[] = { 6576 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 6577 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 6578 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 6579 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 6580 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 6581 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 6582 "BG2FramesTrunc:", "BG3FramesTrunc:" 6583 }; 6584 6585 rc = sysctl_wire_old_buffer(req, 0); 6586 if (rc != 0) 6587 return (rc); 6588 6589 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6590 if (sb == NULL) 6591 return (ENOMEM); 6592 6593 memset(s, 0, sizeof(s)); 6594 6595 for (i = 0; i < sc->chip_params->nchan; i += 2) { 6596 t4_get_lb_stats(sc, i, &s[0]); 6597 t4_get_lb_stats(sc, i + 1, &s[1]); 6598 6599 p0 = &s[0].octets; 6600 p1 = &s[1].octets; 6601 sbuf_printf(sb, "%s Loopback %u" 6602 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 6603 6604 for (j = 0; j < nitems(stat_name); j++) 6605 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 6606 *p0++, *p1++); 6607 } 6608 6609 rc = sbuf_finish(sb); 6610 sbuf_delete(sb); 6611 6612 return (rc); 6613 } 6614 6615 static int 6616 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 6617 { 6618 int rc = 0; 6619 struct port_info *pi = arg1; 6620 struct link_config *lc = &pi->link_cfg; 6621 struct sbuf *sb; 6622 6623 rc = sysctl_wire_old_buffer(req, 0); 6624 if (rc != 0) 6625 return(rc); 6626 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 6627 if (sb == NULL) 6628 return (ENOMEM); 6629 6630 if (lc->link_ok || lc->link_down_rc == 255) 6631 sbuf_printf(sb, "n/a"); 6632 else 6633 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 6634 6635 rc = sbuf_finish(sb); 6636 sbuf_delete(sb); 6637 6638 return (rc); 6639 } 6640 6641 struct mem_desc { 6642 unsigned int base; 6643 unsigned int limit; 6644 unsigned int idx; 6645 }; 6646 6647 static int 6648 mem_desc_cmp(const void *a, const void *b) 6649 { 6650 return ((const struct mem_desc *)a)->base - 6651 ((const struct mem_desc *)b)->base; 6652 } 6653 6654 static void 6655 mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 6656 unsigned int to) 6657 { 6658 unsigned int size; 6659 6660 if (from == to) 6661 return; 6662 6663 size = to - from + 1; 6664 if (size == 0) 6665 return; 6666 6667 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 6668 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 6669 } 6670 6671 static int 6672 sysctl_meminfo(SYSCTL_HANDLER_ARGS) 6673 { 6674 struct adapter *sc = arg1; 6675 struct sbuf *sb; 6676 int rc, i, n; 6677 uint32_t lo, hi, used, alloc; 6678 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 6679 static const char *region[] = { 6680 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 6681 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 6682 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 6683 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 6684 "RQUDP region:", "PBL region:", "TXPBL region:", 6685 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 6686 "On-chip queues:" 6687 }; 6688 struct mem_desc avail[4]; 6689 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 6690 struct mem_desc *md = mem; 6691 6692 rc = sysctl_wire_old_buffer(req, 0); 6693 if (rc != 0) 6694 return (rc); 6695 6696 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6697 if (sb == NULL) 6698 return (ENOMEM); 6699 6700 for (i = 0; i < nitems(mem); i++) { 6701 mem[i].limit = 0; 6702 mem[i].idx = i; 6703 } 6704 6705 /* Find and sort the populated memory ranges */ 6706 i = 0; 6707 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 6708 if (lo & F_EDRAM0_ENABLE) { 6709 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 6710 avail[i].base = G_EDRAM0_BASE(hi) << 20; 6711 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 6712 avail[i].idx = 0; 6713 i++; 6714 } 6715 if (lo & F_EDRAM1_ENABLE) { 6716 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 6717 avail[i].base = G_EDRAM1_BASE(hi) << 20; 6718 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 6719 avail[i].idx = 1; 6720 i++; 6721 } 6722 if (lo & F_EXT_MEM_ENABLE) { 6723 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 6724 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 6725 avail[i].limit = avail[i].base + 6726 (G_EXT_MEM_SIZE(hi) << 20); 6727 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 6728 i++; 6729 } 6730 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 6731 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 6732 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 6733 avail[i].limit = avail[i].base + 6734 (G_EXT_MEM1_SIZE(hi) << 20); 6735 avail[i].idx = 4; 6736 i++; 6737 } 6738 if (!i) /* no memory available */ 6739 return 0; 6740 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 6741 6742 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 6743 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 6744 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 6745 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 6746 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 6747 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 6748 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 6749 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 6750 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 6751 6752 /* the next few have explicit upper bounds */ 6753 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 6754 md->limit = md->base - 1 + 6755 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 6756 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 6757 md++; 6758 6759 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 6760 md->limit = md->base - 1 + 6761 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 6762 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 6763 md++; 6764 6765 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 6766 if (chip_id(sc) <= CHELSIO_T5) 6767 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 6768 else 6769 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 6770 md->limit = 0; 6771 } else { 6772 md->base = 0; 6773 md->idx = nitems(region); /* hide it */ 6774 } 6775 md++; 6776 6777 #define ulp_region(reg) \ 6778 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 6779 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 6780 6781 ulp_region(RX_ISCSI); 6782 ulp_region(RX_TDDP); 6783 ulp_region(TX_TPT); 6784 ulp_region(RX_STAG); 6785 ulp_region(RX_RQ); 6786 ulp_region(RX_RQUDP); 6787 ulp_region(RX_PBL); 6788 ulp_region(TX_PBL); 6789 #undef ulp_region 6790 6791 md->base = 0; 6792 md->idx = nitems(region); 6793 if (!is_t4(sc)) { 6794 uint32_t size = 0; 6795 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 6796 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 6797 6798 if (is_t5(sc)) { 6799 if (sge_ctrl & F_VFIFO_ENABLE) 6800 size = G_DBVFIFO_SIZE(fifo_size); 6801 } else 6802 size = G_T6_DBVFIFO_SIZE(fifo_size); 6803 6804 if (size) { 6805 md->base = G_BASEADDR(t4_read_reg(sc, 6806 A_SGE_DBVFIFO_BADDR)); 6807 md->limit = md->base + (size << 2) - 1; 6808 } 6809 } 6810 md++; 6811 6812 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 6813 md->limit = 0; 6814 md++; 6815 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 6816 md->limit = 0; 6817 md++; 6818 6819 md->base = sc->vres.ocq.start; 6820 if (sc->vres.ocq.size) 6821 md->limit = md->base + sc->vres.ocq.size - 1; 6822 else 6823 md->idx = nitems(region); /* hide it */ 6824 md++; 6825 6826 /* add any address-space holes, there can be up to 3 */ 6827 for (n = 0; n < i - 1; n++) 6828 if (avail[n].limit < avail[n + 1].base) 6829 (md++)->base = avail[n].limit; 6830 if (avail[n].limit) 6831 (md++)->base = avail[n].limit; 6832 6833 n = md - mem; 6834 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 6835 6836 for (lo = 0; lo < i; lo++) 6837 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 6838 avail[lo].limit - 1); 6839 6840 sbuf_printf(sb, "\n"); 6841 for (i = 0; i < n; i++) { 6842 if (mem[i].idx >= nitems(region)) 6843 continue; /* skip holes */ 6844 if (!mem[i].limit) 6845 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 6846 mem_region_show(sb, region[mem[i].idx], mem[i].base, 6847 mem[i].limit); 6848 } 6849 6850 sbuf_printf(sb, "\n"); 6851 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 6852 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 6853 mem_region_show(sb, "uP RAM:", lo, hi); 6854 6855 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 6856 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 6857 mem_region_show(sb, "uP Extmem2:", lo, hi); 6858 6859 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 6860 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 6861 G_PMRXMAXPAGE(lo), 6862 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 6863 (lo & F_PMRXNUMCHN) ? 2 : 1); 6864 6865 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 6866 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 6867 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 6868 G_PMTXMAXPAGE(lo), 6869 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 6870 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 6871 sbuf_printf(sb, "%u p-structs\n", 6872 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 6873 6874 for (i = 0; i < 4; i++) { 6875 if (chip_id(sc) > CHELSIO_T5) 6876 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 6877 else 6878 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 6879 if (is_t5(sc)) { 6880 used = G_T5_USED(lo); 6881 alloc = G_T5_ALLOC(lo); 6882 } else { 6883 used = G_USED(lo); 6884 alloc = G_ALLOC(lo); 6885 } 6886 /* For T6 these are MAC buffer groups */ 6887 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 6888 i, used, alloc); 6889 } 6890 for (i = 0; i < sc->chip_params->nchan; i++) { 6891 if (chip_id(sc) > CHELSIO_T5) 6892 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 6893 else 6894 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 6895 if (is_t5(sc)) { 6896 used = G_T5_USED(lo); 6897 alloc = G_T5_ALLOC(lo); 6898 } else { 6899 used = G_USED(lo); 6900 alloc = G_ALLOC(lo); 6901 } 6902 /* For T6 these are MAC buffer groups */ 6903 sbuf_printf(sb, 6904 "\nLoopback %d using %u pages out of %u allocated", 6905 i, used, alloc); 6906 } 6907 6908 rc = sbuf_finish(sb); 6909 sbuf_delete(sb); 6910 6911 return (rc); 6912 } 6913 6914 static inline void 6915 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 6916 { 6917 *mask = x | y; 6918 y = htobe64(y); 6919 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 6920 } 6921 6922 static int 6923 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 6924 { 6925 struct adapter *sc = arg1; 6926 struct sbuf *sb; 6927 int rc, i; 6928 6929 MPASS(chip_id(sc) <= CHELSIO_T5); 6930 6931 rc = sysctl_wire_old_buffer(req, 0); 6932 if (rc != 0) 6933 return (rc); 6934 6935 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6936 if (sb == NULL) 6937 return (ENOMEM); 6938 6939 sbuf_printf(sb, 6940 "Idx Ethernet address Mask Vld Ports PF" 6941 " VF Replication P0 P1 P2 P3 ML"); 6942 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 6943 uint64_t tcamx, tcamy, mask; 6944 uint32_t cls_lo, cls_hi; 6945 uint8_t addr[ETHER_ADDR_LEN]; 6946 6947 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 6948 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 6949 if (tcamx & tcamy) 6950 continue; 6951 tcamxy2valmask(tcamx, tcamy, addr, &mask); 6952 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 6953 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 6954 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 6955 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 6956 addr[3], addr[4], addr[5], (uintmax_t)mask, 6957 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 6958 G_PORTMAP(cls_hi), G_PF(cls_lo), 6959 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 6960 6961 if (cls_lo & F_REPLICATE) { 6962 struct fw_ldst_cmd ldst_cmd; 6963 6964 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 6965 ldst_cmd.op_to_addrspace = 6966 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 6967 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6968 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 6969 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 6970 ldst_cmd.u.mps.rplc.fid_idx = 6971 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 6972 V_FW_LDST_CMD_IDX(i)); 6973 6974 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 6975 "t4mps"); 6976 if (rc) 6977 break; 6978 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 6979 sizeof(ldst_cmd), &ldst_cmd); 6980 end_synchronized_op(sc, 0); 6981 6982 if (rc != 0) { 6983 sbuf_printf(sb, "%36d", rc); 6984 rc = 0; 6985 } else { 6986 sbuf_printf(sb, " %08x %08x %08x %08x", 6987 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 6988 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 6989 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 6990 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 6991 } 6992 } else 6993 sbuf_printf(sb, "%36s", ""); 6994 6995 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 6996 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 6997 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 6998 } 6999 7000 if (rc) 7001 (void) sbuf_finish(sb); 7002 else 7003 rc = sbuf_finish(sb); 7004 sbuf_delete(sb); 7005 7006 return (rc); 7007 } 7008 7009 static int 7010 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 7011 { 7012 struct adapter *sc = arg1; 7013 struct sbuf *sb; 7014 int rc, i; 7015 7016 MPASS(chip_id(sc) > CHELSIO_T5); 7017 7018 rc = sysctl_wire_old_buffer(req, 0); 7019 if (rc != 0) 7020 return (rc); 7021 7022 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7023 if (sb == NULL) 7024 return (ENOMEM); 7025 7026 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 7027 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 7028 " Replication" 7029 " P0 P1 P2 P3 ML\n"); 7030 7031 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7032 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 7033 uint16_t ivlan; 7034 uint64_t tcamx, tcamy, val, mask; 7035 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 7036 uint8_t addr[ETHER_ADDR_LEN]; 7037 7038 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 7039 if (i < 256) 7040 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 7041 else 7042 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 7043 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7044 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7045 tcamy = G_DMACH(val) << 32; 7046 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7047 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7048 lookup_type = G_DATALKPTYPE(data2); 7049 port_num = G_DATAPORTNUM(data2); 7050 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7051 /* Inner header VNI */ 7052 vniy = ((data2 & F_DATAVIDH2) << 23) | 7053 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7054 dip_hit = data2 & F_DATADIPHIT; 7055 vlan_vld = 0; 7056 } else { 7057 vniy = 0; 7058 dip_hit = 0; 7059 vlan_vld = data2 & F_DATAVIDH2; 7060 ivlan = G_VIDL(val); 7061 } 7062 7063 ctl |= V_CTLXYBITSEL(1); 7064 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7065 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7066 tcamx = G_DMACH(val) << 32; 7067 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7068 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7069 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7070 /* Inner header VNI mask */ 7071 vnix = ((data2 & F_DATAVIDH2) << 23) | 7072 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7073 } else 7074 vnix = 0; 7075 7076 if (tcamx & tcamy) 7077 continue; 7078 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7079 7080 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7081 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7082 7083 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7084 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7085 "%012jx %06x %06x - - %3c" 7086 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 7087 addr[1], addr[2], addr[3], addr[4], addr[5], 7088 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 7089 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7090 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7091 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7092 } else { 7093 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7094 "%012jx - - ", i, addr[0], addr[1], 7095 addr[2], addr[3], addr[4], addr[5], 7096 (uintmax_t)mask); 7097 7098 if (vlan_vld) 7099 sbuf_printf(sb, "%4u Y ", ivlan); 7100 else 7101 sbuf_printf(sb, " - N "); 7102 7103 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 7104 lookup_type ? 'I' : 'O', port_num, 7105 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7106 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7107 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7108 } 7109 7110 7111 if (cls_lo & F_T6_REPLICATE) { 7112 struct fw_ldst_cmd ldst_cmd; 7113 7114 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7115 ldst_cmd.op_to_addrspace = 7116 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7117 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7118 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7119 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7120 ldst_cmd.u.mps.rplc.fid_idx = 7121 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7122 V_FW_LDST_CMD_IDX(i)); 7123 7124 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7125 "t6mps"); 7126 if (rc) 7127 break; 7128 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7129 sizeof(ldst_cmd), &ldst_cmd); 7130 end_synchronized_op(sc, 0); 7131 7132 if (rc != 0) { 7133 sbuf_printf(sb, "%72d", rc); 7134 rc = 0; 7135 } else { 7136 sbuf_printf(sb, " %08x %08x %08x %08x" 7137 " %08x %08x %08x %08x", 7138 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 7139 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 7140 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 7141 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 7142 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7143 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7144 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7145 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7146 } 7147 } else 7148 sbuf_printf(sb, "%72s", ""); 7149 7150 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 7151 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 7152 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 7153 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 7154 } 7155 7156 if (rc) 7157 (void) sbuf_finish(sb); 7158 else 7159 rc = sbuf_finish(sb); 7160 sbuf_delete(sb); 7161 7162 return (rc); 7163 } 7164 7165 static int 7166 sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 7167 { 7168 struct adapter *sc = arg1; 7169 struct sbuf *sb; 7170 int rc; 7171 uint16_t mtus[NMTUS]; 7172 7173 rc = sysctl_wire_old_buffer(req, 0); 7174 if (rc != 0) 7175 return (rc); 7176 7177 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7178 if (sb == NULL) 7179 return (ENOMEM); 7180 7181 t4_read_mtu_tbl(sc, mtus, NULL); 7182 7183 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 7184 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 7185 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 7186 mtus[14], mtus[15]); 7187 7188 rc = sbuf_finish(sb); 7189 sbuf_delete(sb); 7190 7191 return (rc); 7192 } 7193 7194 static int 7195 sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 7196 { 7197 struct adapter *sc = arg1; 7198 struct sbuf *sb; 7199 int rc, i; 7200 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 7201 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 7202 static const char *tx_stats[MAX_PM_NSTATS] = { 7203 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 7204 "Tx FIFO wait", NULL, "Tx latency" 7205 }; 7206 static const char *rx_stats[MAX_PM_NSTATS] = { 7207 "Read:", "Write bypass:", "Write mem:", "Flush:", 7208 "Rx FIFO wait", NULL, "Rx latency" 7209 }; 7210 7211 rc = sysctl_wire_old_buffer(req, 0); 7212 if (rc != 0) 7213 return (rc); 7214 7215 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7216 if (sb == NULL) 7217 return (ENOMEM); 7218 7219 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 7220 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 7221 7222 sbuf_printf(sb, " Tx pcmds Tx bytes"); 7223 for (i = 0; i < 4; i++) { 7224 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7225 tx_cyc[i]); 7226 } 7227 7228 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 7229 for (i = 0; i < 4; i++) { 7230 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7231 rx_cyc[i]); 7232 } 7233 7234 if (chip_id(sc) > CHELSIO_T5) { 7235 sbuf_printf(sb, 7236 "\n Total wait Total occupancy"); 7237 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7238 tx_cyc[i]); 7239 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7240 rx_cyc[i]); 7241 7242 i += 2; 7243 MPASS(i < nitems(tx_stats)); 7244 7245 sbuf_printf(sb, 7246 "\n Reads Total wait"); 7247 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7248 tx_cyc[i]); 7249 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7250 rx_cyc[i]); 7251 } 7252 7253 rc = sbuf_finish(sb); 7254 sbuf_delete(sb); 7255 7256 return (rc); 7257 } 7258 7259 static int 7260 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 7261 { 7262 struct adapter *sc = arg1; 7263 struct sbuf *sb; 7264 int rc; 7265 struct tp_rdma_stats stats; 7266 7267 rc = sysctl_wire_old_buffer(req, 0); 7268 if (rc != 0) 7269 return (rc); 7270 7271 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7272 if (sb == NULL) 7273 return (ENOMEM); 7274 7275 mtx_lock(&sc->reg_lock); 7276 t4_tp_get_rdma_stats(sc, &stats); 7277 mtx_unlock(&sc->reg_lock); 7278 7279 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 7280 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 7281 7282 rc = sbuf_finish(sb); 7283 sbuf_delete(sb); 7284 7285 return (rc); 7286 } 7287 7288 static int 7289 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 7290 { 7291 struct adapter *sc = arg1; 7292 struct sbuf *sb; 7293 int rc; 7294 struct tp_tcp_stats v4, v6; 7295 7296 rc = sysctl_wire_old_buffer(req, 0); 7297 if (rc != 0) 7298 return (rc); 7299 7300 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7301 if (sb == NULL) 7302 return (ENOMEM); 7303 7304 mtx_lock(&sc->reg_lock); 7305 t4_tp_get_tcp_stats(sc, &v4, &v6); 7306 mtx_unlock(&sc->reg_lock); 7307 7308 sbuf_printf(sb, 7309 " IP IPv6\n"); 7310 sbuf_printf(sb, "OutRsts: %20u %20u\n", 7311 v4.tcp_out_rsts, v6.tcp_out_rsts); 7312 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 7313 v4.tcp_in_segs, v6.tcp_in_segs); 7314 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 7315 v4.tcp_out_segs, v6.tcp_out_segs); 7316 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 7317 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 7318 7319 rc = sbuf_finish(sb); 7320 sbuf_delete(sb); 7321 7322 return (rc); 7323 } 7324 7325 static int 7326 sysctl_tids(SYSCTL_HANDLER_ARGS) 7327 { 7328 struct adapter *sc = arg1; 7329 struct sbuf *sb; 7330 int rc; 7331 struct tid_info *t = &sc->tids; 7332 7333 rc = sysctl_wire_old_buffer(req, 0); 7334 if (rc != 0) 7335 return (rc); 7336 7337 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7338 if (sb == NULL) 7339 return (ENOMEM); 7340 7341 if (t->natids) { 7342 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 7343 t->atids_in_use); 7344 } 7345 7346 if (t->ntids) { 7347 sbuf_printf(sb, "TID range: "); 7348 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7349 uint32_t b, hb; 7350 7351 if (chip_id(sc) <= CHELSIO_T5) { 7352 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 7353 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 7354 } else { 7355 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 7356 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 7357 } 7358 7359 if (b) 7360 sbuf_printf(sb, "0-%u, ", b - 1); 7361 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 7362 } else 7363 sbuf_printf(sb, "0-%u", t->ntids - 1); 7364 sbuf_printf(sb, ", in use: %u\n", 7365 atomic_load_acq_int(&t->tids_in_use)); 7366 } 7367 7368 if (t->nstids) { 7369 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 7370 t->stid_base + t->nstids - 1, t->stids_in_use); 7371 } 7372 7373 if (t->nftids) { 7374 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base, 7375 t->ftid_base + t->nftids - 1); 7376 } 7377 7378 if (t->netids) { 7379 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base, 7380 t->etid_base + t->netids - 1); 7381 } 7382 7383 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 7384 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 7385 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 7386 7387 rc = sbuf_finish(sb); 7388 sbuf_delete(sb); 7389 7390 return (rc); 7391 } 7392 7393 static int 7394 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 7395 { 7396 struct adapter *sc = arg1; 7397 struct sbuf *sb; 7398 int rc; 7399 struct tp_err_stats stats; 7400 7401 rc = sysctl_wire_old_buffer(req, 0); 7402 if (rc != 0) 7403 return (rc); 7404 7405 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7406 if (sb == NULL) 7407 return (ENOMEM); 7408 7409 mtx_lock(&sc->reg_lock); 7410 t4_tp_get_err_stats(sc, &stats); 7411 mtx_unlock(&sc->reg_lock); 7412 7413 if (sc->chip_params->nchan > 2) { 7414 sbuf_printf(sb, " channel 0 channel 1" 7415 " channel 2 channel 3\n"); 7416 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 7417 stats.mac_in_errs[0], stats.mac_in_errs[1], 7418 stats.mac_in_errs[2], stats.mac_in_errs[3]); 7419 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 7420 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 7421 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 7422 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 7423 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 7424 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 7425 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 7426 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 7427 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 7428 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 7429 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 7430 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 7431 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 7432 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 7433 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 7434 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 7435 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 7436 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 7437 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 7438 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 7439 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 7440 } else { 7441 sbuf_printf(sb, " channel 0 channel 1\n"); 7442 sbuf_printf(sb, "macInErrs: %10u %10u\n", 7443 stats.mac_in_errs[0], stats.mac_in_errs[1]); 7444 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 7445 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 7446 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 7447 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 7448 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 7449 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 7450 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 7451 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 7452 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 7453 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 7454 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 7455 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 7456 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 7457 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 7458 } 7459 7460 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 7461 stats.ofld_no_neigh, stats.ofld_cong_defer); 7462 7463 rc = sbuf_finish(sb); 7464 sbuf_delete(sb); 7465 7466 return (rc); 7467 } 7468 7469 static int 7470 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 7471 { 7472 struct adapter *sc = arg1; 7473 struct tp_params *tpp = &sc->params.tp; 7474 u_int mask; 7475 int rc; 7476 7477 mask = tpp->la_mask >> 16; 7478 rc = sysctl_handle_int(oidp, &mask, 0, req); 7479 if (rc != 0 || req->newptr == NULL) 7480 return (rc); 7481 if (mask > 0xffff) 7482 return (EINVAL); 7483 tpp->la_mask = mask << 16; 7484 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 7485 7486 return (0); 7487 } 7488 7489 struct field_desc { 7490 const char *name; 7491 u_int start; 7492 u_int width; 7493 }; 7494 7495 static void 7496 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 7497 { 7498 char buf[32]; 7499 int line_size = 0; 7500 7501 while (f->name) { 7502 uint64_t mask = (1ULL << f->width) - 1; 7503 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 7504 ((uintmax_t)v >> f->start) & mask); 7505 7506 if (line_size + len >= 79) { 7507 line_size = 8; 7508 sbuf_printf(sb, "\n "); 7509 } 7510 sbuf_printf(sb, "%s ", buf); 7511 line_size += len + 1; 7512 f++; 7513 } 7514 sbuf_printf(sb, "\n"); 7515 } 7516 7517 static const struct field_desc tp_la0[] = { 7518 { "RcfOpCodeOut", 60, 4 }, 7519 { "State", 56, 4 }, 7520 { "WcfState", 52, 4 }, 7521 { "RcfOpcSrcOut", 50, 2 }, 7522 { "CRxError", 49, 1 }, 7523 { "ERxError", 48, 1 }, 7524 { "SanityFailed", 47, 1 }, 7525 { "SpuriousMsg", 46, 1 }, 7526 { "FlushInputMsg", 45, 1 }, 7527 { "FlushInputCpl", 44, 1 }, 7528 { "RssUpBit", 43, 1 }, 7529 { "RssFilterHit", 42, 1 }, 7530 { "Tid", 32, 10 }, 7531 { "InitTcb", 31, 1 }, 7532 { "LineNumber", 24, 7 }, 7533 { "Emsg", 23, 1 }, 7534 { "EdataOut", 22, 1 }, 7535 { "Cmsg", 21, 1 }, 7536 { "CdataOut", 20, 1 }, 7537 { "EreadPdu", 19, 1 }, 7538 { "CreadPdu", 18, 1 }, 7539 { "TunnelPkt", 17, 1 }, 7540 { "RcfPeerFin", 16, 1 }, 7541 { "RcfReasonOut", 12, 4 }, 7542 { "TxCchannel", 10, 2 }, 7543 { "RcfTxChannel", 8, 2 }, 7544 { "RxEchannel", 6, 2 }, 7545 { "RcfRxChannel", 5, 1 }, 7546 { "RcfDataOutSrdy", 4, 1 }, 7547 { "RxDvld", 3, 1 }, 7548 { "RxOoDvld", 2, 1 }, 7549 { "RxCongestion", 1, 1 }, 7550 { "TxCongestion", 0, 1 }, 7551 { NULL } 7552 }; 7553 7554 static const struct field_desc tp_la1[] = { 7555 { "CplCmdIn", 56, 8 }, 7556 { "CplCmdOut", 48, 8 }, 7557 { "ESynOut", 47, 1 }, 7558 { "EAckOut", 46, 1 }, 7559 { "EFinOut", 45, 1 }, 7560 { "ERstOut", 44, 1 }, 7561 { "SynIn", 43, 1 }, 7562 { "AckIn", 42, 1 }, 7563 { "FinIn", 41, 1 }, 7564 { "RstIn", 40, 1 }, 7565 { "DataIn", 39, 1 }, 7566 { "DataInVld", 38, 1 }, 7567 { "PadIn", 37, 1 }, 7568 { "RxBufEmpty", 36, 1 }, 7569 { "RxDdp", 35, 1 }, 7570 { "RxFbCongestion", 34, 1 }, 7571 { "TxFbCongestion", 33, 1 }, 7572 { "TxPktSumSrdy", 32, 1 }, 7573 { "RcfUlpType", 28, 4 }, 7574 { "Eread", 27, 1 }, 7575 { "Ebypass", 26, 1 }, 7576 { "Esave", 25, 1 }, 7577 { "Static0", 24, 1 }, 7578 { "Cread", 23, 1 }, 7579 { "Cbypass", 22, 1 }, 7580 { "Csave", 21, 1 }, 7581 { "CPktOut", 20, 1 }, 7582 { "RxPagePoolFull", 18, 2 }, 7583 { "RxLpbkPkt", 17, 1 }, 7584 { "TxLpbkPkt", 16, 1 }, 7585 { "RxVfValid", 15, 1 }, 7586 { "SynLearned", 14, 1 }, 7587 { "SetDelEntry", 13, 1 }, 7588 { "SetInvEntry", 12, 1 }, 7589 { "CpcmdDvld", 11, 1 }, 7590 { "CpcmdSave", 10, 1 }, 7591 { "RxPstructsFull", 8, 2 }, 7592 { "EpcmdDvld", 7, 1 }, 7593 { "EpcmdFlush", 6, 1 }, 7594 { "EpcmdTrimPrefix", 5, 1 }, 7595 { "EpcmdTrimPostfix", 4, 1 }, 7596 { "ERssIp4Pkt", 3, 1 }, 7597 { "ERssIp6Pkt", 2, 1 }, 7598 { "ERssTcpUdpPkt", 1, 1 }, 7599 { "ERssFceFipPkt", 0, 1 }, 7600 { NULL } 7601 }; 7602 7603 static const struct field_desc tp_la2[] = { 7604 { "CplCmdIn", 56, 8 }, 7605 { "MpsVfVld", 55, 1 }, 7606 { "MpsPf", 52, 3 }, 7607 { "MpsVf", 44, 8 }, 7608 { "SynIn", 43, 1 }, 7609 { "AckIn", 42, 1 }, 7610 { "FinIn", 41, 1 }, 7611 { "RstIn", 40, 1 }, 7612 { "DataIn", 39, 1 }, 7613 { "DataInVld", 38, 1 }, 7614 { "PadIn", 37, 1 }, 7615 { "RxBufEmpty", 36, 1 }, 7616 { "RxDdp", 35, 1 }, 7617 { "RxFbCongestion", 34, 1 }, 7618 { "TxFbCongestion", 33, 1 }, 7619 { "TxPktSumSrdy", 32, 1 }, 7620 { "RcfUlpType", 28, 4 }, 7621 { "Eread", 27, 1 }, 7622 { "Ebypass", 26, 1 }, 7623 { "Esave", 25, 1 }, 7624 { "Static0", 24, 1 }, 7625 { "Cread", 23, 1 }, 7626 { "Cbypass", 22, 1 }, 7627 { "Csave", 21, 1 }, 7628 { "CPktOut", 20, 1 }, 7629 { "RxPagePoolFull", 18, 2 }, 7630 { "RxLpbkPkt", 17, 1 }, 7631 { "TxLpbkPkt", 16, 1 }, 7632 { "RxVfValid", 15, 1 }, 7633 { "SynLearned", 14, 1 }, 7634 { "SetDelEntry", 13, 1 }, 7635 { "SetInvEntry", 12, 1 }, 7636 { "CpcmdDvld", 11, 1 }, 7637 { "CpcmdSave", 10, 1 }, 7638 { "RxPstructsFull", 8, 2 }, 7639 { "EpcmdDvld", 7, 1 }, 7640 { "EpcmdFlush", 6, 1 }, 7641 { "EpcmdTrimPrefix", 5, 1 }, 7642 { "EpcmdTrimPostfix", 4, 1 }, 7643 { "ERssIp4Pkt", 3, 1 }, 7644 { "ERssIp6Pkt", 2, 1 }, 7645 { "ERssTcpUdpPkt", 1, 1 }, 7646 { "ERssFceFipPkt", 0, 1 }, 7647 { NULL } 7648 }; 7649 7650 static void 7651 tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 7652 { 7653 7654 field_desc_show(sb, *p, tp_la0); 7655 } 7656 7657 static void 7658 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 7659 { 7660 7661 if (idx) 7662 sbuf_printf(sb, "\n"); 7663 field_desc_show(sb, p[0], tp_la0); 7664 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 7665 field_desc_show(sb, p[1], tp_la0); 7666 } 7667 7668 static void 7669 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 7670 { 7671 7672 if (idx) 7673 sbuf_printf(sb, "\n"); 7674 field_desc_show(sb, p[0], tp_la0); 7675 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 7676 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 7677 } 7678 7679 static int 7680 sysctl_tp_la(SYSCTL_HANDLER_ARGS) 7681 { 7682 struct adapter *sc = arg1; 7683 struct sbuf *sb; 7684 uint64_t *buf, *p; 7685 int rc; 7686 u_int i, inc; 7687 void (*show_func)(struct sbuf *, uint64_t *, int); 7688 7689 rc = sysctl_wire_old_buffer(req, 0); 7690 if (rc != 0) 7691 return (rc); 7692 7693 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7694 if (sb == NULL) 7695 return (ENOMEM); 7696 7697 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 7698 7699 t4_tp_read_la(sc, buf, NULL); 7700 p = buf; 7701 7702 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 7703 case 2: 7704 inc = 2; 7705 show_func = tp_la_show2; 7706 break; 7707 case 3: 7708 inc = 2; 7709 show_func = tp_la_show3; 7710 break; 7711 default: 7712 inc = 1; 7713 show_func = tp_la_show; 7714 } 7715 7716 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 7717 (*show_func)(sb, p, i); 7718 7719 rc = sbuf_finish(sb); 7720 sbuf_delete(sb); 7721 free(buf, M_CXGBE); 7722 return (rc); 7723 } 7724 7725 static int 7726 sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 7727 { 7728 struct adapter *sc = arg1; 7729 struct sbuf *sb; 7730 int rc; 7731 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 7732 7733 rc = sysctl_wire_old_buffer(req, 0); 7734 if (rc != 0) 7735 return (rc); 7736 7737 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7738 if (sb == NULL) 7739 return (ENOMEM); 7740 7741 t4_get_chan_txrate(sc, nrate, orate); 7742 7743 if (sc->chip_params->nchan > 2) { 7744 sbuf_printf(sb, " channel 0 channel 1" 7745 " channel 2 channel 3\n"); 7746 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 7747 nrate[0], nrate[1], nrate[2], nrate[3]); 7748 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 7749 orate[0], orate[1], orate[2], orate[3]); 7750 } else { 7751 sbuf_printf(sb, " channel 0 channel 1\n"); 7752 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 7753 nrate[0], nrate[1]); 7754 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 7755 orate[0], orate[1]); 7756 } 7757 7758 rc = sbuf_finish(sb); 7759 sbuf_delete(sb); 7760 7761 return (rc); 7762 } 7763 7764 static int 7765 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 7766 { 7767 struct adapter *sc = arg1; 7768 struct sbuf *sb; 7769 uint32_t *buf, *p; 7770 int rc, i; 7771 7772 rc = sysctl_wire_old_buffer(req, 0); 7773 if (rc != 0) 7774 return (rc); 7775 7776 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7777 if (sb == NULL) 7778 return (ENOMEM); 7779 7780 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 7781 M_ZERO | M_WAITOK); 7782 7783 t4_ulprx_read_la(sc, buf); 7784 p = buf; 7785 7786 sbuf_printf(sb, " Pcmd Type Message" 7787 " Data"); 7788 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 7789 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 7790 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 7791 } 7792 7793 rc = sbuf_finish(sb); 7794 sbuf_delete(sb); 7795 free(buf, M_CXGBE); 7796 return (rc); 7797 } 7798 7799 static int 7800 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 7801 { 7802 struct adapter *sc = arg1; 7803 struct sbuf *sb; 7804 int rc, v; 7805 7806 MPASS(chip_id(sc) >= CHELSIO_T5); 7807 7808 rc = sysctl_wire_old_buffer(req, 0); 7809 if (rc != 0) 7810 return (rc); 7811 7812 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7813 if (sb == NULL) 7814 return (ENOMEM); 7815 7816 v = t4_read_reg(sc, A_SGE_STAT_CFG); 7817 if (G_STATSOURCE_T5(v) == 7) { 7818 int mode; 7819 7820 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 7821 if (mode == 0) { 7822 sbuf_printf(sb, "total %d, incomplete %d", 7823 t4_read_reg(sc, A_SGE_STAT_TOTAL), 7824 t4_read_reg(sc, A_SGE_STAT_MATCH)); 7825 } else if (mode == 1) { 7826 sbuf_printf(sb, "total %d, data overflow %d", 7827 t4_read_reg(sc, A_SGE_STAT_TOTAL), 7828 t4_read_reg(sc, A_SGE_STAT_MATCH)); 7829 } else { 7830 sbuf_printf(sb, "unknown mode %d", mode); 7831 } 7832 } 7833 rc = sbuf_finish(sb); 7834 sbuf_delete(sb); 7835 7836 return (rc); 7837 } 7838 7839 static int 7840 sysctl_tc_params(SYSCTL_HANDLER_ARGS) 7841 { 7842 struct adapter *sc = arg1; 7843 struct tx_sched_class *tc; 7844 struct t4_sched_class_params p; 7845 struct sbuf *sb; 7846 int i, rc, port_id, flags, mbps, gbps; 7847 7848 rc = sysctl_wire_old_buffer(req, 0); 7849 if (rc != 0) 7850 return (rc); 7851 7852 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7853 if (sb == NULL) 7854 return (ENOMEM); 7855 7856 port_id = arg2 >> 16; 7857 MPASS(port_id < sc->params.nports); 7858 MPASS(sc->port[port_id] != NULL); 7859 i = arg2 & 0xffff; 7860 MPASS(i < sc->chip_params->nsched_cls); 7861 tc = &sc->port[port_id]->tc[i]; 7862 7863 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 7864 "t4tc_p"); 7865 if (rc) 7866 goto done; 7867 flags = tc->flags; 7868 p = tc->params; 7869 end_synchronized_op(sc, LOCK_HELD); 7870 7871 if ((flags & TX_SC_OK) == 0) { 7872 sbuf_printf(sb, "none"); 7873 goto done; 7874 } 7875 7876 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) { 7877 sbuf_printf(sb, "cl-wrr weight %u", p.weight); 7878 goto done; 7879 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL) 7880 sbuf_printf(sb, "cl-rl"); 7881 else if (p.level == SCHED_CLASS_LEVEL_CH_RL) 7882 sbuf_printf(sb, "ch-rl"); 7883 else { 7884 rc = ENXIO; 7885 goto done; 7886 } 7887 7888 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) { 7889 /* XXX: top speed or actual link speed? */ 7890 gbps = port_top_speed(sc->port[port_id]); 7891 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps); 7892 } 7893 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) { 7894 switch (p.rateunit) { 7895 case SCHED_CLASS_RATEUNIT_BITS: 7896 mbps = p.maxrate / 1000; 7897 gbps = p.maxrate / 1000000; 7898 if (p.maxrate == gbps * 1000000) 7899 sbuf_printf(sb, " %uGbps", gbps); 7900 else if (p.maxrate == mbps * 1000) 7901 sbuf_printf(sb, " %uMbps", mbps); 7902 else 7903 sbuf_printf(sb, " %uKbps", p.maxrate); 7904 break; 7905 case SCHED_CLASS_RATEUNIT_PKTS: 7906 sbuf_printf(sb, " %upps", p.maxrate); 7907 break; 7908 default: 7909 rc = ENXIO; 7910 goto done; 7911 } 7912 } 7913 7914 switch (p.mode) { 7915 case SCHED_CLASS_MODE_CLASS: 7916 sbuf_printf(sb, " aggregate"); 7917 break; 7918 case SCHED_CLASS_MODE_FLOW: 7919 sbuf_printf(sb, " per-flow"); 7920 break; 7921 default: 7922 rc = ENXIO; 7923 goto done; 7924 } 7925 7926 done: 7927 if (rc == 0) 7928 rc = sbuf_finish(sb); 7929 sbuf_delete(sb); 7930 7931 return (rc); 7932 } 7933 #endif 7934 7935 #ifdef TCP_OFFLOAD 7936 static void 7937 unit_conv(char *buf, size_t len, u_int val, u_int factor) 7938 { 7939 u_int rem = val % factor; 7940 7941 if (rem == 0) 7942 snprintf(buf, len, "%u", val / factor); 7943 else { 7944 while (rem % 10 == 0) 7945 rem /= 10; 7946 snprintf(buf, len, "%u.%u", val / factor, rem); 7947 } 7948 } 7949 7950 static int 7951 sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 7952 { 7953 struct adapter *sc = arg1; 7954 char buf[16]; 7955 u_int res, re; 7956 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7957 7958 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 7959 switch (arg2) { 7960 case 0: 7961 /* timer_tick */ 7962 re = G_TIMERRESOLUTION(res); 7963 break; 7964 case 1: 7965 /* TCP timestamp tick */ 7966 re = G_TIMESTAMPRESOLUTION(res); 7967 break; 7968 case 2: 7969 /* DACK tick */ 7970 re = G_DELAYEDACKRESOLUTION(res); 7971 break; 7972 default: 7973 return (EDOOFUS); 7974 } 7975 7976 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 7977 7978 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 7979 } 7980 7981 static int 7982 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 7983 { 7984 struct adapter *sc = arg1; 7985 u_int res, dack_re, v; 7986 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7987 7988 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 7989 dack_re = G_DELAYEDACKRESOLUTION(res); 7990 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 7991 7992 return (sysctl_handle_int(oidp, &v, 0, req)); 7993 } 7994 7995 static int 7996 sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 7997 { 7998 struct adapter *sc = arg1; 7999 int reg = arg2; 8000 u_int tre; 8001 u_long tp_tick_us, v; 8002 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8003 8004 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 8005 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 8006 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 8007 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 8008 8009 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 8010 tp_tick_us = (cclk_ps << tre) / 1000000; 8011 8012 if (reg == A_TP_INIT_SRTT) 8013 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 8014 else 8015 v = tp_tick_us * t4_read_reg(sc, reg); 8016 8017 return (sysctl_handle_long(oidp, &v, 0, req)); 8018 } 8019 #endif 8020 8021 static uint32_t 8022 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf) 8023 { 8024 uint32_t mode; 8025 8026 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR | 8027 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT; 8028 8029 if (fconf & F_FRAGMENTATION) 8030 mode |= T4_FILTER_IP_FRAGMENT; 8031 8032 if (fconf & F_MPSHITTYPE) 8033 mode |= T4_FILTER_MPS_HIT_TYPE; 8034 8035 if (fconf & F_MACMATCH) 8036 mode |= T4_FILTER_MAC_IDX; 8037 8038 if (fconf & F_ETHERTYPE) 8039 mode |= T4_FILTER_ETH_TYPE; 8040 8041 if (fconf & F_PROTOCOL) 8042 mode |= T4_FILTER_IP_PROTO; 8043 8044 if (fconf & F_TOS) 8045 mode |= T4_FILTER_IP_TOS; 8046 8047 if (fconf & F_VLAN) 8048 mode |= T4_FILTER_VLAN; 8049 8050 if (fconf & F_VNIC_ID) { 8051 mode |= T4_FILTER_VNIC; 8052 if (iconf & F_VNIC) 8053 mode |= T4_FILTER_IC_VNIC; 8054 } 8055 8056 if (fconf & F_PORT) 8057 mode |= T4_FILTER_PORT; 8058 8059 if (fconf & F_FCOE) 8060 mode |= T4_FILTER_FCoE; 8061 8062 return (mode); 8063 } 8064 8065 static uint32_t 8066 mode_to_fconf(uint32_t mode) 8067 { 8068 uint32_t fconf = 0; 8069 8070 if (mode & T4_FILTER_IP_FRAGMENT) 8071 fconf |= F_FRAGMENTATION; 8072 8073 if (mode & T4_FILTER_MPS_HIT_TYPE) 8074 fconf |= F_MPSHITTYPE; 8075 8076 if (mode & T4_FILTER_MAC_IDX) 8077 fconf |= F_MACMATCH; 8078 8079 if (mode & T4_FILTER_ETH_TYPE) 8080 fconf |= F_ETHERTYPE; 8081 8082 if (mode & T4_FILTER_IP_PROTO) 8083 fconf |= F_PROTOCOL; 8084 8085 if (mode & T4_FILTER_IP_TOS) 8086 fconf |= F_TOS; 8087 8088 if (mode & T4_FILTER_VLAN) 8089 fconf |= F_VLAN; 8090 8091 if (mode & T4_FILTER_VNIC) 8092 fconf |= F_VNIC_ID; 8093 8094 if (mode & T4_FILTER_PORT) 8095 fconf |= F_PORT; 8096 8097 if (mode & T4_FILTER_FCoE) 8098 fconf |= F_FCOE; 8099 8100 return (fconf); 8101 } 8102 8103 static uint32_t 8104 mode_to_iconf(uint32_t mode) 8105 { 8106 8107 if (mode & T4_FILTER_IC_VNIC) 8108 return (F_VNIC); 8109 return (0); 8110 } 8111 8112 static int check_fspec_against_fconf_iconf(struct adapter *sc, 8113 struct t4_filter_specification *fs) 8114 { 8115 struct tp_params *tpp = &sc->params.tp; 8116 uint32_t fconf = 0; 8117 8118 if (fs->val.frag || fs->mask.frag) 8119 fconf |= F_FRAGMENTATION; 8120 8121 if (fs->val.matchtype || fs->mask.matchtype) 8122 fconf |= F_MPSHITTYPE; 8123 8124 if (fs->val.macidx || fs->mask.macidx) 8125 fconf |= F_MACMATCH; 8126 8127 if (fs->val.ethtype || fs->mask.ethtype) 8128 fconf |= F_ETHERTYPE; 8129 8130 if (fs->val.proto || fs->mask.proto) 8131 fconf |= F_PROTOCOL; 8132 8133 if (fs->val.tos || fs->mask.tos) 8134 fconf |= F_TOS; 8135 8136 if (fs->val.vlan_vld || fs->mask.vlan_vld) 8137 fconf |= F_VLAN; 8138 8139 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) { 8140 fconf |= F_VNIC_ID; 8141 if (tpp->ingress_config & F_VNIC) 8142 return (EINVAL); 8143 } 8144 8145 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) { 8146 fconf |= F_VNIC_ID; 8147 if ((tpp->ingress_config & F_VNIC) == 0) 8148 return (EINVAL); 8149 } 8150 8151 if (fs->val.iport || fs->mask.iport) 8152 fconf |= F_PORT; 8153 8154 if (fs->val.fcoe || fs->mask.fcoe) 8155 fconf |= F_FCOE; 8156 8157 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map) 8158 return (E2BIG); 8159 8160 return (0); 8161 } 8162 8163 static int 8164 get_filter_mode(struct adapter *sc, uint32_t *mode) 8165 { 8166 struct tp_params *tpp = &sc->params.tp; 8167 8168 /* 8169 * We trust the cached values of the relevant TP registers. This means 8170 * things work reliably only if writes to those registers are always via 8171 * t4_set_filter_mode. 8172 */ 8173 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config); 8174 8175 return (0); 8176 } 8177 8178 static int 8179 set_filter_mode(struct adapter *sc, uint32_t mode) 8180 { 8181 struct tp_params *tpp = &sc->params.tp; 8182 uint32_t fconf, iconf; 8183 int rc; 8184 8185 iconf = mode_to_iconf(mode); 8186 if ((iconf ^ tpp->ingress_config) & F_VNIC) { 8187 /* 8188 * For now we just complain if A_TP_INGRESS_CONFIG is not 8189 * already set to the correct value for the requested filter 8190 * mode. It's not clear if it's safe to write to this register 8191 * on the fly. (And we trust the cached value of the register). 8192 */ 8193 return (EBUSY); 8194 } 8195 8196 fconf = mode_to_fconf(mode); 8197 8198 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8199 "t4setfm"); 8200 if (rc) 8201 return (rc); 8202 8203 if (sc->tids.ftids_in_use > 0) { 8204 rc = EBUSY; 8205 goto done; 8206 } 8207 8208 #ifdef TCP_OFFLOAD 8209 if (uld_active(sc, ULD_TOM)) { 8210 rc = EBUSY; 8211 goto done; 8212 } 8213 #endif 8214 8215 rc = -t4_set_filter_mode(sc, fconf); 8216 done: 8217 end_synchronized_op(sc, LOCK_HELD); 8218 return (rc); 8219 } 8220 8221 static inline uint64_t 8222 get_filter_hits(struct adapter *sc, uint32_t fid) 8223 { 8224 uint32_t tcb_addr; 8225 8226 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) + 8227 (fid + sc->tids.ftid_base) * TCB_SIZE; 8228 8229 if (is_t4(sc)) { 8230 uint64_t hits; 8231 8232 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8); 8233 return (be64toh(hits)); 8234 } else { 8235 uint32_t hits; 8236 8237 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4); 8238 return (be32toh(hits)); 8239 } 8240 } 8241 8242 static int 8243 get_filter(struct adapter *sc, struct t4_filter *t) 8244 { 8245 int i, rc, nfilters = sc->tids.nftids; 8246 struct filter_entry *f; 8247 8248 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8249 "t4getf"); 8250 if (rc) 8251 return (rc); 8252 8253 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL || 8254 t->idx >= nfilters) { 8255 t->idx = 0xffffffff; 8256 goto done; 8257 } 8258 8259 f = &sc->tids.ftid_tab[t->idx]; 8260 for (i = t->idx; i < nfilters; i++, f++) { 8261 if (f->valid) { 8262 t->idx = i; 8263 t->l2tidx = f->l2t ? f->l2t->idx : 0; 8264 t->smtidx = f->smtidx; 8265 if (f->fs.hitcnts) 8266 t->hits = get_filter_hits(sc, t->idx); 8267 else 8268 t->hits = UINT64_MAX; 8269 t->fs = f->fs; 8270 8271 goto done; 8272 } 8273 } 8274 8275 t->idx = 0xffffffff; 8276 done: 8277 end_synchronized_op(sc, LOCK_HELD); 8278 return (0); 8279 } 8280 8281 static int 8282 set_filter(struct adapter *sc, struct t4_filter *t) 8283 { 8284 unsigned int nfilters, nports; 8285 struct filter_entry *f; 8286 int i, rc; 8287 8288 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf"); 8289 if (rc) 8290 return (rc); 8291 8292 nfilters = sc->tids.nftids; 8293 nports = sc->params.nports; 8294 8295 if (nfilters == 0) { 8296 rc = ENOTSUP; 8297 goto done; 8298 } 8299 8300 if (t->idx >= nfilters) { 8301 rc = EINVAL; 8302 goto done; 8303 } 8304 8305 /* Validate against the global filter mode and ingress config */ 8306 rc = check_fspec_against_fconf_iconf(sc, &t->fs); 8307 if (rc != 0) 8308 goto done; 8309 8310 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) { 8311 rc = EINVAL; 8312 goto done; 8313 } 8314 8315 if (t->fs.val.iport >= nports) { 8316 rc = EINVAL; 8317 goto done; 8318 } 8319 8320 /* Can't specify an iq if not steering to it */ 8321 if (!t->fs.dirsteer && t->fs.iq) { 8322 rc = EINVAL; 8323 goto done; 8324 } 8325 8326 /* IPv6 filter idx must be 4 aligned */ 8327 if (t->fs.type == 1 && 8328 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) { 8329 rc = EINVAL; 8330 goto done; 8331 } 8332 8333 if (!(sc->flags & FULL_INIT_DONE) && 8334 ((rc = adapter_full_init(sc)) != 0)) 8335 goto done; 8336 8337 if (sc->tids.ftid_tab == NULL) { 8338 KASSERT(sc->tids.ftids_in_use == 0, 8339 ("%s: no memory allocated but filters_in_use > 0", 8340 __func__)); 8341 8342 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) * 8343 nfilters, M_CXGBE, M_NOWAIT | M_ZERO); 8344 if (sc->tids.ftid_tab == NULL) { 8345 rc = ENOMEM; 8346 goto done; 8347 } 8348 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF); 8349 } 8350 8351 for (i = 0; i < 4; i++) { 8352 f = &sc->tids.ftid_tab[t->idx + i]; 8353 8354 if (f->pending || f->valid) { 8355 rc = EBUSY; 8356 goto done; 8357 } 8358 if (f->locked) { 8359 rc = EPERM; 8360 goto done; 8361 } 8362 8363 if (t->fs.type == 0) 8364 break; 8365 } 8366 8367 f = &sc->tids.ftid_tab[t->idx]; 8368 f->fs = t->fs; 8369 8370 rc = set_filter_wr(sc, t->idx); 8371 done: 8372 end_synchronized_op(sc, 0); 8373 8374 if (rc == 0) { 8375 mtx_lock(&sc->tids.ftid_lock); 8376 for (;;) { 8377 if (f->pending == 0) { 8378 rc = f->valid ? 0 : EIO; 8379 break; 8380 } 8381 8382 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8383 PCATCH, "t4setfw", 0)) { 8384 rc = EINPROGRESS; 8385 break; 8386 } 8387 } 8388 mtx_unlock(&sc->tids.ftid_lock); 8389 } 8390 return (rc); 8391 } 8392 8393 static int 8394 del_filter(struct adapter *sc, struct t4_filter *t) 8395 { 8396 unsigned int nfilters; 8397 struct filter_entry *f; 8398 int rc; 8399 8400 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf"); 8401 if (rc) 8402 return (rc); 8403 8404 nfilters = sc->tids.nftids; 8405 8406 if (nfilters == 0) { 8407 rc = ENOTSUP; 8408 goto done; 8409 } 8410 8411 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 || 8412 t->idx >= nfilters) { 8413 rc = EINVAL; 8414 goto done; 8415 } 8416 8417 if (!(sc->flags & FULL_INIT_DONE)) { 8418 rc = EAGAIN; 8419 goto done; 8420 } 8421 8422 f = &sc->tids.ftid_tab[t->idx]; 8423 8424 if (f->pending) { 8425 rc = EBUSY; 8426 goto done; 8427 } 8428 if (f->locked) { 8429 rc = EPERM; 8430 goto done; 8431 } 8432 8433 if (f->valid) { 8434 t->fs = f->fs; /* extra info for the caller */ 8435 rc = del_filter_wr(sc, t->idx); 8436 } 8437 8438 done: 8439 end_synchronized_op(sc, 0); 8440 8441 if (rc == 0) { 8442 mtx_lock(&sc->tids.ftid_lock); 8443 for (;;) { 8444 if (f->pending == 0) { 8445 rc = f->valid ? EIO : 0; 8446 break; 8447 } 8448 8449 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8450 PCATCH, "t4delfw", 0)) { 8451 rc = EINPROGRESS; 8452 break; 8453 } 8454 } 8455 mtx_unlock(&sc->tids.ftid_lock); 8456 } 8457 8458 return (rc); 8459 } 8460 8461 static void 8462 clear_filter(struct filter_entry *f) 8463 { 8464 if (f->l2t) 8465 t4_l2t_release(f->l2t); 8466 8467 bzero(f, sizeof (*f)); 8468 } 8469 8470 static int 8471 set_filter_wr(struct adapter *sc, int fidx) 8472 { 8473 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8474 struct fw_filter_wr *fwr; 8475 unsigned int ftid, vnic_vld, vnic_vld_mask; 8476 struct wrq_cookie cookie; 8477 8478 ASSERT_SYNCHRONIZED_OP(sc); 8479 8480 if (f->fs.newdmac || f->fs.newvlan) { 8481 /* This filter needs an L2T entry; allocate one. */ 8482 f->l2t = t4_l2t_alloc_switching(sc->l2t); 8483 if (f->l2t == NULL) 8484 return (EAGAIN); 8485 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport, 8486 f->fs.dmac)) { 8487 t4_l2t_release(f->l2t); 8488 f->l2t = NULL; 8489 return (ENOMEM); 8490 } 8491 } 8492 8493 /* Already validated against fconf, iconf */ 8494 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0); 8495 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0); 8496 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld) 8497 vnic_vld = 1; 8498 else 8499 vnic_vld = 0; 8500 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld) 8501 vnic_vld_mask = 1; 8502 else 8503 vnic_vld_mask = 0; 8504 8505 ftid = sc->tids.ftid_base + fidx; 8506 8507 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 8508 if (fwr == NULL) 8509 return (ENOMEM); 8510 bzero(fwr, sizeof(*fwr)); 8511 8512 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR)); 8513 fwr->len16_pkd = htobe32(FW_LEN16(*fwr)); 8514 fwr->tid_to_iq = 8515 htobe32(V_FW_FILTER_WR_TID(ftid) | 8516 V_FW_FILTER_WR_RQTYPE(f->fs.type) | 8517 V_FW_FILTER_WR_NOREPLY(0) | 8518 V_FW_FILTER_WR_IQ(f->fs.iq)); 8519 fwr->del_filter_to_l2tix = 8520 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) | 8521 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) | 8522 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) | 8523 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) | 8524 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) | 8525 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) | 8526 V_FW_FILTER_WR_DMAC(f->fs.newdmac) | 8527 V_FW_FILTER_WR_SMAC(f->fs.newsmac) | 8528 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT || 8529 f->fs.newvlan == VLAN_REWRITE) | 8530 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE || 8531 f->fs.newvlan == VLAN_REWRITE) | 8532 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) | 8533 V_FW_FILTER_WR_TXCHAN(f->fs.eport) | 8534 V_FW_FILTER_WR_PRIO(f->fs.prio) | 8535 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0)); 8536 fwr->ethtype = htobe16(f->fs.val.ethtype); 8537 fwr->ethtypem = htobe16(f->fs.mask.ethtype); 8538 fwr->frag_to_ovlan_vldm = 8539 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) | 8540 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) | 8541 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) | 8542 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) | 8543 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) | 8544 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask)); 8545 fwr->smac_sel = 0; 8546 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) | 8547 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id)); 8548 fwr->maci_to_matchtypem = 8549 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) | 8550 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) | 8551 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) | 8552 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) | 8553 V_FW_FILTER_WR_PORT(f->fs.val.iport) | 8554 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) | 8555 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) | 8556 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype)); 8557 fwr->ptcl = f->fs.val.proto; 8558 fwr->ptclm = f->fs.mask.proto; 8559 fwr->ttyp = f->fs.val.tos; 8560 fwr->ttypm = f->fs.mask.tos; 8561 fwr->ivlan = htobe16(f->fs.val.vlan); 8562 fwr->ivlanm = htobe16(f->fs.mask.vlan); 8563 fwr->ovlan = htobe16(f->fs.val.vnic); 8564 fwr->ovlanm = htobe16(f->fs.mask.vnic); 8565 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip)); 8566 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm)); 8567 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip)); 8568 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm)); 8569 fwr->lp = htobe16(f->fs.val.dport); 8570 fwr->lpm = htobe16(f->fs.mask.dport); 8571 fwr->fp = htobe16(f->fs.val.sport); 8572 fwr->fpm = htobe16(f->fs.mask.sport); 8573 if (f->fs.newsmac) 8574 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma)); 8575 8576 f->pending = 1; 8577 sc->tids.ftids_in_use++; 8578 8579 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 8580 return (0); 8581 } 8582 8583 static int 8584 del_filter_wr(struct adapter *sc, int fidx) 8585 { 8586 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8587 struct fw_filter_wr *fwr; 8588 unsigned int ftid; 8589 struct wrq_cookie cookie; 8590 8591 ftid = sc->tids.ftid_base + fidx; 8592 8593 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 8594 if (fwr == NULL) 8595 return (ENOMEM); 8596 bzero(fwr, sizeof (*fwr)); 8597 8598 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id); 8599 8600 f->pending = 1; 8601 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 8602 return (0); 8603 } 8604 8605 int 8606 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8607 { 8608 struct adapter *sc = iq->adapter; 8609 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1); 8610 unsigned int idx = GET_TID(rpl); 8611 unsigned int rc; 8612 struct filter_entry *f; 8613 8614 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 8615 rss->opcode)); 8616 MPASS(iq == &sc->sge.fwq); 8617 MPASS(is_ftid(sc, idx)); 8618 8619 idx -= sc->tids.ftid_base; 8620 f = &sc->tids.ftid_tab[idx]; 8621 rc = G_COOKIE(rpl->cookie); 8622 8623 mtx_lock(&sc->tids.ftid_lock); 8624 if (rc == FW_FILTER_WR_FLT_ADDED) { 8625 KASSERT(f->pending, ("%s: filter[%u] isn't pending.", 8626 __func__, idx)); 8627 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff; 8628 f->pending = 0; /* asynchronous setup completed */ 8629 f->valid = 1; 8630 } else { 8631 if (rc != FW_FILTER_WR_FLT_DELETED) { 8632 /* Add or delete failed, display an error */ 8633 log(LOG_ERR, 8634 "filter %u setup failed with error %u\n", 8635 idx, rc); 8636 } 8637 8638 clear_filter(f); 8639 sc->tids.ftids_in_use--; 8640 } 8641 wakeup(&sc->tids.ftid_tab); 8642 mtx_unlock(&sc->tids.ftid_lock); 8643 8644 return (0); 8645 } 8646 8647 static int 8648 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8649 { 8650 8651 MPASS(iq->set_tcb_rpl != NULL); 8652 return (iq->set_tcb_rpl(iq, rss, m)); 8653 } 8654 8655 static int 8656 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8657 { 8658 8659 MPASS(iq->l2t_write_rpl != NULL); 8660 return (iq->l2t_write_rpl(iq, rss, m)); 8661 } 8662 8663 static int 8664 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 8665 { 8666 int rc; 8667 8668 if (cntxt->cid > M_CTXTQID) 8669 return (EINVAL); 8670 8671 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 8672 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 8673 return (EINVAL); 8674 8675 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 8676 if (rc) 8677 return (rc); 8678 8679 if (sc->flags & FW_OK) { 8680 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 8681 &cntxt->data[0]); 8682 if (rc == 0) 8683 goto done; 8684 } 8685 8686 /* 8687 * Read via firmware failed or wasn't even attempted. Read directly via 8688 * the backdoor. 8689 */ 8690 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 8691 done: 8692 end_synchronized_op(sc, 0); 8693 return (rc); 8694 } 8695 8696 static int 8697 load_fw(struct adapter *sc, struct t4_data *fw) 8698 { 8699 int rc; 8700 uint8_t *fw_data; 8701 8702 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 8703 if (rc) 8704 return (rc); 8705 8706 if (sc->flags & FULL_INIT_DONE) { 8707 rc = EBUSY; 8708 goto done; 8709 } 8710 8711 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 8712 if (fw_data == NULL) { 8713 rc = ENOMEM; 8714 goto done; 8715 } 8716 8717 rc = copyin(fw->data, fw_data, fw->len); 8718 if (rc == 0) 8719 rc = -t4_load_fw(sc, fw_data, fw->len); 8720 8721 free(fw_data, M_CXGBE); 8722 done: 8723 end_synchronized_op(sc, 0); 8724 return (rc); 8725 } 8726 8727 static int 8728 load_cfg(struct adapter *sc, struct t4_data *cfg) 8729 { 8730 int rc; 8731 uint8_t *cfg_data = NULL; 8732 8733 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 8734 if (rc) 8735 return (rc); 8736 8737 if (cfg->len == 0) { 8738 /* clear */ 8739 rc = -t4_load_cfg(sc, NULL, 0); 8740 goto done; 8741 } 8742 8743 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 8744 if (cfg_data == NULL) { 8745 rc = ENOMEM; 8746 goto done; 8747 } 8748 8749 rc = copyin(cfg->data, cfg_data, cfg->len); 8750 if (rc == 0) 8751 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 8752 8753 free(cfg_data, M_CXGBE); 8754 done: 8755 end_synchronized_op(sc, 0); 8756 return (rc); 8757 } 8758 8759 #define MAX_READ_BUF_SIZE (128 * 1024) 8760 static int 8761 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 8762 { 8763 uint32_t addr, remaining, n; 8764 uint32_t *buf; 8765 int rc; 8766 uint8_t *dst; 8767 8768 rc = validate_mem_range(sc, mr->addr, mr->len); 8769 if (rc != 0) 8770 return (rc); 8771 8772 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 8773 addr = mr->addr; 8774 remaining = mr->len; 8775 dst = (void *)mr->data; 8776 8777 while (remaining) { 8778 n = min(remaining, MAX_READ_BUF_SIZE); 8779 read_via_memwin(sc, 2, addr, buf, n); 8780 8781 rc = copyout(buf, dst, n); 8782 if (rc != 0) 8783 break; 8784 8785 dst += n; 8786 remaining -= n; 8787 addr += n; 8788 } 8789 8790 free(buf, M_CXGBE); 8791 return (rc); 8792 } 8793 #undef MAX_READ_BUF_SIZE 8794 8795 static int 8796 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 8797 { 8798 int rc; 8799 8800 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 8801 return (EINVAL); 8802 8803 if (i2cd->len > sizeof(i2cd->data)) 8804 return (EFBIG); 8805 8806 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 8807 if (rc) 8808 return (rc); 8809 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 8810 i2cd->offset, i2cd->len, &i2cd->data[0]); 8811 end_synchronized_op(sc, 0); 8812 8813 return (rc); 8814 } 8815 8816 static int 8817 in_range(int val, int lo, int hi) 8818 { 8819 8820 return (val < 0 || (val <= hi && val >= lo)); 8821 } 8822 8823 static int 8824 set_sched_class_config(struct adapter *sc, int minmax) 8825 { 8826 int rc; 8827 8828 if (minmax < 0) 8829 return (EINVAL); 8830 8831 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc"); 8832 if (rc) 8833 return (rc); 8834 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1); 8835 end_synchronized_op(sc, 0); 8836 8837 return (rc); 8838 } 8839 8840 static int 8841 set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p, 8842 int sleep_ok) 8843 { 8844 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode; 8845 struct port_info *pi; 8846 struct tx_sched_class *tc; 8847 8848 if (p->level == SCHED_CLASS_LEVEL_CL_RL) 8849 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL; 8850 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR) 8851 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 8852 else if (p->level == SCHED_CLASS_LEVEL_CH_RL) 8853 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL; 8854 else 8855 return (EINVAL); 8856 8857 if (p->mode == SCHED_CLASS_MODE_CLASS) 8858 fw_mode = FW_SCHED_PARAMS_MODE_CLASS; 8859 else if (p->mode == SCHED_CLASS_MODE_FLOW) 8860 fw_mode = FW_SCHED_PARAMS_MODE_FLOW; 8861 else 8862 return (EINVAL); 8863 8864 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS) 8865 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE; 8866 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS) 8867 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE; 8868 else 8869 return (EINVAL); 8870 8871 if (p->ratemode == SCHED_CLASS_RATEMODE_REL) 8872 fw_ratemode = FW_SCHED_PARAMS_RATE_REL; 8873 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS) 8874 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS; 8875 else 8876 return (EINVAL); 8877 8878 /* Vet our parameters ... */ 8879 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1)) 8880 return (ERANGE); 8881 8882 pi = sc->port[sc->chan_map[p->channel]]; 8883 if (pi == NULL) 8884 return (ENXIO); 8885 MPASS(pi->tx_chan == p->channel); 8886 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */ 8887 8888 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) || 8889 !in_range(p->minrate, 0, top_speed) || 8890 !in_range(p->maxrate, 0, top_speed) || 8891 !in_range(p->weight, 0, 100)) 8892 return (ERANGE); 8893 8894 /* 8895 * Translate any unset parameters into the firmware's 8896 * nomenclature and/or fail the call if the parameters 8897 * are required ... 8898 */ 8899 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0) 8900 return (EINVAL); 8901 8902 if (p->minrate < 0) 8903 p->minrate = 0; 8904 if (p->maxrate < 0) { 8905 if (p->level == SCHED_CLASS_LEVEL_CL_RL || 8906 p->level == SCHED_CLASS_LEVEL_CH_RL) 8907 return (EINVAL); 8908 else 8909 p->maxrate = 0; 8910 } 8911 if (p->weight < 0) { 8912 if (p->level == SCHED_CLASS_LEVEL_CL_WRR) 8913 return (EINVAL); 8914 else 8915 p->weight = 0; 8916 } 8917 if (p->pktsize < 0) { 8918 if (p->level == SCHED_CLASS_LEVEL_CL_RL || 8919 p->level == SCHED_CLASS_LEVEL_CH_RL) 8920 return (EINVAL); 8921 else 8922 p->pktsize = 0; 8923 } 8924 8925 rc = begin_synchronized_op(sc, NULL, 8926 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp"); 8927 if (rc) 8928 return (rc); 8929 tc = &pi->tc[p->cl]; 8930 tc->params = *p; 8931 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode, 8932 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate, 8933 p->weight, p->pktsize, sleep_ok); 8934 if (rc == 0) 8935 tc->flags |= TX_SC_OK; 8936 else { 8937 /* 8938 * Unknown state at this point, see tc->params for what was 8939 * attempted. 8940 */ 8941 tc->flags &= ~TX_SC_OK; 8942 } 8943 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD); 8944 8945 return (rc); 8946 } 8947 8948 int 8949 t4_set_sched_class(struct adapter *sc, struct t4_sched_params *p) 8950 { 8951 8952 if (p->type != SCHED_CLASS_TYPE_PACKET) 8953 return (EINVAL); 8954 8955 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG) 8956 return (set_sched_class_config(sc, p->u.config.minmax)); 8957 8958 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS) 8959 return (set_sched_class_params(sc, &p->u.params, 1)); 8960 8961 return (EINVAL); 8962 } 8963 8964 int 8965 t4_set_sched_queue(struct adapter *sc, struct t4_sched_queue *p) 8966 { 8967 struct port_info *pi = NULL; 8968 struct vi_info *vi; 8969 struct sge_txq *txq; 8970 uint32_t fw_mnem, fw_queue, fw_class; 8971 int i, rc; 8972 8973 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq"); 8974 if (rc) 8975 return (rc); 8976 8977 if (p->port >= sc->params.nports) { 8978 rc = EINVAL; 8979 goto done; 8980 } 8981 8982 /* XXX: Only supported for the main VI. */ 8983 pi = sc->port[p->port]; 8984 vi = &pi->vi[0]; 8985 if (!(vi->flags & VI_INIT_DONE)) { 8986 /* tx queues not set up yet */ 8987 rc = EAGAIN; 8988 goto done; 8989 } 8990 8991 if (!in_range(p->queue, 0, vi->ntxq - 1) || 8992 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) { 8993 rc = EINVAL; 8994 goto done; 8995 } 8996 8997 /* 8998 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX 8999 * Scheduling Class in this case). 9000 */ 9001 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 9002 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH)); 9003 fw_class = p->cl < 0 ? 0xffffffff : p->cl; 9004 9005 /* 9006 * If op.queue is non-negative, then we're only changing the scheduling 9007 * on a single specified TX queue. 9008 */ 9009 if (p->queue >= 0) { 9010 txq = &sc->sge.txq[vi->first_txq + p->queue]; 9011 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id)); 9012 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, 9013 &fw_class); 9014 goto done; 9015 } 9016 9017 /* 9018 * Change the scheduling on all the TX queues for the 9019 * interface. 9020 */ 9021 for_each_txq(vi, i, txq) { 9022 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id)); 9023 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, 9024 &fw_class); 9025 if (rc) 9026 goto done; 9027 } 9028 9029 rc = 0; 9030 done: 9031 end_synchronized_op(sc, 0); 9032 return (rc); 9033 } 9034 9035 int 9036 t4_os_find_pci_capability(struct adapter *sc, int cap) 9037 { 9038 int i; 9039 9040 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9041 } 9042 9043 int 9044 t4_os_pci_save_state(struct adapter *sc) 9045 { 9046 device_t dev; 9047 struct pci_devinfo *dinfo; 9048 9049 dev = sc->dev; 9050 dinfo = device_get_ivars(dev); 9051 9052 pci_cfg_save(dev, dinfo, 0); 9053 return (0); 9054 } 9055 9056 int 9057 t4_os_pci_restore_state(struct adapter *sc) 9058 { 9059 device_t dev; 9060 struct pci_devinfo *dinfo; 9061 9062 dev = sc->dev; 9063 dinfo = device_get_ivars(dev); 9064 9065 pci_cfg_restore(dev, dinfo); 9066 return (0); 9067 } 9068 9069 void 9070 t4_os_portmod_changed(const struct adapter *sc, int idx) 9071 { 9072 struct port_info *pi = sc->port[idx]; 9073 struct vi_info *vi; 9074 struct ifnet *ifp; 9075 int v; 9076 static const char *mod_str[] = { 9077 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9078 }; 9079 9080 for_each_vi(pi, v, vi) { 9081 build_medialist(pi, &vi->media); 9082 } 9083 9084 ifp = pi->vi[0].ifp; 9085 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9086 if_printf(ifp, "transceiver unplugged.\n"); 9087 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9088 if_printf(ifp, "unknown transceiver inserted.\n"); 9089 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9090 if_printf(ifp, "unsupported transceiver inserted.\n"); 9091 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9092 if_printf(ifp, "%s transceiver inserted.\n", 9093 mod_str[pi->mod_type]); 9094 } else { 9095 if_printf(ifp, "transceiver (type %d) inserted.\n", 9096 pi->mod_type); 9097 } 9098 } 9099 9100 void 9101 t4_os_link_changed(struct adapter *sc, int idx, int link_stat) 9102 { 9103 struct port_info *pi = sc->port[idx]; 9104 struct vi_info *vi; 9105 struct ifnet *ifp; 9106 int v; 9107 9108 for_each_vi(pi, v, vi) { 9109 ifp = vi->ifp; 9110 if (ifp == NULL) 9111 continue; 9112 9113 if (link_stat) { 9114 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed); 9115 if_link_state_change(ifp, LINK_STATE_UP); 9116 } else { 9117 if_link_state_change(ifp, LINK_STATE_DOWN); 9118 } 9119 } 9120 } 9121 9122 void 9123 t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9124 { 9125 struct adapter *sc; 9126 9127 sx_slock(&t4_list_lock); 9128 SLIST_FOREACH(sc, &t4_list, link) { 9129 /* 9130 * func should not make any assumptions about what state sc is 9131 * in - the only guarantee is that sc->sc_lock is a valid lock. 9132 */ 9133 func(sc, arg); 9134 } 9135 sx_sunlock(&t4_list_lock); 9136 } 9137 9138 static int 9139 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9140 struct thread *td) 9141 { 9142 int rc; 9143 struct adapter *sc = dev->si_drv1; 9144 9145 rc = priv_check(td, PRIV_DRIVER); 9146 if (rc != 0) 9147 return (rc); 9148 9149 switch (cmd) { 9150 case CHELSIO_T4_GETREG: { 9151 struct t4_reg *edata = (struct t4_reg *)data; 9152 9153 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9154 return (EFAULT); 9155 9156 if (edata->size == 4) 9157 edata->val = t4_read_reg(sc, edata->addr); 9158 else if (edata->size == 8) 9159 edata->val = t4_read_reg64(sc, edata->addr); 9160 else 9161 return (EINVAL); 9162 9163 break; 9164 } 9165 case CHELSIO_T4_SETREG: { 9166 struct t4_reg *edata = (struct t4_reg *)data; 9167 9168 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9169 return (EFAULT); 9170 9171 if (edata->size == 4) { 9172 if (edata->val & 0xffffffff00000000) 9173 return (EINVAL); 9174 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9175 } else if (edata->size == 8) 9176 t4_write_reg64(sc, edata->addr, edata->val); 9177 else 9178 return (EINVAL); 9179 break; 9180 } 9181 case CHELSIO_T4_REGDUMP: { 9182 struct t4_regdump *regs = (struct t4_regdump *)data; 9183 int reglen = t4_get_regs_len(sc); 9184 uint8_t *buf; 9185 9186 if (regs->len < reglen) { 9187 regs->len = reglen; /* hint to the caller */ 9188 return (ENOBUFS); 9189 } 9190 9191 regs->len = reglen; 9192 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 9193 get_regs(sc, regs, buf); 9194 rc = copyout(buf, regs->data, reglen); 9195 free(buf, M_CXGBE); 9196 break; 9197 } 9198 case CHELSIO_T4_GET_FILTER_MODE: 9199 rc = get_filter_mode(sc, (uint32_t *)data); 9200 break; 9201 case CHELSIO_T4_SET_FILTER_MODE: 9202 rc = set_filter_mode(sc, *(uint32_t *)data); 9203 break; 9204 case CHELSIO_T4_GET_FILTER: 9205 rc = get_filter(sc, (struct t4_filter *)data); 9206 break; 9207 case CHELSIO_T4_SET_FILTER: 9208 rc = set_filter(sc, (struct t4_filter *)data); 9209 break; 9210 case CHELSIO_T4_DEL_FILTER: 9211 rc = del_filter(sc, (struct t4_filter *)data); 9212 break; 9213 case CHELSIO_T4_GET_SGE_CONTEXT: 9214 rc = get_sge_context(sc, (struct t4_sge_context *)data); 9215 break; 9216 case CHELSIO_T4_LOAD_FW: 9217 rc = load_fw(sc, (struct t4_data *)data); 9218 break; 9219 case CHELSIO_T4_GET_MEM: 9220 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 9221 break; 9222 case CHELSIO_T4_GET_I2C: 9223 rc = read_i2c(sc, (struct t4_i2c_data *)data); 9224 break; 9225 case CHELSIO_T4_CLEAR_STATS: { 9226 int i, v; 9227 u_int port_id = *(uint32_t *)data; 9228 struct port_info *pi; 9229 struct vi_info *vi; 9230 9231 if (port_id >= sc->params.nports) 9232 return (EINVAL); 9233 pi = sc->port[port_id]; 9234 if (pi == NULL) 9235 return (EIO); 9236 9237 /* MAC stats */ 9238 t4_clr_port_stats(sc, pi->tx_chan); 9239 pi->tx_parse_error = 0; 9240 mtx_lock(&sc->reg_lock); 9241 for_each_vi(pi, v, vi) { 9242 if (vi->flags & VI_INIT_DONE) 9243 t4_clr_vi_stats(sc, vi->viid); 9244 } 9245 mtx_unlock(&sc->reg_lock); 9246 9247 /* 9248 * Since this command accepts a port, clear stats for 9249 * all VIs on this port. 9250 */ 9251 for_each_vi(pi, v, vi) { 9252 if (vi->flags & VI_INIT_DONE) { 9253 struct sge_rxq *rxq; 9254 struct sge_txq *txq; 9255 struct sge_wrq *wrq; 9256 9257 for_each_rxq(vi, i, rxq) { 9258 #if defined(INET) || defined(INET6) 9259 rxq->lro.lro_queued = 0; 9260 rxq->lro.lro_flushed = 0; 9261 #endif 9262 rxq->rxcsum = 0; 9263 rxq->vlan_extraction = 0; 9264 } 9265 9266 for_each_txq(vi, i, txq) { 9267 txq->txcsum = 0; 9268 txq->tso_wrs = 0; 9269 txq->vlan_insertion = 0; 9270 txq->imm_wrs = 0; 9271 txq->sgl_wrs = 0; 9272 txq->txpkt_wrs = 0; 9273 txq->txpkts0_wrs = 0; 9274 txq->txpkts1_wrs = 0; 9275 txq->txpkts0_pkts = 0; 9276 txq->txpkts1_pkts = 0; 9277 mp_ring_reset_stats(txq->r); 9278 } 9279 9280 #ifdef TCP_OFFLOAD 9281 /* nothing to clear for each ofld_rxq */ 9282 9283 for_each_ofld_txq(vi, i, wrq) { 9284 wrq->tx_wrs_direct = 0; 9285 wrq->tx_wrs_copied = 0; 9286 } 9287 #endif 9288 9289 if (IS_MAIN_VI(vi)) { 9290 wrq = &sc->sge.ctrlq[pi->port_id]; 9291 wrq->tx_wrs_direct = 0; 9292 wrq->tx_wrs_copied = 0; 9293 } 9294 } 9295 } 9296 break; 9297 } 9298 case CHELSIO_T4_SCHED_CLASS: 9299 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9300 break; 9301 case CHELSIO_T4_SCHED_QUEUE: 9302 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9303 break; 9304 case CHELSIO_T4_GET_TRACER: 9305 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9306 break; 9307 case CHELSIO_T4_SET_TRACER: 9308 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9309 break; 9310 case CHELSIO_T4_LOAD_CFG: 9311 rc = load_cfg(sc, (struct t4_data *)data); 9312 break; 9313 default: 9314 rc = ENOTTY; 9315 } 9316 9317 return (rc); 9318 } 9319 9320 void 9321 t4_db_full(struct adapter *sc) 9322 { 9323 9324 CXGBE_UNIMPLEMENTED(__func__); 9325 } 9326 9327 void 9328 t4_db_dropped(struct adapter *sc) 9329 { 9330 9331 CXGBE_UNIMPLEMENTED(__func__); 9332 } 9333 9334 #ifdef TCP_OFFLOAD 9335 static int 9336 toe_capability(struct vi_info *vi, int enable) 9337 { 9338 int rc; 9339 struct port_info *pi = vi->pi; 9340 struct adapter *sc = pi->adapter; 9341 9342 ASSERT_SYNCHRONIZED_OP(sc); 9343 9344 if (!is_offload(sc)) 9345 return (ENODEV); 9346 9347 if (enable) { 9348 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9349 /* TOE is already enabled. */ 9350 return (0); 9351 } 9352 9353 /* 9354 * We need the port's queues around so that we're able to send 9355 * and receive CPLs to/from the TOE even if the ifnet for this 9356 * port has never been UP'd administratively. 9357 */ 9358 if (!(vi->flags & VI_INIT_DONE)) { 9359 rc = vi_full_init(vi); 9360 if (rc) 9361 return (rc); 9362 } 9363 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9364 rc = vi_full_init(&pi->vi[0]); 9365 if (rc) 9366 return (rc); 9367 } 9368 9369 if (isset(&sc->offload_map, pi->port_id)) { 9370 /* TOE is enabled on another VI of this port. */ 9371 pi->uld_vis++; 9372 return (0); 9373 } 9374 9375 if (!uld_active(sc, ULD_TOM)) { 9376 rc = t4_activate_uld(sc, ULD_TOM); 9377 if (rc == EAGAIN) { 9378 log(LOG_WARNING, 9379 "You must kldload t4_tom.ko before trying " 9380 "to enable TOE on a cxgbe interface.\n"); 9381 } 9382 if (rc != 0) 9383 return (rc); 9384 KASSERT(sc->tom_softc != NULL, 9385 ("%s: TOM activated but softc NULL", __func__)); 9386 KASSERT(uld_active(sc, ULD_TOM), 9387 ("%s: TOM activated but flag not set", __func__)); 9388 } 9389 9390 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9391 if (!uld_active(sc, ULD_IWARP)) 9392 (void) t4_activate_uld(sc, ULD_IWARP); 9393 if (!uld_active(sc, ULD_ISCSI)) 9394 (void) t4_activate_uld(sc, ULD_ISCSI); 9395 9396 pi->uld_vis++; 9397 setbit(&sc->offload_map, pi->port_id); 9398 } else { 9399 pi->uld_vis--; 9400 9401 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9402 return (0); 9403 9404 KASSERT(uld_active(sc, ULD_TOM), 9405 ("%s: TOM never initialized?", __func__)); 9406 clrbit(&sc->offload_map, pi->port_id); 9407 } 9408 9409 return (0); 9410 } 9411 9412 /* 9413 * Add an upper layer driver to the global list. 9414 */ 9415 int 9416 t4_register_uld(struct uld_info *ui) 9417 { 9418 int rc = 0; 9419 struct uld_info *u; 9420 9421 sx_xlock(&t4_uld_list_lock); 9422 SLIST_FOREACH(u, &t4_uld_list, link) { 9423 if (u->uld_id == ui->uld_id) { 9424 rc = EEXIST; 9425 goto done; 9426 } 9427 } 9428 9429 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 9430 ui->refcount = 0; 9431 done: 9432 sx_xunlock(&t4_uld_list_lock); 9433 return (rc); 9434 } 9435 9436 int 9437 t4_unregister_uld(struct uld_info *ui) 9438 { 9439 int rc = EINVAL; 9440 struct uld_info *u; 9441 9442 sx_xlock(&t4_uld_list_lock); 9443 9444 SLIST_FOREACH(u, &t4_uld_list, link) { 9445 if (u == ui) { 9446 if (ui->refcount > 0) { 9447 rc = EBUSY; 9448 goto done; 9449 } 9450 9451 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 9452 rc = 0; 9453 goto done; 9454 } 9455 } 9456 done: 9457 sx_xunlock(&t4_uld_list_lock); 9458 return (rc); 9459 } 9460 9461 int 9462 t4_activate_uld(struct adapter *sc, int id) 9463 { 9464 int rc; 9465 struct uld_info *ui; 9466 9467 ASSERT_SYNCHRONIZED_OP(sc); 9468 9469 if (id < 0 || id > ULD_MAX) 9470 return (EINVAL); 9471 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 9472 9473 sx_slock(&t4_uld_list_lock); 9474 9475 SLIST_FOREACH(ui, &t4_uld_list, link) { 9476 if (ui->uld_id == id) { 9477 if (!(sc->flags & FULL_INIT_DONE)) { 9478 rc = adapter_full_init(sc); 9479 if (rc != 0) 9480 break; 9481 } 9482 9483 rc = ui->activate(sc); 9484 if (rc == 0) { 9485 setbit(&sc->active_ulds, id); 9486 ui->refcount++; 9487 } 9488 break; 9489 } 9490 } 9491 9492 sx_sunlock(&t4_uld_list_lock); 9493 9494 return (rc); 9495 } 9496 9497 int 9498 t4_deactivate_uld(struct adapter *sc, int id) 9499 { 9500 int rc; 9501 struct uld_info *ui; 9502 9503 ASSERT_SYNCHRONIZED_OP(sc); 9504 9505 if (id < 0 || id > ULD_MAX) 9506 return (EINVAL); 9507 rc = ENXIO; 9508 9509 sx_slock(&t4_uld_list_lock); 9510 9511 SLIST_FOREACH(ui, &t4_uld_list, link) { 9512 if (ui->uld_id == id) { 9513 rc = ui->deactivate(sc); 9514 if (rc == 0) { 9515 clrbit(&sc->active_ulds, id); 9516 ui->refcount--; 9517 } 9518 break; 9519 } 9520 } 9521 9522 sx_sunlock(&t4_uld_list_lock); 9523 9524 return (rc); 9525 } 9526 9527 int 9528 uld_active(struct adapter *sc, int uld_id) 9529 { 9530 9531 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 9532 9533 return (isset(&sc->active_ulds, uld_id)); 9534 } 9535 #endif 9536 9537 /* 9538 * t = ptr to tunable. 9539 * nc = number of CPUs. 9540 * c = compiled in default for that tunable. 9541 */ 9542 static void 9543 calculate_nqueues(int *t, int nc, const int c) 9544 { 9545 int nq; 9546 9547 if (*t > 0) 9548 return; 9549 nq = *t < 0 ? -*t : c; 9550 *t = min(nc, nq); 9551 } 9552 9553 /* 9554 * Come up with reasonable defaults for some of the tunables, provided they're 9555 * not set by the user (in which case we'll use the values as is). 9556 */ 9557 static void 9558 tweak_tunables(void) 9559 { 9560 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 9561 9562 if (t4_ntxq10g < 1) { 9563 #ifdef RSS 9564 t4_ntxq10g = rss_getnumbuckets(); 9565 #else 9566 calculate_nqueues(&t4_ntxq10g, nc, NTXQ_10G); 9567 #endif 9568 } 9569 9570 if (t4_ntxq1g < 1) { 9571 #ifdef RSS 9572 /* XXX: way too many for 1GbE? */ 9573 t4_ntxq1g = rss_getnumbuckets(); 9574 #else 9575 calculate_nqueues(&t4_ntxq1g, nc, NTXQ_1G); 9576 #endif 9577 } 9578 9579 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 9580 9581 if (t4_nrxq10g < 1) { 9582 #ifdef RSS 9583 t4_nrxq10g = rss_getnumbuckets(); 9584 #else 9585 calculate_nqueues(&t4_nrxq10g, nc, NRXQ_10G); 9586 #endif 9587 } 9588 9589 if (t4_nrxq1g < 1) { 9590 #ifdef RSS 9591 /* XXX: way too many for 1GbE? */ 9592 t4_nrxq1g = rss_getnumbuckets(); 9593 #else 9594 calculate_nqueues(&t4_nrxq1g, nc, NRXQ_1G); 9595 #endif 9596 } 9597 9598 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 9599 9600 #ifdef TCP_OFFLOAD 9601 calculate_nqueues(&t4_nofldtxq10g, nc, NOFLDTXQ_10G); 9602 calculate_nqueues(&t4_nofldtxq1g, nc, NOFLDTXQ_1G); 9603 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 9604 calculate_nqueues(&t4_nofldrxq10g, nc, NOFLDRXQ_10G); 9605 calculate_nqueues(&t4_nofldrxq1g, nc, NOFLDRXQ_1G); 9606 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 9607 9608 if (t4_toecaps_allowed == -1) 9609 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 9610 9611 if (t4_rdmacaps_allowed == -1) { 9612 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 9613 FW_CAPS_CONFIG_RDMA_RDMAC; 9614 } 9615 9616 if (t4_iscsicaps_allowed == -1) { 9617 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 9618 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 9619 FW_CAPS_CONFIG_ISCSI_T10DIF; 9620 } 9621 #else 9622 if (t4_toecaps_allowed == -1) 9623 t4_toecaps_allowed = 0; 9624 9625 if (t4_rdmacaps_allowed == -1) 9626 t4_rdmacaps_allowed = 0; 9627 9628 if (t4_iscsicaps_allowed == -1) 9629 t4_iscsicaps_allowed = 0; 9630 #endif 9631 9632 #ifdef DEV_NETMAP 9633 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 9634 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 9635 #endif 9636 9637 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS) 9638 t4_tmr_idx_10g = TMR_IDX_10G; 9639 9640 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS) 9641 t4_pktc_idx_10g = PKTC_IDX_10G; 9642 9643 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS) 9644 t4_tmr_idx_1g = TMR_IDX_1G; 9645 9646 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS) 9647 t4_pktc_idx_1g = PKTC_IDX_1G; 9648 9649 if (t4_qsize_txq < 128) 9650 t4_qsize_txq = 128; 9651 9652 if (t4_qsize_rxq < 128) 9653 t4_qsize_rxq = 128; 9654 while (t4_qsize_rxq & 7) 9655 t4_qsize_rxq++; 9656 9657 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 9658 } 9659 9660 #ifdef DDB 9661 static void 9662 t4_dump_tcb(struct adapter *sc, int tid) 9663 { 9664 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 9665 9666 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 9667 save = t4_read_reg(sc, reg); 9668 base = sc->memwin[2].mw_base; 9669 9670 /* Dump TCB for the tid */ 9671 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9672 tcb_addr += tid * TCB_SIZE; 9673 9674 if (is_t4(sc)) { 9675 pf = 0; 9676 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 9677 } else { 9678 pf = V_PFNUM(sc->pf); 9679 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 9680 } 9681 t4_write_reg(sc, reg, win_pos | pf); 9682 t4_read_reg(sc, reg); 9683 9684 off = tcb_addr - win_pos; 9685 for (i = 0; i < 4; i++) { 9686 uint32_t buf[8]; 9687 for (j = 0; j < 8; j++, off += 4) 9688 buf[j] = htonl(t4_read_reg(sc, base + off)); 9689 9690 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 9691 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 9692 buf[7]); 9693 } 9694 9695 t4_write_reg(sc, reg, save); 9696 t4_read_reg(sc, reg); 9697 } 9698 9699 static void 9700 t4_dump_devlog(struct adapter *sc) 9701 { 9702 struct devlog_params *dparams = &sc->params.devlog; 9703 struct fw_devlog_e e; 9704 int i, first, j, m, nentries, rc; 9705 uint64_t ftstamp = UINT64_MAX; 9706 9707 if (dparams->start == 0) { 9708 db_printf("devlog params not valid\n"); 9709 return; 9710 } 9711 9712 nentries = dparams->size / sizeof(struct fw_devlog_e); 9713 m = fwmtype_to_hwmtype(dparams->memtype); 9714 9715 /* Find the first entry. */ 9716 first = -1; 9717 for (i = 0; i < nentries && !db_pager_quit; i++) { 9718 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9719 sizeof(e), (void *)&e); 9720 if (rc != 0) 9721 break; 9722 9723 if (e.timestamp == 0) 9724 break; 9725 9726 e.timestamp = be64toh(e.timestamp); 9727 if (e.timestamp < ftstamp) { 9728 ftstamp = e.timestamp; 9729 first = i; 9730 } 9731 } 9732 9733 if (first == -1) 9734 return; 9735 9736 i = first; 9737 do { 9738 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9739 sizeof(e), (void *)&e); 9740 if (rc != 0) 9741 return; 9742 9743 if (e.timestamp == 0) 9744 return; 9745 9746 e.timestamp = be64toh(e.timestamp); 9747 e.seqno = be32toh(e.seqno); 9748 for (j = 0; j < 8; j++) 9749 e.params[j] = be32toh(e.params[j]); 9750 9751 db_printf("%10d %15ju %8s %8s ", 9752 e.seqno, e.timestamp, 9753 (e.level < nitems(devlog_level_strings) ? 9754 devlog_level_strings[e.level] : "UNKNOWN"), 9755 (e.facility < nitems(devlog_facility_strings) ? 9756 devlog_facility_strings[e.facility] : "UNKNOWN")); 9757 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 9758 e.params[3], e.params[4], e.params[5], e.params[6], 9759 e.params[7]); 9760 9761 if (++i == nentries) 9762 i = 0; 9763 } while (i != first && !db_pager_quit); 9764 } 9765 9766 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 9767 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 9768 9769 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 9770 { 9771 device_t dev; 9772 int t; 9773 bool valid; 9774 9775 valid = false; 9776 t = db_read_token(); 9777 if (t == tIDENT) { 9778 dev = device_lookup_by_name(db_tok_string); 9779 valid = true; 9780 } 9781 db_skip_to_eol(); 9782 if (!valid) { 9783 db_printf("usage: show t4 devlog <nexus>\n"); 9784 return; 9785 } 9786 9787 if (dev == NULL) { 9788 db_printf("device not found\n"); 9789 return; 9790 } 9791 9792 t4_dump_devlog(device_get_softc(dev)); 9793 } 9794 9795 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 9796 { 9797 device_t dev; 9798 int radix, tid, t; 9799 bool valid; 9800 9801 valid = false; 9802 radix = db_radix; 9803 db_radix = 10; 9804 t = db_read_token(); 9805 if (t == tIDENT) { 9806 dev = device_lookup_by_name(db_tok_string); 9807 t = db_read_token(); 9808 if (t == tNUMBER) { 9809 tid = db_tok_number; 9810 valid = true; 9811 } 9812 } 9813 db_radix = radix; 9814 db_skip_to_eol(); 9815 if (!valid) { 9816 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 9817 return; 9818 } 9819 9820 if (dev == NULL) { 9821 db_printf("device not found\n"); 9822 return; 9823 } 9824 if (tid < 0) { 9825 db_printf("invalid tid\n"); 9826 return; 9827 } 9828 9829 t4_dump_tcb(device_get_softc(dev), tid); 9830 } 9831 #endif 9832 9833 static struct sx mlu; /* mod load unload */ 9834 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 9835 9836 static int 9837 mod_event(module_t mod, int cmd, void *arg) 9838 { 9839 int rc = 0; 9840 static int loaded = 0; 9841 9842 switch (cmd) { 9843 case MOD_LOAD: 9844 sx_xlock(&mlu); 9845 if (loaded++ == 0) { 9846 t4_sge_modload(); 9847 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl); 9848 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl); 9849 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 9850 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 9851 sx_init(&t4_list_lock, "T4/T5 adapters"); 9852 SLIST_INIT(&t4_list); 9853 #ifdef TCP_OFFLOAD 9854 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 9855 SLIST_INIT(&t4_uld_list); 9856 #endif 9857 t4_tracer_modload(); 9858 tweak_tunables(); 9859 } 9860 sx_xunlock(&mlu); 9861 break; 9862 9863 case MOD_UNLOAD: 9864 sx_xlock(&mlu); 9865 if (--loaded == 0) { 9866 int tries; 9867 9868 sx_slock(&t4_list_lock); 9869 if (!SLIST_EMPTY(&t4_list)) { 9870 rc = EBUSY; 9871 sx_sunlock(&t4_list_lock); 9872 goto done_unload; 9873 } 9874 #ifdef TCP_OFFLOAD 9875 sx_slock(&t4_uld_list_lock); 9876 if (!SLIST_EMPTY(&t4_uld_list)) { 9877 rc = EBUSY; 9878 sx_sunlock(&t4_uld_list_lock); 9879 sx_sunlock(&t4_list_lock); 9880 goto done_unload; 9881 } 9882 #endif 9883 tries = 0; 9884 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 9885 uprintf("%ju clusters with custom free routine " 9886 "still is use.\n", t4_sge_extfree_refs()); 9887 pause("t4unload", 2 * hz); 9888 } 9889 #ifdef TCP_OFFLOAD 9890 sx_sunlock(&t4_uld_list_lock); 9891 #endif 9892 sx_sunlock(&t4_list_lock); 9893 9894 if (t4_sge_extfree_refs() == 0) { 9895 t4_tracer_modunload(); 9896 #ifdef TCP_OFFLOAD 9897 sx_destroy(&t4_uld_list_lock); 9898 #endif 9899 sx_destroy(&t4_list_lock); 9900 t4_sge_modunload(); 9901 loaded = 0; 9902 } else { 9903 rc = EBUSY; 9904 loaded++; /* undo earlier decrement */ 9905 } 9906 } 9907 done_unload: 9908 sx_xunlock(&mlu); 9909 break; 9910 } 9911 9912 return (rc); 9913 } 9914 9915 static devclass_t t4_devclass, t5_devclass, t6_devclass; 9916 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 9917 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 9918 9919 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 9920 MODULE_VERSION(t4nex, 1); 9921 MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 9922 #ifdef DEV_NETMAP 9923 MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 9924 #endif /* DEV_NETMAP */ 9925 9926 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 9927 MODULE_VERSION(t5nex, 1); 9928 MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 9929 #ifdef DEV_NETMAP 9930 MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 9931 #endif /* DEV_NETMAP */ 9932 9933 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 9934 MODULE_VERSION(t6nex, 1); 9935 MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 9936 #ifdef DEV_NETMAP 9937 MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 9938 #endif /* DEV_NETMAP */ 9939 9940 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 9941 MODULE_VERSION(cxgbe, 1); 9942 9943 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 9944 MODULE_VERSION(cxl, 1); 9945 9946 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 9947 MODULE_VERSION(cc, 1); 9948 9949 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 9950 MODULE_VERSION(vcxgbe, 1); 9951 9952 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 9953 MODULE_VERSION(vcxl, 1); 9954 9955 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 9956 MODULE_VERSION(vcc, 1); 9957