1 /*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #ifdef DEV_NETMAP 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/lock.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/selinfo.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <machine/bus.h> 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_var.h> 49 #include <net/if_clone.h> 50 #include <net/if_types.h> 51 #include <net/netmap.h> 52 #include <dev/netmap/netmap_kern.h> 53 54 #include "common/common.h" 55 #include "common/t4_regs.h" 56 #include "common/t4_regs_values.h" 57 58 extern int fl_pad; /* XXXNM */ 59 60 /* 61 * 0 = normal netmap rx 62 * 1 = black hole 63 * 2 = supermassive black hole (buffer packing enabled) 64 */ 65 int black_hole = 0; 66 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0, 67 "Sink incoming packets."); 68 69 int rx_ndesc = 256; 70 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN, 71 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated."); 72 73 int rx_nframes = 64; 74 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN, 75 &rx_nframes, 0, "max # of frames received before waking up netmap rx."); 76 77 int holdoff_tmr_idx = 2; 78 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN, 79 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues."); 80 81 /* 82 * Congestion drops. 83 * -1: no congestion feedback (not recommended). 84 * 0: backpressure the channel instead of dropping packets right away. 85 * 1: no backpressure, drop packets for the congested queue immediately. 86 */ 87 static int nm_cong_drop = 1; 88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RDTUN, 89 &nm_cong_drop, 0, 90 "Congestion control for netmap rx queues (0 = backpressure, 1 = drop"); 91 92 int starve_fl = 0; 93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN, 94 &starve_fl, 0, "Don't ring fl db for netmap rx queues."); 95 96 /* 97 * Try to process tx credits in bulk. This may cause a delay in the return of 98 * tx credits and is suitable for bursty or non-stop tx only. 99 */ 100 int lazy_tx_credit_flush = 1; 101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN, 102 &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues."); 103 104 /* 105 * Split the netmap rx queues into two groups that populate separate halves of 106 * the RSS indirection table. This allows filters with hashmask to steer to a 107 * particular group of queues. 108 */ 109 static int nm_split_rss = 0; 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN, 111 &nm_split_rss, 0, "Split the netmap rx queues into two groups."); 112 113 static int 114 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong) 115 { 116 int rc, cntxt_id, i; 117 __be32 v; 118 struct adapter *sc = vi->pi->adapter; 119 struct sge_params *sp = &sc->params.sge; 120 struct netmap_adapter *na = NA(vi->ifp); 121 struct fw_iq_cmd c; 122 123 MPASS(na != NULL); 124 MPASS(nm_rxq->iq_desc != NULL); 125 MPASS(nm_rxq->fl_desc != NULL); 126 127 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE); 128 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len); 129 130 bzero(&c, sizeof(c)); 131 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 132 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 133 V_FW_IQ_CMD_VFN(0)); 134 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 135 FW_LEN16(c)); 136 MPASS(!forwarding_intr_to_fwq(sc)); 137 KASSERT(nm_rxq->intr_idx < sc->intr_count, 138 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx)); 139 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx); 140 c.type_to_iqandstindex = htobe32(v | 141 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 142 V_FW_IQ_CMD_VIID(vi->viid) | 143 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 144 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 145 F_FW_IQ_CMD_IQGTSMODE | 146 V_FW_IQ_CMD_IQINTCNTTHRESH(0) | 147 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 148 c.iqsize = htobe16(vi->qsize_rxq); 149 c.iqaddr = htobe64(nm_rxq->iq_ba); 150 if (cong >= 0) { 151 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | 152 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF | 153 F_FW_IQ_CMD_FL0CONGEN); 154 } 155 c.iqns_to_fl0congen |= 156 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 157 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 158 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 159 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 160 c.fl0dcaen_to_fl0cidxfthresh = 161 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 162 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 163 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 164 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 165 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 166 c.fl0addr = htobe64(nm_rxq->fl_ba); 167 168 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 169 if (rc != 0) { 170 device_printf(sc->dev, 171 "failed to create netmap ingress queue: %d\n", rc); 172 return (rc); 173 } 174 175 nm_rxq->iq_cidx = 0; 176 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE); 177 nm_rxq->iq_gen = F_RSPD_GEN; 178 nm_rxq->iq_cntxt_id = be16toh(c.iqid); 179 nm_rxq->iq_abs_id = be16toh(c.physiqid); 180 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start; 181 if (cntxt_id >= sc->sge.niq) { 182 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)", 183 __func__, cntxt_id, sc->sge.niq - 1); 184 } 185 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq; 186 187 nm_rxq->fl_cntxt_id = be16toh(c.fl0id); 188 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 189 MPASS(nm_rxq->fl_sidx == na->num_rx_desc); 190 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start; 191 if (cntxt_id >= sc->sge.neq) { 192 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 193 __func__, cntxt_id, sc->sge.neq - 1); 194 } 195 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 196 197 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 198 sc->chip_params->sge_fl_db; 199 200 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) { 201 uint32_t param, val; 202 203 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 204 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 205 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 206 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 207 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 208 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 209 if (cong == 0) 210 val = 1 << 19; 211 else { 212 val = 2 << 19; 213 for (i = 0; i < 4; i++) { 214 if (cong & (1 << i)) 215 val |= 1 << (i << 2); 216 } 217 } 218 219 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 220 if (rc != 0) { 221 /* report error but carry on */ 222 device_printf(sc->dev, 223 "failed to set congestion manager context for " 224 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc); 225 } 226 } 227 228 t4_write_reg(sc, sc->sge_gts_reg, 229 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 230 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 231 232 return (rc); 233 } 234 235 static int 236 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 237 { 238 struct adapter *sc = vi->pi->adapter; 239 int rc; 240 241 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 242 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 243 if (rc != 0) 244 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n", 245 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc); 246 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 247 return (rc); 248 } 249 250 static int 251 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 252 { 253 int rc, cntxt_id; 254 size_t len; 255 struct adapter *sc = vi->pi->adapter; 256 struct netmap_adapter *na = NA(vi->ifp); 257 struct fw_eq_eth_cmd c; 258 259 MPASS(na != NULL); 260 MPASS(nm_txq->desc != NULL); 261 262 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 263 bzero(nm_txq->desc, len); 264 265 bzero(&c, sizeof(c)); 266 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 267 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 268 V_FW_EQ_ETH_CMD_VFN(0)); 269 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 270 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 271 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 272 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 273 c.fetchszm_to_iqid = 274 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 275 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 276 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id)); 277 c.dcaen_to_eqsize = 278 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 279 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 280 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 281 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE)); 282 c.eqaddr = htobe64(nm_txq->ba); 283 284 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 285 if (rc != 0) { 286 device_printf(vi->dev, 287 "failed to create netmap egress queue: %d\n", rc); 288 return (rc); 289 } 290 291 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 292 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start; 293 if (cntxt_id >= sc->sge.neq) 294 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__, 295 cntxt_id, sc->sge.neq - 1); 296 sc->sge.eqmap[cntxt_id] = (void *)nm_txq; 297 298 nm_txq->pidx = nm_txq->cidx = 0; 299 MPASS(nm_txq->sidx == na->num_tx_desc); 300 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0; 301 302 nm_txq->doorbells = sc->doorbells; 303 if (isset(&nm_txq->doorbells, DOORBELL_UDB) || 304 isset(&nm_txq->doorbells, DOORBELL_UDBWC) || 305 isset(&nm_txq->doorbells, DOORBELL_WCWR)) { 306 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 307 uint32_t mask = (1 << s_qpp) - 1; 308 volatile uint8_t *udb; 309 310 udb = sc->udbs_base + UDBS_DB_OFFSET; 311 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT; 312 nm_txq->udb_qid = nm_txq->cntxt_id & mask; 313 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 314 clrbit(&nm_txq->doorbells, DOORBELL_WCWR); 315 else { 316 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT; 317 nm_txq->udb_qid = 0; 318 } 319 nm_txq->udb = (volatile void *)udb; 320 } 321 322 return (rc); 323 } 324 325 static int 326 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 327 { 328 struct adapter *sc = vi->pi->adapter; 329 int rc; 330 331 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 332 if (rc != 0) 333 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__, 334 nm_txq->cntxt_id, rc); 335 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 336 return (rc); 337 } 338 339 static int 340 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 341 struct netmap_adapter *na) 342 { 343 struct netmap_slot *slot; 344 struct netmap_kring *kring; 345 struct sge_nm_rxq *nm_rxq; 346 struct sge_nm_txq *nm_txq; 347 int rc, i, j, hwidx, defq, nrssq; 348 struct rx_buf_info *rxb; 349 350 ASSERT_SYNCHRONIZED_OP(sc); 351 352 if ((vi->flags & VI_INIT_DONE) == 0 || 353 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 354 return (EAGAIN); 355 356 rxb = &sc->sge.rx_buf_info[0]; 357 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 358 if (rxb->size1 == NETMAP_BUF_SIZE(na)) { 359 hwidx = rxb->hwidx1; 360 break; 361 } 362 if (rxb->size2 == NETMAP_BUF_SIZE(na)) { 363 hwidx = rxb->hwidx2; 364 break; 365 } 366 } 367 if (i >= SW_ZONE_SIZES) { 368 if_printf(ifp, "no hwidx for netmap buffer size %d.\n", 369 NETMAP_BUF_SIZE(na)); 370 return (ENXIO); 371 } 372 373 /* Must set caps before calling netmap_reset */ 374 nm_set_native_flags(na); 375 376 for_each_nm_rxq(vi, i, nm_rxq) { 377 kring = na->rx_rings[nm_rxq->nid]; 378 if (!nm_kring_pending_on(kring) || 379 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID) 380 continue; 381 382 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop)); 383 nm_rxq->fl_hwidx = hwidx; 384 slot = netmap_reset(na, NR_RX, i, 0); 385 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 386 387 /* We deal with 8 bufs at a time */ 388 MPASS((na->num_rx_desc & 7) == 0); 389 MPASS(na->num_rx_desc == nm_rxq->fl_sidx); 390 for (j = 0; j < nm_rxq->fl_sidx; j++) { 391 uint64_t ba; 392 393 PNMB(na, &slot[j], &ba); 394 MPASS(ba != 0); 395 nm_rxq->fl_desc[j] = htobe64(ba | hwidx); 396 } 397 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8; 398 MPASS((j & 7) == 0); 399 j /= 8; /* driver pidx to hardware pidx */ 400 wmb(); 401 t4_write_reg(sc, sc->sge_kdoorbell_reg, 402 nm_rxq->fl_db_val | V_PIDX(j)); 403 404 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON); 405 } 406 407 for_each_nm_txq(vi, i, nm_txq) { 408 kring = na->tx_rings[nm_txq->nid]; 409 if (!nm_kring_pending_on(kring) || 410 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID) 411 continue; 412 413 alloc_nm_txq_hwq(vi, nm_txq); 414 slot = netmap_reset(na, NR_TX, i, 0); 415 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 416 } 417 418 if (vi->nm_rss == NULL) { 419 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE, 420 M_ZERO | M_WAITOK); 421 } 422 423 MPASS(vi->nnmrxq > 0); 424 if (nm_split_rss == 0 || vi->nnmrxq == 1) { 425 for (i = 0; i < vi->rss_size;) { 426 for_each_nm_rxq(vi, j, nm_rxq) { 427 vi->nm_rss[i++] = nm_rxq->iq_abs_id; 428 if (i == vi->rss_size) 429 break; 430 } 431 } 432 defq = vi->nm_rss[0]; 433 } else { 434 /* We have multiple queues and we want to split the table. */ 435 MPASS(nm_split_rss != 0); 436 MPASS(vi->nnmrxq > 1); 437 438 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq]; 439 nrssq = vi->nnmrxq; 440 if (vi->nnmrxq & 1) { 441 /* 442 * Odd number of queues. The first rxq is designated the 443 * default queue, the rest are split evenly. 444 */ 445 defq = nm_rxq->iq_abs_id; 446 nm_rxq++; 447 nrssq--; 448 } else { 449 /* 450 * Even number of queues split into two halves. The 451 * first rxq in one of the halves is designated the 452 * default queue. 453 */ 454 #if 1 455 /* First rxq in the first half. */ 456 defq = nm_rxq->iq_abs_id; 457 #else 458 /* First rxq in the second half. */ 459 defq = nm_rxq[vi->nnmrxq / 2].iq_abs_id; 460 #endif 461 } 462 463 i = 0; 464 while (i < vi->rss_size / 2) { 465 for (j = 0; j < nrssq / 2; j++) { 466 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 467 if (i == vi->rss_size / 2) 468 break; 469 } 470 } 471 while (i < vi->rss_size) { 472 for (j = nrssq / 2; j < nrssq; j++) { 473 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 474 if (i == vi->rss_size) 475 break; 476 } 477 } 478 } 479 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 480 vi->nm_rss, vi->rss_size); 481 if (rc != 0) 482 if_printf(ifp, "netmap rss_config failed: %d\n", rc); 483 484 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 485 if (rc != 0) 486 if_printf(ifp, "netmap rss hash/defaultq config failed: %d\n", rc); 487 488 return (rc); 489 } 490 491 static int 492 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 493 struct netmap_adapter *na) 494 { 495 struct netmap_kring *kring; 496 int rc, i; 497 struct sge_nm_txq *nm_txq; 498 struct sge_nm_rxq *nm_rxq; 499 500 ASSERT_SYNCHRONIZED_OP(sc); 501 502 if (!nm_netmap_on(na)) 503 return (0); 504 505 if ((vi->flags & VI_INIT_DONE) == 0) 506 return (0); 507 508 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 509 vi->rss, vi->rss_size); 510 if (rc != 0) 511 if_printf(ifp, "failed to restore RSS config: %d\n", rc); 512 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, vi->rss[0], 0, 0); 513 if (rc != 0) 514 if_printf(ifp, "failed to restore RSS hash/defaultq: %d\n", rc); 515 nm_clear_native_flags(na); 516 517 for_each_nm_txq(vi, i, nm_txq) { 518 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 519 520 kring = na->tx_rings[nm_txq->nid]; 521 if (!nm_kring_pending_off(kring) || 522 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) 523 continue; 524 525 /* Wait for hw pidx to catch up ... */ 526 while (be16toh(nm_txq->pidx) != spg->pidx) 527 pause("nmpidx", 1); 528 529 /* ... and then for the cidx. */ 530 while (spg->pidx != spg->cidx) 531 pause("nmcidx", 1); 532 533 free_nm_txq_hwq(vi, nm_txq); 534 } 535 for_each_nm_rxq(vi, i, nm_rxq) { 536 kring = na->rx_rings[nm_rxq->nid]; 537 if (!nm_kring_pending_off(kring) || 538 nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID) 539 continue; 540 541 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF)) 542 pause("nmst", 1); 543 544 free_nm_rxq_hwq(vi, nm_rxq); 545 } 546 547 return (rc); 548 } 549 550 static int 551 cxgbe_netmap_reg(struct netmap_adapter *na, int on) 552 { 553 struct ifnet *ifp = na->ifp; 554 struct vi_info *vi = ifp->if_softc; 555 struct adapter *sc = vi->pi->adapter; 556 int rc; 557 558 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg"); 559 if (rc != 0) 560 return (rc); 561 if (on) 562 rc = cxgbe_netmap_on(sc, vi, ifp, na); 563 else 564 rc = cxgbe_netmap_off(sc, vi, ifp, na); 565 end_synchronized_op(sc, 0); 566 567 return (rc); 568 } 569 570 /* How many packets can a single type1 WR carry in n descriptors */ 571 static inline int 572 ndesc_to_npkt(const int n) 573 { 574 575 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC); 576 577 return (n * 2 - 1); 578 } 579 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC)) 580 581 /* 582 * Space (in descriptors) needed for a type1 WR (TX_PKTS or TX_PKTS2) that 583 * carries n packets 584 */ 585 static inline int 586 npkt_to_ndesc(const int n) 587 { 588 589 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 590 591 return ((n + 2) / 2); 592 } 593 594 /* 595 * Space (in 16B units) needed for a type1 WR (TX_PKTS or TX_PKTS2) that 596 * carries n packets 597 */ 598 static inline int 599 npkt_to_len16(const int n) 600 { 601 602 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 603 604 return (n * 2 + 1); 605 } 606 607 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx) 608 609 static void 610 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq) 611 { 612 int n; 613 u_int db = nm_txq->doorbells; 614 615 MPASS(nm_txq->pidx != nm_txq->dbidx); 616 617 n = NMIDXDIFF(nm_txq, dbidx); 618 if (n > 1) 619 clrbit(&db, DOORBELL_WCWR); 620 wmb(); 621 622 switch (ffs(db) - 1) { 623 case DOORBELL_UDB: 624 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 625 break; 626 627 case DOORBELL_WCWR: { 628 volatile uint64_t *dst, *src; 629 630 /* 631 * Queues whose 128B doorbell segment fits in the page do not 632 * use relative qid (udb_qid is always 0). Only queues with 633 * doorbell segments can do WCWR. 634 */ 635 KASSERT(nm_txq->udb_qid == 0 && n == 1, 636 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p", 637 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq)); 638 639 dst = (volatile void *)((uintptr_t)nm_txq->udb + 640 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 641 src = (void *)&nm_txq->desc[nm_txq->dbidx]; 642 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1]) 643 *dst++ = *src++; 644 wmb(); 645 break; 646 } 647 648 case DOORBELL_UDBWC: 649 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 650 wmb(); 651 break; 652 653 case DOORBELL_KDB: 654 t4_write_reg(sc, sc->sge_kdoorbell_reg, 655 V_QID(nm_txq->cntxt_id) | V_PIDX(n)); 656 break; 657 } 658 nm_txq->dbidx = nm_txq->pidx; 659 } 660 661 /* 662 * Write work requests to send 'npkt' frames and ring the doorbell to send them 663 * on their way. No need to check for wraparound. 664 */ 665 static void 666 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq, 667 struct netmap_kring *kring, int npkt, int npkt_remaining) 668 { 669 struct netmap_ring *ring = kring->ring; 670 struct netmap_slot *slot; 671 const u_int lim = kring->nkr_num_slots - 1; 672 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx]; 673 uint16_t len; 674 uint64_t ba; 675 struct cpl_tx_pkt_core *cpl; 676 struct ulptx_sgl *usgl; 677 int i, n; 678 679 while (npkt) { 680 n = min(npkt, MAX_NPKT_IN_TYPE1_WR); 681 len = 0; 682 683 wr = (void *)&nm_txq->desc[nm_txq->pidx]; 684 wr->op_pkd = nm_txq->op_pkd; 685 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n))); 686 wr->npkt = n; 687 wr->r3 = 0; 688 wr->type = 1; 689 cpl = (void *)(wr + 1); 690 691 for (i = 0; i < n; i++) { 692 slot = &ring->slot[kring->nr_hwcur]; 693 PNMB(kring->na, slot, &ba); 694 MPASS(ba != 0); 695 696 cpl->ctrl0 = nm_txq->cpl_ctrl0; 697 cpl->pack = 0; 698 cpl->len = htobe16(slot->len); 699 /* 700 * netmap(4) says "netmap does not use features such as 701 * checksum offloading, TCP segmentation offloading, 702 * encryption, VLAN encapsulation/decapsulation, etc." 703 */ 704 cpl->ctrl1 = htobe64(F_TXPKT_IPCSUM_DIS | 705 F_TXPKT_L4CSUM_DIS); 706 707 usgl = (void *)(cpl + 1); 708 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 709 V_ULPTX_NSGE(1)); 710 usgl->len0 = htobe32(slot->len); 711 usgl->addr0 = htobe64(ba); 712 713 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 714 cpl = (void *)(usgl + 1); 715 MPASS(slot->len + len <= UINT16_MAX); 716 len += slot->len; 717 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim); 718 } 719 wr->plen = htobe16(len); 720 721 npkt -= n; 722 nm_txq->pidx += npkt_to_ndesc(n); 723 MPASS(nm_txq->pidx <= nm_txq->sidx); 724 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) { 725 /* 726 * This routine doesn't know how to write WRs that wrap 727 * around. Make sure it wasn't asked to. 728 */ 729 MPASS(npkt == 0); 730 nm_txq->pidx = 0; 731 } 732 733 if (npkt == 0 && npkt_remaining == 0) { 734 /* All done. */ 735 if (lazy_tx_credit_flush == 0) { 736 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 737 F_FW_WR_EQUIQ); 738 nm_txq->equeqidx = nm_txq->pidx; 739 nm_txq->equiqidx = nm_txq->pidx; 740 } 741 ring_nm_txq_db(sc, nm_txq); 742 return; 743 } 744 745 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) { 746 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 747 F_FW_WR_EQUIQ); 748 nm_txq->equeqidx = nm_txq->pidx; 749 nm_txq->equiqidx = nm_txq->pidx; 750 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) { 751 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 752 nm_txq->equeqidx = nm_txq->pidx; 753 } 754 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC) 755 ring_nm_txq_db(sc, nm_txq); 756 } 757 758 /* Will get called again. */ 759 MPASS(npkt_remaining); 760 } 761 762 /* How many contiguous free descriptors starting at pidx */ 763 static inline int 764 contiguous_ndesc_available(struct sge_nm_txq *nm_txq) 765 { 766 767 if (nm_txq->cidx > nm_txq->pidx) 768 return (nm_txq->cidx - nm_txq->pidx - 1); 769 else if (nm_txq->cidx > 0) 770 return (nm_txq->sidx - nm_txq->pidx); 771 else 772 return (nm_txq->sidx - nm_txq->pidx - 1); 773 } 774 775 static int 776 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq) 777 { 778 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 779 uint16_t hw_cidx = spg->cidx; /* snapshot */ 780 struct fw_eth_tx_pkts_wr *wr; 781 int n = 0; 782 783 hw_cidx = be16toh(hw_cidx); 784 785 while (nm_txq->cidx != hw_cidx) { 786 wr = (void *)&nm_txq->desc[nm_txq->cidx]; 787 788 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)) || 789 wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR))); 790 MPASS(wr->type == 1); 791 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR); 792 793 n += wr->npkt; 794 nm_txq->cidx += npkt_to_ndesc(wr->npkt); 795 796 /* 797 * We never sent a WR that wrapped around so the credits coming 798 * back, WR by WR, should never cause the cidx to wrap around 799 * either. 800 */ 801 MPASS(nm_txq->cidx <= nm_txq->sidx); 802 if (__predict_false(nm_txq->cidx == nm_txq->sidx)) 803 nm_txq->cidx = 0; 804 } 805 806 return (n); 807 } 808 809 static int 810 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) 811 { 812 struct netmap_adapter *na = kring->na; 813 struct ifnet *ifp = na->ifp; 814 struct vi_info *vi = ifp->if_softc; 815 struct adapter *sc = vi->pi->adapter; 816 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id]; 817 const u_int head = kring->rhead; 818 u_int reclaimed = 0; 819 int n, d, npkt_remaining, ndesc_remaining; 820 821 /* 822 * Tx was at kring->nr_hwcur last time around and now we need to advance 823 * to kring->rhead. Note that the driver's pidx moves independent of 824 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation 825 * between descriptors and frames isn't 1:1). 826 */ 827 828 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 829 kring->nkr_num_slots - kring->nr_hwcur + head; 830 while (npkt_remaining) { 831 reclaimed += reclaim_nm_tx_desc(nm_txq); 832 ndesc_remaining = contiguous_ndesc_available(nm_txq); 833 /* Can't run out of descriptors with packets still remaining */ 834 MPASS(ndesc_remaining > 0); 835 836 /* # of desc needed to tx all remaining packets */ 837 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC; 838 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR) 839 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR); 840 841 if (d <= ndesc_remaining) 842 n = npkt_remaining; 843 else { 844 /* Can't send all, calculate how many can be sent */ 845 n = (ndesc_remaining / SGE_MAX_WR_NDESC) * 846 MAX_NPKT_IN_TYPE1_WR; 847 if (ndesc_remaining % SGE_MAX_WR_NDESC) 848 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC); 849 } 850 851 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */ 852 npkt_remaining -= n; 853 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining); 854 } 855 MPASS(npkt_remaining == 0); 856 MPASS(kring->nr_hwcur == head); 857 MPASS(nm_txq->dbidx == nm_txq->pidx); 858 859 /* 860 * Second part: reclaim buffers for completed transmissions. 861 */ 862 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) { 863 reclaimed += reclaim_nm_tx_desc(nm_txq); 864 kring->nr_hwtail += reclaimed; 865 if (kring->nr_hwtail >= kring->nkr_num_slots) 866 kring->nr_hwtail -= kring->nkr_num_slots; 867 } 868 869 return (0); 870 } 871 872 static int 873 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) 874 { 875 struct netmap_adapter *na = kring->na; 876 struct netmap_ring *ring = kring->ring; 877 struct ifnet *ifp = na->ifp; 878 struct vi_info *vi = ifp->if_softc; 879 struct adapter *sc = vi->pi->adapter; 880 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id]; 881 u_int const head = kring->rhead; 882 u_int n; 883 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 884 885 if (black_hole) 886 return (0); /* No updates ever. */ 887 888 if (netmap_no_pendintr || force_update) { 889 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx); 890 kring->nr_kflags &= ~NKR_PENDINTR; 891 } 892 893 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) { 894 wmb(); 895 t4_write_reg(sc, sc->sge_kdoorbell_reg, 896 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved)); 897 nm_rxq->fl_db_saved = 0; 898 } 899 900 /* Userspace done with buffers from kring->nr_hwcur to head */ 901 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 902 kring->nkr_num_slots - kring->nr_hwcur + head; 903 n &= ~7U; 904 if (n > 0) { 905 u_int fl_pidx = nm_rxq->fl_pidx; 906 struct netmap_slot *slot = &ring->slot[fl_pidx]; 907 uint64_t ba; 908 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx; 909 910 /* 911 * We always deal with 8 buffers at a time. We must have 912 * stopped at an 8B boundary (fl_pidx) last time around and we 913 * must have a multiple of 8B buffers to give to the freelist. 914 */ 915 MPASS((fl_pidx & 7) == 0); 916 MPASS((n & 7) == 0); 917 918 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots); 919 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx); 920 921 while (n > 0) { 922 for (i = 0; i < 8; i++, fl_pidx++, slot++) { 923 PNMB(na, slot, &ba); 924 MPASS(ba != 0); 925 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx); 926 slot->flags &= ~NS_BUF_CHANGED; 927 MPASS(fl_pidx <= nm_rxq->fl_sidx); 928 } 929 n -= 8; 930 if (fl_pidx == nm_rxq->fl_sidx) { 931 fl_pidx = 0; 932 slot = &ring->slot[0]; 933 } 934 if (++dbinc == 8 && n >= 32) { 935 wmb(); 936 if (starve_fl) 937 nm_rxq->fl_db_saved += dbinc; 938 else { 939 t4_write_reg(sc, sc->sge_kdoorbell_reg, 940 nm_rxq->fl_db_val | V_PIDX(dbinc)); 941 } 942 dbinc = 0; 943 } 944 } 945 MPASS(nm_rxq->fl_pidx == fl_pidx); 946 947 if (dbinc > 0) { 948 wmb(); 949 if (starve_fl) 950 nm_rxq->fl_db_saved += dbinc; 951 else { 952 t4_write_reg(sc, sc->sge_kdoorbell_reg, 953 nm_rxq->fl_db_val | V_PIDX(dbinc)); 954 } 955 } 956 } 957 958 return (0); 959 } 960 961 void 962 cxgbe_nm_attach(struct vi_info *vi) 963 { 964 struct port_info *pi; 965 struct adapter *sc; 966 struct netmap_adapter na; 967 968 MPASS(vi->nnmrxq > 0); 969 MPASS(vi->ifp != NULL); 970 971 pi = vi->pi; 972 sc = pi->adapter; 973 974 bzero(&na, sizeof(na)); 975 976 na.ifp = vi->ifp; 977 na.na_flags = NAF_BDG_MAYSLEEP; 978 979 /* Netmap doesn't know about the space reserved for the status page. */ 980 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE; 981 982 /* 983 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So 984 * num_rx_desc is based on the number of buffers that can be held in the 985 * freelist, and not the number of entries in the iq. (These two are 986 * not exactly the same due to the space taken up by the status page). 987 */ 988 na.num_rx_desc = rounddown(vi->qsize_rxq, 8); 989 na.nm_txsync = cxgbe_netmap_txsync; 990 na.nm_rxsync = cxgbe_netmap_rxsync; 991 na.nm_register = cxgbe_netmap_reg; 992 na.num_tx_rings = vi->nnmtxq; 993 na.num_rx_rings = vi->nnmrxq; 994 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */ 995 } 996 997 void 998 cxgbe_nm_detach(struct vi_info *vi) 999 { 1000 1001 MPASS(vi->nnmrxq > 0); 1002 MPASS(vi->ifp != NULL); 1003 1004 netmap_detach(vi->ifp); 1005 } 1006 1007 static inline const void * 1008 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl) 1009 { 1010 1011 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL); 1012 1013 /* data[0] is RSS header */ 1014 return (&cpl->data[1]); 1015 } 1016 1017 static void 1018 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp, 1019 const struct cpl_sge_egr_update *egr) 1020 { 1021 uint32_t oq; 1022 struct sge_nm_txq *nm_txq; 1023 1024 oq = be32toh(egr->opcode_qid); 1025 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 1026 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 1027 1028 netmap_tx_irq(ifp, nm_txq->nid); 1029 } 1030 1031 void 1032 service_nm_rxq(struct sge_nm_rxq *nm_rxq) 1033 { 1034 struct vi_info *vi = nm_rxq->vi; 1035 struct adapter *sc = vi->pi->adapter; 1036 struct ifnet *ifp = vi->ifp; 1037 struct netmap_adapter *na = NA(ifp); 1038 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid]; 1039 struct netmap_ring *ring = kring->ring; 1040 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; 1041 const void *cpl; 1042 uint32_t lq; 1043 u_int work = 0; 1044 uint8_t opcode; 1045 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 1046 u_int fl_credits = fl_cidx & 7; 1047 u_int ndesc = 0; /* desc processed since last cidx update */ 1048 u_int nframes = 0; /* frames processed since last netmap wakeup */ 1049 1050 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 1051 1052 rmb(); 1053 1054 lq = be32toh(d->rsp.pldbuflen_qid); 1055 opcode = d->rss.opcode; 1056 cpl = &d->cpl[0]; 1057 1058 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 1059 case X_RSPD_TYPE_FLBUF: 1060 1061 /* fall through */ 1062 1063 case X_RSPD_TYPE_CPL: 1064 MPASS(opcode < NUM_CPL_CMDS); 1065 1066 switch (opcode) { 1067 case CPL_FW4_MSG: 1068 case CPL_FW6_MSG: 1069 cpl = unwrap_nm_fw6_msg(cpl); 1070 /* fall through */ 1071 case CPL_SGE_EGR_UPDATE: 1072 handle_nm_sge_egr_update(sc, ifp, cpl); 1073 break; 1074 case CPL_RX_PKT: 1075 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 1076 sc->params.sge.fl_pktshift; 1077 ring->slot[fl_cidx].flags = 0; 1078 nframes++; 1079 if (!(lq & F_RSPD_NEWBUF)) { 1080 MPASS(black_hole == 2); 1081 break; 1082 } 1083 fl_credits++; 1084 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx)) 1085 fl_cidx = 0; 1086 break; 1087 default: 1088 panic("%s: unexpected opcode 0x%x on nm_rxq %p", 1089 __func__, opcode, nm_rxq); 1090 } 1091 break; 1092 1093 case X_RSPD_TYPE_INTR: 1094 /* Not equipped to handle forwarded interrupts. */ 1095 panic("%s: netmap queue received interrupt for iq %u\n", 1096 __func__, lq); 1097 1098 default: 1099 panic("%s: illegal response type %d on nm_rxq %p", 1100 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq); 1101 } 1102 1103 d++; 1104 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) { 1105 nm_rxq->iq_cidx = 0; 1106 d = &nm_rxq->iq_desc[0]; 1107 nm_rxq->iq_gen ^= F_RSPD_GEN; 1108 } 1109 1110 if (__predict_false(++nframes == rx_nframes) && !black_hole) { 1111 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1112 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1113 nframes = 0; 1114 } 1115 1116 if (__predict_false(++ndesc == rx_ndesc)) { 1117 if (black_hole && fl_credits >= 8) { 1118 fl_credits /= 8; 1119 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, 1120 nm_rxq->fl_sidx); 1121 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1122 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1123 fl_credits = fl_cidx & 7; 1124 } 1125 t4_write_reg(sc, sc->sge_gts_reg, 1126 V_CIDXINC(ndesc) | 1127 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 1128 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1129 ndesc = 0; 1130 } 1131 } 1132 1133 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1134 if (black_hole) { 1135 fl_credits /= 8; 1136 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx); 1137 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1138 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1139 } else if (nframes > 0) 1140 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1141 1142 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) | 1143 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) | 1144 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 1145 } 1146 #endif 1147