1 /*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #ifdef DEV_NETMAP 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/lock.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/selinfo.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <machine/bus.h> 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_var.h> 49 #include <net/if_clone.h> 50 #include <net/if_types.h> 51 #include <net/netmap.h> 52 #include <dev/netmap/netmap_kern.h> 53 54 #include "common/common.h" 55 #include "common/t4_regs.h" 56 #include "common/t4_regs_values.h" 57 58 extern int fl_pad; /* XXXNM */ 59 60 /* 61 * 0 = normal netmap rx 62 * 1 = black hole 63 * 2 = supermassive black hole (buffer packing enabled) 64 */ 65 int black_hole = 0; 66 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RWTUN, &black_hole, 0, 67 "Sink incoming packets."); 68 69 int rx_ndesc = 256; 70 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN, 71 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated."); 72 73 int rx_nframes = 64; 74 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN, 75 &rx_nframes, 0, "max # of frames received before waking up netmap rx."); 76 77 int holdoff_tmr_idx = 2; 78 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN, 79 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues."); 80 81 /* 82 * Congestion drops. 83 * -1: no congestion feedback (not recommended). 84 * 0: backpressure the channel instead of dropping packets right away. 85 * 1: no backpressure, drop packets for the congested queue immediately. 86 */ 87 static int nm_cong_drop = 1; 88 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RWTUN, 89 &nm_cong_drop, 0, 90 "Congestion control for netmap rx queues (0 = backpressure, 1 = drop"); 91 92 int starve_fl = 0; 93 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN, 94 &starve_fl, 0, "Don't ring fl db for netmap rx queues."); 95 96 /* 97 * Try to process tx credits in bulk. This may cause a delay in the return of 98 * tx credits and is suitable for bursty or non-stop tx only. 99 */ 100 int lazy_tx_credit_flush = 1; 101 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN, 102 &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues."); 103 104 /* 105 * Split the netmap rx queues into two groups that populate separate halves of 106 * the RSS indirection table. This allows filters with hashmask to steer to a 107 * particular group of queues. 108 */ 109 static int nm_split_rss = 0; 110 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN, 111 &nm_split_rss, 0, "Split the netmap rx queues into two groups."); 112 113 /* 114 * netmap(4) says "netmap does not use features such as checksum offloading, TCP 115 * segmentation offloading, encryption, VLAN encapsulation/decapsulation, etc." 116 * but this knob can be used to get the hardware to checksum all tx traffic 117 * anyway. 118 */ 119 static int nm_txcsum = 0; 120 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_txcsum, CTLFLAG_RWTUN, 121 &nm_txcsum, 0, "Enable transmit checksum offloading."); 122 123 static int 124 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong) 125 { 126 int rc, cntxt_id, i; 127 __be32 v; 128 struct adapter *sc = vi->adapter; 129 struct sge_params *sp = &sc->params.sge; 130 struct netmap_adapter *na = NA(vi->ifp); 131 struct fw_iq_cmd c; 132 133 MPASS(na != NULL); 134 MPASS(nm_rxq->iq_desc != NULL); 135 MPASS(nm_rxq->fl_desc != NULL); 136 137 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE); 138 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len); 139 140 bzero(&c, sizeof(c)); 141 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 142 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 143 V_FW_IQ_CMD_VFN(0)); 144 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 145 FW_LEN16(c)); 146 MPASS(!forwarding_intr_to_fwq(sc)); 147 KASSERT(nm_rxq->intr_idx < sc->intr_count, 148 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx)); 149 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx); 150 c.type_to_iqandstindex = htobe32(v | 151 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 152 V_FW_IQ_CMD_VIID(vi->viid) | 153 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 154 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 155 F_FW_IQ_CMD_IQGTSMODE | 156 V_FW_IQ_CMD_IQINTCNTTHRESH(0) | 157 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 158 c.iqsize = htobe16(vi->qsize_rxq); 159 c.iqaddr = htobe64(nm_rxq->iq_ba); 160 if (cong >= 0) { 161 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | 162 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF | 163 F_FW_IQ_CMD_FL0CONGEN); 164 } 165 c.iqns_to_fl0congen |= 166 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 167 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 168 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 169 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 170 c.fl0dcaen_to_fl0cidxfthresh = 171 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 172 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 173 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 174 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 175 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 176 c.fl0addr = htobe64(nm_rxq->fl_ba); 177 178 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 179 if (rc != 0) { 180 device_printf(sc->dev, 181 "failed to create netmap ingress queue: %d\n", rc); 182 return (rc); 183 } 184 185 nm_rxq->iq_cidx = 0; 186 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE); 187 nm_rxq->iq_gen = F_RSPD_GEN; 188 nm_rxq->iq_cntxt_id = be16toh(c.iqid); 189 nm_rxq->iq_abs_id = be16toh(c.physiqid); 190 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start; 191 if (cntxt_id >= sc->sge.niq) { 192 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)", 193 __func__, cntxt_id, sc->sge.niq - 1); 194 } 195 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq; 196 197 nm_rxq->fl_cntxt_id = be16toh(c.fl0id); 198 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 199 nm_rxq->fl_db_saved = 0; 200 /* matches the X_FETCHBURSTMAX_512B or X_FETCHBURSTMAX_256B above. */ 201 nm_rxq->fl_db_threshold = chip_id(sc) <= CHELSIO_T5 ? 8 : 4; 202 MPASS(nm_rxq->fl_sidx == na->num_rx_desc); 203 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start; 204 if (cntxt_id >= sc->sge.neq) { 205 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 206 __func__, cntxt_id, sc->sge.neq - 1); 207 } 208 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 209 210 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 211 sc->chip_params->sge_fl_db; 212 213 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) { 214 uint32_t param, val; 215 216 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 217 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 218 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 219 if (cong == 0) 220 val = 1 << 19; 221 else { 222 val = 2 << 19; 223 for (i = 0; i < 4; i++) { 224 if (cong & (1 << i)) 225 val |= 1 << (i << 2); 226 } 227 } 228 229 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 230 if (rc != 0) { 231 /* report error but carry on */ 232 device_printf(sc->dev, 233 "failed to set congestion manager context for " 234 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc); 235 } 236 } 237 238 t4_write_reg(sc, sc->sge_gts_reg, 239 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 240 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 241 242 return (rc); 243 } 244 245 static int 246 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 247 { 248 struct adapter *sc = vi->adapter; 249 int rc; 250 251 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 252 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 253 if (rc != 0) 254 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n", 255 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc); 256 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 257 return (rc); 258 } 259 260 static int 261 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 262 { 263 int rc, cntxt_id; 264 size_t len; 265 struct adapter *sc = vi->adapter; 266 struct netmap_adapter *na = NA(vi->ifp); 267 struct fw_eq_eth_cmd c; 268 269 MPASS(na != NULL); 270 MPASS(nm_txq->desc != NULL); 271 272 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 273 bzero(nm_txq->desc, len); 274 275 bzero(&c, sizeof(c)); 276 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 277 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 278 V_FW_EQ_ETH_CMD_VFN(0)); 279 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 280 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 281 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 282 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 283 c.fetchszm_to_iqid = 284 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 285 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 286 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id)); 287 c.dcaen_to_eqsize = 288 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 289 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 290 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 291 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE)); 292 c.eqaddr = htobe64(nm_txq->ba); 293 294 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 295 if (rc != 0) { 296 device_printf(vi->dev, 297 "failed to create netmap egress queue: %d\n", rc); 298 return (rc); 299 } 300 301 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 302 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start; 303 if (cntxt_id >= sc->sge.neq) 304 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__, 305 cntxt_id, sc->sge.neq - 1); 306 sc->sge.eqmap[cntxt_id] = (void *)nm_txq; 307 308 nm_txq->pidx = nm_txq->cidx = 0; 309 MPASS(nm_txq->sidx == na->num_tx_desc); 310 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0; 311 312 nm_txq->doorbells = sc->doorbells; 313 if (isset(&nm_txq->doorbells, DOORBELL_UDB) || 314 isset(&nm_txq->doorbells, DOORBELL_UDBWC) || 315 isset(&nm_txq->doorbells, DOORBELL_WCWR)) { 316 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 317 uint32_t mask = (1 << s_qpp) - 1; 318 volatile uint8_t *udb; 319 320 udb = sc->udbs_base + UDBS_DB_OFFSET; 321 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT; 322 nm_txq->udb_qid = nm_txq->cntxt_id & mask; 323 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 324 clrbit(&nm_txq->doorbells, DOORBELL_WCWR); 325 else { 326 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT; 327 nm_txq->udb_qid = 0; 328 } 329 nm_txq->udb = (volatile void *)udb; 330 } 331 332 return (rc); 333 } 334 335 static int 336 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 337 { 338 struct adapter *sc = vi->adapter; 339 int rc; 340 341 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 342 if (rc != 0) 343 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__, 344 nm_txq->cntxt_id, rc); 345 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 346 return (rc); 347 } 348 349 static int 350 cxgbe_netmap_simple_rss(struct adapter *sc, struct vi_info *vi, 351 struct ifnet *ifp, struct netmap_adapter *na) 352 { 353 struct netmap_kring *kring; 354 struct sge_nm_rxq *nm_rxq; 355 int rc, i, j, nm_state, defq; 356 uint16_t *rss; 357 358 /* 359 * Check if there's at least one active (or about to go active) netmap 360 * rx queue. 361 */ 362 defq = -1; 363 for_each_nm_rxq(vi, j, nm_rxq) { 364 nm_state = atomic_load_int(&nm_rxq->nm_state); 365 kring = na->rx_rings[nm_rxq->nid]; 366 if ((nm_state != NM_OFF && !nm_kring_pending_off(kring)) || 367 (nm_state == NM_OFF && nm_kring_pending_on(kring))) { 368 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 369 if (defq == -1) { 370 defq = nm_rxq->iq_abs_id; 371 break; 372 } 373 } 374 } 375 376 if (defq == -1) { 377 /* No active netmap queues. Switch back to NIC queues. */ 378 rss = vi->rss; 379 defq = vi->rss[0]; 380 } else { 381 for (i = 0; i < vi->rss_size;) { 382 for_each_nm_rxq(vi, j, nm_rxq) { 383 nm_state = atomic_load_int(&nm_rxq->nm_state); 384 kring = na->rx_rings[nm_rxq->nid]; 385 if ((nm_state != NM_OFF && 386 !nm_kring_pending_off(kring)) || 387 (nm_state == NM_OFF && 388 nm_kring_pending_on(kring))) { 389 MPASS(nm_rxq->iq_cntxt_id != 390 INVALID_NM_RXQ_CNTXT_ID); 391 vi->nm_rss[i++] = nm_rxq->iq_abs_id; 392 if (i == vi->rss_size) 393 break; 394 } 395 } 396 } 397 rss = vi->nm_rss; 398 } 399 400 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 401 vi->rss_size); 402 if (rc != 0) 403 if_printf(ifp, "netmap rss_config failed: %d\n", rc); 404 405 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 406 if (rc != 0) { 407 if_printf(ifp, "netmap defaultq config failed: %d\n", rc); 408 } 409 410 return (rc); 411 } 412 413 /* 414 * Odd number of rx queues work best for split RSS mode as the first queue can 415 * be dedicated for non-RSS traffic and the rest divided into two equal halves. 416 */ 417 static int 418 cxgbe_netmap_split_rss(struct adapter *sc, struct vi_info *vi, 419 struct ifnet *ifp, struct netmap_adapter *na) 420 { 421 struct netmap_kring *kring; 422 struct sge_nm_rxq *nm_rxq; 423 int rc, i, j, nm_state, defq; 424 int nactive[2] = {0, 0}; 425 int dq[2] = {-1, -1}; 426 bool dq_norss; /* default queue should not be in RSS table. */ 427 428 MPASS(nm_split_rss != 0); 429 MPASS(vi->nnmrxq > 1); 430 431 for_each_nm_rxq(vi, i, nm_rxq) { 432 j = i / ((vi->nnmrxq + 1) / 2); 433 nm_state = atomic_load_int(&nm_rxq->nm_state); 434 kring = na->rx_rings[nm_rxq->nid]; 435 if ((nm_state != NM_OFF && !nm_kring_pending_off(kring)) || 436 (nm_state == NM_OFF && nm_kring_pending_on(kring))) { 437 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 438 nactive[j]++; 439 if (dq[j] == -1) { 440 dq[j] = nm_rxq->iq_abs_id; 441 break; 442 } 443 } 444 } 445 446 if (nactive[0] == 0 || nactive[1] == 0) 447 return (cxgbe_netmap_simple_rss(sc, vi, ifp, na)); 448 449 MPASS(dq[0] != -1 && dq[1] != -1); 450 if (nactive[0] > nactive[1]) { 451 defq = dq[0]; 452 dq_norss = true; 453 } else if (nactive[0] < nactive[1]) { 454 defq = dq[1]; 455 dq_norss = true; 456 } else { 457 defq = dq[0]; 458 dq_norss = false; 459 } 460 461 i = 0; 462 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq]; 463 while (i < vi->rss_size / 2) { 464 for (j = 0; j < (vi->nnmrxq + 1) / 2; j++) { 465 nm_state = atomic_load_int(&nm_rxq[j].nm_state); 466 kring = na->rx_rings[nm_rxq[j].nid]; 467 if ((nm_state == NM_OFF && 468 !nm_kring_pending_on(kring)) || 469 (nm_state == NM_ON && 470 nm_kring_pending_off(kring))) { 471 continue; 472 } 473 MPASS(nm_rxq[j].iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 474 if (dq_norss && defq == nm_rxq[j].iq_abs_id) 475 continue; 476 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 477 if (i == vi->rss_size / 2) 478 break; 479 } 480 } 481 while (i < vi->rss_size) { 482 for (j = (vi->nnmrxq + 1) / 2; j < vi->nnmrxq; j++) { 483 nm_state = atomic_load_int(&nm_rxq[j].nm_state); 484 kring = na->rx_rings[nm_rxq[j].nid]; 485 if ((nm_state == NM_OFF && 486 !nm_kring_pending_on(kring)) || 487 (nm_state == NM_ON && 488 nm_kring_pending_off(kring))) { 489 continue; 490 } 491 MPASS(nm_rxq[j].iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 492 if (dq_norss && defq == nm_rxq[j].iq_abs_id) 493 continue; 494 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 495 if (i == vi->rss_size) 496 break; 497 } 498 } 499 500 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 501 vi->nm_rss, vi->rss_size); 502 if (rc != 0) 503 if_printf(ifp, "netmap split_rss_config failed: %d\n", rc); 504 505 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 506 if (rc != 0) 507 if_printf(ifp, "netmap defaultq config failed: %d\n", rc); 508 509 return (rc); 510 } 511 512 static inline int 513 cxgbe_netmap_rss(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 514 struct netmap_adapter *na) 515 { 516 517 if (nm_split_rss == 0 || vi->nnmrxq == 1) 518 return (cxgbe_netmap_simple_rss(sc, vi, ifp, na)); 519 else 520 return (cxgbe_netmap_split_rss(sc, vi, ifp, na)); 521 } 522 523 static int 524 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 525 struct netmap_adapter *na) 526 { 527 struct netmap_slot *slot; 528 struct netmap_kring *kring; 529 struct sge_nm_rxq *nm_rxq; 530 struct sge_nm_txq *nm_txq; 531 int i, j, hwidx; 532 struct rx_buf_info *rxb; 533 534 ASSERT_SYNCHRONIZED_OP(sc); 535 MPASS(vi->nnmrxq > 0); 536 MPASS(vi->nnmtxq > 0); 537 538 if ((vi->flags & VI_INIT_DONE) == 0 || 539 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 540 if_printf(ifp, "cannot enable netmap operation because " 541 "interface is not UP.\n"); 542 return (EAGAIN); 543 } 544 545 rxb = &sc->sge.rx_buf_info[0]; 546 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 547 if (rxb->size1 == NETMAP_BUF_SIZE(na)) { 548 hwidx = rxb->hwidx1; 549 break; 550 } 551 if (rxb->size2 == NETMAP_BUF_SIZE(na)) { 552 hwidx = rxb->hwidx2; 553 break; 554 } 555 } 556 if (i >= SW_ZONE_SIZES) { 557 if_printf(ifp, "no hwidx for netmap buffer size %d.\n", 558 NETMAP_BUF_SIZE(na)); 559 return (ENXIO); 560 } 561 562 /* Must set caps before calling netmap_reset */ 563 nm_set_native_flags(na); 564 565 for_each_nm_rxq(vi, i, nm_rxq) { 566 kring = na->rx_rings[nm_rxq->nid]; 567 if (!nm_kring_pending_on(kring) || 568 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID) 569 continue; 570 571 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop)); 572 nm_rxq->fl_hwidx = hwidx; 573 slot = netmap_reset(na, NR_RX, i, 0); 574 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 575 576 /* We deal with 8 bufs at a time */ 577 MPASS((na->num_rx_desc & 7) == 0); 578 MPASS(na->num_rx_desc == nm_rxq->fl_sidx); 579 for (j = 0; j < nm_rxq->fl_sidx; j++) { 580 uint64_t ba; 581 582 PNMB(na, &slot[j], &ba); 583 MPASS(ba != 0); 584 nm_rxq->fl_desc[j] = htobe64(ba | hwidx); 585 } 586 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8; 587 MPASS((j & 7) == 0); 588 j /= 8; /* driver pidx to hardware pidx */ 589 wmb(); 590 t4_write_reg(sc, sc->sge_kdoorbell_reg, 591 nm_rxq->fl_db_val | V_PIDX(j)); 592 593 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON); 594 } 595 596 for_each_nm_txq(vi, i, nm_txq) { 597 kring = na->tx_rings[nm_txq->nid]; 598 if (!nm_kring_pending_on(kring) || 599 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID) 600 continue; 601 602 alloc_nm_txq_hwq(vi, nm_txq); 603 slot = netmap_reset(na, NR_TX, i, 0); 604 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 605 } 606 607 if (vi->nm_rss == NULL) { 608 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE, 609 M_ZERO | M_WAITOK); 610 } 611 612 return (cxgbe_netmap_rss(sc, vi, ifp, na)); 613 } 614 615 static int 616 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 617 struct netmap_adapter *na) 618 { 619 struct netmap_kring *kring; 620 int rc, i, nm_state, nactive; 621 struct sge_nm_txq *nm_txq; 622 struct sge_nm_rxq *nm_rxq; 623 624 ASSERT_SYNCHRONIZED_OP(sc); 625 MPASS(vi->nnmrxq > 0); 626 MPASS(vi->nnmtxq > 0); 627 628 if (!nm_netmap_on(na)) 629 return (0); 630 631 if ((vi->flags & VI_INIT_DONE) == 0) 632 return (0); 633 634 /* First remove the queues that are stopping from the RSS table. */ 635 rc = cxgbe_netmap_rss(sc, vi, ifp, na); 636 if (rc != 0) 637 return (rc); /* error message logged already. */ 638 639 for_each_nm_txq(vi, i, nm_txq) { 640 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 641 642 kring = na->tx_rings[nm_txq->nid]; 643 if (!nm_kring_pending_off(kring) || 644 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) 645 continue; 646 647 /* Wait for hw pidx to catch up ... */ 648 while (be16toh(nm_txq->pidx) != spg->pidx) 649 pause("nmpidx", 1); 650 651 /* ... and then for the cidx. */ 652 while (spg->pidx != spg->cidx) 653 pause("nmcidx", 1); 654 655 free_nm_txq_hwq(vi, nm_txq); 656 657 /* XXX: netmap, not the driver, should do this. */ 658 kring->rhead = kring->rcur = kring->nr_hwcur = 0; 659 kring->rtail = kring->nr_hwtail = kring->nkr_num_slots - 1; 660 } 661 nactive = 0; 662 for_each_nm_rxq(vi, i, nm_rxq) { 663 nm_state = atomic_load_int(&nm_rxq->nm_state); 664 kring = na->rx_rings[nm_rxq->nid]; 665 if (nm_state != NM_OFF && !nm_kring_pending_off(kring)) 666 nactive++; 667 if (nm_state == NM_OFF || !nm_kring_pending_off(kring)) 668 continue; 669 670 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 671 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF)) 672 pause("nmst", 1); 673 674 free_nm_rxq_hwq(vi, nm_rxq); 675 676 /* XXX: netmap, not the driver, should do this. */ 677 kring->rhead = kring->rcur = kring->nr_hwcur = 0; 678 kring->rtail = kring->nr_hwtail = 0; 679 } 680 netmap_krings_mode_commit(na, 0); 681 if (nactive == 0) 682 nm_clear_native_flags(na); 683 684 return (rc); 685 } 686 687 static int 688 cxgbe_netmap_reg(struct netmap_adapter *na, int on) 689 { 690 struct ifnet *ifp = na->ifp; 691 struct vi_info *vi = ifp->if_softc; 692 struct adapter *sc = vi->adapter; 693 int rc; 694 695 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg"); 696 if (rc != 0) 697 return (rc); 698 if (on) 699 rc = cxgbe_netmap_on(sc, vi, ifp, na); 700 else 701 rc = cxgbe_netmap_off(sc, vi, ifp, na); 702 end_synchronized_op(sc, 0); 703 704 return (rc); 705 } 706 707 /* How many packets can a single type1 WR carry in n descriptors */ 708 static inline int 709 ndesc_to_npkt(const int n) 710 { 711 712 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC); 713 714 return (n * 2 - 1); 715 } 716 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC)) 717 718 /* 719 * Space (in descriptors) needed for a type1 WR (TX_PKTS or TX_PKTS2) that 720 * carries n packets 721 */ 722 static inline int 723 npkt_to_ndesc(const int n) 724 { 725 726 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 727 728 return ((n + 2) / 2); 729 } 730 731 /* 732 * Space (in 16B units) needed for a type1 WR (TX_PKTS or TX_PKTS2) that 733 * carries n packets 734 */ 735 static inline int 736 npkt_to_len16(const int n) 737 { 738 739 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 740 741 return (n * 2 + 1); 742 } 743 744 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx) 745 746 static void 747 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq) 748 { 749 int n; 750 u_int db = nm_txq->doorbells; 751 752 MPASS(nm_txq->pidx != nm_txq->dbidx); 753 754 n = NMIDXDIFF(nm_txq, dbidx); 755 if (n > 1) 756 clrbit(&db, DOORBELL_WCWR); 757 wmb(); 758 759 switch (ffs(db) - 1) { 760 case DOORBELL_UDB: 761 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 762 break; 763 764 case DOORBELL_WCWR: { 765 volatile uint64_t *dst, *src; 766 767 /* 768 * Queues whose 128B doorbell segment fits in the page do not 769 * use relative qid (udb_qid is always 0). Only queues with 770 * doorbell segments can do WCWR. 771 */ 772 KASSERT(nm_txq->udb_qid == 0 && n == 1, 773 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p", 774 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq)); 775 776 dst = (volatile void *)((uintptr_t)nm_txq->udb + 777 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 778 src = (void *)&nm_txq->desc[nm_txq->dbidx]; 779 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1]) 780 *dst++ = *src++; 781 wmb(); 782 break; 783 } 784 785 case DOORBELL_UDBWC: 786 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 787 wmb(); 788 break; 789 790 case DOORBELL_KDB: 791 t4_write_reg(sc, sc->sge_kdoorbell_reg, 792 V_QID(nm_txq->cntxt_id) | V_PIDX(n)); 793 break; 794 } 795 nm_txq->dbidx = nm_txq->pidx; 796 } 797 798 /* 799 * Write work requests to send 'npkt' frames and ring the doorbell to send them 800 * on their way. No need to check for wraparound. 801 */ 802 static void 803 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq, 804 struct netmap_kring *kring, int npkt, int npkt_remaining) 805 { 806 struct netmap_ring *ring = kring->ring; 807 struct netmap_slot *slot; 808 const u_int lim = kring->nkr_num_slots - 1; 809 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx]; 810 uint16_t len; 811 uint64_t ba; 812 struct cpl_tx_pkt_core *cpl; 813 struct ulptx_sgl *usgl; 814 int i, n; 815 816 while (npkt) { 817 n = min(npkt, MAX_NPKT_IN_TYPE1_WR); 818 len = 0; 819 820 wr = (void *)&nm_txq->desc[nm_txq->pidx]; 821 wr->op_pkd = nm_txq->op_pkd; 822 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n))); 823 wr->npkt = n; 824 wr->r3 = 0; 825 wr->type = 1; 826 cpl = (void *)(wr + 1); 827 828 for (i = 0; i < n; i++) { 829 slot = &ring->slot[kring->nr_hwcur]; 830 PNMB(kring->na, slot, &ba); 831 MPASS(ba != 0); 832 833 cpl->ctrl0 = nm_txq->cpl_ctrl0; 834 cpl->pack = 0; 835 cpl->len = htobe16(slot->len); 836 cpl->ctrl1 = nm_txcsum ? 0 : 837 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 838 839 usgl = (void *)(cpl + 1); 840 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 841 V_ULPTX_NSGE(1)); 842 usgl->len0 = htobe32(slot->len); 843 usgl->addr0 = htobe64(ba); 844 845 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 846 cpl = (void *)(usgl + 1); 847 MPASS(slot->len + len <= UINT16_MAX); 848 len += slot->len; 849 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim); 850 } 851 wr->plen = htobe16(len); 852 853 npkt -= n; 854 nm_txq->pidx += npkt_to_ndesc(n); 855 MPASS(nm_txq->pidx <= nm_txq->sidx); 856 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) { 857 /* 858 * This routine doesn't know how to write WRs that wrap 859 * around. Make sure it wasn't asked to. 860 */ 861 MPASS(npkt == 0); 862 nm_txq->pidx = 0; 863 } 864 865 if (npkt == 0 && npkt_remaining == 0) { 866 /* All done. */ 867 if (lazy_tx_credit_flush == 0) { 868 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 869 F_FW_WR_EQUIQ); 870 nm_txq->equeqidx = nm_txq->pidx; 871 nm_txq->equiqidx = nm_txq->pidx; 872 } 873 ring_nm_txq_db(sc, nm_txq); 874 return; 875 } 876 877 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) { 878 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 879 F_FW_WR_EQUIQ); 880 nm_txq->equeqidx = nm_txq->pidx; 881 nm_txq->equiqidx = nm_txq->pidx; 882 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) { 883 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 884 nm_txq->equeqidx = nm_txq->pidx; 885 } 886 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC) 887 ring_nm_txq_db(sc, nm_txq); 888 } 889 890 /* Will get called again. */ 891 MPASS(npkt_remaining); 892 } 893 894 /* How many contiguous free descriptors starting at pidx */ 895 static inline int 896 contiguous_ndesc_available(struct sge_nm_txq *nm_txq) 897 { 898 899 if (nm_txq->cidx > nm_txq->pidx) 900 return (nm_txq->cidx - nm_txq->pidx - 1); 901 else if (nm_txq->cidx > 0) 902 return (nm_txq->sidx - nm_txq->pidx); 903 else 904 return (nm_txq->sidx - nm_txq->pidx - 1); 905 } 906 907 static int 908 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq) 909 { 910 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 911 uint16_t hw_cidx = spg->cidx; /* snapshot */ 912 struct fw_eth_tx_pkts_wr *wr; 913 int n = 0; 914 915 hw_cidx = be16toh(hw_cidx); 916 917 while (nm_txq->cidx != hw_cidx) { 918 wr = (void *)&nm_txq->desc[nm_txq->cidx]; 919 920 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)) || 921 wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR))); 922 MPASS(wr->type == 1); 923 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR); 924 925 n += wr->npkt; 926 nm_txq->cidx += npkt_to_ndesc(wr->npkt); 927 928 /* 929 * We never sent a WR that wrapped around so the credits coming 930 * back, WR by WR, should never cause the cidx to wrap around 931 * either. 932 */ 933 MPASS(nm_txq->cidx <= nm_txq->sidx); 934 if (__predict_false(nm_txq->cidx == nm_txq->sidx)) 935 nm_txq->cidx = 0; 936 } 937 938 return (n); 939 } 940 941 static int 942 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) 943 { 944 struct netmap_adapter *na = kring->na; 945 struct ifnet *ifp = na->ifp; 946 struct vi_info *vi = ifp->if_softc; 947 struct adapter *sc = vi->adapter; 948 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id]; 949 const u_int head = kring->rhead; 950 u_int reclaimed = 0; 951 int n, d, npkt_remaining, ndesc_remaining; 952 953 /* 954 * Tx was at kring->nr_hwcur last time around and now we need to advance 955 * to kring->rhead. Note that the driver's pidx moves independent of 956 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation 957 * between descriptors and frames isn't 1:1). 958 */ 959 960 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 961 kring->nkr_num_slots - kring->nr_hwcur + head; 962 while (npkt_remaining) { 963 reclaimed += reclaim_nm_tx_desc(nm_txq); 964 ndesc_remaining = contiguous_ndesc_available(nm_txq); 965 /* Can't run out of descriptors with packets still remaining */ 966 MPASS(ndesc_remaining > 0); 967 968 /* # of desc needed to tx all remaining packets */ 969 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC; 970 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR) 971 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR); 972 973 if (d <= ndesc_remaining) 974 n = npkt_remaining; 975 else { 976 /* Can't send all, calculate how many can be sent */ 977 n = (ndesc_remaining / SGE_MAX_WR_NDESC) * 978 MAX_NPKT_IN_TYPE1_WR; 979 if (ndesc_remaining % SGE_MAX_WR_NDESC) 980 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC); 981 } 982 983 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */ 984 npkt_remaining -= n; 985 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining); 986 } 987 MPASS(npkt_remaining == 0); 988 MPASS(kring->nr_hwcur == head); 989 MPASS(nm_txq->dbidx == nm_txq->pidx); 990 991 /* 992 * Second part: reclaim buffers for completed transmissions. 993 */ 994 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) { 995 reclaimed += reclaim_nm_tx_desc(nm_txq); 996 kring->nr_hwtail += reclaimed; 997 if (kring->nr_hwtail >= kring->nkr_num_slots) 998 kring->nr_hwtail -= kring->nkr_num_slots; 999 } 1000 1001 return (0); 1002 } 1003 1004 static int 1005 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) 1006 { 1007 struct netmap_adapter *na = kring->na; 1008 struct netmap_ring *ring = kring->ring; 1009 struct ifnet *ifp = na->ifp; 1010 struct vi_info *vi = ifp->if_softc; 1011 struct adapter *sc = vi->adapter; 1012 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id]; 1013 u_int const head = kring->rhead; 1014 u_int n; 1015 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1016 1017 if (black_hole) 1018 return (0); /* No updates ever. */ 1019 1020 if (netmap_no_pendintr || force_update) { 1021 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx); 1022 kring->nr_kflags &= ~NKR_PENDINTR; 1023 } 1024 1025 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) { 1026 wmb(); 1027 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1028 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved)); 1029 nm_rxq->fl_db_saved = 0; 1030 } 1031 1032 /* Userspace done with buffers from kring->nr_hwcur to head */ 1033 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 1034 kring->nkr_num_slots - kring->nr_hwcur + head; 1035 n &= ~7U; 1036 if (n > 0) { 1037 u_int fl_pidx = nm_rxq->fl_pidx; 1038 struct netmap_slot *slot = &ring->slot[fl_pidx]; 1039 uint64_t ba; 1040 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx; 1041 1042 /* 1043 * We always deal with 8 buffers at a time. We must have 1044 * stopped at an 8B boundary (fl_pidx) last time around and we 1045 * must have a multiple of 8B buffers to give to the freelist. 1046 */ 1047 MPASS((fl_pidx & 7) == 0); 1048 MPASS((n & 7) == 0); 1049 1050 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots); 1051 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx2); 1052 1053 while (n > 0) { 1054 for (i = 0; i < 8; i++, fl_pidx++, slot++) { 1055 PNMB(na, slot, &ba); 1056 MPASS(ba != 0); 1057 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx); 1058 slot->flags &= ~NS_BUF_CHANGED; 1059 MPASS(fl_pidx <= nm_rxq->fl_sidx2); 1060 } 1061 n -= 8; 1062 if (fl_pidx == nm_rxq->fl_sidx2) { 1063 fl_pidx = 0; 1064 slot = &ring->slot[0]; 1065 } 1066 if (++dbinc == nm_rxq->fl_db_threshold) { 1067 wmb(); 1068 if (starve_fl) 1069 nm_rxq->fl_db_saved += dbinc; 1070 else { 1071 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1072 nm_rxq->fl_db_val | V_PIDX(dbinc)); 1073 } 1074 dbinc = 0; 1075 } 1076 } 1077 MPASS(nm_rxq->fl_pidx == fl_pidx); 1078 1079 if (dbinc > 0) { 1080 wmb(); 1081 if (starve_fl) 1082 nm_rxq->fl_db_saved += dbinc; 1083 else { 1084 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1085 nm_rxq->fl_db_val | V_PIDX(dbinc)); 1086 } 1087 } 1088 } 1089 1090 return (0); 1091 } 1092 1093 void 1094 cxgbe_nm_attach(struct vi_info *vi) 1095 { 1096 struct port_info *pi; 1097 struct adapter *sc; 1098 struct netmap_adapter na; 1099 1100 MPASS(vi->nnmrxq > 0); 1101 MPASS(vi->ifp != NULL); 1102 1103 pi = vi->pi; 1104 sc = pi->adapter; 1105 1106 bzero(&na, sizeof(na)); 1107 1108 na.ifp = vi->ifp; 1109 na.na_flags = NAF_BDG_MAYSLEEP; 1110 1111 /* Netmap doesn't know about the space reserved for the status page. */ 1112 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE; 1113 1114 /* 1115 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So 1116 * num_rx_desc is based on the number of buffers that can be held in the 1117 * freelist, and not the number of entries in the iq. (These two are 1118 * not exactly the same due to the space taken up by the status page). 1119 */ 1120 na.num_rx_desc = rounddown(vi->qsize_rxq, 8); 1121 na.nm_txsync = cxgbe_netmap_txsync; 1122 na.nm_rxsync = cxgbe_netmap_rxsync; 1123 na.nm_register = cxgbe_netmap_reg; 1124 na.num_tx_rings = vi->nnmtxq; 1125 na.num_rx_rings = vi->nnmrxq; 1126 na.rx_buf_maxsize = MAX_MTU; 1127 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */ 1128 } 1129 1130 void 1131 cxgbe_nm_detach(struct vi_info *vi) 1132 { 1133 1134 MPASS(vi->nnmrxq > 0); 1135 MPASS(vi->ifp != NULL); 1136 1137 netmap_detach(vi->ifp); 1138 } 1139 1140 static inline const void * 1141 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl) 1142 { 1143 1144 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL); 1145 1146 /* data[0] is RSS header */ 1147 return (&cpl->data[1]); 1148 } 1149 1150 static void 1151 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp, 1152 const struct cpl_sge_egr_update *egr) 1153 { 1154 uint32_t oq; 1155 struct sge_nm_txq *nm_txq; 1156 1157 oq = be32toh(egr->opcode_qid); 1158 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 1159 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 1160 1161 netmap_tx_irq(ifp, nm_txq->nid); 1162 } 1163 1164 void 1165 service_nm_rxq(struct sge_nm_rxq *nm_rxq) 1166 { 1167 struct vi_info *vi = nm_rxq->vi; 1168 struct adapter *sc = vi->adapter; 1169 struct ifnet *ifp = vi->ifp; 1170 struct netmap_adapter *na = NA(ifp); 1171 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid]; 1172 struct netmap_ring *ring = kring->ring; 1173 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; 1174 const void *cpl; 1175 uint32_t lq; 1176 u_int work = 0; 1177 uint8_t opcode; 1178 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 1179 u_int fl_credits = fl_cidx & 7; 1180 u_int ndesc = 0; /* desc processed since last cidx update */ 1181 u_int nframes = 0; /* frames processed since last netmap wakeup */ 1182 1183 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 1184 1185 rmb(); 1186 1187 lq = be32toh(d->rsp.pldbuflen_qid); 1188 opcode = d->rss.opcode; 1189 cpl = &d->cpl[0]; 1190 1191 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 1192 case X_RSPD_TYPE_FLBUF: 1193 1194 /* fall through */ 1195 1196 case X_RSPD_TYPE_CPL: 1197 MPASS(opcode < NUM_CPL_CMDS); 1198 1199 switch (opcode) { 1200 case CPL_FW4_MSG: 1201 case CPL_FW6_MSG: 1202 cpl = unwrap_nm_fw6_msg(cpl); 1203 /* fall through */ 1204 case CPL_SGE_EGR_UPDATE: 1205 handle_nm_sge_egr_update(sc, ifp, cpl); 1206 break; 1207 case CPL_RX_PKT: 1208 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 1209 sc->params.sge.fl_pktshift; 1210 ring->slot[fl_cidx].flags = 0; 1211 nframes++; 1212 if (!(lq & F_RSPD_NEWBUF)) { 1213 MPASS(black_hole == 2); 1214 break; 1215 } 1216 fl_credits++; 1217 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx)) 1218 fl_cidx = 0; 1219 break; 1220 default: 1221 panic("%s: unexpected opcode 0x%x on nm_rxq %p", 1222 __func__, opcode, nm_rxq); 1223 } 1224 break; 1225 1226 case X_RSPD_TYPE_INTR: 1227 /* Not equipped to handle forwarded interrupts. */ 1228 panic("%s: netmap queue received interrupt for iq %u\n", 1229 __func__, lq); 1230 1231 default: 1232 panic("%s: illegal response type %d on nm_rxq %p", 1233 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq); 1234 } 1235 1236 d++; 1237 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) { 1238 nm_rxq->iq_cidx = 0; 1239 d = &nm_rxq->iq_desc[0]; 1240 nm_rxq->iq_gen ^= F_RSPD_GEN; 1241 } 1242 1243 if (__predict_false(++nframes == rx_nframes) && !black_hole) { 1244 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1245 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1246 nframes = 0; 1247 } 1248 1249 if (__predict_false(++ndesc == rx_ndesc)) { 1250 if (black_hole && fl_credits >= 8) { 1251 fl_credits /= 8; 1252 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, 1253 nm_rxq->fl_sidx); 1254 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1255 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1256 fl_credits = fl_cidx & 7; 1257 } 1258 t4_write_reg(sc, sc->sge_gts_reg, 1259 V_CIDXINC(ndesc) | 1260 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 1261 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1262 ndesc = 0; 1263 } 1264 } 1265 1266 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1267 if (black_hole) { 1268 fl_credits /= 8; 1269 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx); 1270 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1271 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1272 } else if (nframes > 0) 1273 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1274 1275 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) | 1276 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) | 1277 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 1278 } 1279 #endif 1280