1 /*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 34 #ifdef DEV_NETMAP 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/lock.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/selinfo.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <machine/bus.h> 45 #include <vm/vm.h> 46 #include <vm/pmap.h> 47 #include <net/ethernet.h> 48 #include <net/if.h> 49 #include <net/if_media.h> 50 #include <net/if_var.h> 51 #include <net/if_clone.h> 52 #include <net/if_types.h> 53 #include <net/netmap.h> 54 #include <dev/netmap/netmap_kern.h> 55 56 #include "common/common.h" 57 #include "common/t4_regs.h" 58 #include "common/t4_regs_values.h" 59 60 extern int fl_pad; /* XXXNM */ 61 62 /* 63 * 0 = normal netmap rx 64 * 1 = black hole 65 * 2 = supermassive black hole (buffer packing enabled) 66 */ 67 int black_hole = 0; 68 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RWTUN, &black_hole, 0, 69 "Sink incoming packets."); 70 71 int rx_ndesc = 256; 72 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN, 73 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated."); 74 75 int rx_nframes = 64; 76 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_nframes, CTLFLAG_RWTUN, 77 &rx_nframes, 0, "max # of frames received before waking up netmap rx."); 78 79 int holdoff_tmr_idx = 2; 80 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN, 81 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues."); 82 83 /* 84 * Congestion drops. 85 * -1: no congestion feedback (not recommended). 86 * 0: backpressure the channel instead of dropping packets right away. 87 * 1: no backpressure, drop packets for the congested queue immediately. 88 */ 89 static int nm_cong_drop = 1; 90 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_cong_drop, CTLFLAG_RWTUN, 91 &nm_cong_drop, 0, 92 "Congestion control for netmap rx queues (0 = backpressure, 1 = drop"); 93 94 int starve_fl = 0; 95 SYSCTL_INT(_hw_cxgbe, OID_AUTO, starve_fl, CTLFLAG_RWTUN, 96 &starve_fl, 0, "Don't ring fl db for netmap rx queues."); 97 98 /* 99 * Try to process tx credits in bulk. This may cause a delay in the return of 100 * tx credits and is suitable for bursty or non-stop tx only. 101 */ 102 int lazy_tx_credit_flush = 1; 103 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lazy_tx_credit_flush, CTLFLAG_RWTUN, 104 &lazy_tx_credit_flush, 0, "lazy credit flush for netmap tx queues."); 105 106 /* 107 * Split the netmap rx queues into two groups that populate separate halves of 108 * the RSS indirection table. This allows filters with hashmask to steer to a 109 * particular group of queues. 110 */ 111 static int nm_split_rss = 0; 112 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_split_rss, CTLFLAG_RWTUN, 113 &nm_split_rss, 0, "Split the netmap rx queues into two groups."); 114 115 /* 116 * netmap(4) says "netmap does not use features such as checksum offloading, TCP 117 * segmentation offloading, encryption, VLAN encapsulation/decapsulation, etc." 118 * but this knob can be used to get the hardware to checksum all tx traffic 119 * anyway. 120 */ 121 static int nm_txcsum = 0; 122 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_txcsum, CTLFLAG_RWTUN, 123 &nm_txcsum, 0, "Enable transmit checksum offloading."); 124 125 static int 126 alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong) 127 { 128 int rc, cntxt_id, i; 129 __be32 v; 130 struct adapter *sc = vi->adapter; 131 struct sge_params *sp = &sc->params.sge; 132 struct netmap_adapter *na = NA(vi->ifp); 133 struct fw_iq_cmd c; 134 135 MPASS(na != NULL); 136 MPASS(nm_rxq->iq_desc != NULL); 137 MPASS(nm_rxq->fl_desc != NULL); 138 139 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE); 140 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len); 141 142 bzero(&c, sizeof(c)); 143 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 144 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 145 V_FW_IQ_CMD_VFN(0)); 146 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 147 FW_LEN16(c)); 148 MPASS(!forwarding_intr_to_fwq(sc)); 149 KASSERT(nm_rxq->intr_idx < sc->intr_count, 150 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx)); 151 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx); 152 c.type_to_iqandstindex = htobe32(v | 153 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 154 V_FW_IQ_CMD_VIID(vi->viid) | 155 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 156 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 157 F_FW_IQ_CMD_IQGTSMODE | 158 V_FW_IQ_CMD_IQINTCNTTHRESH(0) | 159 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 160 c.iqsize = htobe16(vi->qsize_rxq); 161 c.iqaddr = htobe64(nm_rxq->iq_ba); 162 if (cong >= 0) { 163 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | 164 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF | 165 F_FW_IQ_CMD_FL0CONGEN); 166 } 167 c.iqns_to_fl0congen |= 168 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 169 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 170 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 171 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 172 c.fl0dcaen_to_fl0cidxfthresh = 173 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ? 174 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) | 175 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ? 176 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B)); 177 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 178 c.fl0addr = htobe64(nm_rxq->fl_ba); 179 180 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 181 if (rc != 0) { 182 device_printf(sc->dev, 183 "failed to create netmap ingress queue: %d\n", rc); 184 return (rc); 185 } 186 187 nm_rxq->iq_cidx = 0; 188 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE); 189 nm_rxq->iq_gen = F_RSPD_GEN; 190 nm_rxq->iq_cntxt_id = be16toh(c.iqid); 191 nm_rxq->iq_abs_id = be16toh(c.physiqid); 192 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start; 193 if (cntxt_id >= sc->sge.iqmap_sz) { 194 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)", 195 __func__, cntxt_id, sc->sge.iqmap_sz - 1); 196 } 197 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq; 198 199 nm_rxq->fl_cntxt_id = be16toh(c.fl0id); 200 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 201 nm_rxq->fl_db_saved = 0; 202 /* matches the X_FETCHBURSTMAX_512B or X_FETCHBURSTMAX_256B above. */ 203 nm_rxq->fl_db_threshold = chip_id(sc) <= CHELSIO_T5 ? 8 : 4; 204 MPASS(nm_rxq->fl_sidx == na->num_rx_desc); 205 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start; 206 if (cntxt_id >= sc->sge.eqmap_sz) { 207 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 208 __func__, cntxt_id, sc->sge.eqmap_sz - 1); 209 } 210 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 211 212 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 213 sc->chip_params->sge_fl_db; 214 215 if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) { 216 uint32_t param, val; 217 218 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 219 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 220 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 221 if (cong == 0) 222 val = 1 << 19; 223 else { 224 val = 2 << 19; 225 for (i = 0; i < 4; i++) { 226 if (cong & (1 << i)) 227 val |= 1 << (i << 2); 228 } 229 } 230 231 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 232 if (rc != 0) { 233 /* report error but carry on */ 234 device_printf(sc->dev, 235 "failed to set congestion manager context for " 236 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc); 237 } 238 } 239 240 t4_write_reg(sc, sc->sge_gts_reg, 241 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 242 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 243 244 return (rc); 245 } 246 247 static int 248 free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 249 { 250 struct adapter *sc = vi->adapter; 251 int rc; 252 253 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 254 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 255 if (rc != 0) 256 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n", 257 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc); 258 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID; 259 return (rc); 260 } 261 262 static int 263 alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 264 { 265 int rc, cntxt_id; 266 size_t len; 267 struct adapter *sc = vi->adapter; 268 struct netmap_adapter *na = NA(vi->ifp); 269 struct fw_eq_eth_cmd c; 270 271 MPASS(na != NULL); 272 MPASS(nm_txq->desc != NULL); 273 274 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 275 bzero(nm_txq->desc, len); 276 277 bzero(&c, sizeof(c)); 278 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 279 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 280 V_FW_EQ_ETH_CMD_VFN(0)); 281 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 282 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 283 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 284 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 285 c.fetchszm_to_iqid = 286 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 287 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 288 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id)); 289 c.dcaen_to_eqsize = 290 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ? 291 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) | 292 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 293 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE)); 294 c.eqaddr = htobe64(nm_txq->ba); 295 296 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 297 if (rc != 0) { 298 device_printf(vi->dev, 299 "failed to create netmap egress queue: %d\n", rc); 300 return (rc); 301 } 302 303 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 304 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start; 305 if (cntxt_id >= sc->sge.eqmap_sz) 306 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__, 307 cntxt_id, sc->sge.eqmap_sz - 1); 308 sc->sge.eqmap[cntxt_id] = (void *)nm_txq; 309 310 nm_txq->pidx = nm_txq->cidx = 0; 311 MPASS(nm_txq->sidx == na->num_tx_desc); 312 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0; 313 314 nm_txq->doorbells = sc->doorbells; 315 if (isset(&nm_txq->doorbells, DOORBELL_UDB) || 316 isset(&nm_txq->doorbells, DOORBELL_UDBWC) || 317 isset(&nm_txq->doorbells, DOORBELL_WCWR)) { 318 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 319 uint32_t mask = (1 << s_qpp) - 1; 320 volatile uint8_t *udb; 321 322 udb = sc->udbs_base + UDBS_DB_OFFSET; 323 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT; 324 nm_txq->udb_qid = nm_txq->cntxt_id & mask; 325 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 326 clrbit(&nm_txq->doorbells, DOORBELL_WCWR); 327 else { 328 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT; 329 nm_txq->udb_qid = 0; 330 } 331 nm_txq->udb = (volatile void *)udb; 332 } 333 334 if (sc->params.fw_vers < FW_VERSION32(1, 25, 1, 0)) { 335 uint32_t param, val; 336 337 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 338 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH) | 339 V_FW_PARAMS_PARAM_YZ(nm_txq->cntxt_id); 340 val = 0xff; 341 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 342 if (rc != 0) { 343 device_printf(vi->dev, 344 "failed to bind netmap txq %d to class 0xff: %d\n", 345 nm_txq->cntxt_id, rc); 346 rc = 0; 347 } 348 } 349 350 return (rc); 351 } 352 353 static int 354 free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 355 { 356 struct adapter *sc = vi->adapter; 357 int rc; 358 359 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 360 if (rc != 0) 361 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__, 362 nm_txq->cntxt_id, rc); 363 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID; 364 return (rc); 365 } 366 367 static int 368 cxgbe_netmap_simple_rss(struct adapter *sc, struct vi_info *vi, 369 struct ifnet *ifp, struct netmap_adapter *na) 370 { 371 struct netmap_kring *kring; 372 struct sge_nm_rxq *nm_rxq; 373 int rc, i, j, nm_state, defq; 374 uint16_t *rss; 375 376 /* 377 * Check if there's at least one active (or about to go active) netmap 378 * rx queue. 379 */ 380 defq = -1; 381 for_each_nm_rxq(vi, j, nm_rxq) { 382 nm_state = atomic_load_int(&nm_rxq->nm_state); 383 kring = na->rx_rings[nm_rxq->nid]; 384 if ((nm_state != NM_OFF && !nm_kring_pending_off(kring)) || 385 (nm_state == NM_OFF && nm_kring_pending_on(kring))) { 386 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 387 if (defq == -1) { 388 defq = nm_rxq->iq_abs_id; 389 break; 390 } 391 } 392 } 393 394 if (defq == -1) { 395 /* No active netmap queues. Switch back to NIC queues. */ 396 rss = vi->rss; 397 defq = vi->rss[0]; 398 } else { 399 for (i = 0; i < vi->rss_size;) { 400 for_each_nm_rxq(vi, j, nm_rxq) { 401 nm_state = atomic_load_int(&nm_rxq->nm_state); 402 kring = na->rx_rings[nm_rxq->nid]; 403 if ((nm_state != NM_OFF && 404 !nm_kring_pending_off(kring)) || 405 (nm_state == NM_OFF && 406 nm_kring_pending_on(kring))) { 407 MPASS(nm_rxq->iq_cntxt_id != 408 INVALID_NM_RXQ_CNTXT_ID); 409 vi->nm_rss[i++] = nm_rxq->iq_abs_id; 410 if (i == vi->rss_size) 411 break; 412 } 413 } 414 } 415 rss = vi->nm_rss; 416 } 417 418 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 419 vi->rss_size); 420 if (rc != 0) 421 if_printf(ifp, "netmap rss_config failed: %d\n", rc); 422 423 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 424 if (rc != 0) { 425 if_printf(ifp, "netmap defaultq config failed: %d\n", rc); 426 } 427 428 return (rc); 429 } 430 431 /* 432 * Odd number of rx queues work best for split RSS mode as the first queue can 433 * be dedicated for non-RSS traffic and the rest divided into two equal halves. 434 */ 435 static int 436 cxgbe_netmap_split_rss(struct adapter *sc, struct vi_info *vi, 437 struct ifnet *ifp, struct netmap_adapter *na) 438 { 439 struct netmap_kring *kring; 440 struct sge_nm_rxq *nm_rxq; 441 int rc, i, j, nm_state, defq; 442 int nactive[2] = {0, 0}; 443 int dq[2] = {-1, -1}; 444 bool dq_norss; /* default queue should not be in RSS table. */ 445 446 MPASS(nm_split_rss != 0); 447 MPASS(vi->nnmrxq > 1); 448 449 for_each_nm_rxq(vi, i, nm_rxq) { 450 j = i / ((vi->nnmrxq + 1) / 2); 451 nm_state = atomic_load_int(&nm_rxq->nm_state); 452 kring = na->rx_rings[nm_rxq->nid]; 453 if ((nm_state != NM_OFF && !nm_kring_pending_off(kring)) || 454 (nm_state == NM_OFF && nm_kring_pending_on(kring))) { 455 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 456 nactive[j]++; 457 if (dq[j] == -1) { 458 dq[j] = nm_rxq->iq_abs_id; 459 break; 460 } 461 } 462 } 463 464 if (nactive[0] == 0 || nactive[1] == 0) 465 return (cxgbe_netmap_simple_rss(sc, vi, ifp, na)); 466 467 MPASS(dq[0] != -1 && dq[1] != -1); 468 if (nactive[0] > nactive[1]) { 469 defq = dq[0]; 470 dq_norss = true; 471 } else if (nactive[0] < nactive[1]) { 472 defq = dq[1]; 473 dq_norss = true; 474 } else { 475 defq = dq[0]; 476 dq_norss = false; 477 } 478 479 i = 0; 480 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq]; 481 while (i < vi->rss_size / 2) { 482 for (j = 0; j < (vi->nnmrxq + 1) / 2; j++) { 483 nm_state = atomic_load_int(&nm_rxq[j].nm_state); 484 kring = na->rx_rings[nm_rxq[j].nid]; 485 if ((nm_state == NM_OFF && 486 !nm_kring_pending_on(kring)) || 487 (nm_state == NM_ON && 488 nm_kring_pending_off(kring))) { 489 continue; 490 } 491 MPASS(nm_rxq[j].iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 492 if (dq_norss && defq == nm_rxq[j].iq_abs_id) 493 continue; 494 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 495 if (i == vi->rss_size / 2) 496 break; 497 } 498 } 499 while (i < vi->rss_size) { 500 for (j = (vi->nnmrxq + 1) / 2; j < vi->nnmrxq; j++) { 501 nm_state = atomic_load_int(&nm_rxq[j].nm_state); 502 kring = na->rx_rings[nm_rxq[j].nid]; 503 if ((nm_state == NM_OFF && 504 !nm_kring_pending_on(kring)) || 505 (nm_state == NM_ON && 506 nm_kring_pending_off(kring))) { 507 continue; 508 } 509 MPASS(nm_rxq[j].iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 510 if (dq_norss && defq == nm_rxq[j].iq_abs_id) 511 continue; 512 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id; 513 if (i == vi->rss_size) 514 break; 515 } 516 } 517 518 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 519 vi->nm_rss, vi->rss_size); 520 if (rc != 0) 521 if_printf(ifp, "netmap split_rss_config failed: %d\n", rc); 522 523 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0); 524 if (rc != 0) 525 if_printf(ifp, "netmap defaultq config failed: %d\n", rc); 526 527 return (rc); 528 } 529 530 static inline int 531 cxgbe_netmap_rss(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 532 struct netmap_adapter *na) 533 { 534 535 if (nm_split_rss == 0 || vi->nnmrxq == 1) 536 return (cxgbe_netmap_simple_rss(sc, vi, ifp, na)); 537 else 538 return (cxgbe_netmap_split_rss(sc, vi, ifp, na)); 539 } 540 541 static int 542 cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 543 struct netmap_adapter *na) 544 { 545 struct netmap_slot *slot; 546 struct netmap_kring *kring; 547 struct sge_nm_rxq *nm_rxq; 548 struct sge_nm_txq *nm_txq; 549 int i, j, hwidx; 550 struct rx_buf_info *rxb; 551 552 ASSERT_SYNCHRONIZED_OP(sc); 553 MPASS(vi->nnmrxq > 0); 554 MPASS(vi->nnmtxq > 0); 555 556 if ((vi->flags & VI_INIT_DONE) == 0 || 557 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 558 if_printf(ifp, "cannot enable netmap operation because " 559 "interface is not UP.\n"); 560 return (EAGAIN); 561 } 562 563 rxb = &sc->sge.rx_buf_info[0]; 564 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) { 565 if (rxb->size1 == NETMAP_BUF_SIZE(na)) { 566 hwidx = rxb->hwidx1; 567 break; 568 } 569 if (rxb->size2 == NETMAP_BUF_SIZE(na)) { 570 hwidx = rxb->hwidx2; 571 break; 572 } 573 } 574 if (i >= SW_ZONE_SIZES) { 575 if_printf(ifp, "no hwidx for netmap buffer size %d.\n", 576 NETMAP_BUF_SIZE(na)); 577 return (ENXIO); 578 } 579 580 /* Must set caps before calling netmap_reset */ 581 nm_set_native_flags(na); 582 583 for_each_nm_rxq(vi, i, nm_rxq) { 584 kring = na->rx_rings[nm_rxq->nid]; 585 if (!nm_kring_pending_on(kring) || 586 nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID) 587 continue; 588 589 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop)); 590 nm_rxq->fl_hwidx = hwidx; 591 nm_rxq->bb_zone = rxb->zone; 592 nm_rxq->bb = uma_zalloc(nm_rxq->bb_zone, M_WAITOK); 593 slot = netmap_reset(na, NR_RX, i, 0); 594 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 595 596 /* We deal with 8 bufs at a time */ 597 MPASS((na->num_rx_desc & 7) == 0); 598 MPASS(na->num_rx_desc == nm_rxq->fl_sidx); 599 for (j = 0; j < nm_rxq->fl_sidx; j++) { 600 uint64_t ba; 601 602 PNMB(na, &slot[j], &ba); 603 MPASS(ba != 0); 604 nm_rxq->fl_desc[j] = htobe64(ba | hwidx); 605 } 606 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8; 607 MPASS((j & 7) == 0); 608 j /= 8; /* driver pidx to hardware pidx */ 609 wmb(); 610 t4_write_reg(sc, sc->sge_kdoorbell_reg, 611 nm_rxq->fl_db_val | V_PIDX(j)); 612 613 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON); 614 } 615 616 for_each_nm_txq(vi, i, nm_txq) { 617 kring = na->tx_rings[nm_txq->nid]; 618 if (!nm_kring_pending_on(kring) || 619 nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID) 620 continue; 621 622 alloc_nm_txq_hwq(vi, nm_txq); 623 slot = netmap_reset(na, NR_TX, i, 0); 624 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 625 } 626 627 if (vi->nm_rss == NULL) { 628 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE, 629 M_ZERO | M_WAITOK); 630 } 631 632 return (cxgbe_netmap_rss(sc, vi, ifp, na)); 633 } 634 635 static void 636 flush_nm_rxq(struct adapter *sc, struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 637 { 638 int i, n; 639 u_int fl_pidx, fl_pidx_target, hw_cidx_desc; 640 const uint64_t ba = pmap_kextract((vm_offset_t)nm_rxq->bb); 641 642 hw_cidx_desc = nm_rxq->fl_cidx / 8; 643 if (hw_cidx_desc == 0) 644 fl_pidx_target = nm_rxq->fl_sidx2 - 8; 645 else 646 fl_pidx_target = (hw_cidx_desc - 1) * 8; 647 MPASS((fl_pidx_target & 7) == 0); 648 649 fl_pidx = nm_rxq->fl_pidx; 650 MPASS((fl_pidx & 7) == 0); 651 for (n = 0; fl_pidx != fl_pidx_target; n++) { 652 for (i = 0; i < 8; i++, fl_pidx++) 653 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | nm_rxq->fl_hwidx); 654 if (__predict_false(fl_pidx == nm_rxq->fl_sidx2)) 655 fl_pidx = 0; 656 } 657 t4_write_reg(sc, sc->sge_kdoorbell_reg, nm_rxq->fl_db_val | V_PIDX(n)); 658 } 659 660 static int 661 cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 662 struct netmap_adapter *na) 663 { 664 struct netmap_kring *kring; 665 int rc, i, nm_state, nactive; 666 struct sge_nm_txq *nm_txq; 667 struct sge_nm_rxq *nm_rxq; 668 669 ASSERT_SYNCHRONIZED_OP(sc); 670 MPASS(vi->nnmrxq > 0); 671 MPASS(vi->nnmtxq > 0); 672 673 if (!nm_netmap_on(na)) 674 return (0); 675 676 if ((vi->flags & VI_INIT_DONE) == 0) 677 return (0); 678 679 /* First remove the queues that are stopping from the RSS table. */ 680 rc = cxgbe_netmap_rss(sc, vi, ifp, na); 681 if (rc != 0) 682 return (rc); /* error message logged already. */ 683 684 /* 685 * First pass over the rx queues to make sure they're all caught up. 686 * 687 * The freelists could be out of buffers and we may need to arrange 688 * things so that any packets still in flight (after TP's cong_drop 689 * logic but not yet DMA'd) have somewhere to go and do not block the 690 * pipeline. Do this before trying to free any queue. 691 */ 692 for_each_nm_rxq(vi, i, nm_rxq) { 693 nm_state = atomic_load_int(&nm_rxq->nm_state); 694 kring = na->rx_rings[nm_rxq->nid]; 695 if (nm_state == NM_OFF || !nm_kring_pending_off(kring)) 696 continue; 697 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 698 flush_nm_rxq(sc, vi, nm_rxq); 699 } 700 701 for_each_nm_txq(vi, i, nm_txq) { 702 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 703 704 kring = na->tx_rings[nm_txq->nid]; 705 if (!nm_kring_pending_off(kring) || 706 nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) 707 continue; 708 709 /* Wait for hw pidx to catch up ... */ 710 while (be16toh(nm_txq->pidx) != spg->pidx) 711 pause("nmpidx", 1); 712 713 /* ... and then for the cidx. */ 714 while (spg->pidx != spg->cidx) 715 pause("nmcidx", 1); 716 717 free_nm_txq_hwq(vi, nm_txq); 718 719 /* XXX: netmap, not the driver, should do this. */ 720 kring->rhead = kring->rcur = kring->nr_hwcur = 0; 721 kring->rtail = kring->nr_hwtail = kring->nkr_num_slots - 1; 722 } 723 nactive = 0; 724 for_each_nm_rxq(vi, i, nm_rxq) { 725 nm_state = atomic_load_int(&nm_rxq->nm_state); 726 kring = na->rx_rings[nm_rxq->nid]; 727 if (nm_state != NM_OFF && !nm_kring_pending_off(kring)) 728 nactive++; 729 if (nm_state == NM_OFF || !nm_kring_pending_off(kring)) 730 continue; 731 732 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID); 733 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF)) 734 pause("nmst", 1); 735 736 free_nm_rxq_hwq(vi, nm_rxq); 737 uma_zfree(nm_rxq->bb_zone, nm_rxq->bb); 738 nm_rxq->bb = NULL; 739 740 /* XXX: netmap, not the driver, should do this. */ 741 kring->rhead = kring->rcur = kring->nr_hwcur = 0; 742 kring->rtail = kring->nr_hwtail = 0; 743 } 744 netmap_krings_mode_commit(na, 0); 745 if (nactive == 0) 746 nm_clear_native_flags(na); 747 748 return (rc); 749 } 750 751 static int 752 cxgbe_netmap_reg(struct netmap_adapter *na, int on) 753 { 754 struct ifnet *ifp = na->ifp; 755 struct vi_info *vi = ifp->if_softc; 756 struct adapter *sc = vi->adapter; 757 int rc; 758 759 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg"); 760 if (rc != 0) 761 return (rc); 762 if (on) 763 rc = cxgbe_netmap_on(sc, vi, ifp, na); 764 else 765 rc = cxgbe_netmap_off(sc, vi, ifp, na); 766 end_synchronized_op(sc, 0); 767 768 return (rc); 769 } 770 771 /* How many packets can a single type1 WR carry in n descriptors */ 772 static inline int 773 ndesc_to_npkt(const int n) 774 { 775 776 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC); 777 778 return (n * 2 - 1); 779 } 780 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC)) 781 782 /* 783 * Space (in descriptors) needed for a type1 WR (TX_PKTS or TX_PKTS2) that 784 * carries n packets 785 */ 786 static inline int 787 npkt_to_ndesc(const int n) 788 { 789 790 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 791 792 return ((n + 2) / 2); 793 } 794 795 /* 796 * Space (in 16B units) needed for a type1 WR (TX_PKTS or TX_PKTS2) that 797 * carries n packets 798 */ 799 static inline int 800 npkt_to_len16(const int n) 801 { 802 803 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 804 805 return (n * 2 + 1); 806 } 807 808 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx) 809 810 static void 811 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq) 812 { 813 int n; 814 u_int db = nm_txq->doorbells; 815 816 MPASS(nm_txq->pidx != nm_txq->dbidx); 817 818 n = NMIDXDIFF(nm_txq, dbidx); 819 if (n > 1) 820 clrbit(&db, DOORBELL_WCWR); 821 wmb(); 822 823 switch (ffs(db) - 1) { 824 case DOORBELL_UDB: 825 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 826 break; 827 828 case DOORBELL_WCWR: { 829 volatile uint64_t *dst, *src; 830 831 /* 832 * Queues whose 128B doorbell segment fits in the page do not 833 * use relative qid (udb_qid is always 0). Only queues with 834 * doorbell segments can do WCWR. 835 */ 836 KASSERT(nm_txq->udb_qid == 0 && n == 1, 837 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p", 838 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq)); 839 840 dst = (volatile void *)((uintptr_t)nm_txq->udb + 841 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 842 src = (void *)&nm_txq->desc[nm_txq->dbidx]; 843 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1]) 844 *dst++ = *src++; 845 wmb(); 846 break; 847 } 848 849 case DOORBELL_UDBWC: 850 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 851 wmb(); 852 break; 853 854 case DOORBELL_KDB: 855 t4_write_reg(sc, sc->sge_kdoorbell_reg, 856 V_QID(nm_txq->cntxt_id) | V_PIDX(n)); 857 break; 858 } 859 nm_txq->dbidx = nm_txq->pidx; 860 } 861 862 /* 863 * Write work requests to send 'npkt' frames and ring the doorbell to send them 864 * on their way. No need to check for wraparound. 865 */ 866 static void 867 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq, 868 struct netmap_kring *kring, int npkt, int npkt_remaining) 869 { 870 struct netmap_ring *ring = kring->ring; 871 struct netmap_slot *slot; 872 const u_int lim = kring->nkr_num_slots - 1; 873 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx]; 874 uint16_t len; 875 uint64_t ba; 876 struct cpl_tx_pkt_core *cpl; 877 struct ulptx_sgl *usgl; 878 int i, n; 879 880 while (npkt) { 881 n = min(npkt, MAX_NPKT_IN_TYPE1_WR); 882 len = 0; 883 884 wr = (void *)&nm_txq->desc[nm_txq->pidx]; 885 wr->op_pkd = nm_txq->op_pkd; 886 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n))); 887 wr->npkt = n; 888 wr->r3 = 0; 889 wr->type = 1; 890 cpl = (void *)(wr + 1); 891 892 for (i = 0; i < n; i++) { 893 slot = &ring->slot[kring->nr_hwcur]; 894 PNMB(kring->na, slot, &ba); 895 MPASS(ba != 0); 896 897 cpl->ctrl0 = nm_txq->cpl_ctrl0; 898 cpl->pack = 0; 899 cpl->len = htobe16(slot->len); 900 cpl->ctrl1 = nm_txcsum ? 0 : 901 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 902 903 usgl = (void *)(cpl + 1); 904 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 905 V_ULPTX_NSGE(1)); 906 usgl->len0 = htobe32(slot->len); 907 usgl->addr0 = htobe64(ba); 908 909 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 910 cpl = (void *)(usgl + 1); 911 MPASS(slot->len + len <= UINT16_MAX); 912 len += slot->len; 913 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim); 914 } 915 wr->plen = htobe16(len); 916 917 npkt -= n; 918 nm_txq->pidx += npkt_to_ndesc(n); 919 MPASS(nm_txq->pidx <= nm_txq->sidx); 920 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) { 921 /* 922 * This routine doesn't know how to write WRs that wrap 923 * around. Make sure it wasn't asked to. 924 */ 925 MPASS(npkt == 0); 926 nm_txq->pidx = 0; 927 } 928 929 if (npkt == 0 && npkt_remaining == 0) { 930 /* All done. */ 931 if (lazy_tx_credit_flush == 0) { 932 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 933 F_FW_WR_EQUIQ); 934 nm_txq->equeqidx = nm_txq->pidx; 935 nm_txq->equiqidx = nm_txq->pidx; 936 } 937 ring_nm_txq_db(sc, nm_txq); 938 return; 939 } 940 941 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) { 942 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 943 F_FW_WR_EQUIQ); 944 nm_txq->equeqidx = nm_txq->pidx; 945 nm_txq->equiqidx = nm_txq->pidx; 946 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) { 947 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 948 nm_txq->equeqidx = nm_txq->pidx; 949 } 950 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC) 951 ring_nm_txq_db(sc, nm_txq); 952 } 953 954 /* Will get called again. */ 955 MPASS(npkt_remaining); 956 } 957 958 /* How many contiguous free descriptors starting at pidx */ 959 static inline int 960 contiguous_ndesc_available(struct sge_nm_txq *nm_txq) 961 { 962 963 if (nm_txq->cidx > nm_txq->pidx) 964 return (nm_txq->cidx - nm_txq->pidx - 1); 965 else if (nm_txq->cidx > 0) 966 return (nm_txq->sidx - nm_txq->pidx); 967 else 968 return (nm_txq->sidx - nm_txq->pidx - 1); 969 } 970 971 static int 972 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq) 973 { 974 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 975 uint16_t hw_cidx = spg->cidx; /* snapshot */ 976 struct fw_eth_tx_pkts_wr *wr; 977 int n = 0; 978 979 hw_cidx = be16toh(hw_cidx); 980 981 while (nm_txq->cidx != hw_cidx) { 982 wr = (void *)&nm_txq->desc[nm_txq->cidx]; 983 984 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)) || 985 wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR))); 986 MPASS(wr->type == 1); 987 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR); 988 989 n += wr->npkt; 990 nm_txq->cidx += npkt_to_ndesc(wr->npkt); 991 992 /* 993 * We never sent a WR that wrapped around so the credits coming 994 * back, WR by WR, should never cause the cidx to wrap around 995 * either. 996 */ 997 MPASS(nm_txq->cidx <= nm_txq->sidx); 998 if (__predict_false(nm_txq->cidx == nm_txq->sidx)) 999 nm_txq->cidx = 0; 1000 } 1001 1002 return (n); 1003 } 1004 1005 static int 1006 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) 1007 { 1008 struct netmap_adapter *na = kring->na; 1009 struct ifnet *ifp = na->ifp; 1010 struct vi_info *vi = ifp->if_softc; 1011 struct adapter *sc = vi->adapter; 1012 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id]; 1013 const u_int head = kring->rhead; 1014 u_int reclaimed = 0; 1015 int n, d, npkt_remaining, ndesc_remaining; 1016 1017 /* 1018 * Tx was at kring->nr_hwcur last time around and now we need to advance 1019 * to kring->rhead. Note that the driver's pidx moves independent of 1020 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation 1021 * between descriptors and frames isn't 1:1). 1022 */ 1023 1024 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 1025 kring->nkr_num_slots - kring->nr_hwcur + head; 1026 while (npkt_remaining) { 1027 reclaimed += reclaim_nm_tx_desc(nm_txq); 1028 ndesc_remaining = contiguous_ndesc_available(nm_txq); 1029 /* Can't run out of descriptors with packets still remaining */ 1030 MPASS(ndesc_remaining > 0); 1031 1032 /* # of desc needed to tx all remaining packets */ 1033 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC; 1034 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR) 1035 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR); 1036 1037 if (d <= ndesc_remaining) 1038 n = npkt_remaining; 1039 else { 1040 /* Can't send all, calculate how many can be sent */ 1041 n = (ndesc_remaining / SGE_MAX_WR_NDESC) * 1042 MAX_NPKT_IN_TYPE1_WR; 1043 if (ndesc_remaining % SGE_MAX_WR_NDESC) 1044 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC); 1045 } 1046 1047 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */ 1048 npkt_remaining -= n; 1049 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining); 1050 } 1051 MPASS(npkt_remaining == 0); 1052 MPASS(kring->nr_hwcur == head); 1053 MPASS(nm_txq->dbidx == nm_txq->pidx); 1054 1055 /* 1056 * Second part: reclaim buffers for completed transmissions. 1057 */ 1058 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) { 1059 reclaimed += reclaim_nm_tx_desc(nm_txq); 1060 kring->nr_hwtail += reclaimed; 1061 if (kring->nr_hwtail >= kring->nkr_num_slots) 1062 kring->nr_hwtail -= kring->nkr_num_slots; 1063 } 1064 1065 return (0); 1066 } 1067 1068 static int 1069 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) 1070 { 1071 struct netmap_adapter *na = kring->na; 1072 struct netmap_ring *ring = kring->ring; 1073 struct ifnet *ifp = na->ifp; 1074 struct vi_info *vi = ifp->if_softc; 1075 struct adapter *sc = vi->adapter; 1076 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id]; 1077 u_int const head = kring->rhead; 1078 u_int n; 1079 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1080 1081 if (black_hole) 1082 return (0); /* No updates ever. */ 1083 1084 if (netmap_no_pendintr || force_update) { 1085 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx); 1086 kring->nr_kflags &= ~NKR_PENDINTR; 1087 } 1088 1089 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) { 1090 wmb(); 1091 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1092 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved)); 1093 nm_rxq->fl_db_saved = 0; 1094 } 1095 1096 /* Userspace done with buffers from kring->nr_hwcur to head */ 1097 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 1098 kring->nkr_num_slots - kring->nr_hwcur + head; 1099 n &= ~7U; 1100 if (n > 0) { 1101 u_int fl_pidx = nm_rxq->fl_pidx; 1102 struct netmap_slot *slot = &ring->slot[fl_pidx]; 1103 uint64_t ba; 1104 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx; 1105 1106 /* 1107 * We always deal with 8 buffers at a time. We must have 1108 * stopped at an 8B boundary (fl_pidx) last time around and we 1109 * must have a multiple of 8B buffers to give to the freelist. 1110 */ 1111 MPASS((fl_pidx & 7) == 0); 1112 MPASS((n & 7) == 0); 1113 1114 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots); 1115 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx2); 1116 1117 while (n > 0) { 1118 for (i = 0; i < 8; i++, fl_pidx++, slot++) { 1119 PNMB(na, slot, &ba); 1120 MPASS(ba != 0); 1121 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx); 1122 slot->flags &= ~NS_BUF_CHANGED; 1123 MPASS(fl_pidx <= nm_rxq->fl_sidx2); 1124 } 1125 n -= 8; 1126 if (fl_pidx == nm_rxq->fl_sidx2) { 1127 fl_pidx = 0; 1128 slot = &ring->slot[0]; 1129 } 1130 if (++dbinc == nm_rxq->fl_db_threshold) { 1131 wmb(); 1132 if (starve_fl) 1133 nm_rxq->fl_db_saved += dbinc; 1134 else { 1135 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1136 nm_rxq->fl_db_val | V_PIDX(dbinc)); 1137 } 1138 dbinc = 0; 1139 } 1140 } 1141 MPASS(nm_rxq->fl_pidx == fl_pidx); 1142 1143 if (dbinc > 0) { 1144 wmb(); 1145 if (starve_fl) 1146 nm_rxq->fl_db_saved += dbinc; 1147 else { 1148 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1149 nm_rxq->fl_db_val | V_PIDX(dbinc)); 1150 } 1151 } 1152 } 1153 1154 return (0); 1155 } 1156 1157 void 1158 cxgbe_nm_attach(struct vi_info *vi) 1159 { 1160 struct port_info *pi; 1161 struct adapter *sc; 1162 struct netmap_adapter na; 1163 1164 MPASS(vi->nnmrxq > 0); 1165 MPASS(vi->ifp != NULL); 1166 1167 pi = vi->pi; 1168 sc = pi->adapter; 1169 1170 bzero(&na, sizeof(na)); 1171 1172 na.ifp = vi->ifp; 1173 na.na_flags = NAF_BDG_MAYSLEEP; 1174 1175 /* Netmap doesn't know about the space reserved for the status page. */ 1176 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE; 1177 1178 /* 1179 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So 1180 * num_rx_desc is based on the number of buffers that can be held in the 1181 * freelist, and not the number of entries in the iq. (These two are 1182 * not exactly the same due to the space taken up by the status page). 1183 */ 1184 na.num_rx_desc = rounddown(vi->qsize_rxq, 8); 1185 na.nm_txsync = cxgbe_netmap_txsync; 1186 na.nm_rxsync = cxgbe_netmap_rxsync; 1187 na.nm_register = cxgbe_netmap_reg; 1188 na.num_tx_rings = vi->nnmtxq; 1189 na.num_rx_rings = vi->nnmrxq; 1190 na.rx_buf_maxsize = MAX_MTU; 1191 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */ 1192 } 1193 1194 void 1195 cxgbe_nm_detach(struct vi_info *vi) 1196 { 1197 1198 MPASS(vi->nnmrxq > 0); 1199 MPASS(vi->ifp != NULL); 1200 1201 netmap_detach(vi->ifp); 1202 } 1203 1204 static inline const void * 1205 unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl) 1206 { 1207 1208 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL); 1209 1210 /* data[0] is RSS header */ 1211 return (&cpl->data[1]); 1212 } 1213 1214 static void 1215 handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp, 1216 const struct cpl_sge_egr_update *egr) 1217 { 1218 uint32_t oq; 1219 struct sge_nm_txq *nm_txq; 1220 1221 oq = be32toh(egr->opcode_qid); 1222 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 1223 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 1224 1225 netmap_tx_irq(ifp, nm_txq->nid); 1226 } 1227 1228 void 1229 service_nm_rxq(struct sge_nm_rxq *nm_rxq) 1230 { 1231 struct vi_info *vi = nm_rxq->vi; 1232 struct adapter *sc = vi->adapter; 1233 struct ifnet *ifp = vi->ifp; 1234 struct netmap_adapter *na = NA(ifp); 1235 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid]; 1236 struct netmap_ring *ring = kring->ring; 1237 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; 1238 const void *cpl; 1239 uint32_t lq; 1240 u_int work = 0; 1241 uint8_t opcode; 1242 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 1243 u_int fl_credits = fl_cidx & 7; 1244 u_int ndesc = 0; /* desc processed since last cidx update */ 1245 u_int nframes = 0; /* frames processed since last netmap wakeup */ 1246 1247 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 1248 1249 rmb(); 1250 1251 lq = be32toh(d->rsp.pldbuflen_qid); 1252 opcode = d->rss.opcode; 1253 cpl = &d->cpl[0]; 1254 1255 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 1256 case X_RSPD_TYPE_FLBUF: 1257 1258 /* fall through */ 1259 1260 case X_RSPD_TYPE_CPL: 1261 MPASS(opcode < NUM_CPL_CMDS); 1262 1263 switch (opcode) { 1264 case CPL_FW4_MSG: 1265 case CPL_FW6_MSG: 1266 cpl = unwrap_nm_fw6_msg(cpl); 1267 /* fall through */ 1268 case CPL_SGE_EGR_UPDATE: 1269 handle_nm_sge_egr_update(sc, ifp, cpl); 1270 break; 1271 case CPL_RX_PKT: 1272 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 1273 sc->params.sge.fl_pktshift; 1274 ring->slot[fl_cidx].flags = 0; 1275 nframes++; 1276 if (!(lq & F_RSPD_NEWBUF)) { 1277 MPASS(black_hole == 2); 1278 break; 1279 } 1280 fl_credits++; 1281 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx)) 1282 fl_cidx = 0; 1283 break; 1284 default: 1285 panic("%s: unexpected opcode 0x%x on nm_rxq %p", 1286 __func__, opcode, nm_rxq); 1287 } 1288 break; 1289 1290 case X_RSPD_TYPE_INTR: 1291 /* Not equipped to handle forwarded interrupts. */ 1292 panic("%s: netmap queue received interrupt for iq %u\n", 1293 __func__, lq); 1294 1295 default: 1296 panic("%s: illegal response type %d on nm_rxq %p", 1297 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq); 1298 } 1299 1300 d++; 1301 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) { 1302 nm_rxq->iq_cidx = 0; 1303 d = &nm_rxq->iq_desc[0]; 1304 nm_rxq->iq_gen ^= F_RSPD_GEN; 1305 } 1306 1307 if (__predict_false(++nframes == rx_nframes) && !black_hole) { 1308 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1309 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1310 nframes = 0; 1311 } 1312 1313 if (__predict_false(++ndesc == rx_ndesc)) { 1314 if (black_hole && fl_credits >= 8) { 1315 fl_credits /= 8; 1316 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, 1317 nm_rxq->fl_sidx); 1318 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1319 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1320 fl_credits = fl_cidx & 7; 1321 } 1322 t4_write_reg(sc, sc->sge_gts_reg, 1323 V_CIDXINC(ndesc) | 1324 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 1325 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 1326 ndesc = 0; 1327 } 1328 } 1329 1330 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1331 if (black_hole) { 1332 fl_credits /= 8; 1333 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx); 1334 t4_write_reg(sc, sc->sge_kdoorbell_reg, 1335 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1336 } else if (nframes > 0) 1337 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1338 1339 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) | 1340 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) | 1341 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 1342 } 1343 #endif 1344