xref: /freebsd/sys/dev/dpaa2/dpaa2_channel.h (revision 58983e4b)
158983e4bSDmitry Salychev /*-
258983e4bSDmitry Salychev  * SPDX-License-Identifier: BSD-2-Clause
358983e4bSDmitry Salychev  *
458983e4bSDmitry Salychev  * Copyright © 2023 Dmitry Salychev
558983e4bSDmitry Salychev  *
658983e4bSDmitry Salychev  * Redistribution and use in source and binary forms, with or without
758983e4bSDmitry Salychev  * modification, are permitted provided that the following conditions
858983e4bSDmitry Salychev  * are met:
958983e4bSDmitry Salychev  * 1. Redistributions of source code must retain the above copyright
1058983e4bSDmitry Salychev  *    notice, this list of conditions and the following disclaimer.
1158983e4bSDmitry Salychev  * 2. Redistributions in binary form must reproduce the above copyright
1258983e4bSDmitry Salychev  *    notice, this list of conditions and the following disclaimer in the
1358983e4bSDmitry Salychev  *    documentation and/or other materials provided with the distribution.
1458983e4bSDmitry Salychev  *
1558983e4bSDmitry Salychev  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
1658983e4bSDmitry Salychev  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1758983e4bSDmitry Salychev  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1858983e4bSDmitry Salychev  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
1958983e4bSDmitry Salychev  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
2058983e4bSDmitry Salychev  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2158983e4bSDmitry Salychev  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2258983e4bSDmitry Salychev  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2358983e4bSDmitry Salychev  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2458983e4bSDmitry Salychev  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2558983e4bSDmitry Salychev  * SUCH DAMAGE.
2658983e4bSDmitry Salychev  */
2758983e4bSDmitry Salychev 
2858983e4bSDmitry Salychev #ifndef	_DPAA2_CHANNEL_H
2958983e4bSDmitry Salychev #define	_DPAA2_CHANNEL_H
3058983e4bSDmitry Salychev 
3158983e4bSDmitry Salychev #include <sys/types.h>
3258983e4bSDmitry Salychev #include <sys/param.h>
3358983e4bSDmitry Salychev #include <sys/systm.h>
3458983e4bSDmitry Salychev #include <sys/kernel.h>
3558983e4bSDmitry Salychev #include <sys/malloc.h>
3658983e4bSDmitry Salychev #include <sys/queue.h>
3758983e4bSDmitry Salychev #include <sys/taskqueue.h>
3858983e4bSDmitry Salychev #include <sys/buf_ring.h>
3958983e4bSDmitry Salychev #include <sys/lock.h>
4058983e4bSDmitry Salychev #include <sys/mutex.h>
4158983e4bSDmitry Salychev 
4258983e4bSDmitry Salychev #include "dpaa2_types.h"
4358983e4bSDmitry Salychev #include "dpaa2_io.h"
4458983e4bSDmitry Salychev #include "dpaa2_ni.h"
4558983e4bSDmitry Salychev 
4658983e4bSDmitry Salychev #define DPAA2_TX_BUFRING_SZ	 (4096u)
4758983e4bSDmitry Salychev 
4858983e4bSDmitry Salychev /**
4958983e4bSDmitry Salychev  * @brief QBMan channel to process ingress traffic.
5058983e4bSDmitry Salychev  *
5158983e4bSDmitry Salychev  * NOTE: Several WQs are organized into a single channel.
5258983e4bSDmitry Salychev  */
5358983e4bSDmitry Salychev struct dpaa2_channel {
5458983e4bSDmitry Salychev 	device_t		 ni_dev;
5558983e4bSDmitry Salychev 	device_t		 io_dev;
5658983e4bSDmitry Salychev 	device_t		 con_dev;
5758983e4bSDmitry Salychev 	uint16_t		 id;
5858983e4bSDmitry Salychev 	uint16_t		 flowid;
5958983e4bSDmitry Salychev 
6058983e4bSDmitry Salychev 	uint64_t		 tx_frames;
6158983e4bSDmitry Salychev 	uint64_t		 tx_dropped;
6258983e4bSDmitry Salychev 
6358983e4bSDmitry Salychev 	struct mtx		 dma_mtx;
6458983e4bSDmitry Salychev 	bus_dma_tag_t		 rx_dmat;
6558983e4bSDmitry Salychev 	bus_dma_tag_t		 tx_dmat;
6658983e4bSDmitry Salychev 	bus_dma_tag_t		 sgt_dmat;
6758983e4bSDmitry Salychev 
6858983e4bSDmitry Salychev 	struct dpaa2_io_notif_ctx ctx;		/* to configure CDANs */
6958983e4bSDmitry Salychev 
7058983e4bSDmitry Salychev 	struct dpaa2_buf	 store;		/* to keep VDQ responses */
7158983e4bSDmitry Salychev 	uint32_t		 store_sz;	/* in frames */
7258983e4bSDmitry Salychev 	uint32_t		 store_idx;	/* frame index */
7358983e4bSDmitry Salychev 
7458983e4bSDmitry Salychev 	uint32_t		 recycled_n;
7558983e4bSDmitry Salychev 	struct dpaa2_buf	*recycled[DPAA2_SWP_BUFS_PER_CMD];
7658983e4bSDmitry Salychev 
7758983e4bSDmitry Salychev 	uint32_t		 rxq_n;
7858983e4bSDmitry Salychev 	struct dpaa2_ni_fq	 rx_queues[DPAA2_MAX_TCS];
7958983e4bSDmitry Salychev 	struct dpaa2_ni_fq	 txc_queue;
8058983e4bSDmitry Salychev 
8158983e4bSDmitry Salychev 	struct taskqueue	*cleanup_tq;
8258983e4bSDmitry Salychev 	struct task		 cleanup_task;
8358983e4bSDmitry Salychev 	struct task		 bp_task;
8458983e4bSDmitry Salychev 
8558983e4bSDmitry Salychev 	struct mtx		 xmit_mtx;
8658983e4bSDmitry Salychev 	struct buf_ring		*xmit_br;
8758983e4bSDmitry Salychev } __aligned(CACHE_LINE_SIZE);
8858983e4bSDmitry Salychev 
8958983e4bSDmitry Salychev int dpaa2_chan_setup(device_t, device_t, device_t, device_t,
9058983e4bSDmitry Salychev     struct dpaa2_channel **, uint32_t, task_fn_t);
9158983e4bSDmitry Salychev int dpaa2_chan_setup_fq(device_t, struct dpaa2_channel *,
9258983e4bSDmitry Salychev     enum dpaa2_ni_queue_type);
9358983e4bSDmitry Salychev int dpaa2_chan_next_frame(struct dpaa2_channel *, struct dpaa2_dq **);
9458983e4bSDmitry Salychev 
9558983e4bSDmitry Salychev #endif /* _DPAA2_CHANNEL_H */
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