1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2022 Dmitry Salychev 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _DPAA2_SWP_H 29 #define _DPAA2_SWP_H 30 31 #include <sys/bus.h> 32 33 #include "dpaa2_types.h" 34 #include "dpaa2_bp.h" 35 36 /* 37 * DPAA2 QBMan software portal. 38 */ 39 40 /* All QBMan commands and result structures use this "valid bit" encoding. */ 41 #define DPAA2_SWP_VALID_BIT ((uint32_t) 0x80) 42 43 #define DPAA2_SWP_TIMEOUT 100000 /* in us */ 44 #define DPAA2_SWP_CMD_PARAMS_N 8u 45 #define DPAA2_SWP_RSP_PARAMS_N 8u 46 47 /* 48 * Maximum number of buffers that can be acquired/released through a single 49 * QBMan command. 50 */ 51 #define DPAA2_SWP_BUFS_PER_CMD 7u 52 53 /* 54 * Number of times to retry DPIO portal operations while waiting for portal to 55 * finish executing current command and become available. 56 * 57 * We want to avoid being stuck in a while loop in case hardware becomes 58 * unresponsive, but not give up too easily if the portal really is busy for 59 * valid reasons. 60 */ 61 #define DPAA2_SWP_BUSY_RETRIES 1000 62 63 /* Versions of the QBMan software portals. */ 64 #define DPAA2_SWP_REV_4000 0x04000000 65 #define DPAA2_SWP_REV_4100 0x04010000 66 #define DPAA2_SWP_REV_4101 0x04010001 67 #define DPAA2_SWP_REV_5000 0x05000000 68 69 #define DPAA2_SWP_REV_MASK 0xFFFF0000 70 71 /* Registers in the cache-inhibited area of the software portal. */ 72 #define DPAA2_SWP_CINH_CR 0x600 /* Management Command reg.*/ 73 #define DPAA2_SWP_CINH_EQCR_PI 0x800 /* Enqueue Ring, Producer Index */ 74 #define DPAA2_SWP_CINH_EQCR_CI 0x840 /* Enqueue Ring, Consumer Index */ 75 #define DPAA2_SWP_CINH_CR_RT 0x900 /* CR Read Trigger */ 76 #define DPAA2_SWP_CINH_VDQCR_RT 0x940 /* VDQCR Read Trigger */ 77 #define DPAA2_SWP_CINH_EQCR_AM_RT 0x980 78 #define DPAA2_SWP_CINH_RCR_AM_RT 0x9C0 79 #define DPAA2_SWP_CINH_DQPI 0xA00 /* DQRR Producer Index reg. */ 80 #define DPAA2_SWP_CINH_DQRR_ITR 0xA80 /* DQRR interrupt timeout reg. */ 81 #define DPAA2_SWP_CINH_DCAP 0xAC0 /* DQRR Consumption Ack. reg. */ 82 #define DPAA2_SWP_CINH_SDQCR 0xB00 /* Static Dequeue Command reg. */ 83 #define DPAA2_SWP_CINH_EQCR_AM_RT2 0xB40 84 #define DPAA2_SWP_CINH_RCR_PI 0xC00 /* Release Ring, Producer Index */ 85 #define DPAA2_SWP_CINH_RAR 0xCC0 /* Release Array Allocation reg. */ 86 #define DPAA2_SWP_CINH_CFG 0xD00 87 #define DPAA2_SWP_CINH_ISR 0xE00 88 #define DPAA2_SWP_CINH_IER 0xE40 89 #define DPAA2_SWP_CINH_ISDR 0xE80 90 #define DPAA2_SWP_CINH_IIR 0xEC0 91 #define DPAA2_SWP_CINH_ITPR 0xF40 92 93 /* Registers in the cache-enabled area of the software portal. */ 94 #define DPAA2_SWP_CENA_EQCR(n) (0x000 + ((uint32_t)(n) << 6)) 95 #define DPAA2_SWP_CENA_DQRR(n) (0x200 + ((uint32_t)(n) << 6)) 96 #define DPAA2_SWP_CENA_RCR(n) (0x400 + ((uint32_t)(n) << 6)) 97 #define DPAA2_SWP_CENA_CR (0x600) /* Management Command reg. */ 98 #define DPAA2_SWP_CENA_RR(vb) (0x700 + ((uint32_t)(vb) >> 1)) 99 #define DPAA2_SWP_CENA_VDQCR (0x780) 100 #define DPAA2_SWP_CENA_EQCR_CI (0x840) 101 102 /* Registers in the cache-enabled area of the software portal (memory-backed). */ 103 #define DPAA2_SWP_CENA_DQRR_MEM(n) (0x0800 + ((uint32_t)(n) << 6)) 104 #define DPAA2_SWP_CENA_RCR_MEM(n) (0x1400 + ((uint32_t)(n) << 6)) 105 #define DPAA2_SWP_CENA_CR_MEM (0x1600) /* Management Command reg. */ 106 #define DPAA2_SWP_CENA_RR_MEM (0x1680) /* Management Response reg. */ 107 #define DPAA2_SWP_CENA_VDQCR_MEM (0x1780) 108 #define DPAA2_SWP_CENA_EQCR_CI_MEMBACK (0x1840) 109 110 /* Shifts in the portal's configuration register. */ 111 #define DPAA2_SWP_CFG_DQRR_MF_SHIFT 20 112 #define DPAA2_SWP_CFG_EST_SHIFT 16 113 #define DPAA2_SWP_CFG_CPBS_SHIFT 15 114 #define DPAA2_SWP_CFG_WN_SHIFT 14 115 #define DPAA2_SWP_CFG_RPM_SHIFT 12 116 #define DPAA2_SWP_CFG_DCM_SHIFT 10 117 #define DPAA2_SWP_CFG_EPM_SHIFT 8 118 #define DPAA2_SWP_CFG_VPM_SHIFT 7 119 #define DPAA2_SWP_CFG_CPM_SHIFT 6 120 #define DPAA2_SWP_CFG_SD_SHIFT 5 121 #define DPAA2_SWP_CFG_SP_SHIFT 4 122 #define DPAA2_SWP_CFG_SE_SHIFT 3 123 #define DPAA2_SWP_CFG_DP_SHIFT 2 124 #define DPAA2_SWP_CFG_DE_SHIFT 1 125 #define DPAA2_SWP_CFG_EP_SHIFT 0 126 127 /* Static Dequeue Command Register attribute codes */ 128 #define DPAA2_SDQCR_FC_SHIFT 29 /* Dequeue Command Frame Count */ 129 #define DPAA2_SDQCR_FC_MASK 0x1 130 #define DPAA2_SDQCR_DCT_SHIFT 24 /* Dequeue Command Type */ 131 #define DPAA2_SDQCR_DCT_MASK 0x3 132 #define DPAA2_SDQCR_TOK_SHIFT 16 /* Dequeue Command Token */ 133 #define DPAA2_SDQCR_TOK_MASK 0xff 134 #define DPAA2_SDQCR_SRC_SHIFT 0 /* Dequeue Source */ 135 #define DPAA2_SDQCR_SRC_MASK 0xffff 136 137 /* 138 * Read trigger bit is used to trigger QMan to read a command from memory, 139 * without having software perform a cache flush to force a write of the command 140 * to QMan. 141 * 142 * NOTE: Implemented in QBMan 5.0 or above. 143 */ 144 #define DPAA2_SWP_RT_MODE ((uint32_t)0x100) 145 146 /* Interrupt Enable Register bits. */ 147 #define DPAA2_SWP_INTR_EQRI 0x01 148 #define DPAA2_SWP_INTR_EQDI 0x02 149 #define DPAA2_SWP_INTR_DQRI 0x04 150 #define DPAA2_SWP_INTR_RCRI 0x08 151 #define DPAA2_SWP_INTR_RCDI 0x10 152 #define DPAA2_SWP_INTR_VDCI 0x20 153 154 /* "Write Enable" bitmask for a command to configure SWP WQ Channel.*/ 155 #define DPAA2_WQCHAN_WE_EN (0x1u) /* Enable CDAN generation */ 156 #define DPAA2_WQCHAN_WE_ICD (0x2u) /* Interrupt Coalescing Disable */ 157 #define DPAA2_WQCHAN_WE_CTX (0x4u) 158 159 /* Definitions for parsing DQRR entries. */ 160 #define DPAA2_DQRR_RESULT_MASK (0x7Fu) 161 #define DPAA2_DQRR_RESULT_DQ (0x60u) 162 #define DPAA2_DQRR_RESULT_FQRN (0x21u) 163 #define DPAA2_DQRR_RESULT_FQRNI (0x22u) 164 #define DPAA2_DQRR_RESULT_FQPN (0x24u) 165 #define DPAA2_DQRR_RESULT_FQDAN (0x25u) 166 #define DPAA2_DQRR_RESULT_CDAN (0x26u) 167 #define DPAA2_DQRR_RESULT_CSCN_MEM (0x27u) 168 #define DPAA2_DQRR_RESULT_CGCU (0x28u) 169 #define DPAA2_DQRR_RESULT_BPSCN (0x29u) 170 #define DPAA2_DQRR_RESULT_CSCN_WQ (0x2au) 171 172 /* Frame dequeue statuses */ 173 #define DPAA2_DQ_STAT_FQEMPTY (0x80u) /* FQ is empty */ 174 #define DPAA2_DQ_STAT_HELDACTIVE (0x40u) /* FQ is held active */ 175 #define DPAA2_DQ_STAT_FORCEELIGIBLE (0x20u) /* FQ force eligible */ 176 #define DPAA2_DQ_STAT_VALIDFRAME (0x10u) /* valid frame */ 177 #define DPAA2_DQ_STAT_ODPVALID (0x04u) /* FQ ODP enable */ 178 #define DPAA2_DQ_STAT_VOLATILE (0x02u) /* volatile dequeue (VDC) */ 179 #define DPAA2_DQ_STAT_EXPIRED (0x01u) /* VDC is expired */ 180 181 /* 182 * Portal flags. 183 * 184 * TODO: Use the same flags for both MC and software portals. 185 */ 186 #define DPAA2_SWP_DEF 0x0u 187 #define DPAA2_SWP_NOWAIT_ALLOC 0x2u /* Do not sleep during init */ 188 #define DPAA2_SWP_LOCKED 0x4000u /* Wait till portal's unlocked */ 189 #define DPAA2_SWP_DESTROYED 0x8000u /* Terminate any operations */ 190 191 /* Command return codes. */ 192 #define DPAA2_SWP_STAT_OK 0x0 193 #define DPAA2_SWP_STAT_NO_MEMORY 0x9 /* No memory available */ 194 #define DPAA2_SWP_STAT_PORTAL_DISABLED 0xFD /* QBMan portal disabled */ 195 #define DPAA2_SWP_STAT_EINVAL 0xFE /* Invalid argument */ 196 #define DPAA2_SWP_STAT_ERR 0xFF /* General error */ 197 198 /* Opaque token for static dequeues. */ 199 #define DPAA2_SWP_SDQCR_TOKEN 0xBBu 200 /* Opaque token for static dequeues. */ 201 #define DPAA2_SWP_VDQCR_TOKEN 0xCCu 202 203 #define DPAA2_SWP_LOCK(__swp, __flags) do { \ 204 mtx_assert(&(__swp)->lock, MA_NOTOWNED); \ 205 mtx_lock(&(__swp)->lock); \ 206 *(__flags) = (__swp)->flags; \ 207 (__swp)->flags |= DPAA2_SWP_LOCKED; \ 208 } while (0) 209 210 #define DPAA2_SWP_UNLOCK(__swp) do { \ 211 mtx_assert(&(__swp)->lock, MA_OWNED); \ 212 (__swp)->flags &= ~DPAA2_SWP_LOCKED; \ 213 mtx_unlock(&(__swp)->lock); \ 214 } while (0) 215 216 enum dpaa2_fd_format { 217 DPAA2_FD_SINGLE = 0, 218 DPAA2_FD_LIST, 219 DPAA2_FD_SG 220 }; 221 222 /** 223 * @brief Enqueue command descriptor. 224 * 225 * NOTE: 32 bytes. 226 */ 227 struct dpaa2_eq_desc { 228 uint8_t verb; 229 uint8_t dca; 230 uint16_t seqnum; 231 uint16_t orpid; 232 uint16_t _reserved; 233 uint32_t tgtid; 234 uint32_t tag; 235 uint16_t qdbin; 236 uint8_t qpri; 237 uint8_t _reserved1[3]; 238 uint8_t wae; 239 uint8_t rspid; 240 uint64_t rsp_addr; 241 } __packed; 242 243 /** 244 * @brief Frame Dequeue Response (FDR) descriptor. 245 * 246 * NOTE: 32 bytes. 247 */ 248 struct dpaa2_fdr_desc { 249 uint8_t verb; 250 uint8_t stat; 251 uint16_t seqnum; 252 uint16_t oprid; 253 uint8_t _reserved; 254 uint8_t tok; 255 uint32_t fqid; 256 uint32_t _reserved1; 257 uint32_t fq_byte_cnt; 258 uint32_t fq_frm_cnt; 259 uint64_t fqd_ctx; 260 } __packed; 261 262 /** 263 * @brief State Change Notification Message (SCNM). 264 * 265 * NOTE: 16 bytes. 266 */ 267 struct dpaa2_scn { 268 uint8_t verb; 269 uint8_t stat; 270 uint8_t state; 271 uint8_t _reserved; 272 uint32_t rid_tok; 273 uint64_t ctx; 274 } __packed; 275 276 /** 277 * @brief DPAA2 frame descriptor. 278 * 279 * addr: Memory address of the start of the buffer holding the 280 * frame data or the buffer containing the scatter/gather 281 * list. 282 * data_length: Length of the frame data (in bytes). 283 * bpid_ivp_bmt: Buffer pool ID (14 bit + BMT bit + IVP bit) 284 * offset_fmt_sl: Frame data offset, frame format and short-length fields. 285 * frame_ctx: Frame context. This field allows the sender of a frame 286 * to communicate some out-of-band information to the 287 * receiver of the frame. 288 * ctrl: Control bits (ERR, CBMT, ASAL, PTAC, DROPP, SC, DD). 289 * flow_ctx: Frame flow context. Associates the frame with a flow 290 * structure. QMan may use the FLC field for 3 purposes: 291 * stashing control, order definition point identification, 292 * and enqueue replication control. 293 * 294 * NOTE: 32 bytes. 295 */ 296 struct dpaa2_fd { 297 uint64_t addr; 298 uint32_t data_length; 299 uint16_t bpid_ivp_bmt; 300 uint16_t offset_fmt_sl; 301 uint32_t frame_ctx; 302 uint32_t ctrl; 303 uint64_t flow_ctx; 304 } __packed; 305 306 /** 307 * @brief DPAA2 scatter/gather entry. 308 * 309 * NOTE: 16 bytes. 310 */ 311 struct dpaa2_sg_entry { 312 uint64_t addr; 313 uint32_t len; 314 uint16_t bpid; 315 uint16_t offset_fmt; 316 } __packed; 317 318 /** 319 * @brief Frame Dequeue Response (FDR). 320 * 321 * NOTE: 64 bytes. 322 */ 323 struct dpaa2_fdr { 324 struct dpaa2_fdr_desc desc; 325 struct dpaa2_fd fd; 326 } __packed; 327 328 /** 329 * @brief Dequeue Response Message. 330 * 331 * NOTE: 64 bytes. 332 */ 333 struct dpaa2_dq { 334 union { 335 struct { 336 uint8_t verb; 337 uint8_t _reserved[63]; 338 } common; 339 struct dpaa2_fdr fdr; /* Frame Dequeue Response */ 340 struct dpaa2_scn scn; /* State Change Notification */ 341 }; 342 } __packed; 343 344 /** 345 * @brief Descriptor of the QBMan software portal. 346 * 347 * cena_res: Unmapped cache-enabled part of the portal's I/O memory. 348 * cena_map: Mapped cache-enabled part of the portal's I/O memory. 349 * cinh_res: Unmapped cache-inhibited part of the portal's I/O memory. 350 * cinh_map: Mapped cache-inhibited part of the portal's I/O memory. 351 * 352 * dpio_dev: Device associated with the DPIO object to manage this 353 * portal. 354 * swp_version: Hardware IP version of the software portal. 355 * swp_clk: QBMAN clock frequency value in Hz. 356 * swp_cycles_ratio: How many 256 QBMAN cycles fit into one ns. 357 * swp_id: Software portal ID. 358 * 359 * has_notif: True if the notification mode is used. 360 * has_8prio: True for a channel with 8 priority WQs. Ignored unless 361 * "has_notif" is true. 362 */ 363 struct dpaa2_swp_desc { 364 struct resource *cena_res; 365 struct resource_map *cena_map; 366 struct resource *cinh_res; 367 struct resource_map *cinh_map; 368 369 device_t dpio_dev; 370 uint32_t swp_version; 371 uint32_t swp_clk; 372 uint32_t swp_cycles_ratio; 373 uint16_t swp_id; 374 375 bool has_notif; 376 bool has_8prio; 377 }; 378 379 /** 380 * @brief Command holds data to be written to the software portal. 381 */ 382 struct dpaa2_swp_cmd { 383 uint64_t params[DPAA2_SWP_CMD_PARAMS_N]; 384 }; 385 386 /** 387 * @brief Command response holds data received from the software portal. 388 */ 389 struct dpaa2_swp_rsp { 390 uint64_t params[DPAA2_SWP_RSP_PARAMS_N]; 391 }; 392 393 /** 394 * @brief QBMan software portal. 395 * 396 * res: Unmapped cache-enabled and cache-inhibited parts of the portal. 397 * map: Mapped cache-enabled and cache-inhibited parts of the portal. 398 * desc: Descriptor of the QBMan software portal. 399 * lock: Lock to guard an access to the portal. 400 * cv: Conditional variable helps to wait for the helper object's state 401 * change. 402 * flags: Current state of the object. 403 * sdq: Push dequeues status. 404 * mc: Management commands data. 405 * mr: Management response data. 406 * dqrr: Dequeue Response Ring is used to issue frame dequeue responses 407 * from the QBMan to the driver. 408 * eqcr: Enqueue Command Ring is used to issue frame enqueue commands 409 * from the driver to the QBMan. 410 */ 411 struct dpaa2_swp { 412 struct resource *cena_res; 413 struct resource_map *cena_map; 414 struct resource *cinh_res; 415 struct resource_map *cinh_map; 416 417 struct mtx lock; 418 struct dpaa2_swp_desc *desc; 419 uint16_t flags; 420 421 /* Static Dequeue Command Register value (to obtain CDANs). */ 422 uint32_t sdq; 423 424 /* Volatile Dequeue Command (to obtain frames). */ 425 struct { 426 uint32_t valid_bit; /* 0x00 or 0x80 */ 427 } vdq; 428 429 struct { 430 bool atomic; 431 bool writes_cinh; 432 bool mem_backed; 433 } cfg; /* Software portal configuration. */ 434 435 struct { 436 uint32_t valid_bit; /* 0x00 or 0x80 */ 437 } mc; 438 439 struct { 440 uint32_t valid_bit; /* 0x00 or 0x80 */ 441 } mr; 442 443 struct { 444 uint32_t next_idx; 445 uint32_t valid_bit; 446 uint8_t ring_size; 447 bool reset_bug; /* dqrr reset workaround */ 448 uint32_t irq_threshold; 449 uint32_t irq_itp; 450 } dqrr; 451 452 struct { 453 uint32_t pi; /* producer index */ 454 uint32_t pi_vb; /* PI valid bits */ 455 uint32_t pi_ring_size; 456 uint32_t pi_ci_mask; 457 uint32_t ci; 458 int available; 459 uint32_t pend; 460 uint32_t no_pfdr; 461 } eqcr; 462 }; 463 464 /* Management routines. */ 465 int dpaa2_swp_init_portal(struct dpaa2_swp **swp, struct dpaa2_swp_desc *desc, 466 uint16_t flags); 467 void dpaa2_swp_free_portal(struct dpaa2_swp *swp); 468 uint32_t dpaa2_swp_set_cfg(uint8_t max_fill, uint8_t wn, uint8_t est, 469 uint8_t rpm, uint8_t dcm, uint8_t epm, int sd, int sp, int se, int dp, 470 int de, int ep); 471 472 /* Read/write registers of a software portal. */ 473 void dpaa2_swp_write_reg(struct dpaa2_swp *swp, uint32_t o, uint32_t v); 474 uint32_t dpaa2_swp_read_reg(struct dpaa2_swp *swp, uint32_t o); 475 476 /* Helper routines. */ 477 void dpaa2_swp_set_ed_norp(struct dpaa2_eq_desc *ed, bool resp_always); 478 void dpaa2_swp_set_ed_fq(struct dpaa2_eq_desc *ed, uint32_t fqid); 479 void dpaa2_swp_set_intr_trigger(struct dpaa2_swp *swp, uint32_t mask); 480 uint32_t dpaa2_swp_get_intr_trigger(struct dpaa2_swp *swp); 481 uint32_t dpaa2_swp_read_intr_status(struct dpaa2_swp *swp); 482 void dpaa2_swp_clear_intr_status(struct dpaa2_swp *swp, uint32_t mask); 483 void dpaa2_swp_set_push_dequeue(struct dpaa2_swp *swp, uint8_t chan_idx, 484 bool en); 485 int dpaa2_swp_set_irq_coalescing(struct dpaa2_swp *swp, uint32_t threshold, 486 uint32_t holdoff); 487 488 /* Software portal commands. */ 489 int dpaa2_swp_conf_wq_channel(struct dpaa2_swp *swp, uint16_t chan_id, 490 uint8_t we_mask, bool cdan_en, uint64_t ctx); 491 int dpaa2_swp_query_bp(struct dpaa2_swp *swp, uint16_t bpid, 492 struct dpaa2_bp_conf *conf); 493 int dpaa2_swp_release_bufs(struct dpaa2_swp *swp, uint16_t bpid, bus_addr_t *buf, 494 uint32_t buf_num); 495 int dpaa2_swp_dqrr_next_locked(struct dpaa2_swp *swp, struct dpaa2_dq *dq, 496 uint32_t *idx); 497 int dpaa2_swp_pull(struct dpaa2_swp *swp, uint16_t chan_id, 498 struct dpaa2_buf *buf, uint32_t frames_n); 499 int dpaa2_swp_enq(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed, 500 struct dpaa2_fd *fd); 501 int dpaa2_swp_enq_mult(struct dpaa2_swp *swp, struct dpaa2_eq_desc *ed, 502 struct dpaa2_fd *fd, uint32_t *flags, int frames_n); 503 504 #endif /* _DPAA2_SWP_H */ 505