1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2022 Dmitry Salychev 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _DPAA2_TYPES_H 29 #define _DPAA2_TYPES_H 30 31 #include <machine/atomic.h> 32 33 #define DPAA2_MAGIC ((uint32_t) 0xD4AA2C0Du) 34 35 /** 36 * @brief Types of the DPAA2 devices. 37 */ 38 enum dpaa2_dev_type { 39 DPAA2_DEV_MC = 7500, /* Management Complex (firmware bus) */ 40 DPAA2_DEV_RC, /* Resource Container (firmware bus) */ 41 DPAA2_DEV_IO, /* I/O object (to work with QBMan portal) */ 42 DPAA2_DEV_NI, /* Network Interface */ 43 DPAA2_DEV_MCP, /* MC portal */ 44 DPAA2_DEV_BP, /* Buffer Pool */ 45 DPAA2_DEV_CON, /* Concentrator */ 46 DPAA2_DEV_MAC, /* MAC object */ 47 DPAA2_DEV_MUX, /* MUX (Datacenter bridge) object */ 48 DPAA2_DEV_SW, /* Ethernet Switch */ 49 50 DPAA2_DEV_NOTYPE /* Shouldn't be assigned to any DPAA2 device. */ 51 }; 52 53 /** 54 * @brief Types of the DPAA2 buffers. 55 */ 56 enum dpaa2_buf_type { 57 DPAA2_BUF_RX = 75, /* Rx buffer */ 58 DPAA2_BUF_TX, /* Tx buffer */ 59 DPAA2_BUF_STORE /* Channel storage, key configuration */ 60 }; 61 62 /** 63 * @brief DMA-mapped buffer (for Rx/Tx buffers, channel storage, etc.). 64 */ 65 struct dpaa2_buf { 66 enum dpaa2_buf_type type; 67 union { 68 struct { 69 bus_dma_tag_t dmat; /* DMA tag for this buffer */ 70 bus_dmamap_t dmap; 71 bus_addr_t paddr; 72 void *vaddr; 73 74 struct mbuf *m; /* associated mbuf */ 75 } rx; 76 struct { 77 bus_dma_tag_t dmat; /* DMA tag for this buffer */ 78 bus_dmamap_t dmap; 79 bus_addr_t paddr; 80 void *vaddr; 81 82 struct mbuf *m; /* associated mbuf */ 83 uint64_t idx; 84 85 /* for scatter/gather table */ 86 bus_dma_tag_t sgt_dmat; 87 bus_dmamap_t sgt_dmap; 88 bus_addr_t sgt_paddr; 89 void *sgt_vaddr; 90 } tx; 91 struct { 92 bus_dma_tag_t dmat; /* DMA tag for this buffer */ 93 bus_dmamap_t dmap; 94 bus_addr_t paddr; 95 void *vaddr; 96 } store; 97 }; 98 }; 99 100 struct dpaa2_atomic { 101 volatile int counter; 102 }; 103 104 /* Handy wrappers over atomic operations. */ 105 #define DPAA2_ATOMIC_XCHG(a, val) \ 106 (atomic_swap_int(&(a)->counter, (val))) 107 #define DPAA2_ATOMIC_READ(a) \ 108 (atomic_load_acq_int(&(a)->counter)) 109 #define DPAA2_ATOMIC_ADD(a, val) \ 110 (atomic_add_acq_int(&(a)->counter, (val))) 111 112 /* Convert DPAA2 type to/from string. */ 113 const char *dpaa2_ttos(enum dpaa2_dev_type type); 114 enum dpaa2_dev_type dpaa2_stot(const char *str); 115 116 #endif /* _DPAA2_TYPES_H */ 117