1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2022 Bjoern A. Zeeb 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/kernel.h> 31 #include <sys/bus.h> 32 #include <sys/rman.h> 33 #include <sys/endian.h> 34 #include <sys/socket.h> 35 36 #include <machine/bus.h> 37 #include <machine/resource.h> 38 39 #include <net/if.h> 40 #include <net/if_var.h> 41 #include <net/if_media.h> 42 43 #include <dev/mii/mii.h> 44 #include <dev/mii/miivar.h> 45 46 #include "memac_mdio.h" 47 #include "miibus_if.h" 48 49 /* #define MEMAC_MDIO_DEBUG */ 50 51 /* -------------------------------------------------------------------------- */ 52 53 int 54 memacphy_miibus_readreg(device_t dev, int phy, int reg) 55 { 56 57 return (MIIBUS_READREG(device_get_parent(dev), phy, reg)); 58 } 59 60 int 61 memacphy_miibus_writereg(device_t dev, int phy, int reg, int data) 62 { 63 64 return (MIIBUS_WRITEREG(device_get_parent(dev), phy, reg, data)); 65 } 66 67 void 68 memacphy_miibus_statchg(struct memacphy_softc_common *sc) 69 { 70 71 if (sc->dpnidev != NULL) 72 MIIBUS_STATCHG(sc->dpnidev); 73 } 74 75 int 76 memacphy_set_ni_dev(struct memacphy_softc_common *sc, device_t nidev) 77 { 78 79 if (nidev == NULL) 80 return (EINVAL); 81 82 #if defined(MEMAC_MDIO_DEBUG) 83 if (bootverbose) 84 device_printf(sc->dev, "setting nidev %p (%s)\n", 85 nidev, device_get_nameunit(nidev)); 86 #endif 87 88 if (sc->dpnidev != NULL) 89 return (EBUSY); 90 91 sc->dpnidev = nidev; 92 return (0); 93 } 94 95 int 96 memacphy_get_phy_loc(struct memacphy_softc_common *sc, int *phy_loc) 97 { 98 int error; 99 100 if (phy_loc == NULL) 101 return (EINVAL); 102 103 if (sc->phy == -1) { 104 *phy_loc = MII_PHY_ANY; 105 error = ENODEV; 106 } else { 107 *phy_loc = sc->phy; 108 error = 0; 109 } 110 111 #if defined(MEMAC_MDIO_DEBUG) 112 if (bootverbose) 113 device_printf(sc->dev, "returning phy_loc %d, error %d\n", 114 *phy_loc, error); 115 #endif 116 117 return (error); 118 } 119 120 /* -------------------------------------------------------------------------- */ 121 122 /* 123 * MDIO Ethernet Management Interface Registers (internal PCS MDIO PHY) 124 * 0x0030 MDIO Configuration Register (MDIO_CFG) 125 * 0x0034 MDIO Control Register (MDIO_CTL) 126 * 0x0038 MDIO Data Register (MDIO_DATA) 127 * 0x003c MDIO Register Address Register (MDIO_ADDR) 128 * 129 * External MDIO interfaces 130 * 0x0030 External MDIO Configuration Register (EMDIO_CFG) 131 * 0x0034 External MDIO Control Register (EMDIO_CTL) 132 * 0x0038 External MDIO Data Register (EMDIO_DATA) 133 * 0x003c External MDIO Register Address Register (EMDIO_ADDR) 134 */ 135 #define MDIO_CFG 0x00030 136 #define MDIO_CFG_MDIO_RD_ER (1 << 1) 137 #define MDIO_CFG_ENC45 (1 << 6) 138 #define MDIO_CFG_BUSY (1 << 31) 139 #define MDIO_CTL 0x00034 140 #define MDIO_CTL_READ (1 << 15) 141 #define MDIO_CTL_PORT_ADDR(_x) (((_x) & 0x1f) << 5) 142 #define MDIO_CTL_DEV_ADDR(_x) ((_x) & 0x1f) 143 #define MDIO_DATA 0x00038 144 #define MDIO_ADDR 0x0003c 145 146 static uint32_t 147 memac_read_4(struct memac_mdio_softc_common *sc, uint32_t reg) 148 { 149 uint32_t v, r; 150 151 v = bus_read_4(sc->mem_res, reg); 152 if (sc->is_little_endian) 153 r = le32toh(v); 154 else 155 r = be32toh(v); 156 157 return (r); 158 } 159 160 static void 161 memac_write_4(struct memac_mdio_softc_common *sc, uint32_t reg, uint32_t val) 162 { 163 uint32_t v; 164 165 if (sc->is_little_endian) 166 v = htole32(val); 167 else 168 v = htobe32(val); 169 bus_write_4(sc->mem_res, reg, v); 170 } 171 172 static uint32_t 173 memac_miibus_wait_no_busy(struct memac_mdio_softc_common *sc) 174 { 175 uint32_t count, val; 176 177 for (count = 1000; count > 0; count--) { 178 val = memac_read_4(sc, MDIO_CFG); 179 if ((val & MDIO_CFG_BUSY) == 0) 180 break; 181 DELAY(1); 182 } 183 184 if (count == 0) 185 return (0xffff); 186 187 return (0); 188 } 189 190 int 191 memac_miibus_readreg(struct memac_mdio_softc_common *sc, int phy, int reg) 192 { 193 uint32_t cfg, ctl, val; 194 195 /* Set proper Clause 45 mode. */ 196 cfg = memac_read_4(sc, MDIO_CFG); 197 /* XXX 45 support? */ 198 cfg &= ~MDIO_CFG_ENC45; /* Use Clause 22 */ 199 memac_write_4(sc, MDIO_CFG, cfg); 200 201 val = memac_miibus_wait_no_busy(sc); 202 if (val != 0) 203 return (0xffff); 204 205 /* To whom do we want to talk to.. */ 206 ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(reg); 207 /* XXX do we need two writes for this to work reliably? */ 208 memac_write_4(sc, MDIO_CTL, ctl | MDIO_CTL_READ); 209 210 val = memac_miibus_wait_no_busy(sc); 211 if (val != 0) 212 return (0xffff); 213 214 cfg = memac_read_4(sc, MDIO_CFG); 215 if (cfg & MDIO_CFG_MDIO_RD_ER) 216 return (0xffff); 217 218 val = memac_read_4(sc, MDIO_DATA); 219 val &= 0xffff; 220 221 #if defined(MEMAC_MDIO_DEBUG) 222 device_printf(sc->dev, "phy read %d:%d = %#06x\n", phy, reg, val); 223 #endif 224 225 return (val); 226 } 227 228 int 229 memac_miibus_writereg(struct memac_mdio_softc_common *sc, int phy, int reg, int data) 230 { 231 uint32_t cfg, ctl, val; 232 233 #if defined(MEMAC_MDIO_DEBUG) 234 device_printf(sc->dev, "phy write %d:%d\n", phy, reg); 235 #endif 236 237 /* Set proper Clause 45 mode. */ 238 cfg = memac_read_4(sc, MDIO_CFG); 239 /* XXX 45 support? */ 240 cfg &= ~MDIO_CFG_ENC45; /* Use Clause 22 */ 241 memac_write_4(sc, MDIO_CFG, cfg); 242 243 val = memac_miibus_wait_no_busy(sc); 244 if (val != 0) 245 return (0xffff); 246 247 /* To whom do we want to talk to.. */ 248 ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(reg); 249 memac_write_4(sc, MDIO_CTL, ctl); 250 251 memac_write_4(sc, MDIO_DATA, data & 0xffff); 252 253 val = memac_miibus_wait_no_busy(sc); 254 if (val != 0) 255 return (0xffff); 256 257 return (0); 258 } 259 260 ssize_t 261 memac_mdio_get_property(device_t dev, device_t child, const char *propname, 262 void *propvalue, size_t size, device_property_type_t type) 263 { 264 265 return (bus_generic_get_property(dev, child, propname, propvalue, size, type)); 266 } 267 268 int 269 memac_mdio_read_ivar(device_t dev, device_t child, int index, uintptr_t *result) 270 { 271 272 return (BUS_READ_IVAR(device_get_parent(dev), dev, index, result)); 273 } 274 275 276 int 277 memac_mdio_generic_attach(struct memac_mdio_softc_common *sc) 278 { 279 int rid; 280 281 rid = 0; 282 sc->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 283 &rid, RF_ACTIVE | RF_SHAREABLE); 284 if (sc->mem_res == NULL) { 285 device_printf(sc->dev, "%s: cannot allocate mem resource\n", 286 __func__); 287 return (ENXIO); 288 } 289 290 sc->is_little_endian = device_has_property(sc->dev, "little-endian"); 291 292 return (0); 293 } 294 295 int 296 memac_mdio_generic_detach(struct memac_mdio_softc_common *sc) 297 { 298 299 if (sc->mem_res != NULL) 300 bus_release_resource(sc->dev, SYS_RES_MEMORY, 301 rman_get_rid(sc->mem_res), sc->mem_res); 302 303 return (0); 304 } 305