1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2022 Bjoern A. Zeeb 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/kernel.h> 31 #include <sys/bus.h> 32 #include <sys/rman.h> 33 #include <sys/malloc.h> 34 #include <sys/module.h> 35 #include <sys/endian.h> 36 #include <sys/socket.h> 37 38 #include <machine/bus.h> 39 #include <machine/resource.h> 40 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 #include <dev/fdt/simplebus.h> 44 45 #include <net/if.h> 46 #include <net/if_var.h> 47 #include <net/if_media.h> 48 49 #include <dev/mii/mii.h> 50 #include <dev/mii/miivar.h> 51 52 #include "memac_mdio.h" 53 #include "memac_mdio_if.h" 54 #include "ofw_bus_if.h" 55 #include "miibus_if.h" 56 57 /* -------------------------------------------------------------------------- */ 58 59 struct memacphy_softc_fdt { 60 struct memacphy_softc_common scc; 61 uint32_t reg; 62 phandle_t xref; 63 }; 64 65 static void 66 memacphy_fdt_miibus_statchg(device_t dev) 67 { 68 struct memacphy_softc_fdt *sc; 69 70 sc = device_get_softc(dev); 71 memacphy_miibus_statchg(&sc->scc); 72 } 73 74 static int 75 memacphy_fdt_set_ni_dev(device_t dev, device_t nidev) 76 { 77 struct memacphy_softc_fdt *sc; 78 79 sc = device_get_softc(dev); 80 return (memacphy_set_ni_dev(&sc->scc, nidev)); 81 } 82 83 static int 84 memacphy_fdt_get_phy_loc(device_t dev, int *phy_loc) 85 { 86 struct memacphy_softc_fdt *sc; 87 88 sc = device_get_softc(dev); 89 return (memacphy_get_phy_loc(&sc->scc, phy_loc)); 90 } 91 92 static int 93 memacphy_fdt_probe(device_t dev) 94 { 95 96 if (!ofw_bus_status_okay(dev)) 97 return (ENXIO); 98 99 device_set_desc(dev, "MEMAC PHY (fdt)"); 100 return (BUS_PROBE_DEFAULT); 101 } 102 103 static int 104 memacphy_fdt_attach(device_t dev) 105 { 106 struct memacphy_softc_fdt *sc; 107 phandle_t node; 108 ssize_t s; 109 int error; 110 111 sc = device_get_softc(dev); 112 sc->scc.dev = dev; 113 node = ofw_bus_get_node(dev); 114 115 s = device_get_property(dev, "reg", &sc->reg, sizeof(sc->reg), 116 DEVICE_PROP_UINT32); 117 if (s != -1) 118 sc->scc.phy = sc->reg; 119 else 120 sc->scc.phy = -1; 121 sc->xref = OF_xref_from_node(node); 122 123 error = OF_device_register_xref(sc->xref, dev); 124 if (error != 0) 125 device_printf(dev, "Failed to register xref %#x\n", sc->xref); 126 127 if (bootverbose) 128 device_printf(dev, "node %#x '%s': reg %#x xref %#x phy %u\n", 129 node, ofw_bus_get_name(dev), sc->reg, sc->xref, sc->scc.phy); 130 131 if (sc->scc.phy == -1) 132 error = ENXIO; 133 return (error); 134 } 135 136 static device_method_t memacphy_fdt_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, memacphy_fdt_probe), 139 DEVMETHOD(device_attach, memacphy_fdt_attach), 140 DEVMETHOD(device_detach, bus_generic_detach), 141 142 /* MII interface */ 143 DEVMETHOD(miibus_readreg, memacphy_miibus_readreg), 144 DEVMETHOD(miibus_writereg, memacphy_miibus_writereg), 145 DEVMETHOD(miibus_statchg, memacphy_fdt_miibus_statchg), 146 147 /* memac */ 148 DEVMETHOD(memac_mdio_set_ni_dev, memacphy_fdt_set_ni_dev), 149 DEVMETHOD(memac_mdio_get_phy_loc, memacphy_fdt_get_phy_loc), 150 151 DEVMETHOD_END 152 }; 153 154 DEFINE_CLASS_0(memacphy_fdt, memacphy_fdt_driver, memacphy_fdt_methods, 155 sizeof(struct memacphy_softc_fdt)); 156 157 EARLY_DRIVER_MODULE(memacphy_fdt, memac_mdio_fdt, memacphy_fdt_driver, 0, 0, 158 BUS_PASS_SUPPORTDEV); 159 DRIVER_MODULE(miibus, memacphy_fdt, miibus_driver, 0, 0); 160 MODULE_DEPEND(memacphy_fdt, miibus, 1, 1, 1); 161 162 /* -------------------------------------------------------------------------- */ 163 164 /* 165 * Order in this softc is important; memac_mdio_fdt_attach() calls 166 * simplebus_init() which expects sb_sc at the beginning. 167 */ 168 struct memac_mdio_softc_fdt { 169 struct simplebus_softc sb_sc; /* Must stay first. */ 170 struct memac_mdio_softc_common scc; 171 }; 172 173 static int 174 memac_fdt_miibus_readreg(device_t dev, int phy, int reg) 175 { 176 struct memac_mdio_softc_fdt *sc; 177 178 sc = device_get_softc(dev); 179 return (memac_miibus_readreg(&sc->scc, phy, reg)); 180 } 181 182 static int 183 memac_fdt_miibus_writereg(device_t dev, int phy, int reg, int data) 184 { 185 struct memac_mdio_softc_fdt *sc; 186 187 sc = device_get_softc(dev); 188 return (memac_miibus_writereg(&sc->scc, phy, reg, data)); 189 } 190 191 static struct ofw_compat_data compat_data[] = { 192 { "fsl,fman-memac-mdio", 1 }, 193 { NULL, 0 } 194 }; 195 196 static int 197 memac_mdio_fdt_probe(device_t dev) 198 { 199 200 if (!ofw_bus_status_okay(dev)) 201 return (ENXIO); 202 203 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 204 return (ENXIO); 205 206 device_set_desc(dev, "Freescale XGMAC MDIO Bus (FDT)"); 207 return (BUS_PROBE_DEFAULT); 208 } 209 210 static int 211 memac_mdio_fdt_probe_child(device_t bus, phandle_t child) 212 { 213 device_t childdev; 214 215 /* Make sure we do not aliready have a device. */ 216 childdev = ofw_bus_find_child_device_by_phandle(bus, child); 217 if (childdev != NULL) 218 return (0); 219 220 childdev = simplebus_add_device(bus, child, 0, NULL, -1, NULL); 221 if (childdev == NULL) 222 return (ENXIO); 223 224 return (device_probe_and_attach(childdev)); 225 } 226 227 static int 228 memac_mdio_fdt_attach(device_t dev) 229 { 230 struct memac_mdio_softc_fdt *sc; 231 phandle_t node, child; 232 int error; 233 234 sc = device_get_softc(dev); 235 sc->scc.dev = dev; 236 237 error = memac_mdio_generic_attach(&sc->scc); 238 if (error != 0) 239 return (error); 240 241 /* Attach the *phy* children represented in the device tree. */ 242 bus_generic_probe(dev); 243 bus_enumerate_hinted_children(dev); 244 node = ofw_bus_get_node(dev); 245 simplebus_init(dev, node); 246 for (child = OF_child(node); child > 0; child = OF_peer(child)) { 247 if (!OF_hasprop(child, "reg")) 248 continue; 249 if (memac_mdio_fdt_probe_child(dev, child) != 0) 250 continue; 251 } 252 253 return (0); 254 } 255 256 static int 257 memac_mdio_fdt_detach(device_t dev) 258 { 259 struct memac_mdio_softc_fdt *sc; 260 261 sc = device_get_softc(dev); 262 return (memac_mdio_generic_detach(&sc->scc)); 263 } 264 265 static const struct ofw_bus_devinfo * 266 memac_simplebus_get_devinfo(device_t bus, device_t child) 267 { 268 269 return (OFW_BUS_GET_DEVINFO(device_get_parent(bus), child)); 270 } 271 272 static device_method_t memac_mdio_fdt_methods[] = { 273 /* Device interface */ 274 DEVMETHOD(device_probe, memac_mdio_fdt_probe), 275 DEVMETHOD(device_attach, memac_mdio_fdt_attach), 276 DEVMETHOD(device_detach, memac_mdio_fdt_detach), 277 278 /* MII interface */ 279 DEVMETHOD(miibus_readreg, memac_fdt_miibus_readreg), 280 DEVMETHOD(miibus_writereg, memac_fdt_miibus_writereg), 281 282 /* OFW/simplebus */ 283 DEVMETHOD(ofw_bus_get_devinfo, memac_simplebus_get_devinfo), 284 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 285 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 286 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 287 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 288 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 289 290 /* Bus interface */ 291 DEVMETHOD(bus_add_child, bus_generic_add_child), 292 DEVMETHOD(bus_read_ivar, memac_mdio_read_ivar), 293 DEVMETHOD(bus_get_property, memac_mdio_get_property), 294 295 DEVMETHOD_END 296 }; 297 298 DEFINE_CLASS_0(memac_mdio_fdt, memac_mdio_fdt_driver, memac_mdio_fdt_methods, 299 sizeof(struct memac_mdio_softc_fdt)); 300 301 EARLY_DRIVER_MODULE(memac_mdio_fdt, simplebus, memac_mdio_fdt_driver, 0, 0, 302 BUS_PASS_SUPPORTDEV); 303 304 DRIVER_MODULE(miibus, memac_mdio_fdt, miibus_driver, 0, 0); 305 MODULE_DEPEND(memac_mdio_fdt, miibus, 1, 1, 1); 306 MODULE_VERSION(memac_mdio_fdt, 1); 307