1592ffb21SWarner Losh /*
2592ffb21SWarner Losh * Copyright © 2008 Keith Packard
3592ffb21SWarner Losh *
4592ffb21SWarner Losh * Permission to use, copy, modify, distribute, and sell this software and its
5592ffb21SWarner Losh * documentation for any purpose is hereby granted without fee, provided that
6592ffb21SWarner Losh * the above copyright notice appear in all copies and that both that copyright
7592ffb21SWarner Losh * notice and this permission notice appear in supporting documentation, and
8592ffb21SWarner Losh * that the name of the copyright holders not be used in advertising or
9592ffb21SWarner Losh * publicity pertaining to distribution of the software without specific,
10592ffb21SWarner Losh * written prior permission. The copyright holders make no representations
11592ffb21SWarner Losh * about the suitability of this software for any purpose. It is provided "as
12592ffb21SWarner Losh * is" without express or implied warranty.
13592ffb21SWarner Losh *
14592ffb21SWarner Losh * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15592ffb21SWarner Losh * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16592ffb21SWarner Losh * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17592ffb21SWarner Losh * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18592ffb21SWarner Losh * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19592ffb21SWarner Losh * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20592ffb21SWarner Losh * OF THIS SOFTWARE.
21592ffb21SWarner Losh */
22592ffb21SWarner Losh
23592ffb21SWarner Losh #ifndef _DRM_DP_HELPER_H_
24592ffb21SWarner Losh #define _DRM_DP_HELPER_H_
25592ffb21SWarner Losh
26592ffb21SWarner Losh /*
27592ffb21SWarner Losh * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
28592ffb21SWarner Losh * DP and DPCD versions are independent. Differences from 1.0 are not noted,
29592ffb21SWarner Losh * 1.0 devices basically don't exist in the wild.
30592ffb21SWarner Losh *
31592ffb21SWarner Losh * Abbreviations, in chronological order:
32592ffb21SWarner Losh *
33592ffb21SWarner Losh * eDP: Embedded DisplayPort version 1
34592ffb21SWarner Losh * DPI: DisplayPort Interoperability Guideline v1.1a
35592ffb21SWarner Losh * 1.2: DisplayPort 1.2
36592ffb21SWarner Losh *
37592ffb21SWarner Losh * 1.2 formally includes both eDP and DPI definitions.
38592ffb21SWarner Losh */
39592ffb21SWarner Losh
40592ffb21SWarner Losh #define AUX_NATIVE_WRITE 0x8
41592ffb21SWarner Losh #define AUX_NATIVE_READ 0x9
42592ffb21SWarner Losh #define AUX_I2C_WRITE 0x0
43592ffb21SWarner Losh #define AUX_I2C_READ 0x1
44592ffb21SWarner Losh #define AUX_I2C_STATUS 0x2
45592ffb21SWarner Losh #define AUX_I2C_MOT 0x4
46592ffb21SWarner Losh
47592ffb21SWarner Losh #define AUX_NATIVE_REPLY_ACK (0x0 << 4)
48592ffb21SWarner Losh #define AUX_NATIVE_REPLY_NACK (0x1 << 4)
49592ffb21SWarner Losh #define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
50592ffb21SWarner Losh #define AUX_NATIVE_REPLY_MASK (0x3 << 4)
51592ffb21SWarner Losh
52592ffb21SWarner Losh #define AUX_I2C_REPLY_ACK (0x0 << 6)
53592ffb21SWarner Losh #define AUX_I2C_REPLY_NACK (0x1 << 6)
54592ffb21SWarner Losh #define AUX_I2C_REPLY_DEFER (0x2 << 6)
55592ffb21SWarner Losh #define AUX_I2C_REPLY_MASK (0x3 << 6)
56592ffb21SWarner Losh
57592ffb21SWarner Losh /* AUX CH addresses */
58592ffb21SWarner Losh /* DPCD */
59592ffb21SWarner Losh #define DP_DPCD_REV 0x000
60592ffb21SWarner Losh
61592ffb21SWarner Losh #define DP_MAX_LINK_RATE 0x001
62592ffb21SWarner Losh
63592ffb21SWarner Losh #define DP_MAX_LANE_COUNT 0x002
64592ffb21SWarner Losh # define DP_MAX_LANE_COUNT_MASK 0x1f
65592ffb21SWarner Losh # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
66592ffb21SWarner Losh # define DP_ENHANCED_FRAME_CAP (1 << 7)
67592ffb21SWarner Losh
68592ffb21SWarner Losh #define DP_MAX_DOWNSPREAD 0x003
69592ffb21SWarner Losh # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
70592ffb21SWarner Losh
71592ffb21SWarner Losh #define DP_NORP 0x004
72592ffb21SWarner Losh
73592ffb21SWarner Losh #define DP_DOWNSTREAMPORT_PRESENT 0x005
74592ffb21SWarner Losh # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
75592ffb21SWarner Losh # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
76592ffb21SWarner Losh /* 00b = DisplayPort */
77592ffb21SWarner Losh /* 01b = Analog */
78592ffb21SWarner Losh /* 10b = TMDS or HDMI */
79592ffb21SWarner Losh /* 11b = Other */
80592ffb21SWarner Losh # define DP_FORMAT_CONVERSION (1 << 3)
81592ffb21SWarner Losh # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
82592ffb21SWarner Losh
83592ffb21SWarner Losh #define DP_MAIN_LINK_CHANNEL_CODING 0x006
84592ffb21SWarner Losh
85592ffb21SWarner Losh #define DP_DOWN_STREAM_PORT_COUNT 0x007
86592ffb21SWarner Losh # define DP_PORT_COUNT_MASK 0x0f
87592ffb21SWarner Losh # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
88592ffb21SWarner Losh # define DP_OUI_SUPPORT (1 << 7)
89592ffb21SWarner Losh
90592ffb21SWarner Losh #define DP_I2C_SPEED_CAP 0x00c /* DPI */
91592ffb21SWarner Losh # define DP_I2C_SPEED_1K 0x01
92592ffb21SWarner Losh # define DP_I2C_SPEED_5K 0x02
93592ffb21SWarner Losh # define DP_I2C_SPEED_10K 0x04
94592ffb21SWarner Losh # define DP_I2C_SPEED_100K 0x08
95592ffb21SWarner Losh # define DP_I2C_SPEED_400K 0x10
96592ffb21SWarner Losh # define DP_I2C_SPEED_1M 0x20
97592ffb21SWarner Losh
98592ffb21SWarner Losh #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
99592ffb21SWarner Losh #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
100592ffb21SWarner Losh
101592ffb21SWarner Losh /* Multiple stream transport */
102592ffb21SWarner Losh #define DP_MSTM_CAP 0x021 /* 1.2 */
103592ffb21SWarner Losh # define DP_MST_CAP (1 << 0)
104592ffb21SWarner Losh
105592ffb21SWarner Losh #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
106592ffb21SWarner Losh # define DP_PSR_IS_SUPPORTED 1
107592ffb21SWarner Losh #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
108592ffb21SWarner Losh # define DP_PSR_NO_TRAIN_ON_EXIT 1
109592ffb21SWarner Losh # define DP_PSR_SETUP_TIME_330 (0 << 1)
110592ffb21SWarner Losh # define DP_PSR_SETUP_TIME_275 (1 << 1)
111592ffb21SWarner Losh # define DP_PSR_SETUP_TIME_220 (2 << 1)
112592ffb21SWarner Losh # define DP_PSR_SETUP_TIME_165 (3 << 1)
113592ffb21SWarner Losh # define DP_PSR_SETUP_TIME_110 (4 << 1)
114592ffb21SWarner Losh # define DP_PSR_SETUP_TIME_55 (5 << 1)
115592ffb21SWarner Losh # define DP_PSR_SETUP_TIME_0 (6 << 1)
116592ffb21SWarner Losh # define DP_PSR_SETUP_TIME_MASK (7 << 1)
117592ffb21SWarner Losh # define DP_PSR_SETUP_TIME_SHIFT 1
118592ffb21SWarner Losh
119592ffb21SWarner Losh /*
120592ffb21SWarner Losh * 0x80-0x8f describe downstream port capabilities, but there are two layouts
121592ffb21SWarner Losh * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
122592ffb21SWarner Losh * each port's descriptor is one byte wide. If it was set, each port's is
123592ffb21SWarner Losh * four bytes wide, starting with the one byte from the base info. As of
124592ffb21SWarner Losh * DP interop v1.1a only VGA defines additional detail.
125592ffb21SWarner Losh */
126592ffb21SWarner Losh
127592ffb21SWarner Losh /* offset 0 */
128592ffb21SWarner Losh #define DP_DOWNSTREAM_PORT_0 0x80
129592ffb21SWarner Losh # define DP_DS_PORT_TYPE_MASK (7 << 0)
130592ffb21SWarner Losh # define DP_DS_PORT_TYPE_DP 0
131592ffb21SWarner Losh # define DP_DS_PORT_TYPE_VGA 1
132592ffb21SWarner Losh # define DP_DS_PORT_TYPE_DVI 2
133592ffb21SWarner Losh # define DP_DS_PORT_TYPE_HDMI 3
134592ffb21SWarner Losh # define DP_DS_PORT_TYPE_NON_EDID 4
135592ffb21SWarner Losh # define DP_DS_PORT_HPD (1 << 3)
136592ffb21SWarner Losh /* offset 1 for VGA is maximum megapixels per second / 8 */
137592ffb21SWarner Losh /* offset 2 */
138592ffb21SWarner Losh # define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
139592ffb21SWarner Losh # define DP_DS_VGA_8BPC 0
140592ffb21SWarner Losh # define DP_DS_VGA_10BPC 1
141592ffb21SWarner Losh # define DP_DS_VGA_12BPC 2
142592ffb21SWarner Losh # define DP_DS_VGA_16BPC 3
143592ffb21SWarner Losh
144592ffb21SWarner Losh /* link configuration */
145592ffb21SWarner Losh #define DP_LINK_BW_SET 0x100
146592ffb21SWarner Losh # define DP_LINK_BW_1_62 0x06
147592ffb21SWarner Losh # define DP_LINK_BW_2_7 0x0a
148592ffb21SWarner Losh # define DP_LINK_BW_5_4 0x14 /* 1.2 */
149592ffb21SWarner Losh
150592ffb21SWarner Losh #define DP_LANE_COUNT_SET 0x101
151592ffb21SWarner Losh # define DP_LANE_COUNT_MASK 0x0f
152592ffb21SWarner Losh # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
153592ffb21SWarner Losh
154592ffb21SWarner Losh #define DP_TRAINING_PATTERN_SET 0x102
155592ffb21SWarner Losh # define DP_TRAINING_PATTERN_DISABLE 0
156592ffb21SWarner Losh # define DP_TRAINING_PATTERN_1 1
157592ffb21SWarner Losh # define DP_TRAINING_PATTERN_2 2
158592ffb21SWarner Losh # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
159592ffb21SWarner Losh # define DP_TRAINING_PATTERN_MASK 0x3
160592ffb21SWarner Losh
161592ffb21SWarner Losh # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
162592ffb21SWarner Losh # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
163592ffb21SWarner Losh # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
164592ffb21SWarner Losh # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
165592ffb21SWarner Losh # define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
166592ffb21SWarner Losh
167592ffb21SWarner Losh # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
168592ffb21SWarner Losh # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
169592ffb21SWarner Losh
170592ffb21SWarner Losh # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
171592ffb21SWarner Losh # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
172592ffb21SWarner Losh # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
173592ffb21SWarner Losh # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
174592ffb21SWarner Losh
175592ffb21SWarner Losh #define DP_TRAINING_LANE0_SET 0x103
176592ffb21SWarner Losh #define DP_TRAINING_LANE1_SET 0x104
177592ffb21SWarner Losh #define DP_TRAINING_LANE2_SET 0x105
178592ffb21SWarner Losh #define DP_TRAINING_LANE3_SET 0x106
179592ffb21SWarner Losh
180592ffb21SWarner Losh # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
181592ffb21SWarner Losh # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
182592ffb21SWarner Losh # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
183592ffb21SWarner Losh # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
184592ffb21SWarner Losh # define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
185592ffb21SWarner Losh # define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
186592ffb21SWarner Losh # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
187592ffb21SWarner Losh
188592ffb21SWarner Losh # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
189592ffb21SWarner Losh # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
190592ffb21SWarner Losh # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
191592ffb21SWarner Losh # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
192592ffb21SWarner Losh # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
193592ffb21SWarner Losh
194592ffb21SWarner Losh # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
195592ffb21SWarner Losh # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
196592ffb21SWarner Losh
197592ffb21SWarner Losh #define DP_DOWNSPREAD_CTRL 0x107
198592ffb21SWarner Losh # define DP_SPREAD_AMP_0_5 (1 << 4)
199592ffb21SWarner Losh # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
200592ffb21SWarner Losh
201592ffb21SWarner Losh #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
202592ffb21SWarner Losh # define DP_SET_ANSI_8B10B (1 << 0)
203592ffb21SWarner Losh
204592ffb21SWarner Losh #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
205592ffb21SWarner Losh /* bitmask as for DP_I2C_SPEED_CAP */
206592ffb21SWarner Losh
207592ffb21SWarner Losh #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
208592ffb21SWarner Losh
209592ffb21SWarner Losh #define DP_MSTM_CTRL 0x111 /* 1.2 */
210592ffb21SWarner Losh # define DP_MST_EN (1 << 0)
211592ffb21SWarner Losh # define DP_UP_REQ_EN (1 << 1)
212592ffb21SWarner Losh # define DP_UPSTREAM_IS_SRC (1 << 2)
213592ffb21SWarner Losh
214592ffb21SWarner Losh #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
215592ffb21SWarner Losh # define DP_PSR_ENABLE (1 << 0)
216592ffb21SWarner Losh # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
217592ffb21SWarner Losh # define DP_PSR_CRC_VERIFICATION (1 << 2)
218592ffb21SWarner Losh # define DP_PSR_FRAME_CAPTURE (1 << 3)
219592ffb21SWarner Losh
220592ffb21SWarner Losh #define DP_SINK_COUNT 0x200
221592ffb21SWarner Losh /* prior to 1.2 bit 7 was reserved mbz */
222592ffb21SWarner Losh # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
223592ffb21SWarner Losh # define DP_SINK_CP_READY (1 << 6)
224592ffb21SWarner Losh
225592ffb21SWarner Losh #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
226592ffb21SWarner Losh # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
227592ffb21SWarner Losh # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
228592ffb21SWarner Losh # define DP_CP_IRQ (1 << 2)
229592ffb21SWarner Losh # define DP_SINK_SPECIFIC_IRQ (1 << 6)
230592ffb21SWarner Losh
231592ffb21SWarner Losh #define DP_LANE0_1_STATUS 0x202
232592ffb21SWarner Losh #define DP_LANE2_3_STATUS 0x203
233592ffb21SWarner Losh # define DP_LANE_CR_DONE (1 << 0)
234592ffb21SWarner Losh # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
235592ffb21SWarner Losh # define DP_LANE_SYMBOL_LOCKED (1 << 2)
236592ffb21SWarner Losh
237592ffb21SWarner Losh #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
238592ffb21SWarner Losh DP_LANE_CHANNEL_EQ_DONE | \
239592ffb21SWarner Losh DP_LANE_SYMBOL_LOCKED)
240592ffb21SWarner Losh
241592ffb21SWarner Losh #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
242592ffb21SWarner Losh
243592ffb21SWarner Losh #define DP_INTERLANE_ALIGN_DONE (1 << 0)
244592ffb21SWarner Losh #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
245592ffb21SWarner Losh #define DP_LINK_STATUS_UPDATED (1 << 7)
246592ffb21SWarner Losh
247592ffb21SWarner Losh #define DP_SINK_STATUS 0x205
248592ffb21SWarner Losh
249592ffb21SWarner Losh #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
250592ffb21SWarner Losh #define DP_RECEIVE_PORT_1_STATUS (1 << 1)
251592ffb21SWarner Losh
252592ffb21SWarner Losh #define DP_ADJUST_REQUEST_LANE0_1 0x206
253592ffb21SWarner Losh #define DP_ADJUST_REQUEST_LANE2_3 0x207
254592ffb21SWarner Losh # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
255592ffb21SWarner Losh # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
256592ffb21SWarner Losh # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
257592ffb21SWarner Losh # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
258592ffb21SWarner Losh # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
259592ffb21SWarner Losh # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
260592ffb21SWarner Losh # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
261592ffb21SWarner Losh # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
262592ffb21SWarner Losh
263592ffb21SWarner Losh #define DP_TEST_REQUEST 0x218
264592ffb21SWarner Losh # define DP_TEST_LINK_TRAINING (1 << 0)
265592ffb21SWarner Losh # define DP_TEST_LINK_PATTERN (1 << 1)
266592ffb21SWarner Losh # define DP_TEST_LINK_EDID_READ (1 << 2)
267592ffb21SWarner Losh # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
268592ffb21SWarner Losh
269592ffb21SWarner Losh #define DP_TEST_LINK_RATE 0x219
270592ffb21SWarner Losh # define DP_LINK_RATE_162 (0x6)
271592ffb21SWarner Losh # define DP_LINK_RATE_27 (0xa)
272592ffb21SWarner Losh
273592ffb21SWarner Losh #define DP_TEST_LANE_COUNT 0x220
274592ffb21SWarner Losh
275592ffb21SWarner Losh #define DP_TEST_PATTERN 0x221
276592ffb21SWarner Losh
277592ffb21SWarner Losh #define DP_TEST_RESPONSE 0x260
278592ffb21SWarner Losh # define DP_TEST_ACK (1 << 0)
279592ffb21SWarner Losh # define DP_TEST_NAK (1 << 1)
280592ffb21SWarner Losh # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
281592ffb21SWarner Losh
282592ffb21SWarner Losh #define DP_SOURCE_OUI 0x300
283592ffb21SWarner Losh #define DP_SINK_OUI 0x400
284592ffb21SWarner Losh #define DP_BRANCH_OUI 0x500
285592ffb21SWarner Losh
286592ffb21SWarner Losh #define DP_SET_POWER 0x600
287592ffb21SWarner Losh # define DP_SET_POWER_D0 0x1
288592ffb21SWarner Losh # define DP_SET_POWER_D3 0x2
289592ffb21SWarner Losh
290592ffb21SWarner Losh #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
291592ffb21SWarner Losh # define DP_PSR_LINK_CRC_ERROR (1 << 0)
292592ffb21SWarner Losh # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
293592ffb21SWarner Losh
294592ffb21SWarner Losh #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
295592ffb21SWarner Losh # define DP_PSR_CAPS_CHANGE (1 << 0)
296592ffb21SWarner Losh
297592ffb21SWarner Losh #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
298592ffb21SWarner Losh # define DP_PSR_SINK_INACTIVE 0
299592ffb21SWarner Losh # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
300592ffb21SWarner Losh # define DP_PSR_SINK_ACTIVE_RFB 2
301592ffb21SWarner Losh # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
302592ffb21SWarner Losh # define DP_PSR_SINK_ACTIVE_RESYNC 4
303592ffb21SWarner Losh # define DP_PSR_SINK_INTERNAL_ERROR 7
304592ffb21SWarner Losh # define DP_PSR_SINK_STATE_MASK 0x07
305592ffb21SWarner Losh
306592ffb21SWarner Losh #define MODE_I2C_START 1
307592ffb21SWarner Losh #define MODE_I2C_WRITE 2
308592ffb21SWarner Losh #define MODE_I2C_READ 4
309592ffb21SWarner Losh #define MODE_I2C_STOP 8
310592ffb21SWarner Losh
311592ffb21SWarner Losh struct iic_dp_aux_data {
312592ffb21SWarner Losh bool running;
313592ffb21SWarner Losh u16 address;
314592ffb21SWarner Losh void *priv;
315592ffb21SWarner Losh int (*aux_ch)(device_t adapter, int mode, uint8_t write_byte,
316592ffb21SWarner Losh uint8_t *read_byte);
317592ffb21SWarner Losh device_t port;
318592ffb21SWarner Losh };
319592ffb21SWarner Losh
320592ffb21SWarner Losh int iic_dp_aux_add_bus(device_t dev, const char *name,
321592ffb21SWarner Losh int (*ch)(device_t idev, int mode, uint8_t write_byte, uint8_t *read_byte),
322592ffb21SWarner Losh void *priv, device_t *bus, device_t *adapter);
323592ffb21SWarner Losh
324592ffb21SWarner Losh
325592ffb21SWarner Losh #define DP_LINK_STATUS_SIZE 6
326592ffb21SWarner Losh bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
327592ffb21SWarner Losh int lane_count);
328592ffb21SWarner Losh bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
329592ffb21SWarner Losh int lane_count);
330592ffb21SWarner Losh u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
331592ffb21SWarner Losh int lane);
332592ffb21SWarner Losh u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
333592ffb21SWarner Losh int lane);
334592ffb21SWarner Losh
335592ffb21SWarner Losh #define DP_RECEIVER_CAP_SIZE 0xf
336592ffb21SWarner Losh void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
337592ffb21SWarner Losh void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
338592ffb21SWarner Losh
339592ffb21SWarner Losh u8 drm_dp_link_rate_to_bw_code(int link_rate);
340592ffb21SWarner Losh int drm_dp_bw_code_to_link_rate(u8 link_bw);
341592ffb21SWarner Losh
342592ffb21SWarner Losh static inline int
drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])343592ffb21SWarner Losh drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
344592ffb21SWarner Losh {
345592ffb21SWarner Losh return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
346592ffb21SWarner Losh }
347592ffb21SWarner Losh
348592ffb21SWarner Losh static inline u8
drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])349592ffb21SWarner Losh drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])
350592ffb21SWarner Losh {
351592ffb21SWarner Losh return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
352592ffb21SWarner Losh }
353592ffb21SWarner Losh
354592ffb21SWarner Losh #endif /* _DRM_DP_HELPER_H_ */
355