1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 /* 37 * 82543GC Gigabit Ethernet Controller (Fiber) 38 * 82543GC Gigabit Ethernet Controller (Copper) 39 * 82544EI Gigabit Ethernet Controller (Copper) 40 * 82544EI Gigabit Ethernet Controller (Fiber) 41 * 82544GC Gigabit Ethernet Controller (Copper) 42 * 82544GC Gigabit Ethernet Controller (LOM) 43 */ 44 45 #include "e1000_api.h" 46 47 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw); 48 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw); 49 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw); 50 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, 51 u16 *data); 52 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, 53 u16 data); 54 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw); 55 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw); 56 static s32 e1000_reset_hw_82543(struct e1000_hw *hw); 57 static s32 e1000_init_hw_82543(struct e1000_hw *hw); 58 static s32 e1000_setup_link_82543(struct e1000_hw *hw); 59 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw); 60 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw); 61 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw); 62 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw); 63 static s32 e1000_led_on_82543(struct e1000_hw *hw); 64 static s32 e1000_led_off_82543(struct e1000_hw *hw); 65 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, 66 u32 value); 67 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw); 68 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw); 69 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw); 70 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 71 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw); 72 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl); 73 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw); 74 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 75 u16 count); 76 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw); 77 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state); 78 static s32 e1000_read_mac_addr_82543(struct e1000_hw *hw); 79 80 81 /** 82 * e1000_init_phy_params_82543 - Init PHY func ptrs. 83 * @hw: pointer to the HW structure 84 **/ 85 static s32 e1000_init_phy_params_82543(struct e1000_hw *hw) 86 { 87 struct e1000_phy_info *phy = &hw->phy; 88 s32 ret_val = E1000_SUCCESS; 89 90 DEBUGFUNC("e1000_init_phy_params_82543"); 91 92 if (hw->phy.media_type != e1000_media_type_copper) { 93 phy->type = e1000_phy_none; 94 goto out; 95 } else { 96 phy->ops.power_up = e1000_power_up_phy_copper; 97 phy->ops.power_down = e1000_power_down_phy_copper; 98 } 99 100 phy->addr = 1; 101 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 102 phy->reset_delay_us = 10000; 103 phy->type = e1000_phy_m88; 104 105 /* Function Pointers */ 106 phy->ops.check_polarity = e1000_check_polarity_m88; 107 phy->ops.commit = e1000_phy_sw_reset_generic; 108 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543; 109 phy->ops.get_cable_length = e1000_get_cable_length_m88; 110 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 111 phy->ops.read_reg = (hw->mac.type == e1000_82543) 112 ? e1000_read_phy_reg_82543 113 : e1000_read_phy_reg_m88; 114 phy->ops.reset = (hw->mac.type == e1000_82543) 115 ? e1000_phy_hw_reset_82543 116 : e1000_phy_hw_reset_generic; 117 phy->ops.write_reg = (hw->mac.type == e1000_82543) 118 ? e1000_write_phy_reg_82543 119 : e1000_write_phy_reg_m88; 120 phy->ops.get_info = e1000_get_phy_info_m88; 121 122 /* 123 * The external PHY of the 82543 can be in a funky state. 124 * Resetting helps us read the PHY registers for acquiring 125 * the PHY ID. 126 */ 127 if (!e1000_init_phy_disabled_82543(hw)) { 128 ret_val = phy->ops.reset(hw); 129 if (ret_val) { 130 DEBUGOUT("Resetting PHY during init failed.\n"); 131 goto out; 132 } 133 msec_delay(20); 134 } 135 136 ret_val = e1000_get_phy_id(hw); 137 if (ret_val) 138 goto out; 139 140 /* Verify phy id */ 141 switch (hw->mac.type) { 142 case e1000_82543: 143 if (phy->id != M88E1000_E_PHY_ID) { 144 ret_val = -E1000_ERR_PHY; 145 goto out; 146 } 147 break; 148 case e1000_82544: 149 if (phy->id != M88E1000_I_PHY_ID) { 150 ret_val = -E1000_ERR_PHY; 151 goto out; 152 } 153 break; 154 default: 155 ret_val = -E1000_ERR_PHY; 156 goto out; 157 break; 158 } 159 160 out: 161 return ret_val; 162 } 163 164 /** 165 * e1000_init_nvm_params_82543 - Init NVM func ptrs. 166 * @hw: pointer to the HW structure 167 **/ 168 static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw) 169 { 170 struct e1000_nvm_info *nvm = &hw->nvm; 171 172 DEBUGFUNC("e1000_init_nvm_params_82543"); 173 174 nvm->type = e1000_nvm_eeprom_microwire; 175 nvm->word_size = 64; 176 nvm->delay_usec = 50; 177 nvm->address_bits = 6; 178 nvm->opcode_bits = 3; 179 180 /* Function Pointers */ 181 nvm->ops.read = e1000_read_nvm_microwire; 182 nvm->ops.update = e1000_update_nvm_checksum_generic; 183 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 184 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 185 nvm->ops.write = e1000_write_nvm_microwire; 186 187 return E1000_SUCCESS; 188 } 189 190 /** 191 * e1000_init_mac_params_82543 - Init MAC func ptrs. 192 * @hw: pointer to the HW structure 193 **/ 194 static s32 e1000_init_mac_params_82543(struct e1000_hw *hw) 195 { 196 struct e1000_mac_info *mac = &hw->mac; 197 198 DEBUGFUNC("e1000_init_mac_params_82543"); 199 200 /* Set media type */ 201 switch (hw->device_id) { 202 case E1000_DEV_ID_82543GC_FIBER: 203 case E1000_DEV_ID_82544EI_FIBER: 204 hw->phy.media_type = e1000_media_type_fiber; 205 break; 206 default: 207 hw->phy.media_type = e1000_media_type_copper; 208 break; 209 } 210 211 /* Set mta register count */ 212 mac->mta_reg_count = 128; 213 /* Set rar entry count */ 214 mac->rar_entry_count = E1000_RAR_ENTRIES; 215 216 /* Function pointers */ 217 218 /* bus type/speed/width */ 219 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 220 /* function id */ 221 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 222 /* reset */ 223 mac->ops.reset_hw = e1000_reset_hw_82543; 224 /* hw initialization */ 225 mac->ops.init_hw = e1000_init_hw_82543; 226 /* link setup */ 227 mac->ops.setup_link = e1000_setup_link_82543; 228 /* physical interface setup */ 229 mac->ops.setup_physical_interface = 230 (hw->phy.media_type == e1000_media_type_copper) 231 ? e1000_setup_copper_link_82543 : e1000_setup_fiber_link_82543; 232 /* check for link */ 233 mac->ops.check_for_link = 234 (hw->phy.media_type == e1000_media_type_copper) 235 ? e1000_check_for_copper_link_82543 236 : e1000_check_for_fiber_link_82543; 237 /* link info */ 238 mac->ops.get_link_up_info = 239 (hw->phy.media_type == e1000_media_type_copper) 240 ? e1000_get_speed_and_duplex_copper_generic 241 : e1000_get_speed_and_duplex_fiber_serdes_generic; 242 /* multicast address update */ 243 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 244 /* writing VFTA */ 245 mac->ops.write_vfta = e1000_write_vfta_82543; 246 /* clearing VFTA */ 247 mac->ops.clear_vfta = e1000_clear_vfta_generic; 248 /* read mac address */ 249 mac->ops.read_mac_addr = e1000_read_mac_addr_82543; 250 /* turn on/off LED */ 251 mac->ops.led_on = e1000_led_on_82543; 252 mac->ops.led_off = e1000_led_off_82543; 253 /* clear hardware counters */ 254 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 255 256 /* Set tbi compatibility */ 257 if ((hw->mac.type != e1000_82543) || 258 (hw->phy.media_type == e1000_media_type_fiber)) 259 e1000_set_tbi_compatibility_82543(hw, false); 260 261 return E1000_SUCCESS; 262 } 263 264 /** 265 * e1000_init_function_pointers_82543 - Init func ptrs. 266 * @hw: pointer to the HW structure 267 * 268 * Called to initialize all function pointers and parameters. 269 **/ 270 void e1000_init_function_pointers_82543(struct e1000_hw *hw) 271 { 272 DEBUGFUNC("e1000_init_function_pointers_82543"); 273 274 hw->mac.ops.init_params = e1000_init_mac_params_82543; 275 hw->nvm.ops.init_params = e1000_init_nvm_params_82543; 276 hw->phy.ops.init_params = e1000_init_phy_params_82543; 277 } 278 279 /** 280 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status 281 * @hw: pointer to the HW structure 282 * 283 * Returns the current status of 10-bit Interface (TBI) compatibility 284 * (enabled/disabled). 285 **/ 286 static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw) 287 { 288 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 289 bool state = false; 290 291 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 292 293 if (hw->mac.type != e1000_82543) { 294 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 295 goto out; 296 } 297 298 state = !!(dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED); 299 300 out: 301 return state; 302 } 303 304 /** 305 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility 306 * @hw: pointer to the HW structure 307 * @state: enable/disable TBI compatibility 308 * 309 * Enables or disabled 10-bit Interface (TBI) compatibility. 310 **/ 311 void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state) 312 { 313 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 314 315 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 316 317 if (hw->mac.type != e1000_82543) { 318 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 319 goto out; 320 } 321 322 if (state) 323 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 324 else 325 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 326 327 out: 328 return; 329 } 330 331 /** 332 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status 333 * @hw: pointer to the HW structure 334 * 335 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) 336 * (enabled/disabled). 337 **/ 338 bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw) 339 { 340 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 341 bool state = false; 342 343 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 344 345 if (hw->mac.type != e1000_82543) { 346 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 347 goto out; 348 } 349 350 state = !!(dev_spec->tbi_compatibility & TBI_SBP_ENABLED); 351 352 out: 353 return state; 354 } 355 356 /** 357 * e1000_set_tbi_sbp_82543 - Set TBI SBP 358 * @hw: pointer to the HW structure 359 * @state: enable/disable TBI store bad packet 360 * 361 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP). 362 **/ 363 static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state) 364 { 365 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 366 367 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 368 369 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 370 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 371 else 372 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 373 374 return; 375 } 376 377 /** 378 * e1000_init_phy_disabled_82543 - Returns init PHY status 379 * @hw: pointer to the HW structure 380 * 381 * Returns the current status of whether PHY initialization is disabled. 382 * True if PHY initialization is disabled else false. 383 **/ 384 static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw) 385 { 386 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 387 bool ret_val; 388 389 DEBUGFUNC("e1000_init_phy_disabled_82543"); 390 391 if (hw->mac.type != e1000_82543) { 392 ret_val = false; 393 goto out; 394 } 395 396 ret_val = dev_spec->init_phy_disabled; 397 398 out: 399 return ret_val; 400 } 401 402 /** 403 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled 404 * @hw: pointer to the HW structure 405 * @stats: Struct containing statistic register values 406 * @frame_len: The length of the frame in question 407 * @mac_addr: The Ethernet destination address of the frame in question 408 * @max_frame_size: The maximum frame size 409 * 410 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 411 **/ 412 void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw, 413 struct e1000_hw_stats *stats, u32 frame_len, 414 u8 *mac_addr, u32 max_frame_size) 415 { 416 if (!(e1000_tbi_sbp_enabled_82543(hw))) 417 goto out; 418 419 /* First adjust the frame length. */ 420 frame_len--; 421 /* 422 * We need to adjust the statistics counters, since the hardware 423 * counters overcount this packet as a CRC error and undercount 424 * the packet as a good packet 425 */ 426 /* This packet should not be counted as a CRC error. */ 427 stats->crcerrs--; 428 /* This packet does count as a Good Packet Received. */ 429 stats->gprc++; 430 431 /* Adjust the Good Octets received counters */ 432 stats->gorc += frame_len; 433 434 /* 435 * Is this a broadcast or multicast? Check broadcast first, 436 * since the test for a multicast frame will test positive on 437 * a broadcast frame. 438 */ 439 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff)) 440 /* Broadcast packet */ 441 stats->bprc++; 442 else if (*mac_addr & 0x01) 443 /* Multicast packet */ 444 stats->mprc++; 445 446 /* 447 * In this case, the hardware has over counted the number of 448 * oversize frames. 449 */ 450 if ((frame_len == max_frame_size) && (stats->roc > 0)) 451 stats->roc--; 452 453 /* 454 * Adjust the bin counters when the extra byte put the frame in the 455 * wrong bin. Remember that the frame_len was adjusted above. 456 */ 457 if (frame_len == 64) { 458 stats->prc64++; 459 stats->prc127--; 460 } else if (frame_len == 127) { 461 stats->prc127++; 462 stats->prc255--; 463 } else if (frame_len == 255) { 464 stats->prc255++; 465 stats->prc511--; 466 } else if (frame_len == 511) { 467 stats->prc511++; 468 stats->prc1023--; 469 } else if (frame_len == 1023) { 470 stats->prc1023++; 471 stats->prc1522--; 472 } else if (frame_len == 1522) { 473 stats->prc1522++; 474 } 475 476 out: 477 return; 478 } 479 480 /** 481 * e1000_read_phy_reg_82543 - Read PHY register 482 * @hw: pointer to the HW structure 483 * @offset: register offset to be read 484 * @data: pointer to the read data 485 * 486 * Reads the PHY at offset and stores the information read to data. 487 **/ 488 static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data) 489 { 490 u32 mdic; 491 s32 ret_val = E1000_SUCCESS; 492 493 DEBUGFUNC("e1000_read_phy_reg_82543"); 494 495 if (offset > MAX_PHY_REG_ADDRESS) { 496 DEBUGOUT1("PHY Address %d is out of range\n", offset); 497 ret_val = -E1000_ERR_PARAM; 498 goto out; 499 } 500 501 /* 502 * We must first send a preamble through the MDIO pin to signal the 503 * beginning of an MII instruction. This is done by sending 32 504 * consecutive "1" bits. 505 */ 506 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 507 508 /* 509 * Now combine the next few fields that are required for a read 510 * operation. We use this method instead of calling the 511 * e1000_shift_out_mdi_bits routine five different times. The format 512 * of an MII read instruction consists of a shift out of 14 bits and 513 * is defined as follows: 514 * <Preamble><SOF><Op Code><Phy Addr><Offset> 515 * followed by a shift in of 18 bits. This first two bits shifted in 516 * are TurnAround bits used to avoid contention on the MDIO pin when a 517 * READ operation is performed. These two bits are thrown away 518 * followed by a shift in of 16 bits which contains the desired data. 519 */ 520 mdic = (offset | (hw->phy.addr << 5) | 521 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 522 523 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 524 525 /* 526 * Now that we've shifted out the read command to the MII, we need to 527 * "shift in" the 16-bit value (18 total bits) of the requested PHY 528 * register address. 529 */ 530 *data = e1000_shift_in_mdi_bits_82543(hw); 531 532 out: 533 return ret_val; 534 } 535 536 /** 537 * e1000_write_phy_reg_82543 - Write PHY register 538 * @hw: pointer to the HW structure 539 * @offset: register offset to be written 540 * @data: pointer to the data to be written at offset 541 * 542 * Writes data to the PHY at offset. 543 **/ 544 static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data) 545 { 546 u32 mdic; 547 s32 ret_val = E1000_SUCCESS; 548 549 DEBUGFUNC("e1000_write_phy_reg_82543"); 550 551 if (offset > MAX_PHY_REG_ADDRESS) { 552 DEBUGOUT1("PHY Address %d is out of range\n", offset); 553 ret_val = -E1000_ERR_PARAM; 554 goto out; 555 } 556 557 /* 558 * We'll need to use the SW defined pins to shift the write command 559 * out to the PHY. We first send a preamble to the PHY to signal the 560 * beginning of the MII instruction. This is done by sending 32 561 * consecutive "1" bits. 562 */ 563 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 564 565 /* 566 * Now combine the remaining required fields that will indicate a 567 * write operation. We use this method instead of calling the 568 * e1000_shift_out_mdi_bits routine for each field in the command. The 569 * format of a MII write instruction is as follows: 570 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 571 */ 572 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 573 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 574 mdic <<= 16; 575 mdic |= (u32)data; 576 577 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 578 579 out: 580 return ret_val; 581 } 582 583 /** 584 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock 585 * @hw: pointer to the HW structure 586 * @ctrl: pointer to the control register 587 * 588 * Raise the management data input clock by setting the MDC bit in the control 589 * register. 590 **/ 591 static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 592 { 593 /* 594 * Raise the clock input to the Management Data Clock (by setting the 595 * MDC bit), and then delay a sufficient amount of time. 596 */ 597 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 598 E1000_WRITE_FLUSH(hw); 599 usec_delay(10); 600 } 601 602 /** 603 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock 604 * @hw: pointer to the HW structure 605 * @ctrl: pointer to the control register 606 * 607 * Lower the management data input clock by clearing the MDC bit in the 608 * control register. 609 **/ 610 static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl) 611 { 612 /* 613 * Lower the clock input to the Management Data Clock (by clearing the 614 * MDC bit), and then delay a sufficient amount of time. 615 */ 616 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 617 E1000_WRITE_FLUSH(hw); 618 usec_delay(10); 619 } 620 621 /** 622 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY 623 * @hw: pointer to the HW structure 624 * @data: data to send to the PHY 625 * @count: number of bits to shift out 626 * 627 * We need to shift 'count' bits out to the PHY. So, the value in the 628 * "data" parameter will be shifted out to the PHY one bit at a time. 629 * In order to do this, "data" must be broken down into bits. 630 **/ 631 static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data, 632 u16 count) 633 { 634 u32 ctrl, mask; 635 636 /* 637 * We need to shift "count" number of bits out to the PHY. So, the 638 * value in the "data" parameter will be shifted out to the PHY one 639 * bit at a time. In order to do this, "data" must be broken down 640 * into bits. 641 */ 642 mask = 0x01; 643 mask <<= (count - 1); 644 645 ctrl = E1000_READ_REG(hw, E1000_CTRL); 646 647 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 648 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 649 650 while (mask) { 651 /* 652 * A "1" is shifted out to the PHY by setting the MDIO bit to 653 * "1" and then raising and lowering the Management Data Clock. 654 * A "0" is shifted out to the PHY by setting the MDIO bit to 655 * "0" and then raising and lowering the clock. 656 */ 657 if (data & mask) 658 ctrl |= E1000_CTRL_MDIO; 659 else 660 ctrl &= ~E1000_CTRL_MDIO; 661 662 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 663 E1000_WRITE_FLUSH(hw); 664 665 usec_delay(10); 666 667 e1000_raise_mdi_clk_82543(hw, &ctrl); 668 e1000_lower_mdi_clk_82543(hw, &ctrl); 669 670 mask >>= 1; 671 } 672 } 673 674 /** 675 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY 676 * @hw: pointer to the HW structure 677 * 678 * In order to read a register from the PHY, we need to shift 18 bits 679 * in from the PHY. Bits are "shifted in" by raising the clock input to 680 * the PHY (setting the MDC bit), and then reading the value of the data out 681 * MDIO bit. 682 **/ 683 static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw) 684 { 685 u32 ctrl; 686 u16 data = 0; 687 u8 i; 688 689 /* 690 * In order to read a register from the PHY, we need to shift in a 691 * total of 18 bits from the PHY. The first two bit (turnaround) 692 * times are used to avoid contention on the MDIO pin when a read 693 * operation is performed. These two bits are ignored by us and 694 * thrown away. Bits are "shifted in" by raising the input to the 695 * Management Data Clock (setting the MDC bit) and then reading the 696 * value of the MDIO bit. 697 */ 698 ctrl = E1000_READ_REG(hw, E1000_CTRL); 699 700 /* 701 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 702 * input. 703 */ 704 ctrl &= ~E1000_CTRL_MDIO_DIR; 705 ctrl &= ~E1000_CTRL_MDIO; 706 707 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 708 E1000_WRITE_FLUSH(hw); 709 710 /* 711 * Raise and lower the clock before reading in the data. This accounts 712 * for the turnaround bits. The first clock occurred when we clocked 713 * out the last bit of the Register Address. 714 */ 715 e1000_raise_mdi_clk_82543(hw, &ctrl); 716 e1000_lower_mdi_clk_82543(hw, &ctrl); 717 718 for (data = 0, i = 0; i < 16; i++) { 719 data <<= 1; 720 e1000_raise_mdi_clk_82543(hw, &ctrl); 721 ctrl = E1000_READ_REG(hw, E1000_CTRL); 722 /* Check to see if we shifted in a "1". */ 723 if (ctrl & E1000_CTRL_MDIO) 724 data |= 1; 725 e1000_lower_mdi_clk_82543(hw, &ctrl); 726 } 727 728 e1000_raise_mdi_clk_82543(hw, &ctrl); 729 e1000_lower_mdi_clk_82543(hw, &ctrl); 730 731 return data; 732 } 733 734 /** 735 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY 736 * @hw: pointer to the HW structure 737 * 738 * Calls the function to force speed and duplex for the m88 PHY, and 739 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit, 740 * then call the function for polarity reversal workaround. 741 **/ 742 static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw) 743 { 744 s32 ret_val; 745 746 DEBUGFUNC("e1000_phy_force_speed_duplex_82543"); 747 748 ret_val = e1000_phy_force_speed_duplex_m88(hw); 749 if (ret_val) 750 goto out; 751 752 if (!hw->mac.autoneg && (hw->mac.forced_speed_duplex & 753 E1000_ALL_10_SPEED)) 754 ret_val = e1000_polarity_reversal_workaround_82543(hw); 755 756 out: 757 return ret_val; 758 } 759 760 /** 761 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal 762 * @hw: pointer to the HW structure 763 * 764 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity 765 * inadvertently. To workaround the issue, we disable the transmitter on 766 * the PHY until we have established the link partner's link parameters. 767 **/ 768 static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw) 769 { 770 s32 ret_val = E1000_SUCCESS; 771 u16 mii_status_reg; 772 u16 i; 773 bool link; 774 775 if (!(hw->phy.ops.write_reg)) 776 goto out; 777 778 /* Polarity reversal workaround for forced 10F/10H links. */ 779 780 /* Disable the transmitter on the PHY */ 781 782 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 783 if (ret_val) 784 goto out; 785 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 786 if (ret_val) 787 goto out; 788 789 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 790 if (ret_val) 791 goto out; 792 793 /* 794 * This loop will early-out if the NO link condition has been met. 795 * In other words, DO NOT use e1000_phy_has_link_generic() here. 796 */ 797 for (i = PHY_FORCE_TIME; i > 0; i--) { 798 /* 799 * Read the MII Status Register and wait for Link Status bit 800 * to be clear. 801 */ 802 803 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 804 if (ret_val) 805 goto out; 806 807 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 808 if (ret_val) 809 goto out; 810 811 if (!(mii_status_reg & ~MII_SR_LINK_STATUS)) 812 break; 813 msec_delay_irq(100); 814 } 815 816 /* Recommended delay time after link has been lost */ 817 msec_delay_irq(1000); 818 819 /* Now we will re-enable the transmitter on the PHY */ 820 821 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 822 if (ret_val) 823 goto out; 824 msec_delay_irq(50); 825 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 826 if (ret_val) 827 goto out; 828 msec_delay_irq(50); 829 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 830 if (ret_val) 831 goto out; 832 msec_delay_irq(50); 833 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 834 if (ret_val) 835 goto out; 836 837 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 838 if (ret_val) 839 goto out; 840 841 /* 842 * Read the MII Status Register and wait for Link Status bit 843 * to be set. 844 */ 845 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 846 if (ret_val) 847 goto out; 848 849 out: 850 return ret_val; 851 } 852 853 /** 854 * e1000_phy_hw_reset_82543 - PHY hardware reset 855 * @hw: pointer to the HW structure 856 * 857 * Sets the PHY_RESET_DIR bit in the extended device control register 858 * to put the PHY into a reset and waits for completion. Once the reset 859 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out 860 * of reset. 861 **/ 862 static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw) 863 { 864 u32 ctrl_ext; 865 s32 ret_val; 866 867 DEBUGFUNC("e1000_phy_hw_reset_82543"); 868 869 /* 870 * Read the Extended Device Control Register, assert the PHY_RESET_DIR 871 * bit to put the PHY into reset... 872 */ 873 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 874 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 875 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 876 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 877 E1000_WRITE_FLUSH(hw); 878 879 msec_delay(10); 880 881 /* ...then take it out of reset. */ 882 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 883 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 884 E1000_WRITE_FLUSH(hw); 885 886 usec_delay(150); 887 888 if (!(hw->phy.ops.get_cfg_done)) 889 return E1000_SUCCESS; 890 891 ret_val = hw->phy.ops.get_cfg_done(hw); 892 893 return ret_val; 894 } 895 896 /** 897 * e1000_reset_hw_82543 - Reset hardware 898 * @hw: pointer to the HW structure 899 * 900 * This resets the hardware into a known state. 901 **/ 902 static s32 e1000_reset_hw_82543(struct e1000_hw *hw) 903 { 904 u32 ctrl; 905 s32 ret_val = E1000_SUCCESS; 906 907 DEBUGFUNC("e1000_reset_hw_82543"); 908 909 DEBUGOUT("Masking off all interrupts\n"); 910 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 911 912 E1000_WRITE_REG(hw, E1000_RCTL, 0); 913 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 914 E1000_WRITE_FLUSH(hw); 915 916 e1000_set_tbi_sbp_82543(hw, false); 917 918 /* 919 * Delay to allow any outstanding PCI transactions to complete before 920 * resetting the device 921 */ 922 msec_delay(10); 923 924 ctrl = E1000_READ_REG(hw, E1000_CTRL); 925 926 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 927 if (hw->mac.type == e1000_82543) { 928 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 929 } else { 930 /* 931 * The 82544 can't ACK the 64-bit write when issuing the 932 * reset, so use IO-mapping as a workaround. 933 */ 934 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 935 } 936 937 /* 938 * After MAC reset, force reload of NVM to restore power-on 939 * settings to device. 940 */ 941 hw->nvm.ops.reload(hw); 942 msec_delay(2); 943 944 /* Masking off and clearing any pending interrupts */ 945 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 946 E1000_READ_REG(hw, E1000_ICR); 947 948 return ret_val; 949 } 950 951 /** 952 * e1000_init_hw_82543 - Initialize hardware 953 * @hw: pointer to the HW structure 954 * 955 * This inits the hardware readying it for operation. 956 **/ 957 static s32 e1000_init_hw_82543(struct e1000_hw *hw) 958 { 959 struct e1000_mac_info *mac = &hw->mac; 960 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 961 u32 ctrl; 962 s32 ret_val; 963 u16 i; 964 965 DEBUGFUNC("e1000_init_hw_82543"); 966 967 /* Disabling VLAN filtering */ 968 E1000_WRITE_REG(hw, E1000_VET, 0); 969 mac->ops.clear_vfta(hw); 970 971 /* Setup the receive address. */ 972 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 973 974 /* Zero out the Multicast HASH table */ 975 DEBUGOUT("Zeroing the MTA\n"); 976 for (i = 0; i < mac->mta_reg_count; i++) { 977 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 978 E1000_WRITE_FLUSH(hw); 979 } 980 981 /* 982 * Set the PCI priority bit correctly in the CTRL register. This 983 * determines if the adapter gives priority to receives, or if it 984 * gives equal priority to transmits and receives. 985 */ 986 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 987 ctrl = E1000_READ_REG(hw, E1000_CTRL); 988 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 989 } 990 991 e1000_pcix_mmrbc_workaround_generic(hw); 992 993 /* Setup link and flow control */ 994 ret_val = mac->ops.setup_link(hw); 995 996 /* 997 * Clear all of the statistics registers (clear on read). It is 998 * important that we do this after we have tried to establish link 999 * because the symbol error count will increment wildly if there 1000 * is no link. 1001 */ 1002 e1000_clear_hw_cntrs_82543(hw); 1003 1004 return ret_val; 1005 } 1006 1007 /** 1008 * e1000_setup_link_82543 - Setup flow control and link settings 1009 * @hw: pointer to the HW structure 1010 * 1011 * Read the EEPROM to determine the initial polarity value and write the 1012 * extended device control register with the information before calling 1013 * the generic setup link function, which does the following: 1014 * Determines which flow control settings to use, then configures flow 1015 * control. Calls the appropriate media-specific link configuration 1016 * function. Assuming the adapter has a valid link partner, a valid link 1017 * should be established. Assumes the hardware has previously been reset 1018 * and the transmitter and receiver are not enabled. 1019 **/ 1020 static s32 e1000_setup_link_82543(struct e1000_hw *hw) 1021 { 1022 u32 ctrl_ext; 1023 s32 ret_val; 1024 u16 data; 1025 1026 DEBUGFUNC("e1000_setup_link_82543"); 1027 1028 /* 1029 * Take the 4 bits from NVM word 0xF that determine the initial 1030 * polarity value for the SW controlled pins, and setup the 1031 * Extended Device Control reg with that info. 1032 * This is needed because one of the SW controlled pins is used for 1033 * signal detection. So this should be done before phy setup. 1034 */ 1035 if (hw->mac.type == e1000_82543) { 1036 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1037 if (ret_val) { 1038 DEBUGOUT("NVM Read Error\n"); 1039 ret_val = -E1000_ERR_NVM; 1040 goto out; 1041 } 1042 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 1043 NVM_SWDPIO_EXT_SHIFT); 1044 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1045 } 1046 1047 ret_val = e1000_setup_link_generic(hw); 1048 1049 out: 1050 return ret_val; 1051 } 1052 1053 /** 1054 * e1000_setup_copper_link_82543 - Configure copper link settings 1055 * @hw: pointer to the HW structure 1056 * 1057 * Configures the link for auto-neg or forced speed and duplex. Then we check 1058 * for link, once link is established calls to configure collision distance 1059 * and flow control are called. 1060 **/ 1061 static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw) 1062 { 1063 u32 ctrl; 1064 s32 ret_val; 1065 bool link = true; 1066 1067 DEBUGFUNC("e1000_setup_copper_link_82543"); 1068 1069 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 1070 /* 1071 * With 82543, we need to force speed and duplex on the MAC 1072 * equal to what the PHY speed and duplex configuration is. 1073 * In addition, we need to perform a hardware reset on the 1074 * PHY to take it out of reset. 1075 */ 1076 if (hw->mac.type == e1000_82543) { 1077 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1078 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1079 ret_val = hw->phy.ops.reset(hw); 1080 if (ret_val) 1081 goto out; 1082 } else { 1083 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1084 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1085 } 1086 1087 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 1088 ret_val = e1000_copper_link_setup_m88(hw); 1089 if (ret_val) 1090 goto out; 1091 1092 if (hw->mac.autoneg) { 1093 /* 1094 * Setup autoneg and flow control advertisement and perform 1095 * autonegotiation. 1096 */ 1097 ret_val = e1000_copper_link_autoneg(hw); 1098 if (ret_val) 1099 goto out; 1100 } else { 1101 /* 1102 * PHY will be set to 10H, 10F, 100H or 100F 1103 * depending on user settings. 1104 */ 1105 DEBUGOUT("Forcing Speed and Duplex\n"); 1106 ret_val = e1000_phy_force_speed_duplex_82543(hw); 1107 if (ret_val) { 1108 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1109 goto out; 1110 } 1111 } 1112 1113 /* 1114 * Check link status. Wait up to 100 microseconds for link to become 1115 * valid. 1116 */ 1117 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1118 &link); 1119 if (ret_val) 1120 goto out; 1121 1122 1123 if (link) { 1124 DEBUGOUT("Valid link established!!!\n"); 1125 /* Config the MAC and PHY after link is up */ 1126 if (hw->mac.type == e1000_82544) { 1127 hw->mac.ops.config_collision_dist(hw); 1128 } else { 1129 ret_val = e1000_config_mac_to_phy_82543(hw); 1130 if (ret_val) 1131 goto out; 1132 } 1133 ret_val = e1000_config_fc_after_link_up_generic(hw); 1134 } else { 1135 DEBUGOUT("Unable to establish link!!!\n"); 1136 } 1137 1138 out: 1139 return ret_val; 1140 } 1141 1142 /** 1143 * e1000_setup_fiber_link_82543 - Setup link for fiber 1144 * @hw: pointer to the HW structure 1145 * 1146 * Configures collision distance and flow control for fiber links. Upon 1147 * successful setup, poll for link. 1148 **/ 1149 static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw) 1150 { 1151 u32 ctrl; 1152 s32 ret_val; 1153 1154 DEBUGFUNC("e1000_setup_fiber_link_82543"); 1155 1156 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1157 1158 /* Take the link out of reset */ 1159 ctrl &= ~E1000_CTRL_LRST; 1160 1161 hw->mac.ops.config_collision_dist(hw); 1162 1163 ret_val = e1000_commit_fc_settings_generic(hw); 1164 if (ret_val) 1165 goto out; 1166 1167 DEBUGOUT("Auto-negotiation enabled\n"); 1168 1169 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1170 E1000_WRITE_FLUSH(hw); 1171 msec_delay(1); 1172 1173 /* 1174 * For these adapters, the SW definable pin 1 is cleared when the 1175 * optics detect a signal. If we have a signal, then poll for a 1176 * "Link-Up" indication. 1177 */ 1178 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) 1179 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1180 else 1181 DEBUGOUT("No signal detected\n"); 1182 1183 out: 1184 return ret_val; 1185 } 1186 1187 /** 1188 * e1000_check_for_copper_link_82543 - Check for link (Copper) 1189 * @hw: pointer to the HW structure 1190 * 1191 * Checks the phy for link, if link exists, do the following: 1192 * - check for downshift 1193 * - do polarity workaround (if necessary) 1194 * - configure collision distance 1195 * - configure flow control after link up 1196 * - configure tbi compatibility 1197 **/ 1198 static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw) 1199 { 1200 struct e1000_mac_info *mac = &hw->mac; 1201 u32 icr, rctl; 1202 s32 ret_val; 1203 u16 speed, duplex; 1204 bool link; 1205 1206 DEBUGFUNC("e1000_check_for_copper_link_82543"); 1207 1208 if (!mac->get_link_status) { 1209 ret_val = E1000_SUCCESS; 1210 goto out; 1211 } 1212 1213 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1214 if (ret_val) 1215 goto out; 1216 1217 if (!link) 1218 goto out; /* No link detected */ 1219 1220 mac->get_link_status = false; 1221 1222 e1000_check_downshift_generic(hw); 1223 1224 /* 1225 * If we are forcing speed/duplex, then we can return since 1226 * we have already determined whether we have link or not. 1227 */ 1228 if (!mac->autoneg) { 1229 /* 1230 * If speed and duplex are forced to 10H or 10F, then we will 1231 * implement the polarity reversal workaround. We disable 1232 * interrupts first, and upon returning, place the devices 1233 * interrupt state to its previous value except for the link 1234 * status change interrupt which will happened due to the 1235 * execution of this workaround. 1236 */ 1237 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 1238 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 1239 ret_val = e1000_polarity_reversal_workaround_82543(hw); 1240 icr = E1000_READ_REG(hw, E1000_ICR); 1241 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 1242 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 1243 } 1244 1245 ret_val = -E1000_ERR_CONFIG; 1246 goto out; 1247 } 1248 1249 /* 1250 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 1251 * have Si on board that is 82544 or newer, Auto 1252 * Speed Detection takes care of MAC speed/duplex 1253 * configuration. So we only need to configure Collision 1254 * Distance in the MAC. Otherwise, we need to force 1255 * speed/duplex on the MAC to the current PHY speed/duplex 1256 * settings. 1257 */ 1258 if (mac->type == e1000_82544) 1259 hw->mac.ops.config_collision_dist(hw); 1260 else { 1261 ret_val = e1000_config_mac_to_phy_82543(hw); 1262 if (ret_val) { 1263 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1264 goto out; 1265 } 1266 } 1267 1268 /* 1269 * Configure Flow Control now that Auto-Neg has completed. 1270 * First, we need to restore the desired flow control 1271 * settings because we may have had to re-autoneg with a 1272 * different link partner. 1273 */ 1274 ret_val = e1000_config_fc_after_link_up_generic(hw); 1275 if (ret_val) 1276 DEBUGOUT("Error configuring flow control\n"); 1277 1278 /* 1279 * At this point we know that we are on copper and we have 1280 * auto-negotiated link. These are conditions for checking the link 1281 * partner capability register. We use the link speed to determine if 1282 * TBI compatibility needs to be turned on or off. If the link is not 1283 * at gigabit speed, then TBI compatibility is not needed. If we are 1284 * at gigabit speed, we turn on TBI compatibility. 1285 */ 1286 if (e1000_tbi_compatibility_enabled_82543(hw)) { 1287 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1288 if (ret_val) { 1289 DEBUGOUT("Error getting link speed and duplex\n"); 1290 return ret_val; 1291 } 1292 if (speed != SPEED_1000) { 1293 /* 1294 * If link speed is not set to gigabit speed, 1295 * we do not need to enable TBI compatibility. 1296 */ 1297 if (e1000_tbi_sbp_enabled_82543(hw)) { 1298 /* 1299 * If we previously were in the mode, 1300 * turn it off. 1301 */ 1302 e1000_set_tbi_sbp_82543(hw, false); 1303 rctl = E1000_READ_REG(hw, E1000_RCTL); 1304 rctl &= ~E1000_RCTL_SBP; 1305 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1306 } 1307 } else { 1308 /* 1309 * If TBI compatibility is was previously off, 1310 * turn it on. For compatibility with a TBI link 1311 * partner, we will store bad packets. Some 1312 * frames have an additional byte on the end and 1313 * will look like CRC errors to the hardware. 1314 */ 1315 if (!e1000_tbi_sbp_enabled_82543(hw)) { 1316 e1000_set_tbi_sbp_82543(hw, true); 1317 rctl = E1000_READ_REG(hw, E1000_RCTL); 1318 rctl |= E1000_RCTL_SBP; 1319 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1320 } 1321 } 1322 } 1323 out: 1324 return ret_val; 1325 } 1326 1327 /** 1328 * e1000_check_for_fiber_link_82543 - Check for link (Fiber) 1329 * @hw: pointer to the HW structure 1330 * 1331 * Checks for link up on the hardware. If link is not up and we have 1332 * a signal, then we need to force link up. 1333 **/ 1334 static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw) 1335 { 1336 struct e1000_mac_info *mac = &hw->mac; 1337 u32 rxcw, ctrl, status; 1338 s32 ret_val = E1000_SUCCESS; 1339 1340 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 1341 1342 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1343 status = E1000_READ_REG(hw, E1000_STATUS); 1344 rxcw = E1000_READ_REG(hw, E1000_RXCW); 1345 1346 /* 1347 * If we don't have link (auto-negotiation failed or link partner 1348 * cannot auto-negotiate), the cable is plugged in (we have signal), 1349 * and our link partner is not trying to auto-negotiate with us (we 1350 * are receiving idles or data), we need to force link up. We also 1351 * need to give auto-negotiation time to complete, in case the cable 1352 * was just plugged in. The autoneg_failed flag does this. 1353 */ 1354 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 1355 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 1356 (!(status & E1000_STATUS_LU)) && 1357 (!(rxcw & E1000_RXCW_C))) { 1358 if (!mac->autoneg_failed) { 1359 mac->autoneg_failed = true; 1360 ret_val = 0; 1361 goto out; 1362 } 1363 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 1364 1365 /* Disable auto-negotiation in the TXCW register */ 1366 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1367 1368 /* Force link-up and also force full-duplex. */ 1369 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1370 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1371 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1372 1373 /* Configure Flow Control after forcing link up. */ 1374 ret_val = e1000_config_fc_after_link_up_generic(hw); 1375 if (ret_val) { 1376 DEBUGOUT("Error configuring flow control\n"); 1377 goto out; 1378 } 1379 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 1380 /* 1381 * If we are forcing link and we are receiving /C/ ordered 1382 * sets, re-enable auto-negotiation in the TXCW register 1383 * and disable forced link in the Device Control register 1384 * in an attempt to auto-negotiate with our link partner. 1385 */ 1386 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 1387 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 1388 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 1389 1390 mac->serdes_has_link = true; 1391 } 1392 1393 out: 1394 return ret_val; 1395 } 1396 1397 /** 1398 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings 1399 * @hw: pointer to the HW structure 1400 * 1401 * For the 82543 silicon, we need to set the MAC to match the settings 1402 * of the PHY, even if the PHY is auto-negotiating. 1403 **/ 1404 static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw) 1405 { 1406 u32 ctrl; 1407 s32 ret_val = E1000_SUCCESS; 1408 u16 phy_data; 1409 1410 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 1411 1412 if (!(hw->phy.ops.read_reg)) 1413 goto out; 1414 1415 /* Set the bits to force speed and duplex */ 1416 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1417 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1418 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1419 1420 /* 1421 * Set up duplex in the Device Control and Transmit Control 1422 * registers depending on negotiated values. 1423 */ 1424 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1425 if (ret_val) 1426 goto out; 1427 1428 ctrl &= ~E1000_CTRL_FD; 1429 if (phy_data & M88E1000_PSSR_DPLX) 1430 ctrl |= E1000_CTRL_FD; 1431 1432 hw->mac.ops.config_collision_dist(hw); 1433 1434 /* 1435 * Set up speed in the Device Control register depending on 1436 * negotiated values. 1437 */ 1438 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1439 ctrl |= E1000_CTRL_SPD_1000; 1440 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1441 ctrl |= E1000_CTRL_SPD_100; 1442 1443 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1444 1445 out: 1446 return ret_val; 1447 } 1448 1449 /** 1450 * e1000_write_vfta_82543 - Write value to VLAN filter table 1451 * @hw: pointer to the HW structure 1452 * @offset: the 32-bit offset in which to write the value to. 1453 * @value: the 32-bit value to write at location offset. 1454 * 1455 * This writes a 32-bit value to a 32-bit offset in the VLAN filter 1456 * table. 1457 **/ 1458 static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value) 1459 { 1460 u32 temp; 1461 1462 DEBUGFUNC("e1000_write_vfta_82543"); 1463 1464 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 1465 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 1466 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 1467 E1000_WRITE_FLUSH(hw); 1468 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 1469 E1000_WRITE_FLUSH(hw); 1470 } else { 1471 e1000_write_vfta_generic(hw, offset, value); 1472 } 1473 } 1474 1475 /** 1476 * e1000_led_on_82543 - Turn on SW controllable LED 1477 * @hw: pointer to the HW structure 1478 * 1479 * Turns the SW defined LED on. 1480 **/ 1481 static s32 e1000_led_on_82543(struct e1000_hw *hw) 1482 { 1483 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1484 1485 DEBUGFUNC("e1000_led_on_82543"); 1486 1487 if (hw->mac.type == e1000_82544 && 1488 hw->phy.media_type == e1000_media_type_copper) { 1489 /* Clear SW-definable Pin 0 to turn on the LED */ 1490 ctrl &= ~E1000_CTRL_SWDPIN0; 1491 ctrl |= E1000_CTRL_SWDPIO0; 1492 } else { 1493 /* Fiber 82544 and all 82543 use this method */ 1494 ctrl |= E1000_CTRL_SWDPIN0; 1495 ctrl |= E1000_CTRL_SWDPIO0; 1496 } 1497 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1498 1499 return E1000_SUCCESS; 1500 } 1501 1502 /** 1503 * e1000_led_off_82543 - Turn off SW controllable LED 1504 * @hw: pointer to the HW structure 1505 * 1506 * Turns the SW defined LED off. 1507 **/ 1508 static s32 e1000_led_off_82543(struct e1000_hw *hw) 1509 { 1510 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1511 1512 DEBUGFUNC("e1000_led_off_82543"); 1513 1514 if (hw->mac.type == e1000_82544 && 1515 hw->phy.media_type == e1000_media_type_copper) { 1516 /* Set SW-definable Pin 0 to turn off the LED */ 1517 ctrl |= E1000_CTRL_SWDPIN0; 1518 ctrl |= E1000_CTRL_SWDPIO0; 1519 } else { 1520 ctrl &= ~E1000_CTRL_SWDPIN0; 1521 ctrl |= E1000_CTRL_SWDPIO0; 1522 } 1523 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1524 1525 return E1000_SUCCESS; 1526 } 1527 1528 /** 1529 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters 1530 * @hw: pointer to the HW structure 1531 * 1532 * Clears the hardware counters by reading the counter registers. 1533 **/ 1534 static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw) 1535 { 1536 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 1537 1538 e1000_clear_hw_cntrs_base_generic(hw); 1539 1540 E1000_READ_REG(hw, E1000_PRC64); 1541 E1000_READ_REG(hw, E1000_PRC127); 1542 E1000_READ_REG(hw, E1000_PRC255); 1543 E1000_READ_REG(hw, E1000_PRC511); 1544 E1000_READ_REG(hw, E1000_PRC1023); 1545 E1000_READ_REG(hw, E1000_PRC1522); 1546 E1000_READ_REG(hw, E1000_PTC64); 1547 E1000_READ_REG(hw, E1000_PTC127); 1548 E1000_READ_REG(hw, E1000_PTC255); 1549 E1000_READ_REG(hw, E1000_PTC511); 1550 E1000_READ_REG(hw, E1000_PTC1023); 1551 E1000_READ_REG(hw, E1000_PTC1522); 1552 1553 E1000_READ_REG(hw, E1000_ALGNERRC); 1554 E1000_READ_REG(hw, E1000_RXERRC); 1555 E1000_READ_REG(hw, E1000_TNCRS); 1556 E1000_READ_REG(hw, E1000_CEXTERR); 1557 E1000_READ_REG(hw, E1000_TSCTC); 1558 E1000_READ_REG(hw, E1000_TSCTFC); 1559 } 1560 1561 /** 1562 * e1000_read_mac_addr_82543 - Read device MAC address 1563 * @hw: pointer to the HW structure 1564 * 1565 * Reads the device MAC address from the EEPROM and stores the value. 1566 * Since devices with two ports use the same EEPROM, we increment the 1567 * last bit in the MAC address for the second port. 1568 * 1569 **/ 1570 s32 e1000_read_mac_addr_82543(struct e1000_hw *hw) 1571 { 1572 s32 ret_val = E1000_SUCCESS; 1573 u16 offset, nvm_data, i; 1574 1575 DEBUGFUNC("e1000_read_mac_addr"); 1576 1577 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1578 offset = i >> 1; 1579 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 1580 if (ret_val) { 1581 DEBUGOUT("NVM Read Error\n"); 1582 goto out; 1583 } 1584 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 1585 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 1586 } 1587 1588 /* Flip last bit of mac address if we're on second port */ 1589 if (hw->bus.func == E1000_FUNC_1) 1590 hw->mac.perm_addr[5] ^= 1; 1591 1592 for (i = 0; i < ETHER_ADDR_LEN; i++) 1593 hw->mac.addr[i] = hw->mac.perm_addr[i]; 1594 1595 out: 1596 return ret_val; 1597 } 1598