1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static void e1000_reload_nvm_generic(struct e1000_hw *hw); 38 39 /** 40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers 41 * @hw: pointer to the HW structure 42 * 43 * Setups up the function pointers to no-op functions 44 **/ 45 void e1000_init_nvm_ops_generic(struct e1000_hw *hw) 46 { 47 struct e1000_nvm_info *nvm = &hw->nvm; 48 DEBUGFUNC("e1000_init_nvm_ops_generic"); 49 50 /* Initialize function pointers */ 51 nvm->ops.init_params = e1000_null_ops_generic; 52 nvm->ops.acquire = e1000_null_ops_generic; 53 nvm->ops.read = e1000_null_read_nvm; 54 nvm->ops.release = e1000_null_nvm_generic; 55 nvm->ops.reload = e1000_reload_nvm_generic; 56 nvm->ops.update = e1000_null_ops_generic; 57 nvm->ops.valid_led_default = e1000_null_led_default; 58 nvm->ops.validate = e1000_null_ops_generic; 59 nvm->ops.write = e1000_null_write_nvm; 60 } 61 62 /** 63 * e1000_null_nvm_read - No-op function, return 0 64 * @hw: pointer to the HW structure 65 **/ 66 s32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 67 { 68 DEBUGFUNC("e1000_null_read_nvm"); 69 return E1000_SUCCESS; 70 } 71 72 /** 73 * e1000_null_nvm_generic - No-op function, return void 74 * @hw: pointer to the HW structure 75 **/ 76 void e1000_null_nvm_generic(struct e1000_hw *hw) 77 { 78 DEBUGFUNC("e1000_null_nvm_generic"); 79 return; 80 } 81 82 /** 83 * e1000_null_led_default - No-op function, return 0 84 * @hw: pointer to the HW structure 85 **/ 86 s32 e1000_null_led_default(struct e1000_hw *hw, u16 *data) 87 { 88 DEBUGFUNC("e1000_null_led_default"); 89 return E1000_SUCCESS; 90 } 91 92 /** 93 * e1000_null_write_nvm - No-op function, return 0 94 * @hw: pointer to the HW structure 95 **/ 96 s32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c) 97 { 98 DEBUGFUNC("e1000_null_write_nvm"); 99 return E1000_SUCCESS; 100 } 101 102 /** 103 * e1000_raise_eec_clk - Raise EEPROM clock 104 * @hw: pointer to the HW structure 105 * @eecd: pointer to the EEPROM 106 * 107 * Enable/Raise the EEPROM clock bit. 108 **/ 109 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 110 { 111 *eecd = *eecd | E1000_EECD_SK; 112 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 113 E1000_WRITE_FLUSH(hw); 114 usec_delay(hw->nvm.delay_usec); 115 } 116 117 /** 118 * e1000_lower_eec_clk - Lower EEPROM clock 119 * @hw: pointer to the HW structure 120 * @eecd: pointer to the EEPROM 121 * 122 * Clear/Lower the EEPROM clock bit. 123 **/ 124 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 125 { 126 *eecd = *eecd & ~E1000_EECD_SK; 127 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 128 E1000_WRITE_FLUSH(hw); 129 usec_delay(hw->nvm.delay_usec); 130 } 131 132 /** 133 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 134 * @hw: pointer to the HW structure 135 * @data: data to send to the EEPROM 136 * @count: number of bits to shift out 137 * 138 * We need to shift 'count' bits out to the EEPROM. So, the value in the 139 * "data" parameter will be shifted out to the EEPROM one bit at a time. 140 * In order to do this, "data" must be broken down into bits. 141 **/ 142 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 143 { 144 struct e1000_nvm_info *nvm = &hw->nvm; 145 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 146 u32 mask; 147 148 DEBUGFUNC("e1000_shift_out_eec_bits"); 149 150 mask = 0x01 << (count - 1); 151 if (nvm->type == e1000_nvm_eeprom_microwire) 152 eecd &= ~E1000_EECD_DO; 153 else 154 if (nvm->type == e1000_nvm_eeprom_spi) 155 eecd |= E1000_EECD_DO; 156 157 do { 158 eecd &= ~E1000_EECD_DI; 159 160 if (data & mask) 161 eecd |= E1000_EECD_DI; 162 163 E1000_WRITE_REG(hw, E1000_EECD, eecd); 164 E1000_WRITE_FLUSH(hw); 165 166 usec_delay(nvm->delay_usec); 167 168 e1000_raise_eec_clk(hw, &eecd); 169 e1000_lower_eec_clk(hw, &eecd); 170 171 mask >>= 1; 172 } while (mask); 173 174 eecd &= ~E1000_EECD_DI; 175 E1000_WRITE_REG(hw, E1000_EECD, eecd); 176 } 177 178 /** 179 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 180 * @hw: pointer to the HW structure 181 * @count: number of bits to shift in 182 * 183 * In order to read a register from the EEPROM, we need to shift 'count' bits 184 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 185 * the EEPROM (setting the SK bit), and then reading the value of the data out 186 * "DO" bit. During this "shifting in" process the data in "DI" bit should 187 * always be clear. 188 **/ 189 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 190 { 191 u32 eecd; 192 u32 i; 193 u16 data; 194 195 DEBUGFUNC("e1000_shift_in_eec_bits"); 196 197 eecd = E1000_READ_REG(hw, E1000_EECD); 198 199 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 200 data = 0; 201 202 for (i = 0; i < count; i++) { 203 data <<= 1; 204 e1000_raise_eec_clk(hw, &eecd); 205 206 eecd = E1000_READ_REG(hw, E1000_EECD); 207 208 eecd &= ~E1000_EECD_DI; 209 if (eecd & E1000_EECD_DO) 210 data |= 1; 211 212 e1000_lower_eec_clk(hw, &eecd); 213 } 214 215 return data; 216 } 217 218 /** 219 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 220 * @hw: pointer to the HW structure 221 * @ee_reg: EEPROM flag for polling 222 * 223 * Polls the EEPROM status bit for either read or write completion based 224 * upon the value of 'ee_reg'. 225 **/ 226 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 227 { 228 u32 attempts = 100000; 229 u32 i, reg = 0; 230 s32 ret_val = -E1000_ERR_NVM; 231 232 DEBUGFUNC("e1000_poll_eerd_eewr_done"); 233 234 for (i = 0; i < attempts; i++) { 235 if (ee_reg == E1000_NVM_POLL_READ) 236 reg = E1000_READ_REG(hw, E1000_EERD); 237 else 238 reg = E1000_READ_REG(hw, E1000_EEWR); 239 240 if (reg & E1000_NVM_RW_REG_DONE) { 241 ret_val = E1000_SUCCESS; 242 break; 243 } 244 245 usec_delay(5); 246 } 247 248 return ret_val; 249 } 250 251 /** 252 * e1000_acquire_nvm_generic - Generic request for access to EEPROM 253 * @hw: pointer to the HW structure 254 * 255 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 256 * Return successful if access grant bit set, else clear the request for 257 * EEPROM access and return -E1000_ERR_NVM (-1). 258 **/ 259 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) 260 { 261 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 262 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 263 s32 ret_val = E1000_SUCCESS; 264 265 DEBUGFUNC("e1000_acquire_nvm_generic"); 266 267 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); 268 eecd = E1000_READ_REG(hw, E1000_EECD); 269 270 while (timeout) { 271 if (eecd & E1000_EECD_GNT) 272 break; 273 usec_delay(5); 274 eecd = E1000_READ_REG(hw, E1000_EECD); 275 timeout--; 276 } 277 278 if (!timeout) { 279 eecd &= ~E1000_EECD_REQ; 280 E1000_WRITE_REG(hw, E1000_EECD, eecd); 281 DEBUGOUT("Could not acquire NVM grant\n"); 282 ret_val = -E1000_ERR_NVM; 283 } 284 285 return ret_val; 286 } 287 288 /** 289 * e1000_standby_nvm - Return EEPROM to standby state 290 * @hw: pointer to the HW structure 291 * 292 * Return the EEPROM to a standby state. 293 **/ 294 static void e1000_standby_nvm(struct e1000_hw *hw) 295 { 296 struct e1000_nvm_info *nvm = &hw->nvm; 297 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 298 299 DEBUGFUNC("e1000_standby_nvm"); 300 301 if (nvm->type == e1000_nvm_eeprom_microwire) { 302 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 303 E1000_WRITE_REG(hw, E1000_EECD, eecd); 304 E1000_WRITE_FLUSH(hw); 305 usec_delay(nvm->delay_usec); 306 307 e1000_raise_eec_clk(hw, &eecd); 308 309 /* Select EEPROM */ 310 eecd |= E1000_EECD_CS; 311 E1000_WRITE_REG(hw, E1000_EECD, eecd); 312 E1000_WRITE_FLUSH(hw); 313 usec_delay(nvm->delay_usec); 314 315 e1000_lower_eec_clk(hw, &eecd); 316 } else 317 if (nvm->type == e1000_nvm_eeprom_spi) { 318 /* Toggle CS to flush commands */ 319 eecd |= E1000_EECD_CS; 320 E1000_WRITE_REG(hw, E1000_EECD, eecd); 321 E1000_WRITE_FLUSH(hw); 322 usec_delay(nvm->delay_usec); 323 eecd &= ~E1000_EECD_CS; 324 E1000_WRITE_REG(hw, E1000_EECD, eecd); 325 E1000_WRITE_FLUSH(hw); 326 usec_delay(nvm->delay_usec); 327 } 328 } 329 330 /** 331 * e1000_stop_nvm - Terminate EEPROM command 332 * @hw: pointer to the HW structure 333 * 334 * Terminates the current command by inverting the EEPROM's chip select pin. 335 **/ 336 void e1000_stop_nvm(struct e1000_hw *hw) 337 { 338 u32 eecd; 339 340 DEBUGFUNC("e1000_stop_nvm"); 341 342 eecd = E1000_READ_REG(hw, E1000_EECD); 343 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 344 /* Pull CS high */ 345 eecd |= E1000_EECD_CS; 346 e1000_lower_eec_clk(hw, &eecd); 347 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { 348 /* CS on Microwire is active-high */ 349 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 350 E1000_WRITE_REG(hw, E1000_EECD, eecd); 351 e1000_raise_eec_clk(hw, &eecd); 352 e1000_lower_eec_clk(hw, &eecd); 353 } 354 } 355 356 /** 357 * e1000_release_nvm_generic - Release exclusive access to EEPROM 358 * @hw: pointer to the HW structure 359 * 360 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 361 **/ 362 void e1000_release_nvm_generic(struct e1000_hw *hw) 363 { 364 u32 eecd; 365 366 DEBUGFUNC("e1000_release_nvm_generic"); 367 368 e1000_stop_nvm(hw); 369 370 eecd = E1000_READ_REG(hw, E1000_EECD); 371 eecd &= ~E1000_EECD_REQ; 372 E1000_WRITE_REG(hw, E1000_EECD, eecd); 373 } 374 375 /** 376 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 377 * @hw: pointer to the HW structure 378 * 379 * Setups the EEPROM for reading and writing. 380 **/ 381 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 382 { 383 struct e1000_nvm_info *nvm = &hw->nvm; 384 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 385 s32 ret_val = E1000_SUCCESS; 386 u8 spi_stat_reg; 387 388 DEBUGFUNC("e1000_ready_nvm_eeprom"); 389 390 if (nvm->type == e1000_nvm_eeprom_microwire) { 391 /* Clear SK and DI */ 392 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 393 E1000_WRITE_REG(hw, E1000_EECD, eecd); 394 /* Set CS */ 395 eecd |= E1000_EECD_CS; 396 E1000_WRITE_REG(hw, E1000_EECD, eecd); 397 } else 398 if (nvm->type == e1000_nvm_eeprom_spi) { 399 u16 timeout = NVM_MAX_RETRY_SPI; 400 401 /* Clear SK and CS */ 402 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 403 E1000_WRITE_REG(hw, E1000_EECD, eecd); 404 usec_delay(1); 405 406 /* 407 * Read "Status Register" repeatedly until the LSB is cleared. 408 * The EEPROM will signal that the command has been completed 409 * by clearing bit 0 of the internal status register. If it's 410 * not cleared within 'timeout', then error out. 411 */ 412 while (timeout) { 413 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 414 hw->nvm.opcode_bits); 415 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 416 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 417 break; 418 419 usec_delay(5); 420 e1000_standby_nvm(hw); 421 timeout--; 422 } 423 424 if (!timeout) { 425 DEBUGOUT("SPI NVM Status error\n"); 426 ret_val = -E1000_ERR_NVM; 427 goto out; 428 } 429 } 430 431 out: 432 return ret_val; 433 } 434 435 /** 436 * e1000_read_nvm_spi - Read EEPROM's using SPI 437 * @hw: pointer to the HW structure 438 * @offset: offset of word in the EEPROM to read 439 * @words: number of words to read 440 * @data: word read from the EEPROM 441 * 442 * Reads a 16 bit word from the EEPROM. 443 **/ 444 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 445 { 446 struct e1000_nvm_info *nvm = &hw->nvm; 447 u32 i = 0; 448 s32 ret_val; 449 u16 word_in; 450 u8 read_opcode = NVM_READ_OPCODE_SPI; 451 452 DEBUGFUNC("e1000_read_nvm_spi"); 453 454 /* 455 * A check for invalid values: offset too large, too many words, 456 * and not enough words. 457 */ 458 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 459 (words == 0)) { 460 DEBUGOUT("nvm parameter(s) out of bounds\n"); 461 ret_val = -E1000_ERR_NVM; 462 goto out; 463 } 464 465 ret_val = nvm->ops.acquire(hw); 466 if (ret_val) 467 goto out; 468 469 ret_val = e1000_ready_nvm_eeprom(hw); 470 if (ret_val) 471 goto release; 472 473 e1000_standby_nvm(hw); 474 475 if ((nvm->address_bits == 8) && (offset >= 128)) 476 read_opcode |= NVM_A8_OPCODE_SPI; 477 478 /* Send the READ command (opcode + addr) */ 479 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 480 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 481 482 /* 483 * Read the data. SPI NVMs increment the address with each byte 484 * read and will roll over if reading beyond the end. This allows 485 * us to read the whole NVM from any offset 486 */ 487 for (i = 0; i < words; i++) { 488 word_in = e1000_shift_in_eec_bits(hw, 16); 489 data[i] = (word_in >> 8) | (word_in << 8); 490 } 491 492 release: 493 nvm->ops.release(hw); 494 495 out: 496 return ret_val; 497 } 498 499 /** 500 * e1000_read_nvm_microwire - Reads EEPROM's using microwire 501 * @hw: pointer to the HW structure 502 * @offset: offset of word in the EEPROM to read 503 * @words: number of words to read 504 * @data: word read from the EEPROM 505 * 506 * Reads a 16 bit word from the EEPROM. 507 **/ 508 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 509 u16 *data) 510 { 511 struct e1000_nvm_info *nvm = &hw->nvm; 512 u32 i = 0; 513 s32 ret_val; 514 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; 515 516 DEBUGFUNC("e1000_read_nvm_microwire"); 517 518 /* 519 * A check for invalid values: offset too large, too many words, 520 * and not enough words. 521 */ 522 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 523 (words == 0)) { 524 DEBUGOUT("nvm parameter(s) out of bounds\n"); 525 ret_val = -E1000_ERR_NVM; 526 goto out; 527 } 528 529 ret_val = nvm->ops.acquire(hw); 530 if (ret_val) 531 goto out; 532 533 ret_val = e1000_ready_nvm_eeprom(hw); 534 if (ret_val) 535 goto release; 536 537 for (i = 0; i < words; i++) { 538 /* Send the READ command (opcode + addr) */ 539 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 540 e1000_shift_out_eec_bits(hw, (u16)(offset + i), 541 nvm->address_bits); 542 543 /* 544 * Read the data. For microwire, each word requires the 545 * overhead of setup and tear-down. 546 */ 547 data[i] = e1000_shift_in_eec_bits(hw, 16); 548 e1000_standby_nvm(hw); 549 } 550 551 release: 552 nvm->ops.release(hw); 553 554 out: 555 return ret_val; 556 } 557 558 /** 559 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 560 * @hw: pointer to the HW structure 561 * @offset: offset of word in the EEPROM to read 562 * @words: number of words to read 563 * @data: word read from the EEPROM 564 * 565 * Reads a 16 bit word from the EEPROM using the EERD register. 566 **/ 567 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 568 { 569 struct e1000_nvm_info *nvm = &hw->nvm; 570 u32 i, eerd = 0; 571 s32 ret_val = E1000_SUCCESS; 572 573 DEBUGFUNC("e1000_read_nvm_eerd"); 574 575 /* 576 * A check for invalid values: offset too large, too many words, 577 * too many words for the offset, and not enough words. 578 */ 579 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 580 (words == 0)) { 581 DEBUGOUT("nvm parameter(s) out of bounds\n"); 582 ret_val = -E1000_ERR_NVM; 583 goto out; 584 } 585 586 for (i = 0; i < words; i++) { 587 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 588 E1000_NVM_RW_REG_START; 589 590 E1000_WRITE_REG(hw, E1000_EERD, eerd); 591 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 592 if (ret_val) 593 break; 594 595 data[i] = (E1000_READ_REG(hw, E1000_EERD) >> 596 E1000_NVM_RW_REG_DATA); 597 } 598 599 out: 600 return ret_val; 601 } 602 603 /** 604 * e1000_write_nvm_spi - Write to EEPROM using SPI 605 * @hw: pointer to the HW structure 606 * @offset: offset within the EEPROM to be written to 607 * @words: number of words to write 608 * @data: 16 bit word(s) to be written to the EEPROM 609 * 610 * Writes data to EEPROM at offset using SPI interface. 611 * 612 * If e1000_update_nvm_checksum is not called after this function , the 613 * EEPROM will most likely contain an invalid checksum. 614 **/ 615 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 616 { 617 struct e1000_nvm_info *nvm = &hw->nvm; 618 s32 ret_val; 619 u16 widx = 0; 620 621 DEBUGFUNC("e1000_write_nvm_spi"); 622 623 /* 624 * A check for invalid values: offset too large, too many words, 625 * and not enough words. 626 */ 627 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 628 (words == 0)) { 629 DEBUGOUT("nvm parameter(s) out of bounds\n"); 630 ret_val = -E1000_ERR_NVM; 631 goto out; 632 } 633 634 ret_val = nvm->ops.acquire(hw); 635 if (ret_val) 636 goto out; 637 638 while (widx < words) { 639 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 640 641 ret_val = e1000_ready_nvm_eeprom(hw); 642 if (ret_val) 643 goto release; 644 645 e1000_standby_nvm(hw); 646 647 /* Send the WRITE ENABLE command (8 bit opcode) */ 648 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 649 nvm->opcode_bits); 650 651 e1000_standby_nvm(hw); 652 653 /* 654 * Some SPI eeproms use the 8th address bit embedded in the 655 * opcode 656 */ 657 if ((nvm->address_bits == 8) && (offset >= 128)) 658 write_opcode |= NVM_A8_OPCODE_SPI; 659 660 /* Send the Write command (8-bit opcode + addr) */ 661 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 662 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 663 nvm->address_bits); 664 665 /* Loop to allow for up to whole page write of eeprom */ 666 while (widx < words) { 667 u16 word_out = data[widx]; 668 word_out = (word_out >> 8) | (word_out << 8); 669 e1000_shift_out_eec_bits(hw, word_out, 16); 670 widx++; 671 672 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 673 e1000_standby_nvm(hw); 674 break; 675 } 676 } 677 } 678 679 msec_delay(10); 680 release: 681 nvm->ops.release(hw); 682 683 out: 684 return ret_val; 685 } 686 687 /** 688 * e1000_write_nvm_microwire - Writes EEPROM using microwire 689 * @hw: pointer to the HW structure 690 * @offset: offset within the EEPROM to be written to 691 * @words: number of words to write 692 * @data: 16 bit word(s) to be written to the EEPROM 693 * 694 * Writes data to EEPROM at offset using microwire interface. 695 * 696 * If e1000_update_nvm_checksum is not called after this function , the 697 * EEPROM will most likely contain an invalid checksum. 698 **/ 699 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 700 u16 *data) 701 { 702 struct e1000_nvm_info *nvm = &hw->nvm; 703 s32 ret_val; 704 u32 eecd; 705 u16 words_written = 0; 706 u16 widx = 0; 707 708 DEBUGFUNC("e1000_write_nvm_microwire"); 709 710 /* 711 * A check for invalid values: offset too large, too many words, 712 * and not enough words. 713 */ 714 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 715 (words == 0)) { 716 DEBUGOUT("nvm parameter(s) out of bounds\n"); 717 ret_val = -E1000_ERR_NVM; 718 goto out; 719 } 720 721 ret_val = nvm->ops.acquire(hw); 722 if (ret_val) 723 goto out; 724 725 ret_val = e1000_ready_nvm_eeprom(hw); 726 if (ret_val) 727 goto release; 728 729 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, 730 (u16)(nvm->opcode_bits + 2)); 731 732 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 733 734 e1000_standby_nvm(hw); 735 736 while (words_written < words) { 737 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, 738 nvm->opcode_bits); 739 740 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), 741 nvm->address_bits); 742 743 e1000_shift_out_eec_bits(hw, data[words_written], 16); 744 745 e1000_standby_nvm(hw); 746 747 for (widx = 0; widx < 200; widx++) { 748 eecd = E1000_READ_REG(hw, E1000_EECD); 749 if (eecd & E1000_EECD_DO) 750 break; 751 usec_delay(50); 752 } 753 754 if (widx == 200) { 755 DEBUGOUT("NVM Write did not complete\n"); 756 ret_val = -E1000_ERR_NVM; 757 goto release; 758 } 759 760 e1000_standby_nvm(hw); 761 762 words_written++; 763 } 764 765 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, 766 (u16)(nvm->opcode_bits + 2)); 767 768 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 769 770 release: 771 nvm->ops.release(hw); 772 773 out: 774 return ret_val; 775 } 776 777 /** 778 * e1000_read_pba_string_generic - Read device part number 779 * @hw: pointer to the HW structure 780 * @pba_num: pointer to device part number 781 * @pba_num_size: size of part number buffer 782 * 783 * Reads the product board assembly (PBA) number from the EEPROM and stores 784 * the value in pba_num. 785 **/ 786 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 787 u32 pba_num_size) 788 { 789 s32 ret_val; 790 u16 nvm_data; 791 u16 pba_ptr; 792 u16 offset; 793 u16 length; 794 795 DEBUGFUNC("e1000_read_pba_string_generic"); 796 797 if (pba_num == NULL) { 798 DEBUGOUT("PBA string buffer was null\n"); 799 ret_val = E1000_ERR_INVALID_ARGUMENT; 800 goto out; 801 } 802 803 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 804 if (ret_val) { 805 DEBUGOUT("NVM Read Error\n"); 806 goto out; 807 } 808 809 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 810 if (ret_val) { 811 DEBUGOUT("NVM Read Error\n"); 812 goto out; 813 } 814 815 /* 816 * if nvm_data is not ptr guard the PBA must be in legacy format which 817 * means pba_ptr is actually our second data word for the PBA number 818 * and we can decode it into an ascii string 819 */ 820 if (nvm_data != NVM_PBA_PTR_GUARD) { 821 DEBUGOUT("NVM PBA number is not stored as string\n"); 822 823 /* we will need 11 characters to store the PBA */ 824 if (pba_num_size < 11) { 825 DEBUGOUT("PBA string buffer too small\n"); 826 return E1000_ERR_NO_SPACE; 827 } 828 829 /* extract hex string from data and pba_ptr */ 830 pba_num[0] = (nvm_data >> 12) & 0xF; 831 pba_num[1] = (nvm_data >> 8) & 0xF; 832 pba_num[2] = (nvm_data >> 4) & 0xF; 833 pba_num[3] = nvm_data & 0xF; 834 pba_num[4] = (pba_ptr >> 12) & 0xF; 835 pba_num[5] = (pba_ptr >> 8) & 0xF; 836 pba_num[6] = '-'; 837 pba_num[7] = 0; 838 pba_num[8] = (pba_ptr >> 4) & 0xF; 839 pba_num[9] = pba_ptr & 0xF; 840 841 /* put a null character on the end of our string */ 842 pba_num[10] = '\0'; 843 844 /* switch all the data but the '-' to hex char */ 845 for (offset = 0; offset < 10; offset++) { 846 if (pba_num[offset] < 0xA) 847 pba_num[offset] += '0'; 848 else if (pba_num[offset] < 0x10) 849 pba_num[offset] += 'A' - 0xA; 850 } 851 852 goto out; 853 } 854 855 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 856 if (ret_val) { 857 DEBUGOUT("NVM Read Error\n"); 858 goto out; 859 } 860 861 if (length == 0xFFFF || length == 0) { 862 DEBUGOUT("NVM PBA number section invalid length\n"); 863 ret_val = E1000_ERR_NVM_PBA_SECTION; 864 goto out; 865 } 866 /* check if pba_num buffer is big enough */ 867 if (pba_num_size < (((u32)length * 2) - 1)) { 868 DEBUGOUT("PBA string buffer too small\n"); 869 ret_val = E1000_ERR_NO_SPACE; 870 goto out; 871 } 872 873 /* trim pba length from start of string */ 874 pba_ptr++; 875 length--; 876 877 for (offset = 0; offset < length; offset++) { 878 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); 879 if (ret_val) { 880 DEBUGOUT("NVM Read Error\n"); 881 goto out; 882 } 883 pba_num[offset * 2] = (u8)(nvm_data >> 8); 884 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 885 } 886 pba_num[offset * 2] = '\0'; 887 888 out: 889 return ret_val; 890 } 891 892 /** 893 * e1000_read_pba_length_generic - Read device part number length 894 * @hw: pointer to the HW structure 895 * @pba_num_size: size of part number buffer 896 * 897 * Reads the product board assembly (PBA) number length from the EEPROM and 898 * stores the value in pba_num_size. 899 **/ 900 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size) 901 { 902 s32 ret_val; 903 u16 nvm_data; 904 u16 pba_ptr; 905 u16 length; 906 907 DEBUGFUNC("e1000_read_pba_length_generic"); 908 909 if (pba_num_size == NULL) { 910 DEBUGOUT("PBA buffer size was null\n"); 911 ret_val = E1000_ERR_INVALID_ARGUMENT; 912 goto out; 913 } 914 915 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 916 if (ret_val) { 917 DEBUGOUT("NVM Read Error\n"); 918 goto out; 919 } 920 921 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 922 if (ret_val) { 923 DEBUGOUT("NVM Read Error\n"); 924 goto out; 925 } 926 927 /* if data is not ptr guard the PBA must be in legacy format */ 928 if (nvm_data != NVM_PBA_PTR_GUARD) { 929 *pba_num_size = 11; 930 goto out; 931 } 932 933 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 934 if (ret_val) { 935 DEBUGOUT("NVM Read Error\n"); 936 goto out; 937 } 938 939 if (length == 0xFFFF || length == 0) { 940 DEBUGOUT("NVM PBA number section invalid length\n"); 941 ret_val = E1000_ERR_NVM_PBA_SECTION; 942 goto out; 943 } 944 945 /* 946 * Convert from length in u16 values to u8 chars, add 1 for NULL, 947 * and subtract 2 because length field is included in length. 948 */ 949 *pba_num_size = ((u32)length * 2) - 1; 950 951 out: 952 return ret_val; 953 } 954 955 /** 956 * e1000_read_mac_addr_generic - Read device MAC address 957 * @hw: pointer to the HW structure 958 * 959 * Reads the device MAC address from the EEPROM and stores the value. 960 * Since devices with two ports use the same EEPROM, we increment the 961 * last bit in the MAC address for the second port. 962 **/ 963 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 964 { 965 u32 rar_high; 966 u32 rar_low; 967 u16 i; 968 969 rar_high = E1000_READ_REG(hw, E1000_RAH(0)); 970 rar_low = E1000_READ_REG(hw, E1000_RAL(0)); 971 972 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 973 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 974 975 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 976 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 977 978 for (i = 0; i < ETH_ADDR_LEN; i++) 979 hw->mac.addr[i] = hw->mac.perm_addr[i]; 980 981 return E1000_SUCCESS; 982 } 983 984 /** 985 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum 986 * @hw: pointer to the HW structure 987 * 988 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 989 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 990 **/ 991 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) 992 { 993 s32 ret_val = E1000_SUCCESS; 994 u16 checksum = 0; 995 u16 i, nvm_data; 996 997 DEBUGFUNC("e1000_validate_nvm_checksum_generic"); 998 999 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 1000 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1001 if (ret_val) { 1002 DEBUGOUT("NVM Read Error\n"); 1003 goto out; 1004 } 1005 checksum += nvm_data; 1006 } 1007 1008 if (checksum != (u16) NVM_SUM) { 1009 DEBUGOUT("NVM Checksum Invalid\n"); 1010 ret_val = -E1000_ERR_NVM; 1011 goto out; 1012 } 1013 1014 out: 1015 return ret_val; 1016 } 1017 1018 /** 1019 * e1000_update_nvm_checksum_generic - Update EEPROM checksum 1020 * @hw: pointer to the HW structure 1021 * 1022 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 1023 * up to the checksum. Then calculates the EEPROM checksum and writes the 1024 * value to the EEPROM. 1025 **/ 1026 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) 1027 { 1028 s32 ret_val; 1029 u16 checksum = 0; 1030 u16 i, nvm_data; 1031 1032 DEBUGFUNC("e1000_update_nvm_checksum"); 1033 1034 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 1035 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1036 if (ret_val) { 1037 DEBUGOUT("NVM Read Error while updating checksum.\n"); 1038 goto out; 1039 } 1040 checksum += nvm_data; 1041 } 1042 checksum = (u16) NVM_SUM - checksum; 1043 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 1044 if (ret_val) 1045 DEBUGOUT("NVM Write Error while updating checksum.\n"); 1046 1047 out: 1048 return ret_val; 1049 } 1050 1051 /** 1052 * e1000_reload_nvm_generic - Reloads EEPROM 1053 * @hw: pointer to the HW structure 1054 * 1055 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 1056 * extended control register. 1057 **/ 1058 static void e1000_reload_nvm_generic(struct e1000_hw *hw) 1059 { 1060 u32 ctrl_ext; 1061 1062 DEBUGFUNC("e1000_reload_nvm_generic"); 1063 1064 usec_delay(10); 1065 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1066 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1067 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1068 E1000_WRITE_FLUSH(hw); 1069 } 1070 1071