1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) - lem-class legacy devices */ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 98 99 /* Intel(R) - em-class devices */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 197 /* required last entry */ 198 PVID_END 199 }; 200 201 static pci_vendor_info_t igb_vendor_info_array[] = 202 { 203 /* Intel(R) - igb-class devices */ 204 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 205 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 206 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 207 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 208 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 209 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 210 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 211 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 212 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 213 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 214 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 215 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 216 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 217 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 218 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 219 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 220 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 221 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 222 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 226 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 227 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 230 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 231 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 232 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 233 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 235 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 238 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 239 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 240 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 241 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 242 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 244 /* required last entry */ 245 PVID_END 246 }; 247 248 /********************************************************************* 249 * Function prototypes 250 *********************************************************************/ 251 static void *em_register(device_t); 252 static void *igb_register(device_t); 253 static int em_if_attach_pre(if_ctx_t); 254 static int em_if_attach_post(if_ctx_t); 255 static int em_if_detach(if_ctx_t); 256 static int em_if_shutdown(if_ctx_t); 257 static int em_if_suspend(if_ctx_t); 258 static int em_if_resume(if_ctx_t); 259 260 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 261 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 262 static void em_if_queues_free(if_ctx_t); 263 264 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 265 static void em_if_init(if_ctx_t); 266 static void em_if_stop(if_ctx_t); 267 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 268 static int em_if_media_change(if_ctx_t); 269 static int em_if_mtu_set(if_ctx_t, uint32_t); 270 static void em_if_timer(if_ctx_t, uint16_t); 271 static void em_if_vlan_register(if_ctx_t, u16); 272 static void em_if_vlan_unregister(if_ctx_t, u16); 273 static void em_if_watchdog_reset(if_ctx_t); 274 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 275 276 static void em_identify_hardware(if_ctx_t); 277 static int em_allocate_pci_resources(if_ctx_t); 278 static void em_free_pci_resources(if_ctx_t); 279 static void em_reset(if_ctx_t); 280 static int em_setup_interface(if_ctx_t); 281 static int em_setup_msix(if_ctx_t); 282 283 static void em_initialize_transmit_unit(if_ctx_t); 284 static void em_initialize_receive_unit(if_ctx_t); 285 286 static void em_if_intr_enable(if_ctx_t); 287 static void em_if_intr_disable(if_ctx_t); 288 static void igb_if_intr_enable(if_ctx_t); 289 static void igb_if_intr_disable(if_ctx_t); 290 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 291 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 292 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 293 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 294 static void em_if_multi_set(if_ctx_t); 295 static void em_if_update_admin_status(if_ctx_t); 296 static void em_if_debug(if_ctx_t); 297 static void em_update_stats_counters(struct e1000_softc *); 298 static void em_add_hw_stats(struct e1000_softc *); 299 static int em_if_set_promisc(if_ctx_t, int); 300 static bool em_if_vlan_filter_capable(if_ctx_t); 301 static bool em_if_vlan_filter_used(if_ctx_t); 302 static void em_if_vlan_filter_enable(struct e1000_softc *); 303 static void em_if_vlan_filter_disable(struct e1000_softc *); 304 static void em_if_vlan_filter_write(struct e1000_softc *); 305 static void em_setup_vlan_hw_support(if_ctx_t ctx); 306 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 307 static void em_print_nvm_info(struct e1000_softc *); 308 static void em_fw_version_locked(if_ctx_t); 309 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 310 static void em_print_fw_version(struct e1000_softc *); 311 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 312 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 313 static int em_get_rs(SYSCTL_HANDLER_ARGS); 314 static void em_print_debug_info(struct e1000_softc *); 315 static int em_is_valid_ether_addr(u8 *); 316 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 317 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 318 const char *, struct em_int_delay_info *, int, int); 319 /* Management and WOL Support */ 320 static void em_init_manageability(struct e1000_softc *); 321 static void em_release_manageability(struct e1000_softc *); 322 static void em_get_hw_control(struct e1000_softc *); 323 static void em_release_hw_control(struct e1000_softc *); 324 static void em_get_wakeup(if_ctx_t); 325 static void em_enable_wakeup(if_ctx_t); 326 static int em_enable_phy_wakeup(struct e1000_softc *); 327 static void em_disable_aspm(struct e1000_softc *); 328 329 int em_intr(void *); 330 331 /* MSI-X handlers */ 332 static int em_if_msix_intr_assign(if_ctx_t, int); 333 static int em_msix_link(void *); 334 static void em_handle_link(void *); 335 336 static void em_enable_vectors_82574(if_ctx_t); 337 338 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 339 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 340 static void em_if_led_func(if_ctx_t, int); 341 342 static int em_get_regs(SYSCTL_HANDLER_ARGS); 343 344 static void lem_smartspeed(struct e1000_softc *); 345 static void igb_configure_queues(struct e1000_softc *); 346 347 348 /********************************************************************* 349 * FreeBSD Device Interface Entry Points 350 *********************************************************************/ 351 static device_method_t em_methods[] = { 352 /* Device interface */ 353 DEVMETHOD(device_register, em_register), 354 DEVMETHOD(device_probe, iflib_device_probe), 355 DEVMETHOD(device_attach, iflib_device_attach), 356 DEVMETHOD(device_detach, iflib_device_detach), 357 DEVMETHOD(device_shutdown, iflib_device_shutdown), 358 DEVMETHOD(device_suspend, iflib_device_suspend), 359 DEVMETHOD(device_resume, iflib_device_resume), 360 DEVMETHOD_END 361 }; 362 363 static device_method_t igb_methods[] = { 364 /* Device interface */ 365 DEVMETHOD(device_register, igb_register), 366 DEVMETHOD(device_probe, iflib_device_probe), 367 DEVMETHOD(device_attach, iflib_device_attach), 368 DEVMETHOD(device_detach, iflib_device_detach), 369 DEVMETHOD(device_shutdown, iflib_device_shutdown), 370 DEVMETHOD(device_suspend, iflib_device_suspend), 371 DEVMETHOD(device_resume, iflib_device_resume), 372 DEVMETHOD_END 373 }; 374 375 376 static driver_t em_driver = { 377 "em", em_methods, sizeof(struct e1000_softc), 378 }; 379 380 DRIVER_MODULE(em, pci, em_driver, 0, 0); 381 382 MODULE_DEPEND(em, pci, 1, 1, 1); 383 MODULE_DEPEND(em, ether, 1, 1, 1); 384 MODULE_DEPEND(em, iflib, 1, 1, 1); 385 386 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 387 388 static driver_t igb_driver = { 389 "igb", igb_methods, sizeof(struct e1000_softc), 390 }; 391 392 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 393 394 MODULE_DEPEND(igb, pci, 1, 1, 1); 395 MODULE_DEPEND(igb, ether, 1, 1, 1); 396 MODULE_DEPEND(igb, iflib, 1, 1, 1); 397 398 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 399 400 static device_method_t em_if_methods[] = { 401 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 402 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 403 DEVMETHOD(ifdi_detach, em_if_detach), 404 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 405 DEVMETHOD(ifdi_suspend, em_if_suspend), 406 DEVMETHOD(ifdi_resume, em_if_resume), 407 DEVMETHOD(ifdi_init, em_if_init), 408 DEVMETHOD(ifdi_stop, em_if_stop), 409 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 410 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 411 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 412 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 413 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 414 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 415 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 416 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 417 DEVMETHOD(ifdi_media_status, em_if_media_status), 418 DEVMETHOD(ifdi_media_change, em_if_media_change), 419 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 420 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 421 DEVMETHOD(ifdi_timer, em_if_timer), 422 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 423 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 424 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 425 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 426 DEVMETHOD(ifdi_led_func, em_if_led_func), 427 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 428 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 429 DEVMETHOD(ifdi_debug, em_if_debug), 430 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 431 DEVMETHOD_END 432 }; 433 434 static driver_t em_if_driver = { 435 "em_if", em_if_methods, sizeof(struct e1000_softc) 436 }; 437 438 static device_method_t igb_if_methods[] = { 439 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 440 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 441 DEVMETHOD(ifdi_detach, em_if_detach), 442 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 443 DEVMETHOD(ifdi_suspend, em_if_suspend), 444 DEVMETHOD(ifdi_resume, em_if_resume), 445 DEVMETHOD(ifdi_init, em_if_init), 446 DEVMETHOD(ifdi_stop, em_if_stop), 447 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 448 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 449 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 450 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 451 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 452 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 453 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 454 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 455 DEVMETHOD(ifdi_media_status, em_if_media_status), 456 DEVMETHOD(ifdi_media_change, em_if_media_change), 457 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 458 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 459 DEVMETHOD(ifdi_timer, em_if_timer), 460 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 461 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 462 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 463 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 464 DEVMETHOD(ifdi_led_func, em_if_led_func), 465 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 466 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 467 DEVMETHOD(ifdi_debug, em_if_debug), 468 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 469 DEVMETHOD_END 470 }; 471 472 static driver_t igb_if_driver = { 473 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 474 }; 475 476 /********************************************************************* 477 * Tunable default values. 478 *********************************************************************/ 479 480 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 481 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 482 483 #define MAX_INTS_PER_SEC 8000 484 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 485 486 /* Allow common code without TSO */ 487 #ifndef CSUM_TSO 488 #define CSUM_TSO 0 489 #endif 490 491 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 492 "EM driver parameters"); 493 494 static int em_disable_crc_stripping = 0; 495 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 496 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 497 498 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 499 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 500 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 501 0, "Default transmit interrupt delay in usecs"); 502 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 503 0, "Default receive interrupt delay in usecs"); 504 505 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 506 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 507 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 508 &em_tx_abs_int_delay_dflt, 0, 509 "Default transmit interrupt delay limit in usecs"); 510 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 511 &em_rx_abs_int_delay_dflt, 0, 512 "Default receive interrupt delay limit in usecs"); 513 514 static int em_smart_pwr_down = false; 515 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 516 0, "Set to true to leave smart power down enabled on newer adapters"); 517 518 /* Controls whether promiscuous also shows bad packets */ 519 static int em_debug_sbp = false; 520 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 521 "Show bad packets in promiscuous mode"); 522 523 /* How many packets rxeof tries to clean at a time */ 524 static int em_rx_process_limit = 100; 525 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 526 &em_rx_process_limit, 0, 527 "Maximum number of received packets to process " 528 "at a time, -1 means unlimited"); 529 530 /* Energy efficient ethernet - default to OFF */ 531 static int eee_setting = 1; 532 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 533 "Enable Energy Efficient Ethernet"); 534 535 /* 536 ** Tuneable Interrupt rate 537 */ 538 static int em_max_interrupt_rate = 8000; 539 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 540 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 541 542 543 544 /* Global used in WOL setup with multiport cards */ 545 static int global_quad_port_a = 0; 546 547 extern struct if_txrx igb_txrx; 548 extern struct if_txrx em_txrx; 549 extern struct if_txrx lem_txrx; 550 551 static struct if_shared_ctx em_sctx_init = { 552 .isc_magic = IFLIB_MAGIC, 553 .isc_q_align = PAGE_SIZE, 554 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 555 .isc_tx_maxsegsize = PAGE_SIZE, 556 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 557 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 558 .isc_rx_maxsize = MJUM9BYTES, 559 .isc_rx_nsegments = 1, 560 .isc_rx_maxsegsize = MJUM9BYTES, 561 .isc_nfl = 1, 562 .isc_nrxqs = 1, 563 .isc_ntxqs = 1, 564 .isc_admin_intrcnt = 1, 565 .isc_vendor_info = em_vendor_info_array, 566 .isc_driver_version = em_driver_version, 567 .isc_driver = &em_if_driver, 568 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 569 570 .isc_nrxd_min = {EM_MIN_RXD}, 571 .isc_ntxd_min = {EM_MIN_TXD}, 572 .isc_nrxd_max = {EM_MAX_RXD}, 573 .isc_ntxd_max = {EM_MAX_TXD}, 574 .isc_nrxd_default = {EM_DEFAULT_RXD}, 575 .isc_ntxd_default = {EM_DEFAULT_TXD}, 576 }; 577 578 static struct if_shared_ctx igb_sctx_init = { 579 .isc_magic = IFLIB_MAGIC, 580 .isc_q_align = PAGE_SIZE, 581 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 582 .isc_tx_maxsegsize = PAGE_SIZE, 583 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 584 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 585 .isc_rx_maxsize = MJUM9BYTES, 586 .isc_rx_nsegments = 1, 587 .isc_rx_maxsegsize = MJUM9BYTES, 588 .isc_nfl = 1, 589 .isc_nrxqs = 1, 590 .isc_ntxqs = 1, 591 .isc_admin_intrcnt = 1, 592 .isc_vendor_info = igb_vendor_info_array, 593 .isc_driver_version = em_driver_version, 594 .isc_driver = &igb_if_driver, 595 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 596 597 .isc_nrxd_min = {EM_MIN_RXD}, 598 .isc_ntxd_min = {EM_MIN_TXD}, 599 .isc_nrxd_max = {IGB_MAX_RXD}, 600 .isc_ntxd_max = {IGB_MAX_TXD}, 601 .isc_nrxd_default = {EM_DEFAULT_RXD}, 602 .isc_ntxd_default = {EM_DEFAULT_TXD}, 603 }; 604 605 /***************************************************************** 606 * 607 * Dump Registers 608 * 609 ****************************************************************/ 610 #define IGB_REGS_LEN 739 611 612 static int em_get_regs(SYSCTL_HANDLER_ARGS) 613 { 614 struct e1000_softc *sc = (struct e1000_softc *)arg1; 615 struct e1000_hw *hw = &sc->hw; 616 struct sbuf *sb; 617 u32 *regs_buff; 618 int rc; 619 620 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 621 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 622 623 rc = sysctl_wire_old_buffer(req, 0); 624 MPASS(rc == 0); 625 if (rc != 0) { 626 free(regs_buff, M_DEVBUF); 627 return (rc); 628 } 629 630 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 631 MPASS(sb != NULL); 632 if (sb == NULL) { 633 free(regs_buff, M_DEVBUF); 634 return (ENOMEM); 635 } 636 637 /* General Registers */ 638 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 639 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 640 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 641 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 642 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 643 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 644 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 645 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 646 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 647 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 648 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 649 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 650 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 651 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 652 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 653 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 654 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 655 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 656 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 657 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 658 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 659 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 660 661 sbuf_printf(sb, "General Registers\n"); 662 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 663 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 664 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 665 666 sbuf_printf(sb, "Interrupt Registers\n"); 667 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 668 669 sbuf_printf(sb, "RX Registers\n"); 670 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 671 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 672 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 673 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 674 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 675 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 676 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 677 678 sbuf_printf(sb, "TX Registers\n"); 679 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 680 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 681 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 682 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 683 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 684 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 685 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 686 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 687 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 688 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 689 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 690 691 free(regs_buff, M_DEVBUF); 692 693 #ifdef DUMP_DESCS 694 { 695 if_softc_ctx_t scctx = sc->shared; 696 struct rx_ring *rxr = &rx_que->rxr; 697 struct tx_ring *txr = &tx_que->txr; 698 int ntxd = scctx->isc_ntxd[0]; 699 int nrxd = scctx->isc_nrxd[0]; 700 int j; 701 702 for (j = 0; j < nrxd; j++) { 703 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 704 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 705 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 706 } 707 708 for (j = 0; j < min(ntxd, 256); j++) { 709 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 710 711 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 712 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 713 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 714 715 } 716 } 717 #endif 718 719 rc = sbuf_finish(sb); 720 sbuf_delete(sb); 721 return(rc); 722 } 723 724 static void * 725 em_register(device_t dev) 726 { 727 return (&em_sctx_init); 728 } 729 730 static void * 731 igb_register(device_t dev) 732 { 733 return (&igb_sctx_init); 734 } 735 736 static int 737 em_set_num_queues(if_ctx_t ctx) 738 { 739 struct e1000_softc *sc = iflib_get_softc(ctx); 740 int maxqueues; 741 742 /* Sanity check based on HW */ 743 switch (sc->hw.mac.type) { 744 case e1000_82576: 745 case e1000_82580: 746 case e1000_i350: 747 case e1000_i354: 748 maxqueues = 8; 749 break; 750 case e1000_i210: 751 case e1000_82575: 752 maxqueues = 4; 753 break; 754 case e1000_i211: 755 case e1000_82574: 756 maxqueues = 2; 757 break; 758 default: 759 maxqueues = 1; 760 break; 761 } 762 763 return (maxqueues); 764 } 765 766 #define LEM_CAPS \ 767 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 768 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 769 770 #define EM_CAPS \ 771 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 772 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 773 IFCAP_LRO | IFCAP_VLAN_HWTSO 774 775 #define IGB_CAPS \ 776 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 777 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 778 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 779 IFCAP_TSO6 780 781 /********************************************************************* 782 * Device initialization routine 783 * 784 * The attach entry point is called when the driver is being loaded. 785 * This routine identifies the type of hardware, allocates all resources 786 * and initializes the hardware. 787 * 788 * return 0 on success, positive on failure 789 *********************************************************************/ 790 static int 791 em_if_attach_pre(if_ctx_t ctx) 792 { 793 struct e1000_softc *sc; 794 if_softc_ctx_t scctx; 795 device_t dev; 796 struct e1000_hw *hw; 797 struct sysctl_oid_list *child; 798 struct sysctl_ctx_list *ctx_list; 799 int error = 0; 800 801 INIT_DEBUGOUT("em_if_attach_pre: begin"); 802 dev = iflib_get_dev(ctx); 803 sc = iflib_get_softc(ctx); 804 805 sc->ctx = sc->osdep.ctx = ctx; 806 sc->dev = sc->osdep.dev = dev; 807 scctx = sc->shared = iflib_get_softc_ctx(ctx); 808 sc->media = iflib_get_media(ctx); 809 hw = &sc->hw; 810 811 sc->tx_process_limit = scctx->isc_ntxd[0]; 812 813 /* Determine hardware and mac info */ 814 em_identify_hardware(ctx); 815 816 /* SYSCTL stuff */ 817 ctx_list = device_get_sysctl_ctx(dev); 818 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 819 820 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 821 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 822 em_sysctl_nvm_info, "I", "NVM Information"); 823 824 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 825 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 826 em_sysctl_print_fw_version, "A", 827 "Prints FW/NVM Versions"); 828 829 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 830 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 831 em_sysctl_debug_info, "I", "Debug Information"); 832 833 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 834 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 835 em_set_flowcntl, "I", "Flow Control"); 836 837 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 838 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 839 em_get_regs, "A", "Dump Registers"); 840 841 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 842 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 843 em_get_rs, "I", "Dump RS indexes"); 844 845 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 846 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 847 if (bootverbose) 848 device_printf(dev, "attach_pre capping queues at %d\n", 849 scctx->isc_ntxqsets_max); 850 851 if (hw->mac.type >= igb_mac_min) { 852 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 853 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 854 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 855 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 856 scctx->isc_txrx = &igb_txrx; 857 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 858 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 859 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 860 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 861 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 862 CSUM_IP6_TCP | CSUM_IP6_UDP; 863 if (hw->mac.type != e1000_82575) 864 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 865 /* 866 ** Some new devices, as with ixgbe, now may 867 ** use a different BAR, so we need to keep 868 ** track of which is used. 869 */ 870 scctx->isc_msix_bar = pci_msix_table_bar(dev); 871 } else if (hw->mac.type >= em_mac_min) { 872 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 873 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 874 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 875 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 876 scctx->isc_txrx = &em_txrx; 877 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 878 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 879 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 880 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 881 /* 882 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 883 * by default as we don't have workarounds for all associated 884 * silicon errata. E. g., with several MACs such as 82573E, 885 * TSO only works at Gigabit speed and otherwise can cause the 886 * hardware to hang (which also would be next to impossible to 887 * work around given that already queued TSO-using descriptors 888 * would need to be flushed and vlan(4) reconfigured at runtime 889 * in case of a link speed change). Moreover, MACs like 82579 890 * still can hang at Gigabit even with all publicly documented 891 * TSO workarounds implemented. Generally, the penality of 892 * these workarounds is rather high and may involve copying 893 * mbuf data around so advantages of TSO lapse. Still, TSO may 894 * work for a few MACs of this class - at least when sticking 895 * with Gigabit - in which case users may enable TSO manually. 896 */ 897 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 898 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 899 /* 900 * We support MSI-X with 82574 only, but indicate to iflib(4) 901 * that it shall give MSI at least a try with other devices. 902 */ 903 if (hw->mac.type == e1000_82574) { 904 scctx->isc_msix_bar = pci_msix_table_bar(dev); 905 } else { 906 scctx->isc_msix_bar = -1; 907 scctx->isc_disable_msix = 1; 908 } 909 } else { 910 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 911 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 912 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 913 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 914 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 915 scctx->isc_txrx = &lem_txrx; 916 scctx->isc_capabilities = LEM_CAPS; 917 if (hw->mac.type < e1000_82543) 918 scctx->isc_capabilities &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 919 /* 82541ER doesn't do HW tagging */ 920 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM) 921 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 922 /* INTx only */ 923 scctx->isc_msix_bar = 0; 924 scctx->isc_capenable = scctx->isc_capabilities; 925 } 926 927 /* Setup PCI resources */ 928 if (em_allocate_pci_resources(ctx)) { 929 device_printf(dev, "Allocation of PCI resources failed\n"); 930 error = ENXIO; 931 goto err_pci; 932 } 933 934 /* 935 ** For ICH8 and family we need to 936 ** map the flash memory, and this 937 ** must happen after the MAC is 938 ** identified 939 */ 940 if ((hw->mac.type == e1000_ich8lan) || 941 (hw->mac.type == e1000_ich9lan) || 942 (hw->mac.type == e1000_ich10lan) || 943 (hw->mac.type == e1000_pchlan) || 944 (hw->mac.type == e1000_pch2lan) || 945 (hw->mac.type == e1000_pch_lpt)) { 946 int rid = EM_BAR_TYPE_FLASH; 947 sc->flash = bus_alloc_resource_any(dev, 948 SYS_RES_MEMORY, &rid, RF_ACTIVE); 949 if (sc->flash == NULL) { 950 device_printf(dev, "Mapping of Flash failed\n"); 951 error = ENXIO; 952 goto err_pci; 953 } 954 /* This is used in the shared code */ 955 hw->flash_address = (u8 *)sc->flash; 956 sc->osdep.flash_bus_space_tag = 957 rman_get_bustag(sc->flash); 958 sc->osdep.flash_bus_space_handle = 959 rman_get_bushandle(sc->flash); 960 } 961 /* 962 ** In the new SPT device flash is not a 963 ** separate BAR, rather it is also in BAR0, 964 ** so use the same tag and an offset handle for the 965 ** FLASH read/write macros in the shared code. 966 */ 967 else if (hw->mac.type >= e1000_pch_spt) { 968 sc->osdep.flash_bus_space_tag = 969 sc->osdep.mem_bus_space_tag; 970 sc->osdep.flash_bus_space_handle = 971 sc->osdep.mem_bus_space_handle 972 + E1000_FLASH_BASE_ADDR; 973 } 974 975 /* Do Shared Code initialization */ 976 error = e1000_setup_init_funcs(hw, true); 977 if (error) { 978 device_printf(dev, "Setup of Shared code failed, error %d\n", 979 error); 980 error = ENXIO; 981 goto err_pci; 982 } 983 984 em_setup_msix(ctx); 985 e1000_get_bus_info(hw); 986 987 /* Set up some sysctls for the tunable interrupt delays */ 988 em_add_int_delay_sysctl(sc, "rx_int_delay", 989 "receive interrupt delay in usecs", &sc->rx_int_delay, 990 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 991 em_add_int_delay_sysctl(sc, "tx_int_delay", 992 "transmit interrupt delay in usecs", &sc->tx_int_delay, 993 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 994 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 995 "receive interrupt delay limit in usecs", 996 &sc->rx_abs_int_delay, 997 E1000_REGISTER(hw, E1000_RADV), 998 em_rx_abs_int_delay_dflt); 999 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1000 "transmit interrupt delay limit in usecs", 1001 &sc->tx_abs_int_delay, 1002 E1000_REGISTER(hw, E1000_TADV), 1003 em_tx_abs_int_delay_dflt); 1004 em_add_int_delay_sysctl(sc, "itr", 1005 "interrupt delay limit in usecs/4", 1006 &sc->tx_itr, 1007 E1000_REGISTER(hw, E1000_ITR), 1008 DEFAULT_ITR); 1009 1010 hw->mac.autoneg = DO_AUTO_NEG; 1011 hw->phy.autoneg_wait_to_complete = false; 1012 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1013 1014 if (hw->mac.type < em_mac_min) { 1015 e1000_init_script_state_82541(hw, true); 1016 e1000_set_tbi_compatibility_82543(hw, true); 1017 } 1018 /* Copper options */ 1019 if (hw->phy.media_type == e1000_media_type_copper) { 1020 hw->phy.mdix = AUTO_ALL_MODES; 1021 hw->phy.disable_polarity_correction = false; 1022 hw->phy.ms_type = EM_MASTER_SLAVE; 1023 } 1024 1025 /* 1026 * Set the frame limits assuming 1027 * standard ethernet sized frames. 1028 */ 1029 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1030 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1031 1032 /* 1033 * This controls when hardware reports transmit completion 1034 * status. 1035 */ 1036 hw->mac.report_tx_early = 1; 1037 1038 /* Allocate multicast array memory. */ 1039 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1040 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1041 if (sc->mta == NULL) { 1042 device_printf(dev, "Can not allocate multicast setup array\n"); 1043 error = ENOMEM; 1044 goto err_late; 1045 } 1046 1047 /* Check SOL/IDER usage */ 1048 if (e1000_check_reset_block(hw)) 1049 device_printf(dev, "PHY reset is blocked" 1050 " due to SOL/IDER session.\n"); 1051 1052 /* Sysctl for setting Energy Efficient Ethernet */ 1053 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1054 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1055 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1056 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1057 1058 /* 1059 ** Start from a known state, this is 1060 ** important in reading the nvm and 1061 ** mac from that. 1062 */ 1063 e1000_reset_hw(hw); 1064 1065 /* Make sure we have a good EEPROM before we read from it */ 1066 if (e1000_validate_nvm_checksum(hw) < 0) { 1067 /* 1068 ** Some PCI-E parts fail the first check due to 1069 ** the link being in sleep state, call it again, 1070 ** if it fails a second time its a real issue. 1071 */ 1072 if (e1000_validate_nvm_checksum(hw) < 0) { 1073 device_printf(dev, 1074 "The EEPROM Checksum Is Not Valid\n"); 1075 error = EIO; 1076 goto err_late; 1077 } 1078 } 1079 1080 /* Copy the permanent MAC address out of the EEPROM */ 1081 if (e1000_read_mac_addr(hw) < 0) { 1082 device_printf(dev, "EEPROM read error while reading MAC" 1083 " address\n"); 1084 error = EIO; 1085 goto err_late; 1086 } 1087 1088 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1089 if (sc->vf_ifp) { 1090 ether_gen_addr(iflib_get_ifp(ctx), 1091 (struct ether_addr *)hw->mac.addr); 1092 } else { 1093 device_printf(dev, "Invalid MAC address\n"); 1094 error = EIO; 1095 goto err_late; 1096 } 1097 } 1098 1099 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1100 em_fw_version_locked(ctx); 1101 1102 em_print_fw_version(sc); 1103 1104 /* Disable ULP support */ 1105 e1000_disable_ulp_lpt_lp(hw, true); 1106 1107 /* 1108 * Get Wake-on-Lan and Management info for later use 1109 */ 1110 em_get_wakeup(ctx); 1111 1112 /* Enable only WOL MAGIC by default */ 1113 scctx->isc_capenable &= ~IFCAP_WOL; 1114 if (sc->wol != 0) 1115 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1116 1117 iflib_set_mac(ctx, hw->mac.addr); 1118 1119 return (0); 1120 1121 err_late: 1122 em_release_hw_control(sc); 1123 err_pci: 1124 em_free_pci_resources(ctx); 1125 free(sc->mta, M_DEVBUF); 1126 1127 return (error); 1128 } 1129 1130 static int 1131 em_if_attach_post(if_ctx_t ctx) 1132 { 1133 struct e1000_softc *sc = iflib_get_softc(ctx); 1134 struct e1000_hw *hw = &sc->hw; 1135 int error = 0; 1136 1137 /* Setup OS specific network interface */ 1138 error = em_setup_interface(ctx); 1139 if (error != 0) { 1140 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1141 goto err_late; 1142 } 1143 1144 em_reset(ctx); 1145 1146 /* Initialize statistics */ 1147 em_update_stats_counters(sc); 1148 hw->mac.get_link_status = 1; 1149 em_if_update_admin_status(ctx); 1150 em_add_hw_stats(sc); 1151 1152 /* Non-AMT based hardware can now take control from firmware */ 1153 if (sc->has_manage && !sc->has_amt) 1154 em_get_hw_control(sc); 1155 1156 INIT_DEBUGOUT("em_if_attach_post: end"); 1157 1158 return (0); 1159 1160 err_late: 1161 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1162 return (error); 1163 } 1164 1165 /********************************************************************* 1166 * Device removal routine 1167 * 1168 * The detach entry point is called when the driver is being removed. 1169 * This routine stops the adapter and deallocates all the resources 1170 * that were allocated for driver operation. 1171 * 1172 * return 0 on success, positive on failure 1173 *********************************************************************/ 1174 static int 1175 em_if_detach(if_ctx_t ctx) 1176 { 1177 struct e1000_softc *sc = iflib_get_softc(ctx); 1178 1179 INIT_DEBUGOUT("em_if_detach: begin"); 1180 1181 e1000_phy_hw_reset(&sc->hw); 1182 1183 em_release_manageability(sc); 1184 em_release_hw_control(sc); 1185 em_free_pci_resources(ctx); 1186 free(sc->mta, M_DEVBUF); 1187 sc->mta = NULL; 1188 1189 return (0); 1190 } 1191 1192 /********************************************************************* 1193 * 1194 * Shutdown entry point 1195 * 1196 **********************************************************************/ 1197 1198 static int 1199 em_if_shutdown(if_ctx_t ctx) 1200 { 1201 return em_if_suspend(ctx); 1202 } 1203 1204 /* 1205 * Suspend/resume device methods. 1206 */ 1207 static int 1208 em_if_suspend(if_ctx_t ctx) 1209 { 1210 struct e1000_softc *sc = iflib_get_softc(ctx); 1211 1212 em_release_manageability(sc); 1213 em_release_hw_control(sc); 1214 em_enable_wakeup(ctx); 1215 return (0); 1216 } 1217 1218 static int 1219 em_if_resume(if_ctx_t ctx) 1220 { 1221 struct e1000_softc *sc = iflib_get_softc(ctx); 1222 1223 if (sc->hw.mac.type == e1000_pch2lan) 1224 e1000_resume_workarounds_pchlan(&sc->hw); 1225 em_if_init(ctx); 1226 em_init_manageability(sc); 1227 1228 return(0); 1229 } 1230 1231 static int 1232 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1233 { 1234 int max_frame_size; 1235 struct e1000_softc *sc = iflib_get_softc(ctx); 1236 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1237 1238 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1239 1240 switch (sc->hw.mac.type) { 1241 case e1000_82571: 1242 case e1000_82572: 1243 case e1000_ich9lan: 1244 case e1000_ich10lan: 1245 case e1000_pch2lan: 1246 case e1000_pch_lpt: 1247 case e1000_pch_spt: 1248 case e1000_pch_cnp: 1249 case e1000_pch_tgp: 1250 case e1000_pch_adp: 1251 case e1000_pch_mtp: 1252 case e1000_82574: 1253 case e1000_82583: 1254 case e1000_80003es2lan: 1255 /* 9K Jumbo Frame size */ 1256 max_frame_size = 9234; 1257 break; 1258 case e1000_pchlan: 1259 max_frame_size = 4096; 1260 break; 1261 case e1000_82542: 1262 case e1000_ich8lan: 1263 /* Adapters that do not support jumbo frames */ 1264 max_frame_size = ETHER_MAX_LEN; 1265 break; 1266 default: 1267 if (sc->hw.mac.type >= igb_mac_min) 1268 max_frame_size = 9234; 1269 else /* lem */ 1270 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1271 } 1272 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1273 return (EINVAL); 1274 } 1275 1276 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1277 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1278 return (0); 1279 } 1280 1281 /********************************************************************* 1282 * Init entry point 1283 * 1284 * This routine is used in two ways. It is used by the stack as 1285 * init entry point in network interface structure. It is also used 1286 * by the driver as a hw/sw initialization routine to get to a 1287 * consistent state. 1288 * 1289 **********************************************************************/ 1290 static void 1291 em_if_init(if_ctx_t ctx) 1292 { 1293 struct e1000_softc *sc = iflib_get_softc(ctx); 1294 if_softc_ctx_t scctx = sc->shared; 1295 if_t ifp = iflib_get_ifp(ctx); 1296 struct em_tx_queue *tx_que; 1297 int i; 1298 1299 INIT_DEBUGOUT("em_if_init: begin"); 1300 1301 /* Get the latest mac address, User can use a LAA */ 1302 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1303 ETHER_ADDR_LEN); 1304 1305 /* Put the address into the Receive Address Array */ 1306 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1307 1308 /* 1309 * With the 82571 adapter, RAR[0] may be overwritten 1310 * when the other port is reset, we make a duplicate 1311 * in RAR[14] for that eventuality, this assures 1312 * the interface continues to function. 1313 */ 1314 if (sc->hw.mac.type == e1000_82571) { 1315 e1000_set_laa_state_82571(&sc->hw, true); 1316 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1317 E1000_RAR_ENTRIES - 1); 1318 } 1319 1320 1321 /* Initialize the hardware */ 1322 em_reset(ctx); 1323 em_if_update_admin_status(ctx); 1324 1325 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1326 struct tx_ring *txr = &tx_que->txr; 1327 1328 txr->tx_rs_cidx = txr->tx_rs_pidx; 1329 1330 /* Initialize the last processed descriptor to be the end of 1331 * the ring, rather than the start, so that we avoid an 1332 * off-by-one error when calculating how many descriptors are 1333 * done in the credits_update function. 1334 */ 1335 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1336 } 1337 1338 /* Setup VLAN support, basic and offload if available */ 1339 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1340 1341 /* Clear bad data from Rx FIFOs */ 1342 if (sc->hw.mac.type >= igb_mac_min) 1343 e1000_rx_fifo_flush_base(&sc->hw); 1344 1345 /* Configure for OS presence */ 1346 em_init_manageability(sc); 1347 1348 /* Prepare transmit descriptors and buffers */ 1349 em_initialize_transmit_unit(ctx); 1350 1351 /* Setup Multicast table */ 1352 em_if_multi_set(ctx); 1353 1354 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1355 em_initialize_receive_unit(ctx); 1356 1357 /* Set up VLAN support and filter */ 1358 em_setup_vlan_hw_support(ctx); 1359 1360 /* Don't lose promiscuous settings */ 1361 em_if_set_promisc(ctx, if_getflags(ifp)); 1362 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1363 1364 /* MSI-X configuration for 82574 */ 1365 if (sc->hw.mac.type == e1000_82574) { 1366 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1367 1368 tmp |= E1000_CTRL_EXT_PBA_CLR; 1369 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1370 /* Set the IVAR - interrupt vector routing. */ 1371 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1372 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1373 igb_configure_queues(sc); 1374 1375 /* this clears any pending interrupts */ 1376 E1000_READ_REG(&sc->hw, E1000_ICR); 1377 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1378 1379 /* AMT based hardware can now take control from firmware */ 1380 if (sc->has_manage && sc->has_amt) 1381 em_get_hw_control(sc); 1382 1383 /* Set Energy Efficient Ethernet */ 1384 if (sc->hw.mac.type >= igb_mac_min && 1385 sc->hw.phy.media_type == e1000_media_type_copper) { 1386 if (sc->hw.mac.type == e1000_i354) 1387 e1000_set_eee_i354(&sc->hw, true, true); 1388 else 1389 e1000_set_eee_i350(&sc->hw, true, true); 1390 } 1391 } 1392 1393 /********************************************************************* 1394 * 1395 * Fast Legacy/MSI Combined Interrupt Service routine 1396 * 1397 *********************************************************************/ 1398 int 1399 em_intr(void *arg) 1400 { 1401 struct e1000_softc *sc = arg; 1402 if_ctx_t ctx = sc->ctx; 1403 u32 reg_icr; 1404 1405 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1406 1407 /* Hot eject? */ 1408 if (reg_icr == 0xffffffff) 1409 return FILTER_STRAY; 1410 1411 /* Definitely not our interrupt. */ 1412 if (reg_icr == 0x0) 1413 return FILTER_STRAY; 1414 1415 /* 1416 * Starting with the 82571 chip, bit 31 should be used to 1417 * determine whether the interrupt belongs to us. 1418 */ 1419 if (sc->hw.mac.type >= e1000_82571 && 1420 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1421 return FILTER_STRAY; 1422 1423 /* 1424 * Only MSI-X interrupts have one-shot behavior by taking advantage 1425 * of the EIAC register. Thus, explicitly disable interrupts. This 1426 * also works around the MSI message reordering errata on certain 1427 * systems. 1428 */ 1429 IFDI_INTR_DISABLE(ctx); 1430 1431 /* Link status change */ 1432 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1433 em_handle_link(ctx); 1434 1435 if (reg_icr & E1000_ICR_RXO) 1436 sc->rx_overruns++; 1437 1438 return (FILTER_SCHEDULE_THREAD); 1439 } 1440 1441 static int 1442 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1443 { 1444 struct e1000_softc *sc = iflib_get_softc(ctx); 1445 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1446 1447 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1448 return (0); 1449 } 1450 1451 static int 1452 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1453 { 1454 struct e1000_softc *sc = iflib_get_softc(ctx); 1455 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1456 1457 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1458 return (0); 1459 } 1460 1461 static int 1462 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1463 { 1464 struct e1000_softc *sc = iflib_get_softc(ctx); 1465 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1466 1467 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1468 return (0); 1469 } 1470 1471 static int 1472 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1473 { 1474 struct e1000_softc *sc = iflib_get_softc(ctx); 1475 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1476 1477 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1478 return (0); 1479 } 1480 1481 /********************************************************************* 1482 * 1483 * MSI-X RX Interrupt Service routine 1484 * 1485 **********************************************************************/ 1486 static int 1487 em_msix_que(void *arg) 1488 { 1489 struct em_rx_queue *que = arg; 1490 1491 ++que->irqs; 1492 1493 return (FILTER_SCHEDULE_THREAD); 1494 } 1495 1496 /********************************************************************* 1497 * 1498 * MSI-X Link Fast Interrupt Service routine 1499 * 1500 **********************************************************************/ 1501 static int 1502 em_msix_link(void *arg) 1503 { 1504 struct e1000_softc *sc = arg; 1505 u32 reg_icr; 1506 1507 ++sc->link_irq; 1508 MPASS(sc->hw.back != NULL); 1509 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1510 1511 if (reg_icr & E1000_ICR_RXO) 1512 sc->rx_overruns++; 1513 1514 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1515 em_handle_link(sc->ctx); 1516 1517 /* Re-arm unconditionally */ 1518 if (sc->hw.mac.type >= igb_mac_min) { 1519 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1520 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1521 } else if (sc->hw.mac.type == e1000_82574) { 1522 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1523 E1000_IMS_OTHER); 1524 /* 1525 * Because we must read the ICR for this interrupt it may 1526 * clear other causes using autoclear, for this reason we 1527 * simply create a soft interrupt for all these vectors. 1528 */ 1529 if (reg_icr) 1530 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1531 } else 1532 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1533 1534 return (FILTER_HANDLED); 1535 } 1536 1537 static void 1538 em_handle_link(void *context) 1539 { 1540 if_ctx_t ctx = context; 1541 struct e1000_softc *sc = iflib_get_softc(ctx); 1542 1543 sc->hw.mac.get_link_status = 1; 1544 iflib_admin_intr_deferred(ctx); 1545 } 1546 1547 /********************************************************************* 1548 * 1549 * Media Ioctl callback 1550 * 1551 * This routine is called whenever the user queries the status of 1552 * the interface using ifconfig. 1553 * 1554 **********************************************************************/ 1555 static void 1556 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1557 { 1558 struct e1000_softc *sc = iflib_get_softc(ctx); 1559 u_char fiber_type = IFM_1000_SX; 1560 1561 INIT_DEBUGOUT("em_if_media_status: begin"); 1562 1563 iflib_admin_intr_deferred(ctx); 1564 1565 ifmr->ifm_status = IFM_AVALID; 1566 ifmr->ifm_active = IFM_ETHER; 1567 1568 if (!sc->link_active) { 1569 return; 1570 } 1571 1572 ifmr->ifm_status |= IFM_ACTIVE; 1573 1574 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1575 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1576 if (sc->hw.mac.type == e1000_82545) 1577 fiber_type = IFM_1000_LX; 1578 ifmr->ifm_active |= fiber_type | IFM_FDX; 1579 } else { 1580 switch (sc->link_speed) { 1581 case 10: 1582 ifmr->ifm_active |= IFM_10_T; 1583 break; 1584 case 100: 1585 ifmr->ifm_active |= IFM_100_TX; 1586 break; 1587 case 1000: 1588 ifmr->ifm_active |= IFM_1000_T; 1589 break; 1590 } 1591 if (sc->link_duplex == FULL_DUPLEX) 1592 ifmr->ifm_active |= IFM_FDX; 1593 else 1594 ifmr->ifm_active |= IFM_HDX; 1595 } 1596 } 1597 1598 /********************************************************************* 1599 * 1600 * Media Ioctl callback 1601 * 1602 * This routine is called when the user changes speed/duplex using 1603 * media/mediopt option with ifconfig. 1604 * 1605 **********************************************************************/ 1606 static int 1607 em_if_media_change(if_ctx_t ctx) 1608 { 1609 struct e1000_softc *sc = iflib_get_softc(ctx); 1610 struct ifmedia *ifm = iflib_get_media(ctx); 1611 1612 INIT_DEBUGOUT("em_if_media_change: begin"); 1613 1614 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1615 return (EINVAL); 1616 1617 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1618 case IFM_AUTO: 1619 sc->hw.mac.autoneg = DO_AUTO_NEG; 1620 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1621 break; 1622 case IFM_1000_LX: 1623 case IFM_1000_SX: 1624 case IFM_1000_T: 1625 sc->hw.mac.autoneg = DO_AUTO_NEG; 1626 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1627 break; 1628 case IFM_100_TX: 1629 sc->hw.mac.autoneg = false; 1630 sc->hw.phy.autoneg_advertised = 0; 1631 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1632 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1633 else 1634 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1635 break; 1636 case IFM_10_T: 1637 sc->hw.mac.autoneg = false; 1638 sc->hw.phy.autoneg_advertised = 0; 1639 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1640 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1641 else 1642 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1643 break; 1644 default: 1645 device_printf(sc->dev, "Unsupported media type\n"); 1646 } 1647 1648 em_if_init(ctx); 1649 1650 return (0); 1651 } 1652 1653 static int 1654 em_if_set_promisc(if_ctx_t ctx, int flags) 1655 { 1656 struct e1000_softc *sc = iflib_get_softc(ctx); 1657 if_t ifp = iflib_get_ifp(ctx); 1658 u32 reg_rctl; 1659 int mcnt = 0; 1660 1661 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1662 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1663 if (flags & IFF_ALLMULTI) 1664 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1665 else 1666 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1667 1668 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1669 reg_rctl &= (~E1000_RCTL_MPE); 1670 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1671 1672 if (flags & IFF_PROMISC) { 1673 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1674 em_if_vlan_filter_disable(sc); 1675 /* Turn this on if you want to see bad packets */ 1676 if (em_debug_sbp) 1677 reg_rctl |= E1000_RCTL_SBP; 1678 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1679 } else { 1680 if (flags & IFF_ALLMULTI) { 1681 reg_rctl |= E1000_RCTL_MPE; 1682 reg_rctl &= ~E1000_RCTL_UPE; 1683 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1684 } 1685 if (em_if_vlan_filter_used(ctx)) 1686 em_if_vlan_filter_enable(sc); 1687 } 1688 return (0); 1689 } 1690 1691 static u_int 1692 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1693 { 1694 u8 *mta = arg; 1695 1696 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1697 return (0); 1698 1699 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1700 1701 return (1); 1702 } 1703 1704 /********************************************************************* 1705 * Multicast Update 1706 * 1707 * This routine is called whenever multicast address list is updated. 1708 * 1709 **********************************************************************/ 1710 static void 1711 em_if_multi_set(if_ctx_t ctx) 1712 { 1713 struct e1000_softc *sc = iflib_get_softc(ctx); 1714 if_t ifp = iflib_get_ifp(ctx); 1715 u8 *mta; /* Multicast array memory */ 1716 u32 reg_rctl = 0; 1717 int mcnt = 0; 1718 1719 IOCTL_DEBUGOUT("em_set_multi: begin"); 1720 1721 mta = sc->mta; 1722 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1723 1724 if (sc->hw.mac.type == e1000_82542 && 1725 sc->hw.revision_id == E1000_REVISION_2) { 1726 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1727 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1728 e1000_pci_clear_mwi(&sc->hw); 1729 reg_rctl |= E1000_RCTL_RST; 1730 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1731 msec_delay(5); 1732 } 1733 1734 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1735 1736 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1737 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1738 1739 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1740 1741 if (if_getflags(ifp) & IFF_PROMISC) 1742 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1743 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1744 if_getflags(ifp) & IFF_ALLMULTI) { 1745 reg_rctl |= E1000_RCTL_MPE; 1746 reg_rctl &= ~E1000_RCTL_UPE; 1747 } else 1748 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1749 1750 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1751 1752 if (sc->hw.mac.type == e1000_82542 && 1753 sc->hw.revision_id == E1000_REVISION_2) { 1754 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1755 reg_rctl &= ~E1000_RCTL_RST; 1756 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1757 msec_delay(5); 1758 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1759 e1000_pci_set_mwi(&sc->hw); 1760 } 1761 } 1762 1763 /********************************************************************* 1764 * Timer routine 1765 * 1766 * This routine schedules em_if_update_admin_status() to check for 1767 * link status and to gather statistics as well as to perform some 1768 * controller-specific hardware patting. 1769 * 1770 **********************************************************************/ 1771 static void 1772 em_if_timer(if_ctx_t ctx, uint16_t qid) 1773 { 1774 1775 if (qid != 0) 1776 return; 1777 1778 iflib_admin_intr_deferred(ctx); 1779 } 1780 1781 static void 1782 em_if_update_admin_status(if_ctx_t ctx) 1783 { 1784 struct e1000_softc *sc = iflib_get_softc(ctx); 1785 struct e1000_hw *hw = &sc->hw; 1786 device_t dev = iflib_get_dev(ctx); 1787 u32 link_check, thstat, ctrl; 1788 1789 link_check = thstat = ctrl = 0; 1790 /* Get the cached link value or read phy for real */ 1791 switch (hw->phy.media_type) { 1792 case e1000_media_type_copper: 1793 if (hw->mac.get_link_status) { 1794 if (hw->mac.type == e1000_pch_spt) 1795 msec_delay(50); 1796 /* Do the work to read phy */ 1797 e1000_check_for_link(hw); 1798 link_check = !hw->mac.get_link_status; 1799 if (link_check) /* ESB2 fix */ 1800 e1000_cfg_on_link_up(hw); 1801 } else { 1802 link_check = true; 1803 } 1804 break; 1805 case e1000_media_type_fiber: 1806 e1000_check_for_link(hw); 1807 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1808 E1000_STATUS_LU); 1809 break; 1810 case e1000_media_type_internal_serdes: 1811 e1000_check_for_link(hw); 1812 link_check = hw->mac.serdes_has_link; 1813 break; 1814 /* VF device is type_unknown */ 1815 case e1000_media_type_unknown: 1816 e1000_check_for_link(hw); 1817 link_check = !hw->mac.get_link_status; 1818 /* FALLTHROUGH */ 1819 default: 1820 break; 1821 } 1822 1823 /* Check for thermal downshift or shutdown */ 1824 if (hw->mac.type == e1000_i350) { 1825 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1826 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1827 } 1828 1829 /* Now check for a transition */ 1830 if (link_check && (sc->link_active == 0)) { 1831 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1832 &sc->link_duplex); 1833 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1834 if ((sc->link_speed != SPEED_1000) && 1835 ((hw->mac.type == e1000_82571) || 1836 (hw->mac.type == e1000_82572))) { 1837 int tarc0; 1838 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1839 tarc0 &= ~TARC_SPEED_MODE_BIT; 1840 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1841 } 1842 if (bootverbose) 1843 device_printf(dev, "Link is up %d Mbps %s\n", 1844 sc->link_speed, 1845 ((sc->link_duplex == FULL_DUPLEX) ? 1846 "Full Duplex" : "Half Duplex")); 1847 sc->link_active = 1; 1848 sc->smartspeed = 0; 1849 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1850 E1000_CTRL_EXT_LINK_MODE_GMII && 1851 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1852 device_printf(dev, "Link: thermal downshift\n"); 1853 /* Delay Link Up for Phy update */ 1854 if (((hw->mac.type == e1000_i210) || 1855 (hw->mac.type == e1000_i211)) && 1856 (hw->phy.id == I210_I_PHY_ID)) 1857 msec_delay(I210_LINK_DELAY); 1858 /* Reset if the media type changed. */ 1859 if (hw->dev_spec._82575.media_changed && 1860 hw->mac.type >= igb_mac_min) { 1861 hw->dev_spec._82575.media_changed = false; 1862 sc->flags |= IGB_MEDIA_RESET; 1863 em_reset(ctx); 1864 } 1865 iflib_link_state_change(ctx, LINK_STATE_UP, 1866 IF_Mbps(sc->link_speed)); 1867 } else if (!link_check && (sc->link_active == 1)) { 1868 sc->link_speed = 0; 1869 sc->link_duplex = 0; 1870 sc->link_active = 0; 1871 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1872 } 1873 em_update_stats_counters(sc); 1874 1875 /* Reset LAA into RAR[0] on 82571 */ 1876 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1877 e1000_rar_set(hw, hw->mac.addr, 0); 1878 1879 if (hw->mac.type < em_mac_min) 1880 lem_smartspeed(sc); 1881 } 1882 1883 static void 1884 em_if_watchdog_reset(if_ctx_t ctx) 1885 { 1886 struct e1000_softc *sc = iflib_get_softc(ctx); 1887 1888 /* 1889 * Just count the event; iflib(4) will already trigger a 1890 * sufficient reset of the controller. 1891 */ 1892 sc->watchdog_events++; 1893 } 1894 1895 /********************************************************************* 1896 * 1897 * This routine disables all traffic on the adapter by issuing a 1898 * global reset on the MAC. 1899 * 1900 **********************************************************************/ 1901 static void 1902 em_if_stop(if_ctx_t ctx) 1903 { 1904 struct e1000_softc *sc = iflib_get_softc(ctx); 1905 1906 INIT_DEBUGOUT("em_if_stop: begin"); 1907 1908 e1000_reset_hw(&sc->hw); 1909 if (sc->hw.mac.type >= e1000_82544) 1910 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1911 1912 e1000_led_off(&sc->hw); 1913 e1000_cleanup_led(&sc->hw); 1914 } 1915 1916 /********************************************************************* 1917 * 1918 * Determine hardware revision. 1919 * 1920 **********************************************************************/ 1921 static void 1922 em_identify_hardware(if_ctx_t ctx) 1923 { 1924 device_t dev = iflib_get_dev(ctx); 1925 struct e1000_softc *sc = iflib_get_softc(ctx); 1926 1927 /* Make sure our PCI config space has the necessary stuff set */ 1928 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1929 1930 /* Save off the information about this board */ 1931 sc->hw.vendor_id = pci_get_vendor(dev); 1932 sc->hw.device_id = pci_get_device(dev); 1933 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1934 sc->hw.subsystem_vendor_id = 1935 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1936 sc->hw.subsystem_device_id = 1937 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1938 1939 /* Do Shared Code Init and Setup */ 1940 if (e1000_set_mac_type(&sc->hw)) { 1941 device_printf(dev, "Setup init failure\n"); 1942 return; 1943 } 1944 1945 /* Are we a VF device? */ 1946 if ((sc->hw.mac.type == e1000_vfadapt) || 1947 (sc->hw.mac.type == e1000_vfadapt_i350)) 1948 sc->vf_ifp = 1; 1949 else 1950 sc->vf_ifp = 0; 1951 } 1952 1953 static int 1954 em_allocate_pci_resources(if_ctx_t ctx) 1955 { 1956 struct e1000_softc *sc = iflib_get_softc(ctx); 1957 device_t dev = iflib_get_dev(ctx); 1958 int rid, val; 1959 1960 rid = PCIR_BAR(0); 1961 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1962 &rid, RF_ACTIVE); 1963 if (sc->memory == NULL) { 1964 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1965 return (ENXIO); 1966 } 1967 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 1968 sc->osdep.mem_bus_space_handle = 1969 rman_get_bushandle(sc->memory); 1970 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 1971 1972 /* Only older adapters use IO mapping */ 1973 if (sc->hw.mac.type < em_mac_min && 1974 sc->hw.mac.type > e1000_82543) { 1975 /* Figure our where our IO BAR is ? */ 1976 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1977 val = pci_read_config(dev, rid, 4); 1978 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1979 break; 1980 } 1981 rid += 4; 1982 /* check for 64bit BAR */ 1983 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1984 rid += 4; 1985 } 1986 if (rid >= PCIR_CIS) { 1987 device_printf(dev, "Unable to locate IO BAR\n"); 1988 return (ENXIO); 1989 } 1990 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1991 &rid, RF_ACTIVE); 1992 if (sc->ioport == NULL) { 1993 device_printf(dev, "Unable to allocate bus resource: " 1994 "ioport\n"); 1995 return (ENXIO); 1996 } 1997 sc->hw.io_base = 0; 1998 sc->osdep.io_bus_space_tag = 1999 rman_get_bustag(sc->ioport); 2000 sc->osdep.io_bus_space_handle = 2001 rman_get_bushandle(sc->ioport); 2002 } 2003 2004 sc->hw.back = &sc->osdep; 2005 2006 return (0); 2007 } 2008 2009 /********************************************************************* 2010 * 2011 * Set up the MSI-X Interrupt handlers 2012 * 2013 **********************************************************************/ 2014 static int 2015 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2016 { 2017 struct e1000_softc *sc = iflib_get_softc(ctx); 2018 struct em_rx_queue *rx_que = sc->rx_queues; 2019 struct em_tx_queue *tx_que = sc->tx_queues; 2020 int error, rid, i, vector = 0, rx_vectors; 2021 char buf[16]; 2022 2023 /* First set up ring resources */ 2024 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2025 rid = vector + 1; 2026 snprintf(buf, sizeof(buf), "rxq%d", i); 2027 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2028 if (error) { 2029 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2030 sc->rx_num_queues = i + 1; 2031 goto fail; 2032 } 2033 2034 rx_que->msix = vector; 2035 2036 /* 2037 * Set the bit to enable interrupt 2038 * in E1000_IMS -- bits 20 and 21 2039 * are for RX0 and RX1, note this has 2040 * NOTHING to do with the MSI-X vector 2041 */ 2042 if (sc->hw.mac.type == e1000_82574) { 2043 rx_que->eims = 1 << (20 + i); 2044 sc->ims |= rx_que->eims; 2045 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2046 } else if (sc->hw.mac.type == e1000_82575) 2047 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2048 else 2049 rx_que->eims = 1 << vector; 2050 } 2051 rx_vectors = vector; 2052 2053 vector = 0; 2054 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2055 snprintf(buf, sizeof(buf), "txq%d", i); 2056 tx_que = &sc->tx_queues[i]; 2057 iflib_softirq_alloc_generic(ctx, 2058 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2059 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2060 2061 tx_que->msix = (vector % sc->rx_num_queues); 2062 2063 /* 2064 * Set the bit to enable interrupt 2065 * in E1000_IMS -- bits 22 and 23 2066 * are for TX0 and TX1, note this has 2067 * NOTHING to do with the MSI-X vector 2068 */ 2069 if (sc->hw.mac.type == e1000_82574) { 2070 tx_que->eims = 1 << (22 + i); 2071 sc->ims |= tx_que->eims; 2072 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2073 } else if (sc->hw.mac.type == e1000_82575) { 2074 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2075 } else { 2076 tx_que->eims = 1 << i; 2077 } 2078 } 2079 2080 /* Link interrupt */ 2081 rid = rx_vectors + 1; 2082 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2083 2084 if (error) { 2085 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2086 goto fail; 2087 } 2088 sc->linkvec = rx_vectors; 2089 if (sc->hw.mac.type < igb_mac_min) { 2090 sc->ivars |= (8 | rx_vectors) << 16; 2091 sc->ivars |= 0x80000000; 2092 /* Enable the "Other" interrupt type for link status change */ 2093 sc->ims |= E1000_IMS_OTHER; 2094 } 2095 2096 return (0); 2097 fail: 2098 iflib_irq_free(ctx, &sc->irq); 2099 rx_que = sc->rx_queues; 2100 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2101 iflib_irq_free(ctx, &rx_que->que_irq); 2102 return (error); 2103 } 2104 2105 static void 2106 igb_configure_queues(struct e1000_softc *sc) 2107 { 2108 struct e1000_hw *hw = &sc->hw; 2109 struct em_rx_queue *rx_que; 2110 struct em_tx_queue *tx_que; 2111 u32 tmp, ivar = 0, newitr = 0; 2112 2113 /* First turn on RSS capability */ 2114 if (hw->mac.type != e1000_82575) 2115 E1000_WRITE_REG(hw, E1000_GPIE, 2116 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2117 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2118 2119 /* Turn on MSI-X */ 2120 switch (hw->mac.type) { 2121 case e1000_82580: 2122 case e1000_i350: 2123 case e1000_i354: 2124 case e1000_i210: 2125 case e1000_i211: 2126 case e1000_vfadapt: 2127 case e1000_vfadapt_i350: 2128 /* RX entries */ 2129 for (int i = 0; i < sc->rx_num_queues; i++) { 2130 u32 index = i >> 1; 2131 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2132 rx_que = &sc->rx_queues[i]; 2133 if (i & 1) { 2134 ivar &= 0xFF00FFFF; 2135 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2136 } else { 2137 ivar &= 0xFFFFFF00; 2138 ivar |= rx_que->msix | E1000_IVAR_VALID; 2139 } 2140 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2141 } 2142 /* TX entries */ 2143 for (int i = 0; i < sc->tx_num_queues; i++) { 2144 u32 index = i >> 1; 2145 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2146 tx_que = &sc->tx_queues[i]; 2147 if (i & 1) { 2148 ivar &= 0x00FFFFFF; 2149 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2150 } else { 2151 ivar &= 0xFFFF00FF; 2152 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2153 } 2154 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2155 sc->que_mask |= tx_que->eims; 2156 } 2157 2158 /* And for the link interrupt */ 2159 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2160 sc->link_mask = 1 << sc->linkvec; 2161 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2162 break; 2163 case e1000_82576: 2164 /* RX entries */ 2165 for (int i = 0; i < sc->rx_num_queues; i++) { 2166 u32 index = i & 0x7; /* Each IVAR has two entries */ 2167 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2168 rx_que = &sc->rx_queues[i]; 2169 if (i < 8) { 2170 ivar &= 0xFFFFFF00; 2171 ivar |= rx_que->msix | E1000_IVAR_VALID; 2172 } else { 2173 ivar &= 0xFF00FFFF; 2174 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2175 } 2176 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2177 sc->que_mask |= rx_que->eims; 2178 } 2179 /* TX entries */ 2180 for (int i = 0; i < sc->tx_num_queues; i++) { 2181 u32 index = i & 0x7; /* Each IVAR has two entries */ 2182 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2183 tx_que = &sc->tx_queues[i]; 2184 if (i < 8) { 2185 ivar &= 0xFFFF00FF; 2186 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2187 } else { 2188 ivar &= 0x00FFFFFF; 2189 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2190 } 2191 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2192 sc->que_mask |= tx_que->eims; 2193 } 2194 2195 /* And for the link interrupt */ 2196 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2197 sc->link_mask = 1 << sc->linkvec; 2198 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2199 break; 2200 2201 case e1000_82575: 2202 /* enable MSI-X support*/ 2203 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2204 tmp |= E1000_CTRL_EXT_PBA_CLR; 2205 /* Auto-Mask interrupts upon ICR read. */ 2206 tmp |= E1000_CTRL_EXT_EIAME; 2207 tmp |= E1000_CTRL_EXT_IRCA; 2208 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2209 2210 /* Queues */ 2211 for (int i = 0; i < sc->rx_num_queues; i++) { 2212 rx_que = &sc->rx_queues[i]; 2213 tmp = E1000_EICR_RX_QUEUE0 << i; 2214 tmp |= E1000_EICR_TX_QUEUE0 << i; 2215 rx_que->eims = tmp; 2216 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2217 i, rx_que->eims); 2218 sc->que_mask |= rx_que->eims; 2219 } 2220 2221 /* Link */ 2222 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2223 E1000_EIMS_OTHER); 2224 sc->link_mask |= E1000_EIMS_OTHER; 2225 default: 2226 break; 2227 } 2228 2229 /* Set the starting interrupt rate */ 2230 if (em_max_interrupt_rate > 0) 2231 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2232 2233 if (hw->mac.type == e1000_82575) 2234 newitr |= newitr << 16; 2235 else 2236 newitr |= E1000_EITR_CNT_IGNR; 2237 2238 for (int i = 0; i < sc->rx_num_queues; i++) { 2239 rx_que = &sc->rx_queues[i]; 2240 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2241 } 2242 2243 return; 2244 } 2245 2246 static void 2247 em_free_pci_resources(if_ctx_t ctx) 2248 { 2249 struct e1000_softc *sc = iflib_get_softc(ctx); 2250 struct em_rx_queue *que = sc->rx_queues; 2251 device_t dev = iflib_get_dev(ctx); 2252 2253 /* Release all MSI-X queue resources */ 2254 if (sc->intr_type == IFLIB_INTR_MSIX) 2255 iflib_irq_free(ctx, &sc->irq); 2256 2257 if (que != NULL) { 2258 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2259 iflib_irq_free(ctx, &que->que_irq); 2260 } 2261 } 2262 2263 if (sc->memory != NULL) { 2264 bus_release_resource(dev, SYS_RES_MEMORY, 2265 rman_get_rid(sc->memory), sc->memory); 2266 sc->memory = NULL; 2267 } 2268 2269 if (sc->flash != NULL) { 2270 bus_release_resource(dev, SYS_RES_MEMORY, 2271 rman_get_rid(sc->flash), sc->flash); 2272 sc->flash = NULL; 2273 } 2274 2275 if (sc->ioport != NULL) { 2276 bus_release_resource(dev, SYS_RES_IOPORT, 2277 rman_get_rid(sc->ioport), sc->ioport); 2278 sc->ioport = NULL; 2279 } 2280 } 2281 2282 /* Set up MSI or MSI-X */ 2283 static int 2284 em_setup_msix(if_ctx_t ctx) 2285 { 2286 struct e1000_softc *sc = iflib_get_softc(ctx); 2287 2288 if (sc->hw.mac.type == e1000_82574) { 2289 em_enable_vectors_82574(ctx); 2290 } 2291 return (0); 2292 } 2293 2294 /********************************************************************* 2295 * 2296 * Workaround for SmartSpeed on 82541 and 82547 controllers 2297 * 2298 **********************************************************************/ 2299 static void 2300 lem_smartspeed(struct e1000_softc *sc) 2301 { 2302 u16 phy_tmp; 2303 2304 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2305 sc->hw.mac.autoneg == 0 || 2306 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2307 return; 2308 2309 if (sc->smartspeed == 0) { 2310 /* If Master/Slave config fault is asserted twice, 2311 * we assume back-to-back */ 2312 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2313 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2314 return; 2315 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2316 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2317 e1000_read_phy_reg(&sc->hw, 2318 PHY_1000T_CTRL, &phy_tmp); 2319 if(phy_tmp & CR_1000T_MS_ENABLE) { 2320 phy_tmp &= ~CR_1000T_MS_ENABLE; 2321 e1000_write_phy_reg(&sc->hw, 2322 PHY_1000T_CTRL, phy_tmp); 2323 sc->smartspeed++; 2324 if(sc->hw.mac.autoneg && 2325 !e1000_copper_link_autoneg(&sc->hw) && 2326 !e1000_read_phy_reg(&sc->hw, 2327 PHY_CONTROL, &phy_tmp)) { 2328 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2329 MII_CR_RESTART_AUTO_NEG); 2330 e1000_write_phy_reg(&sc->hw, 2331 PHY_CONTROL, phy_tmp); 2332 } 2333 } 2334 } 2335 return; 2336 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2337 /* If still no link, perhaps using 2/3 pair cable */ 2338 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2339 phy_tmp |= CR_1000T_MS_ENABLE; 2340 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2341 if(sc->hw.mac.autoneg && 2342 !e1000_copper_link_autoneg(&sc->hw) && 2343 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2344 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2345 MII_CR_RESTART_AUTO_NEG); 2346 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2347 } 2348 } 2349 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2350 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2351 sc->smartspeed = 0; 2352 } 2353 2354 /********************************************************************* 2355 * 2356 * Initialize the DMA Coalescing feature 2357 * 2358 **********************************************************************/ 2359 static void 2360 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2361 { 2362 device_t dev = sc->dev; 2363 struct e1000_hw *hw = &sc->hw; 2364 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2365 u16 hwm; 2366 u16 max_frame_size; 2367 2368 if (hw->mac.type == e1000_i211) 2369 return; 2370 2371 max_frame_size = sc->shared->isc_max_frame_size; 2372 if (hw->mac.type > e1000_82580) { 2373 2374 if (sc->dmac == 0) { /* Disabling it */ 2375 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2376 return; 2377 } else 2378 device_printf(dev, "DMA Coalescing enabled\n"); 2379 2380 /* Set starting threshold */ 2381 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2382 2383 hwm = 64 * pba - max_frame_size / 16; 2384 if (hwm < 64 * (pba - 6)) 2385 hwm = 64 * (pba - 6); 2386 reg = E1000_READ_REG(hw, E1000_FCRTC); 2387 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2388 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2389 & E1000_FCRTC_RTH_COAL_MASK); 2390 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2391 2392 2393 dmac = pba - max_frame_size / 512; 2394 if (dmac < pba - 10) 2395 dmac = pba - 10; 2396 reg = E1000_READ_REG(hw, E1000_DMACR); 2397 reg &= ~E1000_DMACR_DMACTHR_MASK; 2398 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2399 & E1000_DMACR_DMACTHR_MASK); 2400 2401 /* transition to L0x or L1 if available..*/ 2402 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2403 2404 /* Check if status is 2.5Gb backplane connection 2405 * before configuration of watchdog timer, which is 2406 * in msec values in 12.8usec intervals 2407 * watchdog timer= msec values in 32usec intervals 2408 * for non 2.5Gb connection 2409 */ 2410 if (hw->mac.type == e1000_i354) { 2411 int status = E1000_READ_REG(hw, E1000_STATUS); 2412 if ((status & E1000_STATUS_2P5_SKU) && 2413 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2414 reg |= ((sc->dmac * 5) >> 6); 2415 else 2416 reg |= (sc->dmac >> 5); 2417 } else { 2418 reg |= (sc->dmac >> 5); 2419 } 2420 2421 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2422 2423 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2424 2425 /* Set the interval before transition */ 2426 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2427 if (hw->mac.type == e1000_i350) 2428 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2429 /* 2430 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2431 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2432 */ 2433 if (hw->mac.type == e1000_i354) { 2434 int status = E1000_READ_REG(hw, E1000_STATUS); 2435 if ((status & E1000_STATUS_2P5_SKU) && 2436 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2437 reg |= 0xA; 2438 else 2439 reg |= 0x4; 2440 } else { 2441 reg |= 0x4; 2442 } 2443 2444 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2445 2446 /* free space in tx packet buffer to wake from DMA coal */ 2447 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2448 (2 * max_frame_size)) >> 6); 2449 2450 /* make low power state decision controlled by DMA coal */ 2451 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2452 reg &= ~E1000_PCIEMISC_LX_DECISION; 2453 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2454 2455 } else if (hw->mac.type == e1000_82580) { 2456 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2457 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2458 reg & ~E1000_PCIEMISC_LX_DECISION); 2459 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2460 } 2461 } 2462 2463 /********************************************************************* 2464 * 2465 * Initialize the hardware to a configuration as specified by the 2466 * sc structure. 2467 * 2468 **********************************************************************/ 2469 static void 2470 em_reset(if_ctx_t ctx) 2471 { 2472 device_t dev = iflib_get_dev(ctx); 2473 struct e1000_softc *sc = iflib_get_softc(ctx); 2474 if_t ifp = iflib_get_ifp(ctx); 2475 struct e1000_hw *hw = &sc->hw; 2476 u32 rx_buffer_size; 2477 u32 pba; 2478 2479 INIT_DEBUGOUT("em_reset: begin"); 2480 /* Let the firmware know the OS is in control */ 2481 em_get_hw_control(sc); 2482 2483 /* Set up smart power down as default off on newer adapters. */ 2484 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2485 hw->mac.type == e1000_82572)) { 2486 u16 phy_tmp = 0; 2487 2488 /* Speed up time to link by disabling smart power down. */ 2489 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2490 phy_tmp &= ~IGP02E1000_PM_SPD; 2491 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2492 } 2493 2494 /* 2495 * Packet Buffer Allocation (PBA) 2496 * Writing PBA sets the receive portion of the buffer 2497 * the remainder is used for the transmit buffer. 2498 */ 2499 switch (hw->mac.type) { 2500 /* 82547: Total Packet Buffer is 40K */ 2501 case e1000_82547: 2502 case e1000_82547_rev_2: 2503 if (hw->mac.max_frame_size > 8192) 2504 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2505 else 2506 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2507 break; 2508 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2509 case e1000_82571: 2510 case e1000_82572: 2511 case e1000_80003es2lan: 2512 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2513 break; 2514 /* 82573: Total Packet Buffer is 32K */ 2515 case e1000_82573: 2516 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2517 break; 2518 case e1000_82574: 2519 case e1000_82583: 2520 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2521 break; 2522 case e1000_ich8lan: 2523 pba = E1000_PBA_8K; 2524 break; 2525 case e1000_ich9lan: 2526 case e1000_ich10lan: 2527 /* Boost Receive side for jumbo frames */ 2528 if (hw->mac.max_frame_size > 4096) 2529 pba = E1000_PBA_14K; 2530 else 2531 pba = E1000_PBA_10K; 2532 break; 2533 case e1000_pchlan: 2534 case e1000_pch2lan: 2535 case e1000_pch_lpt: 2536 case e1000_pch_spt: 2537 case e1000_pch_cnp: 2538 case e1000_pch_tgp: 2539 case e1000_pch_adp: 2540 case e1000_pch_mtp: 2541 pba = E1000_PBA_26K; 2542 break; 2543 case e1000_82575: 2544 pba = E1000_PBA_32K; 2545 break; 2546 case e1000_82576: 2547 case e1000_vfadapt: 2548 pba = E1000_READ_REG(hw, E1000_RXPBS); 2549 pba &= E1000_RXPBS_SIZE_MASK_82576; 2550 break; 2551 case e1000_82580: 2552 case e1000_i350: 2553 case e1000_i354: 2554 case e1000_vfadapt_i350: 2555 pba = E1000_READ_REG(hw, E1000_RXPBS); 2556 pba = e1000_rxpbs_adjust_82580(pba); 2557 break; 2558 case e1000_i210: 2559 case e1000_i211: 2560 pba = E1000_PBA_34K; 2561 break; 2562 default: 2563 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2564 if (hw->mac.max_frame_size > 8192) 2565 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2566 else 2567 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2568 } 2569 2570 /* Special needs in case of Jumbo frames */ 2571 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2572 u32 tx_space, min_tx, min_rx; 2573 pba = E1000_READ_REG(hw, E1000_PBA); 2574 tx_space = pba >> 16; 2575 pba &= 0xffff; 2576 min_tx = (hw->mac.max_frame_size + 2577 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2578 min_tx = roundup2(min_tx, 1024); 2579 min_tx >>= 10; 2580 min_rx = hw->mac.max_frame_size; 2581 min_rx = roundup2(min_rx, 1024); 2582 min_rx >>= 10; 2583 if (tx_space < min_tx && 2584 ((min_tx - tx_space) < pba)) { 2585 pba = pba - (min_tx - tx_space); 2586 /* 2587 * if short on rx space, rx wins 2588 * and must trump tx adjustment 2589 */ 2590 if (pba < min_rx) 2591 pba = min_rx; 2592 } 2593 E1000_WRITE_REG(hw, E1000_PBA, pba); 2594 } 2595 2596 if (hw->mac.type < igb_mac_min) 2597 E1000_WRITE_REG(hw, E1000_PBA, pba); 2598 2599 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2600 2601 /* 2602 * These parameters control the automatic generation (Tx) and 2603 * response (Rx) to Ethernet PAUSE frames. 2604 * - High water mark should allow for at least two frames to be 2605 * received after sending an XOFF. 2606 * - Low water mark works best when it is very near the high water mark. 2607 * This allows the receiver to restart by sending XON when it has 2608 * drained a bit. Here we use an arbitrary value of 1500 which will 2609 * restart after one full frame is pulled from the buffer. There 2610 * could be several smaller frames in the buffer and if so they will 2611 * not trigger the XON until their total number reduces the buffer 2612 * by 1500. 2613 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2614 */ 2615 rx_buffer_size = (pba & 0xffff) << 10; 2616 hw->fc.high_water = rx_buffer_size - 2617 roundup2(hw->mac.max_frame_size, 1024); 2618 hw->fc.low_water = hw->fc.high_water - 1500; 2619 2620 if (sc->fc) /* locally set flow control value? */ 2621 hw->fc.requested_mode = sc->fc; 2622 else 2623 hw->fc.requested_mode = e1000_fc_full; 2624 2625 if (hw->mac.type == e1000_80003es2lan) 2626 hw->fc.pause_time = 0xFFFF; 2627 else 2628 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2629 2630 hw->fc.send_xon = true; 2631 2632 /* Device specific overrides/settings */ 2633 switch (hw->mac.type) { 2634 case e1000_pchlan: 2635 /* Workaround: no TX flow ctrl for PCH */ 2636 hw->fc.requested_mode = e1000_fc_rx_pause; 2637 hw->fc.pause_time = 0xFFFF; /* override */ 2638 if (if_getmtu(ifp) > ETHERMTU) { 2639 hw->fc.high_water = 0x3500; 2640 hw->fc.low_water = 0x1500; 2641 } else { 2642 hw->fc.high_water = 0x5000; 2643 hw->fc.low_water = 0x3000; 2644 } 2645 hw->fc.refresh_time = 0x1000; 2646 break; 2647 case e1000_pch2lan: 2648 case e1000_pch_lpt: 2649 case e1000_pch_spt: 2650 case e1000_pch_cnp: 2651 case e1000_pch_tgp: 2652 case e1000_pch_adp: 2653 case e1000_pch_mtp: 2654 hw->fc.high_water = 0x5C20; 2655 hw->fc.low_water = 0x5048; 2656 hw->fc.pause_time = 0x0650; 2657 hw->fc.refresh_time = 0x0400; 2658 /* Jumbos need adjusted PBA */ 2659 if (if_getmtu(ifp) > ETHERMTU) 2660 E1000_WRITE_REG(hw, E1000_PBA, 12); 2661 else 2662 E1000_WRITE_REG(hw, E1000_PBA, 26); 2663 break; 2664 case e1000_82575: 2665 case e1000_82576: 2666 /* 8-byte granularity */ 2667 hw->fc.low_water = hw->fc.high_water - 8; 2668 break; 2669 case e1000_82580: 2670 case e1000_i350: 2671 case e1000_i354: 2672 case e1000_i210: 2673 case e1000_i211: 2674 case e1000_vfadapt: 2675 case e1000_vfadapt_i350: 2676 /* 16-byte granularity */ 2677 hw->fc.low_water = hw->fc.high_water - 16; 2678 break; 2679 case e1000_ich9lan: 2680 case e1000_ich10lan: 2681 if (if_getmtu(ifp) > ETHERMTU) { 2682 hw->fc.high_water = 0x2800; 2683 hw->fc.low_water = hw->fc.high_water - 8; 2684 break; 2685 } 2686 /* FALLTHROUGH */ 2687 default: 2688 if (hw->mac.type == e1000_80003es2lan) 2689 hw->fc.pause_time = 0xFFFF; 2690 break; 2691 } 2692 2693 /* Issue a global reset */ 2694 e1000_reset_hw(hw); 2695 if (hw->mac.type >= igb_mac_min) { 2696 E1000_WRITE_REG(hw, E1000_WUC, 0); 2697 } else { 2698 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2699 em_disable_aspm(sc); 2700 } 2701 if (sc->flags & IGB_MEDIA_RESET) { 2702 e1000_setup_init_funcs(hw, true); 2703 e1000_get_bus_info(hw); 2704 sc->flags &= ~IGB_MEDIA_RESET; 2705 } 2706 /* and a re-init */ 2707 if (e1000_init_hw(hw) < 0) { 2708 device_printf(dev, "Hardware Initialization Failed\n"); 2709 return; 2710 } 2711 if (hw->mac.type >= igb_mac_min) 2712 igb_init_dmac(sc, pba); 2713 2714 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2715 e1000_get_phy_info(hw); 2716 e1000_check_for_link(hw); 2717 } 2718 2719 /* 2720 * Initialise the RSS mapping for NICs that support multiple transmit/ 2721 * receive rings. 2722 */ 2723 2724 #define RSSKEYLEN 10 2725 static void 2726 em_initialize_rss_mapping(struct e1000_softc *sc) 2727 { 2728 uint8_t rss_key[4 * RSSKEYLEN]; 2729 uint32_t reta = 0; 2730 struct e1000_hw *hw = &sc->hw; 2731 int i; 2732 2733 /* 2734 * Configure RSS key 2735 */ 2736 arc4rand(rss_key, sizeof(rss_key), 0); 2737 for (i = 0; i < RSSKEYLEN; ++i) { 2738 uint32_t rssrk = 0; 2739 2740 rssrk = EM_RSSRK_VAL(rss_key, i); 2741 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2742 } 2743 2744 /* 2745 * Configure RSS redirect table in following fashion: 2746 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2747 */ 2748 for (i = 0; i < sizeof(reta); ++i) { 2749 uint32_t q; 2750 2751 q = (i % sc->rx_num_queues) << 7; 2752 reta |= q << (8 * i); 2753 } 2754 2755 for (i = 0; i < 32; ++i) 2756 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2757 2758 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2759 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2760 E1000_MRQC_RSS_FIELD_IPV4 | 2761 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2762 E1000_MRQC_RSS_FIELD_IPV6_EX | 2763 E1000_MRQC_RSS_FIELD_IPV6); 2764 } 2765 2766 static void 2767 igb_initialize_rss_mapping(struct e1000_softc *sc) 2768 { 2769 struct e1000_hw *hw = &sc->hw; 2770 int i; 2771 int queue_id; 2772 u32 reta; 2773 u32 rss_key[10], mrqc, shift = 0; 2774 2775 /* XXX? */ 2776 if (hw->mac.type == e1000_82575) 2777 shift = 6; 2778 2779 /* 2780 * The redirection table controls which destination 2781 * queue each bucket redirects traffic to. 2782 * Each DWORD represents four queues, with the LSB 2783 * being the first queue in the DWORD. 2784 * 2785 * This just allocates buckets to queues using round-robin 2786 * allocation. 2787 * 2788 * NOTE: It Just Happens to line up with the default 2789 * RSS allocation method. 2790 */ 2791 2792 /* Warning FM follows */ 2793 reta = 0; 2794 for (i = 0; i < 128; i++) { 2795 #ifdef RSS 2796 queue_id = rss_get_indirection_to_bucket(i); 2797 /* 2798 * If we have more queues than buckets, we'll 2799 * end up mapping buckets to a subset of the 2800 * queues. 2801 * 2802 * If we have more buckets than queues, we'll 2803 * end up instead assigning multiple buckets 2804 * to queues. 2805 * 2806 * Both are suboptimal, but we need to handle 2807 * the case so we don't go out of bounds 2808 * indexing arrays and such. 2809 */ 2810 queue_id = queue_id % sc->rx_num_queues; 2811 #else 2812 queue_id = (i % sc->rx_num_queues); 2813 #endif 2814 /* Adjust if required */ 2815 queue_id = queue_id << shift; 2816 2817 /* 2818 * The low 8 bits are for hash value (n+0); 2819 * The next 8 bits are for hash value (n+1), etc. 2820 */ 2821 reta = reta >> 8; 2822 reta = reta | ( ((uint32_t) queue_id) << 24); 2823 if ((i & 3) == 3) { 2824 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2825 reta = 0; 2826 } 2827 } 2828 2829 /* Now fill in hash table */ 2830 2831 /* 2832 * MRQC: Multiple Receive Queues Command 2833 * Set queuing to RSS control, number depends on the device. 2834 */ 2835 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2836 2837 #ifdef RSS 2838 /* XXX ew typecasting */ 2839 rss_getkey((uint8_t *) &rss_key); 2840 #else 2841 arc4rand(&rss_key, sizeof(rss_key), 0); 2842 #endif 2843 for (i = 0; i < 10; i++) 2844 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2845 2846 /* 2847 * Configure the RSS fields to hash upon. 2848 */ 2849 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2850 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2851 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2852 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2853 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2854 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2855 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2856 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2857 2858 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2859 } 2860 2861 /********************************************************************* 2862 * 2863 * Setup networking device structure and register interface media. 2864 * 2865 **********************************************************************/ 2866 static int 2867 em_setup_interface(if_ctx_t ctx) 2868 { 2869 if_t ifp = iflib_get_ifp(ctx); 2870 struct e1000_softc *sc = iflib_get_softc(ctx); 2871 if_softc_ctx_t scctx = sc->shared; 2872 2873 INIT_DEBUGOUT("em_setup_interface: begin"); 2874 2875 /* Single Queue */ 2876 if (sc->tx_num_queues == 1) { 2877 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2878 if_setsendqready(ifp); 2879 } 2880 2881 /* 2882 * Specify the media types supported by this adapter and register 2883 * callbacks to update media and link information 2884 */ 2885 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2886 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 2887 u_char fiber_type = IFM_1000_SX; /* default type */ 2888 2889 if (sc->hw.mac.type == e1000_82545) 2890 fiber_type = IFM_1000_LX; 2891 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2892 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 2893 } else { 2894 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2895 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2896 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2897 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2898 if (sc->hw.phy.type != e1000_phy_ife) { 2899 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2900 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2901 } 2902 } 2903 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2904 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 2905 return (0); 2906 } 2907 2908 static int 2909 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2910 { 2911 struct e1000_softc *sc = iflib_get_softc(ctx); 2912 if_softc_ctx_t scctx = sc->shared; 2913 int error = E1000_SUCCESS; 2914 struct em_tx_queue *que; 2915 int i, j; 2916 2917 MPASS(sc->tx_num_queues > 0); 2918 MPASS(sc->tx_num_queues == ntxqsets); 2919 2920 /* First allocate the top level queue structs */ 2921 if (!(sc->tx_queues = 2922 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2923 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2924 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2925 return(ENOMEM); 2926 } 2927 2928 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 2929 /* Set up some basics */ 2930 2931 struct tx_ring *txr = &que->txr; 2932 txr->sc = que->sc = sc; 2933 que->me = txr->me = i; 2934 2935 /* Allocate report status array */ 2936 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2937 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2938 error = ENOMEM; 2939 goto fail; 2940 } 2941 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2942 txr->tx_rsq[j] = QIDX_INVALID; 2943 /* get the virtual and physical address of the hardware queues */ 2944 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2945 txr->tx_paddr = paddrs[i*ntxqs]; 2946 } 2947 2948 if (bootverbose) 2949 device_printf(iflib_get_dev(ctx), 2950 "allocated for %d tx_queues\n", sc->tx_num_queues); 2951 return (0); 2952 fail: 2953 em_if_queues_free(ctx); 2954 return (error); 2955 } 2956 2957 static int 2958 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2959 { 2960 struct e1000_softc *sc = iflib_get_softc(ctx); 2961 int error = E1000_SUCCESS; 2962 struct em_rx_queue *que; 2963 int i; 2964 2965 MPASS(sc->rx_num_queues > 0); 2966 MPASS(sc->rx_num_queues == nrxqsets); 2967 2968 /* First allocate the top level queue structs */ 2969 if (!(sc->rx_queues = 2970 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2971 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2972 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2973 error = ENOMEM; 2974 goto fail; 2975 } 2976 2977 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 2978 /* Set up some basics */ 2979 struct rx_ring *rxr = &que->rxr; 2980 rxr->sc = que->sc = sc; 2981 rxr->que = que; 2982 que->me = rxr->me = i; 2983 2984 /* get the virtual and physical address of the hardware queues */ 2985 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2986 rxr->rx_paddr = paddrs[i*nrxqs]; 2987 } 2988 2989 if (bootverbose) 2990 device_printf(iflib_get_dev(ctx), 2991 "allocated for %d rx_queues\n", sc->rx_num_queues); 2992 2993 return (0); 2994 fail: 2995 em_if_queues_free(ctx); 2996 return (error); 2997 } 2998 2999 static void 3000 em_if_queues_free(if_ctx_t ctx) 3001 { 3002 struct e1000_softc *sc = iflib_get_softc(ctx); 3003 struct em_tx_queue *tx_que = sc->tx_queues; 3004 struct em_rx_queue *rx_que = sc->rx_queues; 3005 3006 if (tx_que != NULL) { 3007 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3008 struct tx_ring *txr = &tx_que->txr; 3009 if (txr->tx_rsq == NULL) 3010 break; 3011 3012 free(txr->tx_rsq, M_DEVBUF); 3013 txr->tx_rsq = NULL; 3014 } 3015 free(sc->tx_queues, M_DEVBUF); 3016 sc->tx_queues = NULL; 3017 } 3018 3019 if (rx_que != NULL) { 3020 free(sc->rx_queues, M_DEVBUF); 3021 sc->rx_queues = NULL; 3022 } 3023 } 3024 3025 /********************************************************************* 3026 * 3027 * Enable transmit unit. 3028 * 3029 **********************************************************************/ 3030 static void 3031 em_initialize_transmit_unit(if_ctx_t ctx) 3032 { 3033 struct e1000_softc *sc = iflib_get_softc(ctx); 3034 if_softc_ctx_t scctx = sc->shared; 3035 struct em_tx_queue *que; 3036 struct tx_ring *txr; 3037 struct e1000_hw *hw = &sc->hw; 3038 u32 tctl, txdctl = 0, tarc, tipg = 0; 3039 3040 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3041 3042 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3043 u64 bus_addr; 3044 caddr_t offp, endp; 3045 3046 que = &sc->tx_queues[i]; 3047 txr = &que->txr; 3048 bus_addr = txr->tx_paddr; 3049 3050 /* Clear checksum offload context. */ 3051 offp = (caddr_t)&txr->csum_flags; 3052 endp = (caddr_t)(txr + 1); 3053 bzero(offp, endp - offp); 3054 3055 /* Base and Len of TX Ring */ 3056 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3057 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3058 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3059 (u32)(bus_addr >> 32)); 3060 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3061 (u32)bus_addr); 3062 /* Init the HEAD/TAIL indices */ 3063 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3064 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3065 3066 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3067 E1000_READ_REG(hw, E1000_TDBAL(i)), 3068 E1000_READ_REG(hw, E1000_TDLEN(i))); 3069 3070 txdctl = 0; /* clear txdctl */ 3071 txdctl |= 0x1f; /* PTHRESH */ 3072 txdctl |= 1 << 8; /* HTHRESH */ 3073 txdctl |= 1 << 16;/* WTHRESH */ 3074 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3075 txdctl |= E1000_TXDCTL_GRAN; 3076 txdctl |= 1 << 25; /* LWTHRESH */ 3077 3078 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3079 } 3080 3081 /* Set the default values for the Tx Inter Packet Gap timer */ 3082 switch (hw->mac.type) { 3083 case e1000_80003es2lan: 3084 tipg = DEFAULT_82543_TIPG_IPGR1; 3085 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3086 E1000_TIPG_IPGR2_SHIFT; 3087 break; 3088 case e1000_82542: 3089 tipg = DEFAULT_82542_TIPG_IPGT; 3090 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3091 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3092 break; 3093 default: 3094 if (hw->phy.media_type == e1000_media_type_fiber || 3095 hw->phy.media_type == e1000_media_type_internal_serdes) 3096 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3097 else 3098 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3099 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3100 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3101 } 3102 3103 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3104 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3105 3106 if(hw->mac.type >= e1000_82540) 3107 E1000_WRITE_REG(hw, E1000_TADV, 3108 sc->tx_abs_int_delay.value); 3109 3110 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3111 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3112 tarc |= TARC_SPEED_MODE_BIT; 3113 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3114 } else if (hw->mac.type == e1000_80003es2lan) { 3115 /* errata: program both queues to unweighted RR */ 3116 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3117 tarc |= 1; 3118 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3119 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3120 tarc |= 1; 3121 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3122 } else if (hw->mac.type == e1000_82574) { 3123 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3124 tarc |= TARC_ERRATA_BIT; 3125 if ( sc->tx_num_queues > 1) { 3126 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3127 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3128 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3129 } else 3130 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3131 } 3132 3133 if (sc->tx_int_delay.value > 0) 3134 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3135 3136 /* Program the Transmit Control Register */ 3137 tctl = E1000_READ_REG(hw, E1000_TCTL); 3138 tctl &= ~E1000_TCTL_CT; 3139 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3140 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3141 3142 if (hw->mac.type >= e1000_82571) 3143 tctl |= E1000_TCTL_MULR; 3144 3145 /* This write will effectively turn on the transmit unit. */ 3146 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3147 3148 /* SPT and KBL errata workarounds */ 3149 if (hw->mac.type == e1000_pch_spt) { 3150 u32 reg; 3151 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3152 reg |= E1000_RCTL_RDMTS_HEX; 3153 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3154 /* i218-i219 Specification Update 1.5.4.5 */ 3155 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3156 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3157 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3158 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3159 } 3160 } 3161 3162 /********************************************************************* 3163 * 3164 * Enable receive unit. 3165 * 3166 **********************************************************************/ 3167 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3168 3169 static void 3170 em_initialize_receive_unit(if_ctx_t ctx) 3171 { 3172 struct e1000_softc *sc = iflib_get_softc(ctx); 3173 if_softc_ctx_t scctx = sc->shared; 3174 if_t ifp = iflib_get_ifp(ctx); 3175 struct e1000_hw *hw = &sc->hw; 3176 struct em_rx_queue *que; 3177 int i; 3178 uint32_t rctl, rxcsum; 3179 3180 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3181 3182 /* 3183 * Make sure receives are disabled while setting 3184 * up the descriptor ring 3185 */ 3186 rctl = E1000_READ_REG(hw, E1000_RCTL); 3187 /* Do not disable if ever enabled on this hardware */ 3188 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3189 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3190 3191 /* Setup the Receive Control Register */ 3192 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3193 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3194 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3195 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3196 3197 /* Do not store bad packets */ 3198 rctl &= ~E1000_RCTL_SBP; 3199 3200 /* Enable Long Packet receive */ 3201 if (if_getmtu(ifp) > ETHERMTU) 3202 rctl |= E1000_RCTL_LPE; 3203 else 3204 rctl &= ~E1000_RCTL_LPE; 3205 3206 /* Strip the CRC */ 3207 if (!em_disable_crc_stripping) 3208 rctl |= E1000_RCTL_SECRC; 3209 3210 if (hw->mac.type >= e1000_82540) { 3211 E1000_WRITE_REG(hw, E1000_RADV, 3212 sc->rx_abs_int_delay.value); 3213 3214 /* 3215 * Set the interrupt throttling rate. Value is calculated 3216 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3217 */ 3218 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3219 } 3220 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3221 3222 if (hw->mac.type >= em_mac_min) { 3223 uint32_t rfctl; 3224 /* Use extended rx descriptor formats */ 3225 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3226 rfctl |= E1000_RFCTL_EXTEN; 3227 3228 /* 3229 * When using MSI-X interrupts we need to throttle 3230 * using the EITR register (82574 only) 3231 */ 3232 if (hw->mac.type == e1000_82574) { 3233 for (int i = 0; i < 4; i++) 3234 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3235 DEFAULT_ITR); 3236 /* Disable accelerated acknowledge */ 3237 rfctl |= E1000_RFCTL_ACK_DIS; 3238 } 3239 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3240 } 3241 3242 /* Set up L3 and L4 csum Rx descriptor offloads */ 3243 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3244 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3245 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3246 if (hw->mac.type > e1000_82575) 3247 rxcsum |= E1000_RXCSUM_CRCOFL; 3248 else if (hw->mac.type < em_mac_min && 3249 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3250 rxcsum |= E1000_RXCSUM_IPV6OFL; 3251 } else { 3252 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3253 if (hw->mac.type > e1000_82575) 3254 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3255 else if (hw->mac.type < em_mac_min) 3256 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3257 } 3258 3259 if (sc->rx_num_queues > 1) { 3260 /* RSS hash needed in the Rx descriptor */ 3261 rxcsum |= E1000_RXCSUM_PCSD; 3262 3263 if (hw->mac.type >= igb_mac_min) 3264 igb_initialize_rss_mapping(sc); 3265 else 3266 em_initialize_rss_mapping(sc); 3267 } 3268 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3269 3270 /* 3271 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3272 * long latencies are observed, like Lenovo X60. This 3273 * change eliminates the problem, but since having positive 3274 * values in RDTR is a known source of problems on other 3275 * platforms another solution is being sought. 3276 */ 3277 if (hw->mac.type == e1000_82573) 3278 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3279 3280 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3281 struct rx_ring *rxr = &que->rxr; 3282 /* Setup the Base and Length of the Rx Descriptor Ring */ 3283 u64 bus_addr = rxr->rx_paddr; 3284 #if 0 3285 u32 rdt = sc->rx_num_queues -1; /* default */ 3286 #endif 3287 3288 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3289 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3290 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3291 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3292 /* Setup the Head and Tail Descriptor Pointers */ 3293 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3294 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3295 } 3296 3297 /* 3298 * Set PTHRESH for improved jumbo performance 3299 * According to 10.2.5.11 of Intel 82574 Datasheet, 3300 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3301 * Only write to RXDCTL(1) if there is a need for different 3302 * settings. 3303 */ 3304 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3305 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3306 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3307 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3308 } else if (hw->mac.type == e1000_82574) { 3309 for (int i = 0; i < sc->rx_num_queues; i++) { 3310 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3311 rxdctl |= 0x20; /* PTHRESH */ 3312 rxdctl |= 4 << 8; /* HTHRESH */ 3313 rxdctl |= 4 << 16;/* WTHRESH */ 3314 rxdctl |= 1 << 24; /* Switch to granularity */ 3315 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3316 } 3317 } else if (hw->mac.type >= igb_mac_min) { 3318 u32 psize, srrctl = 0; 3319 3320 if (if_getmtu(ifp) > ETHERMTU) { 3321 psize = scctx->isc_max_frame_size; 3322 /* are we on a vlan? */ 3323 if (if_vlantrunkinuse(ifp)) 3324 psize += VLAN_TAG_SIZE; 3325 3326 if (sc->vf_ifp) 3327 e1000_rlpml_set_vf(hw, psize); 3328 else 3329 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3330 } 3331 3332 /* Set maximum packet buffer len */ 3333 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3334 E1000_SRRCTL_BSIZEPKT_SHIFT; 3335 3336 /* 3337 * If TX flow control is disabled and there's >1 queue defined, 3338 * enable DROP. 3339 * 3340 * This drops frames rather than hanging the RX MAC for all queues. 3341 */ 3342 if ((sc->rx_num_queues > 1) && 3343 (sc->fc == e1000_fc_none || 3344 sc->fc == e1000_fc_rx_pause)) { 3345 srrctl |= E1000_SRRCTL_DROP_EN; 3346 } 3347 /* Setup the Base and Length of the Rx Descriptor Rings */ 3348 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3349 struct rx_ring *rxr = &que->rxr; 3350 u64 bus_addr = rxr->rx_paddr; 3351 u32 rxdctl; 3352 3353 #ifdef notyet 3354 /* Configure for header split? -- ignore for now */ 3355 rxr->hdr_split = igb_header_split; 3356 #else 3357 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3358 #endif 3359 3360 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3361 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3362 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3363 (uint32_t)(bus_addr >> 32)); 3364 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3365 (uint32_t)bus_addr); 3366 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3367 /* Enable this Queue */ 3368 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3369 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3370 rxdctl &= 0xFFF00000; 3371 rxdctl |= IGB_RX_PTHRESH; 3372 rxdctl |= IGB_RX_HTHRESH << 8; 3373 rxdctl |= IGB_RX_WTHRESH << 16; 3374 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3375 } 3376 } else if (hw->mac.type >= e1000_pch2lan) { 3377 if (if_getmtu(ifp) > ETHERMTU) 3378 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3379 else 3380 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3381 } 3382 3383 /* Make sure VLAN Filters are off */ 3384 rctl &= ~E1000_RCTL_VFE; 3385 3386 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3387 if (hw->mac.type < igb_mac_min) { 3388 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3389 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3390 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3391 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3392 else if (sc->rx_mbuf_sz > 8192) 3393 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3394 else { 3395 rctl |= E1000_RCTL_SZ_2048; 3396 rctl &= ~E1000_RCTL_BSEX; 3397 } 3398 } else 3399 rctl |= E1000_RCTL_SZ_2048; 3400 3401 /* 3402 * rctl bits 11:10 are as follows 3403 * lem: reserved 3404 * em: DTYPE 3405 * igb: reserved 3406 * and should be 00 on all of the above 3407 */ 3408 rctl &= ~0x00000C00; 3409 3410 /* Write out the settings */ 3411 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3412 3413 return; 3414 } 3415 3416 static void 3417 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3418 { 3419 struct e1000_softc *sc = iflib_get_softc(ctx); 3420 u32 index, bit; 3421 3422 index = (vtag >> 5) & 0x7F; 3423 bit = vtag & 0x1F; 3424 sc->shadow_vfta[index] |= (1 << bit); 3425 ++sc->num_vlans; 3426 em_if_vlan_filter_write(sc); 3427 } 3428 3429 static void 3430 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3431 { 3432 struct e1000_softc *sc = iflib_get_softc(ctx); 3433 u32 index, bit; 3434 3435 index = (vtag >> 5) & 0x7F; 3436 bit = vtag & 0x1F; 3437 sc->shadow_vfta[index] &= ~(1 << bit); 3438 --sc->num_vlans; 3439 em_if_vlan_filter_write(sc); 3440 } 3441 3442 static bool 3443 em_if_vlan_filter_capable(if_ctx_t ctx) 3444 { 3445 if_t ifp = iflib_get_ifp(ctx); 3446 3447 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3448 !em_disable_crc_stripping) 3449 return (true); 3450 3451 return (false); 3452 } 3453 3454 static bool 3455 em_if_vlan_filter_used(if_ctx_t ctx) 3456 { 3457 struct e1000_softc *sc = iflib_get_softc(ctx); 3458 3459 if (!em_if_vlan_filter_capable(ctx)) 3460 return (false); 3461 3462 for (int i = 0; i < EM_VFTA_SIZE; i++) 3463 if (sc->shadow_vfta[i] != 0) 3464 return (true); 3465 3466 return (false); 3467 } 3468 3469 static void 3470 em_if_vlan_filter_enable(struct e1000_softc *sc) 3471 { 3472 struct e1000_hw *hw = &sc->hw; 3473 u32 reg; 3474 3475 reg = E1000_READ_REG(hw, E1000_RCTL); 3476 reg &= ~E1000_RCTL_CFIEN; 3477 reg |= E1000_RCTL_VFE; 3478 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3479 } 3480 3481 static void 3482 em_if_vlan_filter_disable(struct e1000_softc *sc) 3483 { 3484 struct e1000_hw *hw = &sc->hw; 3485 u32 reg; 3486 3487 reg = E1000_READ_REG(hw, E1000_RCTL); 3488 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3489 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3490 } 3491 3492 static void 3493 em_if_vlan_filter_write(struct e1000_softc *sc) 3494 { 3495 struct e1000_hw *hw = &sc->hw; 3496 3497 if (sc->vf_ifp) 3498 return; 3499 3500 /* Disable interrupts for lem-class devices during the filter change */ 3501 if (hw->mac.type < em_mac_min) 3502 em_if_intr_disable(sc->ctx); 3503 3504 for (int i = 0; i < EM_VFTA_SIZE; i++) 3505 if (sc->shadow_vfta[i] != 0) { 3506 /* XXXKB: incomplete VF support, we return early above */ 3507 if (sc->vf_ifp) 3508 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3509 else 3510 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3511 } 3512 3513 /* Re-enable interrupts for lem-class devices */ 3514 if (hw->mac.type < em_mac_min) 3515 em_if_intr_enable(sc->ctx); 3516 } 3517 3518 static void 3519 em_setup_vlan_hw_support(if_ctx_t ctx) 3520 { 3521 struct e1000_softc *sc = iflib_get_softc(ctx); 3522 struct e1000_hw *hw = &sc->hw; 3523 if_t ifp = iflib_get_ifp(ctx); 3524 u32 reg; 3525 3526 /* XXXKB: Return early if we are a VF until VF decap and filter management 3527 * is ready and tested. 3528 */ 3529 if (sc->vf_ifp) 3530 return; 3531 3532 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3533 !em_disable_crc_stripping) { 3534 reg = E1000_READ_REG(hw, E1000_CTRL); 3535 reg |= E1000_CTRL_VME; 3536 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3537 } else { 3538 reg = E1000_READ_REG(hw, E1000_CTRL); 3539 reg &= ~E1000_CTRL_VME; 3540 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3541 } 3542 3543 /* If we aren't doing HW filtering, we're done */ 3544 if (!em_if_vlan_filter_capable(ctx)) { 3545 em_if_vlan_filter_disable(sc); 3546 return; 3547 } 3548 3549 /* 3550 * A soft reset zero's out the VFTA, so 3551 * we need to repopulate it now. 3552 */ 3553 em_if_vlan_filter_write(sc); 3554 3555 /* Enable the Filter Table */ 3556 em_if_vlan_filter_enable(sc); 3557 } 3558 3559 static void 3560 em_if_intr_enable(if_ctx_t ctx) 3561 { 3562 struct e1000_softc *sc = iflib_get_softc(ctx); 3563 struct e1000_hw *hw = &sc->hw; 3564 u32 ims_mask = IMS_ENABLE_MASK; 3565 3566 if (sc->intr_type == IFLIB_INTR_MSIX) { 3567 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3568 ims_mask |= sc->ims; 3569 } 3570 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3571 E1000_WRITE_FLUSH(hw); 3572 } 3573 3574 static void 3575 em_if_intr_disable(if_ctx_t ctx) 3576 { 3577 struct e1000_softc *sc = iflib_get_softc(ctx); 3578 struct e1000_hw *hw = &sc->hw; 3579 3580 if (sc->intr_type == IFLIB_INTR_MSIX) 3581 E1000_WRITE_REG(hw, EM_EIAC, 0); 3582 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3583 E1000_WRITE_FLUSH(hw); 3584 } 3585 3586 static void 3587 igb_if_intr_enable(if_ctx_t ctx) 3588 { 3589 struct e1000_softc *sc = iflib_get_softc(ctx); 3590 struct e1000_hw *hw = &sc->hw; 3591 u32 mask; 3592 3593 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3594 mask = (sc->que_mask | sc->link_mask); 3595 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3596 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3597 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3598 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3599 } else 3600 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3601 E1000_WRITE_FLUSH(hw); 3602 } 3603 3604 static void 3605 igb_if_intr_disable(if_ctx_t ctx) 3606 { 3607 struct e1000_softc *sc = iflib_get_softc(ctx); 3608 struct e1000_hw *hw = &sc->hw; 3609 3610 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3611 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3612 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3613 } 3614 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3615 E1000_WRITE_FLUSH(hw); 3616 } 3617 3618 /* 3619 * Bit of a misnomer, what this really means is 3620 * to enable OS management of the system... aka 3621 * to disable special hardware management features 3622 */ 3623 static void 3624 em_init_manageability(struct e1000_softc *sc) 3625 { 3626 /* A shared code workaround */ 3627 #define E1000_82542_MANC2H E1000_MANC2H 3628 if (sc->has_manage) { 3629 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3630 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3631 3632 /* disable hardware interception of ARP */ 3633 manc &= ~(E1000_MANC_ARP_EN); 3634 3635 /* enable receiving management packets to the host */ 3636 manc |= E1000_MANC_EN_MNG2HOST; 3637 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3638 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3639 manc2h |= E1000_MNG2HOST_PORT_623; 3640 manc2h |= E1000_MNG2HOST_PORT_664; 3641 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3642 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3643 } 3644 } 3645 3646 /* 3647 * Give control back to hardware management 3648 * controller if there is one. 3649 */ 3650 static void 3651 em_release_manageability(struct e1000_softc *sc) 3652 { 3653 if (sc->has_manage) { 3654 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3655 3656 /* re-enable hardware interception of ARP */ 3657 manc |= E1000_MANC_ARP_EN; 3658 manc &= ~E1000_MANC_EN_MNG2HOST; 3659 3660 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3661 } 3662 } 3663 3664 /* 3665 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3666 * For ASF and Pass Through versions of f/w this means 3667 * that the driver is loaded. For AMT version type f/w 3668 * this means that the network i/f is open. 3669 */ 3670 static void 3671 em_get_hw_control(struct e1000_softc *sc) 3672 { 3673 u32 ctrl_ext, swsm; 3674 3675 if (sc->vf_ifp) 3676 return; 3677 3678 if (sc->hw.mac.type == e1000_82573) { 3679 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3680 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3681 swsm | E1000_SWSM_DRV_LOAD); 3682 return; 3683 } 3684 /* else */ 3685 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3686 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3687 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3688 } 3689 3690 /* 3691 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3692 * For ASF and Pass Through versions of f/w this means that 3693 * the driver is no longer loaded. For AMT versions of the 3694 * f/w this means that the network i/f is closed. 3695 */ 3696 static void 3697 em_release_hw_control(struct e1000_softc *sc) 3698 { 3699 u32 ctrl_ext, swsm; 3700 3701 if (!sc->has_manage) 3702 return; 3703 3704 if (sc->hw.mac.type == e1000_82573) { 3705 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3706 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3707 swsm & ~E1000_SWSM_DRV_LOAD); 3708 return; 3709 } 3710 /* else */ 3711 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3712 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3713 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3714 return; 3715 } 3716 3717 static int 3718 em_is_valid_ether_addr(u8 *addr) 3719 { 3720 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3721 3722 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3723 return (false); 3724 } 3725 3726 return (true); 3727 } 3728 3729 /* 3730 ** Parse the interface capabilities with regard 3731 ** to both system management and wake-on-lan for 3732 ** later use. 3733 */ 3734 static void 3735 em_get_wakeup(if_ctx_t ctx) 3736 { 3737 struct e1000_softc *sc = iflib_get_softc(ctx); 3738 device_t dev = iflib_get_dev(ctx); 3739 u16 eeprom_data = 0, device_id, apme_mask; 3740 3741 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3742 apme_mask = EM_EEPROM_APME; 3743 3744 switch (sc->hw.mac.type) { 3745 case e1000_82542: 3746 case e1000_82543: 3747 break; 3748 case e1000_82544: 3749 e1000_read_nvm(&sc->hw, 3750 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3751 apme_mask = EM_82544_APME; 3752 break; 3753 case e1000_82546: 3754 case e1000_82546_rev_3: 3755 if (sc->hw.bus.func == 1) { 3756 e1000_read_nvm(&sc->hw, 3757 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3758 break; 3759 } else 3760 e1000_read_nvm(&sc->hw, 3761 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3762 break; 3763 case e1000_82573: 3764 case e1000_82583: 3765 sc->has_amt = true; 3766 /* FALLTHROUGH */ 3767 case e1000_82571: 3768 case e1000_82572: 3769 case e1000_80003es2lan: 3770 if (sc->hw.bus.func == 1) { 3771 e1000_read_nvm(&sc->hw, 3772 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3773 break; 3774 } else 3775 e1000_read_nvm(&sc->hw, 3776 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3777 break; 3778 case e1000_ich8lan: 3779 case e1000_ich9lan: 3780 case e1000_ich10lan: 3781 case e1000_pchlan: 3782 case e1000_pch2lan: 3783 case e1000_pch_lpt: 3784 case e1000_pch_spt: 3785 case e1000_82575: /* listing all igb devices */ 3786 case e1000_82576: 3787 case e1000_82580: 3788 case e1000_i350: 3789 case e1000_i354: 3790 case e1000_i210: 3791 case e1000_i211: 3792 case e1000_vfadapt: 3793 case e1000_vfadapt_i350: 3794 apme_mask = E1000_WUC_APME; 3795 sc->has_amt = true; 3796 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 3797 break; 3798 default: 3799 e1000_read_nvm(&sc->hw, 3800 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3801 break; 3802 } 3803 if (eeprom_data & apme_mask) 3804 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3805 /* 3806 * We have the eeprom settings, now apply the special cases 3807 * where the eeprom may be wrong or the board won't support 3808 * wake on lan on a particular port 3809 */ 3810 device_id = pci_get_device(dev); 3811 switch (device_id) { 3812 case E1000_DEV_ID_82546GB_PCIE: 3813 sc->wol = 0; 3814 break; 3815 case E1000_DEV_ID_82546EB_FIBER: 3816 case E1000_DEV_ID_82546GB_FIBER: 3817 /* Wake events only supported on port A for dual fiber 3818 * regardless of eeprom setting */ 3819 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3820 E1000_STATUS_FUNC_1) 3821 sc->wol = 0; 3822 break; 3823 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3824 /* if quad port adapter, disable WoL on all but port A */ 3825 if (global_quad_port_a != 0) 3826 sc->wol = 0; 3827 /* Reset for multiple quad port adapters */ 3828 if (++global_quad_port_a == 4) 3829 global_quad_port_a = 0; 3830 break; 3831 case E1000_DEV_ID_82571EB_FIBER: 3832 /* Wake events only supported on port A for dual fiber 3833 * regardless of eeprom setting */ 3834 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3835 E1000_STATUS_FUNC_1) 3836 sc->wol = 0; 3837 break; 3838 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3839 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3840 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3841 /* if quad port adapter, disable WoL on all but port A */ 3842 if (global_quad_port_a != 0) 3843 sc->wol = 0; 3844 /* Reset for multiple quad port adapters */ 3845 if (++global_quad_port_a == 4) 3846 global_quad_port_a = 0; 3847 break; 3848 } 3849 return; 3850 } 3851 3852 3853 /* 3854 * Enable PCI Wake On Lan capability 3855 */ 3856 static void 3857 em_enable_wakeup(if_ctx_t ctx) 3858 { 3859 struct e1000_softc *sc = iflib_get_softc(ctx); 3860 device_t dev = iflib_get_dev(ctx); 3861 if_t ifp = iflib_get_ifp(ctx); 3862 int error = 0; 3863 u32 pmc, ctrl, ctrl_ext, rctl; 3864 u16 status; 3865 3866 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3867 return; 3868 3869 /* 3870 * Determine type of Wakeup: note that wol 3871 * is set with all bits on by default. 3872 */ 3873 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3874 sc->wol &= ~E1000_WUFC_MAG; 3875 3876 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3877 sc->wol &= ~E1000_WUFC_EX; 3878 3879 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3880 sc->wol &= ~E1000_WUFC_MC; 3881 else { 3882 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 3883 rctl |= E1000_RCTL_MPE; 3884 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 3885 } 3886 3887 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3888 goto pme; 3889 3890 /* Advertise the wakeup capability */ 3891 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 3892 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3893 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 3894 3895 /* Keep the laser running on Fiber adapters */ 3896 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3897 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3898 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3899 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3900 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 3901 } 3902 3903 if ((sc->hw.mac.type == e1000_ich8lan) || 3904 (sc->hw.mac.type == e1000_pchlan) || 3905 (sc->hw.mac.type == e1000_ich9lan) || 3906 (sc->hw.mac.type == e1000_ich10lan)) 3907 e1000_suspend_workarounds_ich8lan(&sc->hw); 3908 3909 if ( sc->hw.mac.type >= e1000_pchlan) { 3910 error = em_enable_phy_wakeup(sc); 3911 if (error) 3912 goto pme; 3913 } else { 3914 /* Enable wakeup by the MAC */ 3915 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 3916 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 3917 } 3918 3919 if (sc->hw.phy.type == e1000_phy_igp_3) 3920 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 3921 3922 pme: 3923 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3924 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3925 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3926 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3927 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3928 3929 return; 3930 } 3931 3932 /* 3933 * WOL in the newer chipset interfaces (pchlan) 3934 * require thing to be copied into the phy 3935 */ 3936 static int 3937 em_enable_phy_wakeup(struct e1000_softc *sc) 3938 { 3939 struct e1000_hw *hw = &sc->hw; 3940 u32 mreg, ret = 0; 3941 u16 preg; 3942 3943 /* copy MAC RARs to PHY RARs */ 3944 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3945 3946 /* copy MAC MTA to PHY MTA */ 3947 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 3948 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3949 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3950 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3951 (u16)((mreg >> 16) & 0xFFFF)); 3952 } 3953 3954 /* configure PHY Rx Control register */ 3955 e1000_read_phy_reg(hw, BM_RCTL, &preg); 3956 mreg = E1000_READ_REG(hw, E1000_RCTL); 3957 if (mreg & E1000_RCTL_UPE) 3958 preg |= BM_RCTL_UPE; 3959 if (mreg & E1000_RCTL_MPE) 3960 preg |= BM_RCTL_MPE; 3961 preg &= ~(BM_RCTL_MO_MASK); 3962 if (mreg & E1000_RCTL_MO_3) 3963 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3964 << BM_RCTL_MO_SHIFT); 3965 if (mreg & E1000_RCTL_BAM) 3966 preg |= BM_RCTL_BAM; 3967 if (mreg & E1000_RCTL_PMCF) 3968 preg |= BM_RCTL_PMCF; 3969 mreg = E1000_READ_REG(hw, E1000_CTRL); 3970 if (mreg & E1000_CTRL_RFCE) 3971 preg |= BM_RCTL_RFCE; 3972 e1000_write_phy_reg(hw, BM_RCTL, preg); 3973 3974 /* enable PHY wakeup in MAC register */ 3975 E1000_WRITE_REG(hw, E1000_WUC, 3976 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3977 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 3978 3979 /* configure and enable PHY wakeup in PHY registers */ 3980 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 3981 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 3982 3983 /* activate PHY wakeup */ 3984 ret = hw->phy.ops.acquire(hw); 3985 if (ret) { 3986 printf("Could not acquire PHY\n"); 3987 return ret; 3988 } 3989 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3990 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3991 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3992 if (ret) { 3993 printf("Could not read PHY page 769\n"); 3994 goto out; 3995 } 3996 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3997 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3998 if (ret) 3999 printf("Could not set PHY Host Wakeup bit\n"); 4000 out: 4001 hw->phy.ops.release(hw); 4002 4003 return ret; 4004 } 4005 4006 static void 4007 em_if_led_func(if_ctx_t ctx, int onoff) 4008 { 4009 struct e1000_softc *sc = iflib_get_softc(ctx); 4010 4011 if (onoff) { 4012 e1000_setup_led(&sc->hw); 4013 e1000_led_on(&sc->hw); 4014 } else { 4015 e1000_led_off(&sc->hw); 4016 e1000_cleanup_led(&sc->hw); 4017 } 4018 } 4019 4020 /* 4021 * Disable the L0S and L1 LINK states 4022 */ 4023 static void 4024 em_disable_aspm(struct e1000_softc *sc) 4025 { 4026 int base, reg; 4027 u16 link_cap,link_ctrl; 4028 device_t dev = sc->dev; 4029 4030 switch (sc->hw.mac.type) { 4031 case e1000_82573: 4032 case e1000_82574: 4033 case e1000_82583: 4034 break; 4035 default: 4036 return; 4037 } 4038 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4039 return; 4040 reg = base + PCIER_LINK_CAP; 4041 link_cap = pci_read_config(dev, reg, 2); 4042 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4043 return; 4044 reg = base + PCIER_LINK_CTL; 4045 link_ctrl = pci_read_config(dev, reg, 2); 4046 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4047 pci_write_config(dev, reg, link_ctrl, 2); 4048 return; 4049 } 4050 4051 /********************************************************************** 4052 * 4053 * Update the board statistics counters. 4054 * 4055 **********************************************************************/ 4056 static void 4057 em_update_stats_counters(struct e1000_softc *sc) 4058 { 4059 u64 prev_xoffrxc = sc->stats.xoffrxc; 4060 4061 if(sc->hw.phy.media_type == e1000_media_type_copper || 4062 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4063 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4064 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4065 } 4066 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4067 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4068 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4069 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4070 4071 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4072 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4073 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4074 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4075 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4076 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4077 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4078 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4079 /* 4080 ** For watchdog management we need to know if we have been 4081 ** paused during the last interval, so capture that here. 4082 */ 4083 if (sc->stats.xoffrxc != prev_xoffrxc) 4084 sc->shared->isc_pause_frames = 1; 4085 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4086 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4087 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4088 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4089 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4090 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4091 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4092 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4093 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4094 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4095 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4096 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4097 4098 /* For the 64-bit byte counters the low dword must be read first. */ 4099 /* Both registers clear on the read of the high dword */ 4100 4101 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4102 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4103 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4104 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4105 4106 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4107 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4108 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4109 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4110 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4111 4112 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4113 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4114 4115 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4116 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4117 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4118 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4119 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4120 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4121 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4122 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4123 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4124 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4125 4126 /* Interrupt Counts */ 4127 4128 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4129 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4130 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4131 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4132 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4133 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4134 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4135 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4136 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4137 4138 if (sc->hw.mac.type >= e1000_82543) { 4139 sc->stats.algnerrc += 4140 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4141 sc->stats.rxerrc += 4142 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4143 sc->stats.tncrs += 4144 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4145 sc->stats.cexterr += 4146 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4147 sc->stats.tsctc += 4148 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4149 sc->stats.tsctfc += 4150 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4151 } 4152 } 4153 4154 static uint64_t 4155 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4156 { 4157 struct e1000_softc *sc = iflib_get_softc(ctx); 4158 if_t ifp = iflib_get_ifp(ctx); 4159 4160 switch (cnt) { 4161 case IFCOUNTER_COLLISIONS: 4162 return (sc->stats.colc); 4163 case IFCOUNTER_IERRORS: 4164 return (sc->dropped_pkts + sc->stats.rxerrc + 4165 sc->stats.crcerrs + sc->stats.algnerrc + 4166 sc->stats.ruc + sc->stats.roc + 4167 sc->stats.mpc + sc->stats.cexterr); 4168 case IFCOUNTER_OERRORS: 4169 return (sc->stats.ecol + sc->stats.latecol + 4170 sc->watchdog_events); 4171 default: 4172 return (if_get_counter_default(ifp, cnt)); 4173 } 4174 } 4175 4176 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4177 * @ctx: iflib context 4178 * @event: event code to check 4179 * 4180 * Defaults to returning true for unknown events. 4181 * 4182 * @returns true if iflib needs to reinit the interface 4183 */ 4184 static bool 4185 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4186 { 4187 switch (event) { 4188 case IFLIB_RESTART_VLAN_CONFIG: 4189 return (false); 4190 default: 4191 return (true); 4192 } 4193 } 4194 4195 /* Export a single 32-bit register via a read-only sysctl. */ 4196 static int 4197 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4198 { 4199 struct e1000_softc *sc; 4200 u_int val; 4201 4202 sc = oidp->oid_arg1; 4203 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4204 return (sysctl_handle_int(oidp, &val, 0, req)); 4205 } 4206 4207 /* 4208 * Add sysctl variables, one per statistic, to the system. 4209 */ 4210 static void 4211 em_add_hw_stats(struct e1000_softc *sc) 4212 { 4213 device_t dev = iflib_get_dev(sc->ctx); 4214 struct em_tx_queue *tx_que = sc->tx_queues; 4215 struct em_rx_queue *rx_que = sc->rx_queues; 4216 4217 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4218 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4219 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4220 struct e1000_hw_stats *stats = &sc->stats; 4221 4222 struct sysctl_oid *stat_node, *queue_node, *int_node; 4223 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4224 4225 #define QUEUE_NAME_LEN 32 4226 char namebuf[QUEUE_NAME_LEN]; 4227 4228 /* Driver Statistics */ 4229 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4230 CTLFLAG_RD, &sc->dropped_pkts, 4231 "Driver dropped packets"); 4232 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4233 CTLFLAG_RD, &sc->link_irq, 4234 "Link MSI-X IRQ Handled"); 4235 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4236 CTLFLAG_RD, &sc->rx_overruns, 4237 "RX overruns"); 4238 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4239 CTLFLAG_RD, &sc->watchdog_events, 4240 "Watchdog timeouts"); 4241 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4242 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4243 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4244 "Device Control Register"); 4245 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4246 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4247 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4248 "Receiver Control Register"); 4249 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4250 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4251 "Flow Control High Watermark"); 4252 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4253 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4254 "Flow Control Low Watermark"); 4255 4256 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4257 struct tx_ring *txr = &tx_que->txr; 4258 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4259 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4260 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4261 queue_list = SYSCTL_CHILDREN(queue_node); 4262 4263 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4264 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4265 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4266 "Transmit Descriptor Head"); 4267 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4268 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4269 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4270 "Transmit Descriptor Tail"); 4271 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4272 CTLFLAG_RD, &txr->tx_irq, 4273 "Queue MSI-X Transmit Interrupts"); 4274 } 4275 4276 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4277 struct rx_ring *rxr = &rx_que->rxr; 4278 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4279 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4280 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4281 queue_list = SYSCTL_CHILDREN(queue_node); 4282 4283 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4284 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4285 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4286 "Receive Descriptor Head"); 4287 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4288 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4289 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4290 "Receive Descriptor Tail"); 4291 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4292 CTLFLAG_RD, &rxr->rx_irq, 4293 "Queue MSI-X Receive Interrupts"); 4294 } 4295 4296 /* MAC stats get their own sub node */ 4297 4298 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4299 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4300 stat_list = SYSCTL_CHILDREN(stat_node); 4301 4302 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4303 CTLFLAG_RD, &stats->ecol, 4304 "Excessive collisions"); 4305 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4306 CTLFLAG_RD, &stats->scc, 4307 "Single collisions"); 4308 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4309 CTLFLAG_RD, &stats->mcc, 4310 "Multiple collisions"); 4311 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4312 CTLFLAG_RD, &stats->latecol, 4313 "Late collisions"); 4314 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4315 CTLFLAG_RD, &stats->colc, 4316 "Collision Count"); 4317 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4318 CTLFLAG_RD, &sc->stats.symerrs, 4319 "Symbol Errors"); 4320 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4321 CTLFLAG_RD, &sc->stats.sec, 4322 "Sequence Errors"); 4323 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4324 CTLFLAG_RD, &sc->stats.dc, 4325 "Defer Count"); 4326 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4327 CTLFLAG_RD, &sc->stats.mpc, 4328 "Missed Packets"); 4329 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4330 CTLFLAG_RD, &sc->stats.rnbc, 4331 "Receive No Buffers"); 4332 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4333 CTLFLAG_RD, &sc->stats.ruc, 4334 "Receive Undersize"); 4335 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4336 CTLFLAG_RD, &sc->stats.rfc, 4337 "Fragmented Packets Received "); 4338 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4339 CTLFLAG_RD, &sc->stats.roc, 4340 "Oversized Packets Received"); 4341 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4342 CTLFLAG_RD, &sc->stats.rjc, 4343 "Recevied Jabber"); 4344 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4345 CTLFLAG_RD, &sc->stats.rxerrc, 4346 "Receive Errors"); 4347 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4348 CTLFLAG_RD, &sc->stats.crcerrs, 4349 "CRC errors"); 4350 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4351 CTLFLAG_RD, &sc->stats.algnerrc, 4352 "Alignment Errors"); 4353 /* On 82575 these are collision counts */ 4354 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4355 CTLFLAG_RD, &sc->stats.cexterr, 4356 "Collision/Carrier extension errors"); 4357 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4358 CTLFLAG_RD, &sc->stats.xonrxc, 4359 "XON Received"); 4360 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4361 CTLFLAG_RD, &sc->stats.xontxc, 4362 "XON Transmitted"); 4363 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4364 CTLFLAG_RD, &sc->stats.xoffrxc, 4365 "XOFF Received"); 4366 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4367 CTLFLAG_RD, &sc->stats.xofftxc, 4368 "XOFF Transmitted"); 4369 4370 /* Packet Reception Stats */ 4371 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4372 CTLFLAG_RD, &sc->stats.tpr, 4373 "Total Packets Received "); 4374 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4375 CTLFLAG_RD, &sc->stats.gprc, 4376 "Good Packets Received"); 4377 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4378 CTLFLAG_RD, &sc->stats.bprc, 4379 "Broadcast Packets Received"); 4380 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4381 CTLFLAG_RD, &sc->stats.mprc, 4382 "Multicast Packets Received"); 4383 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4384 CTLFLAG_RD, &sc->stats.prc64, 4385 "64 byte frames received "); 4386 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4387 CTLFLAG_RD, &sc->stats.prc127, 4388 "65-127 byte frames received"); 4389 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4390 CTLFLAG_RD, &sc->stats.prc255, 4391 "128-255 byte frames received"); 4392 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4393 CTLFLAG_RD, &sc->stats.prc511, 4394 "256-511 byte frames received"); 4395 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4396 CTLFLAG_RD, &sc->stats.prc1023, 4397 "512-1023 byte frames received"); 4398 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4399 CTLFLAG_RD, &sc->stats.prc1522, 4400 "1023-1522 byte frames received"); 4401 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4402 CTLFLAG_RD, &sc->stats.gorc, 4403 "Good Octets Received"); 4404 4405 /* Packet Transmission Stats */ 4406 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4407 CTLFLAG_RD, &sc->stats.gotc, 4408 "Good Octets Transmitted"); 4409 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4410 CTLFLAG_RD, &sc->stats.tpt, 4411 "Total Packets Transmitted"); 4412 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4413 CTLFLAG_RD, &sc->stats.gptc, 4414 "Good Packets Transmitted"); 4415 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4416 CTLFLAG_RD, &sc->stats.bptc, 4417 "Broadcast Packets Transmitted"); 4418 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4419 CTLFLAG_RD, &sc->stats.mptc, 4420 "Multicast Packets Transmitted"); 4421 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4422 CTLFLAG_RD, &sc->stats.ptc64, 4423 "64 byte frames transmitted "); 4424 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4425 CTLFLAG_RD, &sc->stats.ptc127, 4426 "65-127 byte frames transmitted"); 4427 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4428 CTLFLAG_RD, &sc->stats.ptc255, 4429 "128-255 byte frames transmitted"); 4430 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4431 CTLFLAG_RD, &sc->stats.ptc511, 4432 "256-511 byte frames transmitted"); 4433 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4434 CTLFLAG_RD, &sc->stats.ptc1023, 4435 "512-1023 byte frames transmitted"); 4436 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4437 CTLFLAG_RD, &sc->stats.ptc1522, 4438 "1024-1522 byte frames transmitted"); 4439 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4440 CTLFLAG_RD, &sc->stats.tsctc, 4441 "TSO Contexts Transmitted"); 4442 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4443 CTLFLAG_RD, &sc->stats.tsctfc, 4444 "TSO Contexts Failed"); 4445 4446 4447 /* Interrupt Stats */ 4448 4449 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4450 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4451 int_list = SYSCTL_CHILDREN(int_node); 4452 4453 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4454 CTLFLAG_RD, &sc->stats.iac, 4455 "Interrupt Assertion Count"); 4456 4457 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4458 CTLFLAG_RD, &sc->stats.icrxptc, 4459 "Interrupt Cause Rx Pkt Timer Expire Count"); 4460 4461 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4462 CTLFLAG_RD, &sc->stats.icrxatc, 4463 "Interrupt Cause Rx Abs Timer Expire Count"); 4464 4465 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4466 CTLFLAG_RD, &sc->stats.ictxptc, 4467 "Interrupt Cause Tx Pkt Timer Expire Count"); 4468 4469 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4470 CTLFLAG_RD, &sc->stats.ictxatc, 4471 "Interrupt Cause Tx Abs Timer Expire Count"); 4472 4473 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4474 CTLFLAG_RD, &sc->stats.ictxqec, 4475 "Interrupt Cause Tx Queue Empty Count"); 4476 4477 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4478 CTLFLAG_RD, &sc->stats.ictxqmtc, 4479 "Interrupt Cause Tx Queue Min Thresh Count"); 4480 4481 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4482 CTLFLAG_RD, &sc->stats.icrxdmtc, 4483 "Interrupt Cause Rx Desc Min Thresh Count"); 4484 4485 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4486 CTLFLAG_RD, &sc->stats.icrxoc, 4487 "Interrupt Cause Receiver Overrun Count"); 4488 } 4489 4490 static void 4491 em_fw_version_locked(if_ctx_t ctx) 4492 { 4493 struct e1000_softc *sc = iflib_get_softc(ctx); 4494 struct e1000_hw *hw = &sc->hw; 4495 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4496 uint16_t eep = 0; 4497 4498 /* 4499 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4500 * NVM locking model, so we do it in em_if_attach_pre() and store the 4501 * info in the softc 4502 */ 4503 ASSERT_CTX_LOCK_HELD(hw); 4504 4505 *fw_ver = (struct e1000_fw_version){0}; 4506 4507 if (hw->mac.type >= igb_mac_min) { 4508 /* 4509 * Use the Shared Code for igb(4) 4510 */ 4511 e1000_get_fw_version(hw, fw_ver); 4512 } else { 4513 /* 4514 * Otherwise, EEPROM version should be present on (almost?) all 4515 * devices here 4516 */ 4517 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4518 INIT_DEBUGOUT("can't get EEPROM version"); 4519 return; 4520 } 4521 4522 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4523 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4524 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4525 } 4526 } 4527 4528 static void 4529 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4530 { 4531 const char *space = ""; 4532 4533 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4534 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4535 fw_ver->eep_minor, fw_ver->eep_build); 4536 space = " "; 4537 } 4538 4539 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4540 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4541 space, fw_ver->invm_major, fw_ver->invm_minor, 4542 fw_ver->invm_img_type); 4543 space = " "; 4544 } 4545 4546 if (fw_ver->or_valid) { 4547 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4548 space, fw_ver->or_major, fw_ver->or_build, 4549 fw_ver->or_patch); 4550 space = " "; 4551 } 4552 4553 if (fw_ver->etrack_id) 4554 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4555 } 4556 4557 static void 4558 em_print_fw_version(struct e1000_softc *sc ) 4559 { 4560 device_t dev = sc->dev; 4561 struct sbuf *buf; 4562 int error = 0; 4563 4564 buf = sbuf_new_auto(); 4565 if (!buf) { 4566 device_printf(dev, "Could not allocate sbuf for output.\n"); 4567 return; 4568 } 4569 4570 em_sbuf_fw_version(&sc->fw_ver, buf); 4571 4572 error = sbuf_finish(buf); 4573 if (error) 4574 device_printf(dev, "Error finishing sbuf: %d\n", error); 4575 else if (sbuf_len(buf)) 4576 device_printf(dev, "%s\n", sbuf_data(buf)); 4577 4578 sbuf_delete(buf); 4579 } 4580 4581 static int 4582 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4583 { 4584 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4585 device_t dev = sc->dev; 4586 struct sbuf *buf; 4587 int error = 0; 4588 4589 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4590 if (!buf) { 4591 device_printf(dev, "Could not allocate sbuf for output.\n"); 4592 return (ENOMEM); 4593 } 4594 4595 em_sbuf_fw_version(&sc->fw_ver, buf); 4596 4597 error = sbuf_finish(buf); 4598 if (error) 4599 device_printf(dev, "Error finishing sbuf: %d\n", error); 4600 4601 sbuf_delete(buf); 4602 4603 return (0); 4604 } 4605 4606 /********************************************************************** 4607 * 4608 * This routine provides a way to dump out the adapter eeprom, 4609 * often a useful debug/service tool. This only dumps the first 4610 * 32 words, stuff that matters is in that extent. 4611 * 4612 **********************************************************************/ 4613 static int 4614 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4615 { 4616 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4617 int error; 4618 int result; 4619 4620 result = -1; 4621 error = sysctl_handle_int(oidp, &result, 0, req); 4622 4623 if (error || !req->newptr) 4624 return (error); 4625 4626 /* 4627 * This value will cause a hex dump of the 4628 * first 32 16-bit words of the EEPROM to 4629 * the screen. 4630 */ 4631 if (result == 1) 4632 em_print_nvm_info(sc); 4633 4634 return (error); 4635 } 4636 4637 static void 4638 em_print_nvm_info(struct e1000_softc *sc) 4639 { 4640 struct e1000_hw *hw = &sc->hw; 4641 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4642 u16 eeprom_data; 4643 int i, j, row = 0; 4644 4645 /* Its a bit crude, but it gets the job done */ 4646 printf("\nInterface EEPROM Dump:\n"); 4647 printf("Offset\n0x0000 "); 4648 4649 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4650 sx_xlock(iflib_ctx_lock); 4651 ASSERT_CTX_LOCK_HELD(hw); 4652 for (i = 0, j = 0; i < 32; i++, j++) { 4653 if (j == 8) { /* Make the offset block */ 4654 j = 0; ++row; 4655 printf("\n0x00%x0 ",row); 4656 } 4657 e1000_read_nvm(hw, i, 1, &eeprom_data); 4658 printf("%04x ", eeprom_data); 4659 } 4660 sx_xunlock(iflib_ctx_lock); 4661 printf("\n"); 4662 } 4663 4664 static int 4665 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4666 { 4667 struct em_int_delay_info *info; 4668 struct e1000_softc *sc; 4669 u32 regval; 4670 int error, usecs, ticks; 4671 4672 info = (struct em_int_delay_info *) arg1; 4673 usecs = info->value; 4674 error = sysctl_handle_int(oidp, &usecs, 0, req); 4675 if (error != 0 || req->newptr == NULL) 4676 return (error); 4677 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4678 return (EINVAL); 4679 info->value = usecs; 4680 ticks = EM_USECS_TO_TICKS(usecs); 4681 if (info->offset == E1000_ITR) /* units are 256ns here */ 4682 ticks *= 4; 4683 4684 sc = info->sc; 4685 4686 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4687 regval = (regval & ~0xffff) | (ticks & 0xffff); 4688 /* Handle a few special cases. */ 4689 switch (info->offset) { 4690 case E1000_RDTR: 4691 break; 4692 case E1000_TIDV: 4693 if (ticks == 0) { 4694 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4695 /* Don't write 0 into the TIDV register. */ 4696 regval++; 4697 } else 4698 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4699 break; 4700 } 4701 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4702 return (0); 4703 } 4704 4705 static void 4706 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4707 const char *description, struct em_int_delay_info *info, 4708 int offset, int value) 4709 { 4710 info->sc = sc; 4711 info->offset = offset; 4712 info->value = value; 4713 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4714 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4715 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4716 info, 0, em_sysctl_int_delay, "I", description); 4717 } 4718 4719 /* 4720 * Set flow control using sysctl: 4721 * Flow control values: 4722 * 0 - off 4723 * 1 - rx pause 4724 * 2 - tx pause 4725 * 3 - full 4726 */ 4727 static int 4728 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4729 { 4730 int error; 4731 static int input = 3; /* default is full */ 4732 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4733 4734 error = sysctl_handle_int(oidp, &input, 0, req); 4735 4736 if ((error) || (req->newptr == NULL)) 4737 return (error); 4738 4739 if (input == sc->fc) /* no change? */ 4740 return (error); 4741 4742 switch (input) { 4743 case e1000_fc_rx_pause: 4744 case e1000_fc_tx_pause: 4745 case e1000_fc_full: 4746 case e1000_fc_none: 4747 sc->hw.fc.requested_mode = input; 4748 sc->fc = input; 4749 break; 4750 default: 4751 /* Do nothing */ 4752 return (error); 4753 } 4754 4755 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4756 e1000_force_mac_fc(&sc->hw); 4757 return (error); 4758 } 4759 4760 /* 4761 * Manage Energy Efficient Ethernet: 4762 * Control values: 4763 * 0/1 - enabled/disabled 4764 */ 4765 static int 4766 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4767 { 4768 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4769 int error, value; 4770 4771 value = sc->hw.dev_spec.ich8lan.eee_disable; 4772 error = sysctl_handle_int(oidp, &value, 0, req); 4773 if (error || req->newptr == NULL) 4774 return (error); 4775 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4776 em_if_init(sc->ctx); 4777 4778 return (0); 4779 } 4780 4781 static int 4782 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4783 { 4784 struct e1000_softc *sc; 4785 int error; 4786 int result; 4787 4788 result = -1; 4789 error = sysctl_handle_int(oidp, &result, 0, req); 4790 4791 if (error || !req->newptr) 4792 return (error); 4793 4794 if (result == 1) { 4795 sc = (struct e1000_softc *) arg1; 4796 em_print_debug_info(sc); 4797 } 4798 4799 return (error); 4800 } 4801 4802 static int 4803 em_get_rs(SYSCTL_HANDLER_ARGS) 4804 { 4805 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4806 int error; 4807 int result; 4808 4809 result = 0; 4810 error = sysctl_handle_int(oidp, &result, 0, req); 4811 4812 if (error || !req->newptr || result != 1) 4813 return (error); 4814 em_dump_rs(sc); 4815 4816 return (error); 4817 } 4818 4819 static void 4820 em_if_debug(if_ctx_t ctx) 4821 { 4822 em_dump_rs(iflib_get_softc(ctx)); 4823 } 4824 4825 /* 4826 * This routine is meant to be fluid, add whatever is 4827 * needed for debugging a problem. -jfv 4828 */ 4829 static void 4830 em_print_debug_info(struct e1000_softc *sc) 4831 { 4832 device_t dev = iflib_get_dev(sc->ctx); 4833 if_t ifp = iflib_get_ifp(sc->ctx); 4834 struct tx_ring *txr = &sc->tx_queues->txr; 4835 struct rx_ring *rxr = &sc->rx_queues->rxr; 4836 4837 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4838 printf("Interface is RUNNING "); 4839 else 4840 printf("Interface is NOT RUNNING\n"); 4841 4842 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4843 printf("and INACTIVE\n"); 4844 else 4845 printf("and ACTIVE\n"); 4846 4847 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 4848 device_printf(dev, "TX Queue %d ------\n", i); 4849 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4850 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 4851 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 4852 4853 } 4854 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 4855 device_printf(dev, "RX Queue %d ------\n", j); 4856 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4857 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 4858 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 4859 } 4860 } 4861 4862 /* 4863 * 82574 only: 4864 * Write a new value to the EEPROM increasing the number of MSI-X 4865 * vectors from 3 to 5, for proper multiqueue support. 4866 */ 4867 static void 4868 em_enable_vectors_82574(if_ctx_t ctx) 4869 { 4870 struct e1000_softc *sc = iflib_get_softc(ctx); 4871 struct e1000_hw *hw = &sc->hw; 4872 device_t dev = iflib_get_dev(ctx); 4873 u16 edata; 4874 4875 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4876 if (bootverbose) 4877 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4878 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4879 device_printf(dev, "Writing to eeprom: increasing " 4880 "reported MSI-X vectors from 3 to 5...\n"); 4881 edata &= ~(EM_NVM_MSIX_N_MASK); 4882 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4883 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4884 e1000_update_nvm_checksum(hw); 4885 device_printf(dev, "Writing to eeprom: done\n"); 4886 } 4887 } 4888