1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.7.8-fbsd"; 41 char igb_driver_version[] = "2.5.19-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 57 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 58 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 61 62 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 63 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 65 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 66 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 68 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 69 70 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 71 72 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 73 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 74 75 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 76 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 78 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 79 80 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 81 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 84 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 85 86 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 88 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 95 96 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 97 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 98 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 99 100 /* Intel(R) - em-class devices */ 101 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 108 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 109 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 113 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 114 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 116 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 117 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 121 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 139 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 140 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 148 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 150 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 152 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 213 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 214 /* required last entry */ 215 PVID_END 216 }; 217 218 static pci_vendor_info_t igb_vendor_info_array[] = 219 { 220 /* Intel(R) - igb-class devices */ 221 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 222 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 224 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 226 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 227 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 232 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 233 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 234 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 238 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 242 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 244 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 246 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 247 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 251 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 253 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 254 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 256 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 257 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 260 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 261 /* required last entry */ 262 PVID_END 263 }; 264 265 /********************************************************************* 266 * Function prototypes 267 *********************************************************************/ 268 static void *em_register(device_t); 269 static void *igb_register(device_t); 270 static int em_if_attach_pre(if_ctx_t); 271 static int em_if_attach_post(if_ctx_t); 272 static int em_if_detach(if_ctx_t); 273 static int em_if_shutdown(if_ctx_t); 274 static int em_if_suspend(if_ctx_t); 275 static int em_if_resume(if_ctx_t); 276 277 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 279 static void em_if_queues_free(if_ctx_t); 280 281 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 282 static void em_if_init(if_ctx_t); 283 static void em_if_stop(if_ctx_t); 284 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 285 static int em_if_media_change(if_ctx_t); 286 static int em_if_mtu_set(if_ctx_t, uint32_t); 287 static void em_if_timer(if_ctx_t, uint16_t); 288 static void em_if_vlan_register(if_ctx_t, u16); 289 static void em_if_vlan_unregister(if_ctx_t, u16); 290 static void em_if_watchdog_reset(if_ctx_t); 291 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 292 293 static void em_identify_hardware(if_ctx_t); 294 static int em_allocate_pci_resources(if_ctx_t); 295 static void em_free_pci_resources(if_ctx_t); 296 static void em_reset(if_ctx_t); 297 static int em_setup_interface(if_ctx_t); 298 static int em_setup_msix(if_ctx_t); 299 300 static void em_initialize_transmit_unit(if_ctx_t); 301 static void em_initialize_receive_unit(if_ctx_t); 302 303 static void em_if_intr_enable(if_ctx_t); 304 static void em_if_intr_disable(if_ctx_t); 305 static void igb_if_intr_enable(if_ctx_t); 306 static void igb_if_intr_disable(if_ctx_t); 307 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 310 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 311 static void em_if_multi_set(if_ctx_t); 312 static void em_if_update_admin_status(if_ctx_t); 313 static void em_if_debug(if_ctx_t); 314 static void em_update_stats_counters(struct e1000_softc *); 315 static void em_add_hw_stats(struct e1000_softc *); 316 static int em_if_set_promisc(if_ctx_t, int); 317 static bool em_if_vlan_filter_capable(if_ctx_t); 318 static bool em_if_vlan_filter_used(if_ctx_t); 319 static void em_if_vlan_filter_enable(struct e1000_softc *); 320 static void em_if_vlan_filter_disable(struct e1000_softc *); 321 static void em_if_vlan_filter_write(struct e1000_softc *); 322 static void em_setup_vlan_hw_support(if_ctx_t ctx); 323 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 324 static void em_print_nvm_info(struct e1000_softc *); 325 static void em_fw_version_locked(if_ctx_t); 326 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 327 static void em_print_fw_version(struct e1000_softc *); 328 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 330 static int em_get_rs(SYSCTL_HANDLER_ARGS); 331 static void em_print_debug_info(struct e1000_softc *); 332 static int em_is_valid_ether_addr(u8 *); 333 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 334 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 335 const char *, struct em_int_delay_info *, int, int); 336 /* Management and WOL Support */ 337 static void em_init_manageability(struct e1000_softc *); 338 static void em_release_manageability(struct e1000_softc *); 339 static void em_get_hw_control(struct e1000_softc *); 340 static void em_release_hw_control(struct e1000_softc *); 341 static void em_get_wakeup(if_ctx_t); 342 static void em_enable_wakeup(if_ctx_t); 343 static int em_enable_phy_wakeup(struct e1000_softc *); 344 static void em_disable_aspm(struct e1000_softc *); 345 346 int em_intr(void *); 347 348 /* MSI-X handlers */ 349 static int em_if_msix_intr_assign(if_ctx_t, int); 350 static int em_msix_link(void *); 351 static void em_handle_link(void *); 352 353 static void em_enable_vectors_82574(if_ctx_t); 354 355 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 356 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 357 static void em_if_led_func(if_ctx_t, int); 358 359 static int em_get_regs(SYSCTL_HANDLER_ARGS); 360 361 static void lem_smartspeed(struct e1000_softc *); 362 static void igb_configure_queues(struct e1000_softc *); 363 static void em_flush_desc_rings(struct e1000_softc *); 364 365 366 /********************************************************************* 367 * FreeBSD Device Interface Entry Points 368 *********************************************************************/ 369 static device_method_t em_methods[] = { 370 /* Device interface */ 371 DEVMETHOD(device_register, em_register), 372 DEVMETHOD(device_probe, iflib_device_probe), 373 DEVMETHOD(device_attach, iflib_device_attach), 374 DEVMETHOD(device_detach, iflib_device_detach), 375 DEVMETHOD(device_shutdown, iflib_device_shutdown), 376 DEVMETHOD(device_suspend, iflib_device_suspend), 377 DEVMETHOD(device_resume, iflib_device_resume), 378 DEVMETHOD_END 379 }; 380 381 static device_method_t igb_methods[] = { 382 /* Device interface */ 383 DEVMETHOD(device_register, igb_register), 384 DEVMETHOD(device_probe, iflib_device_probe), 385 DEVMETHOD(device_attach, iflib_device_attach), 386 DEVMETHOD(device_detach, iflib_device_detach), 387 DEVMETHOD(device_shutdown, iflib_device_shutdown), 388 DEVMETHOD(device_suspend, iflib_device_suspend), 389 DEVMETHOD(device_resume, iflib_device_resume), 390 DEVMETHOD_END 391 }; 392 393 394 static driver_t em_driver = { 395 "em", em_methods, sizeof(struct e1000_softc), 396 }; 397 398 DRIVER_MODULE(em, pci, em_driver, 0, 0); 399 400 MODULE_DEPEND(em, pci, 1, 1, 1); 401 MODULE_DEPEND(em, ether, 1, 1, 1); 402 MODULE_DEPEND(em, iflib, 1, 1, 1); 403 404 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 405 406 static driver_t igb_driver = { 407 "igb", igb_methods, sizeof(struct e1000_softc), 408 }; 409 410 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 411 412 MODULE_DEPEND(igb, pci, 1, 1, 1); 413 MODULE_DEPEND(igb, ether, 1, 1, 1); 414 MODULE_DEPEND(igb, iflib, 1, 1, 1); 415 416 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 417 418 static device_method_t em_if_methods[] = { 419 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 420 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 421 DEVMETHOD(ifdi_detach, em_if_detach), 422 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 423 DEVMETHOD(ifdi_suspend, em_if_suspend), 424 DEVMETHOD(ifdi_resume, em_if_resume), 425 DEVMETHOD(ifdi_init, em_if_init), 426 DEVMETHOD(ifdi_stop, em_if_stop), 427 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 428 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 429 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 430 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 431 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 432 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 433 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 434 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 435 DEVMETHOD(ifdi_media_status, em_if_media_status), 436 DEVMETHOD(ifdi_media_change, em_if_media_change), 437 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 438 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 439 DEVMETHOD(ifdi_timer, em_if_timer), 440 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 441 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 442 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 443 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 444 DEVMETHOD(ifdi_led_func, em_if_led_func), 445 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 446 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 447 DEVMETHOD(ifdi_debug, em_if_debug), 448 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 449 DEVMETHOD_END 450 }; 451 452 static driver_t em_if_driver = { 453 "em_if", em_if_methods, sizeof(struct e1000_softc) 454 }; 455 456 static device_method_t igb_if_methods[] = { 457 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 458 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 459 DEVMETHOD(ifdi_detach, em_if_detach), 460 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 461 DEVMETHOD(ifdi_suspend, em_if_suspend), 462 DEVMETHOD(ifdi_resume, em_if_resume), 463 DEVMETHOD(ifdi_init, em_if_init), 464 DEVMETHOD(ifdi_stop, em_if_stop), 465 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 466 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 467 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 468 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 469 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 470 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 471 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 472 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 473 DEVMETHOD(ifdi_media_status, em_if_media_status), 474 DEVMETHOD(ifdi_media_change, em_if_media_change), 475 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 476 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 477 DEVMETHOD(ifdi_timer, em_if_timer), 478 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 479 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 480 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 481 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 482 DEVMETHOD(ifdi_led_func, em_if_led_func), 483 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 484 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 485 DEVMETHOD(ifdi_debug, em_if_debug), 486 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 487 DEVMETHOD_END 488 }; 489 490 static driver_t igb_if_driver = { 491 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 492 }; 493 494 /********************************************************************* 495 * Tunable default values. 496 *********************************************************************/ 497 498 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 499 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 500 501 #define MAX_INTS_PER_SEC 8000 502 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 503 504 /* Allow common code without TSO */ 505 #ifndef CSUM_TSO 506 #define CSUM_TSO 0 507 #endif 508 509 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 510 "EM driver parameters"); 511 512 static int em_disable_crc_stripping = 0; 513 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 514 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 515 516 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 517 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 518 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 519 0, "Default transmit interrupt delay in usecs"); 520 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 521 0, "Default receive interrupt delay in usecs"); 522 523 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 524 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 525 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 526 &em_tx_abs_int_delay_dflt, 0, 527 "Default transmit interrupt delay limit in usecs"); 528 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 529 &em_rx_abs_int_delay_dflt, 0, 530 "Default receive interrupt delay limit in usecs"); 531 532 static int em_smart_pwr_down = false; 533 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 534 0, "Set to true to leave smart power down enabled on newer adapters"); 535 536 /* Controls whether promiscuous also shows bad packets */ 537 static int em_debug_sbp = false; 538 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 539 "Show bad packets in promiscuous mode"); 540 541 /* How many packets rxeof tries to clean at a time */ 542 static int em_rx_process_limit = 100; 543 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 544 &em_rx_process_limit, 0, 545 "Maximum number of received packets to process " 546 "at a time, -1 means unlimited"); 547 548 /* Energy efficient ethernet - default to OFF */ 549 static int eee_setting = 1; 550 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 551 "Enable Energy Efficient Ethernet"); 552 553 /* 554 ** Tuneable Interrupt rate 555 */ 556 static int em_max_interrupt_rate = 8000; 557 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 558 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 559 560 561 562 /* Global used in WOL setup with multiport cards */ 563 static int global_quad_port_a = 0; 564 565 extern struct if_txrx igb_txrx; 566 extern struct if_txrx em_txrx; 567 extern struct if_txrx lem_txrx; 568 569 static struct if_shared_ctx em_sctx_init = { 570 .isc_magic = IFLIB_MAGIC, 571 .isc_q_align = PAGE_SIZE, 572 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 573 .isc_tx_maxsegsize = PAGE_SIZE, 574 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 575 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 576 .isc_rx_maxsize = MJUM9BYTES, 577 .isc_rx_nsegments = 1, 578 .isc_rx_maxsegsize = MJUM9BYTES, 579 .isc_nfl = 1, 580 .isc_nrxqs = 1, 581 .isc_ntxqs = 1, 582 .isc_admin_intrcnt = 1, 583 .isc_vendor_info = em_vendor_info_array, 584 .isc_driver_version = em_driver_version, 585 .isc_driver = &em_if_driver, 586 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 587 588 .isc_nrxd_min = {EM_MIN_RXD}, 589 .isc_ntxd_min = {EM_MIN_TXD}, 590 .isc_nrxd_max = {EM_MAX_RXD}, 591 .isc_ntxd_max = {EM_MAX_TXD}, 592 .isc_nrxd_default = {EM_DEFAULT_RXD}, 593 .isc_ntxd_default = {EM_DEFAULT_TXD}, 594 }; 595 596 static struct if_shared_ctx igb_sctx_init = { 597 .isc_magic = IFLIB_MAGIC, 598 .isc_q_align = PAGE_SIZE, 599 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 600 .isc_tx_maxsegsize = PAGE_SIZE, 601 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 602 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 603 .isc_rx_maxsize = MJUM9BYTES, 604 .isc_rx_nsegments = 1, 605 .isc_rx_maxsegsize = MJUM9BYTES, 606 .isc_nfl = 1, 607 .isc_nrxqs = 1, 608 .isc_ntxqs = 1, 609 .isc_admin_intrcnt = 1, 610 .isc_vendor_info = igb_vendor_info_array, 611 .isc_driver_version = igb_driver_version, 612 .isc_driver = &igb_if_driver, 613 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 614 615 .isc_nrxd_min = {EM_MIN_RXD}, 616 .isc_ntxd_min = {EM_MIN_TXD}, 617 .isc_nrxd_max = {IGB_MAX_RXD}, 618 .isc_ntxd_max = {IGB_MAX_TXD}, 619 .isc_nrxd_default = {EM_DEFAULT_RXD}, 620 .isc_ntxd_default = {EM_DEFAULT_TXD}, 621 }; 622 623 /***************************************************************** 624 * 625 * Dump Registers 626 * 627 ****************************************************************/ 628 #define IGB_REGS_LEN 739 629 630 static int em_get_regs(SYSCTL_HANDLER_ARGS) 631 { 632 struct e1000_softc *sc = (struct e1000_softc *)arg1; 633 struct e1000_hw *hw = &sc->hw; 634 struct sbuf *sb; 635 u32 *regs_buff; 636 int rc; 637 638 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 639 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 640 641 rc = sysctl_wire_old_buffer(req, 0); 642 MPASS(rc == 0); 643 if (rc != 0) { 644 free(regs_buff, M_DEVBUF); 645 return (rc); 646 } 647 648 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 649 MPASS(sb != NULL); 650 if (sb == NULL) { 651 free(regs_buff, M_DEVBUF); 652 return (ENOMEM); 653 } 654 655 /* General Registers */ 656 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 657 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 658 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 659 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 660 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 661 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 662 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 663 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 664 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 665 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 666 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 667 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 668 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 669 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 670 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 671 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 672 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 673 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 674 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 675 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 676 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 677 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 678 679 sbuf_printf(sb, "General Registers\n"); 680 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 681 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 682 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 683 684 sbuf_printf(sb, "Interrupt Registers\n"); 685 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 686 687 sbuf_printf(sb, "RX Registers\n"); 688 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 689 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 690 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 691 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 692 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 693 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 694 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 695 696 sbuf_printf(sb, "TX Registers\n"); 697 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 698 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 699 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 700 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 701 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 702 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 703 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 704 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 705 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 706 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 707 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 708 709 free(regs_buff, M_DEVBUF); 710 711 #ifdef DUMP_DESCS 712 { 713 if_softc_ctx_t scctx = sc->shared; 714 struct rx_ring *rxr = &rx_que->rxr; 715 struct tx_ring *txr = &tx_que->txr; 716 int ntxd = scctx->isc_ntxd[0]; 717 int nrxd = scctx->isc_nrxd[0]; 718 int j; 719 720 for (j = 0; j < nrxd; j++) { 721 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 722 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 723 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 724 } 725 726 for (j = 0; j < min(ntxd, 256); j++) { 727 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 728 729 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 730 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 731 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 732 733 } 734 } 735 #endif 736 737 rc = sbuf_finish(sb); 738 sbuf_delete(sb); 739 return(rc); 740 } 741 742 static void * 743 em_register(device_t dev) 744 { 745 return (&em_sctx_init); 746 } 747 748 static void * 749 igb_register(device_t dev) 750 { 751 return (&igb_sctx_init); 752 } 753 754 static int 755 em_set_num_queues(if_ctx_t ctx) 756 { 757 struct e1000_softc *sc = iflib_get_softc(ctx); 758 int maxqueues; 759 760 /* Sanity check based on HW */ 761 switch (sc->hw.mac.type) { 762 case e1000_82576: 763 case e1000_82580: 764 case e1000_i350: 765 case e1000_i354: 766 maxqueues = 8; 767 break; 768 case e1000_i210: 769 case e1000_82575: 770 maxqueues = 4; 771 break; 772 case e1000_i211: 773 case e1000_82574: 774 maxqueues = 2; 775 break; 776 default: 777 maxqueues = 1; 778 break; 779 } 780 781 return (maxqueues); 782 } 783 784 #define LEM_CAPS \ 785 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 786 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 787 788 #define EM_CAPS \ 789 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 790 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 791 IFCAP_LRO | IFCAP_VLAN_HWTSO 792 793 #define IGB_CAPS \ 794 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 795 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 796 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 797 IFCAP_TSO6 798 799 /********************************************************************* 800 * Device initialization routine 801 * 802 * The attach entry point is called when the driver is being loaded. 803 * This routine identifies the type of hardware, allocates all resources 804 * and initializes the hardware. 805 * 806 * return 0 on success, positive on failure 807 *********************************************************************/ 808 static int 809 em_if_attach_pre(if_ctx_t ctx) 810 { 811 struct e1000_softc *sc; 812 if_softc_ctx_t scctx; 813 device_t dev; 814 struct e1000_hw *hw; 815 struct sysctl_oid_list *child; 816 struct sysctl_ctx_list *ctx_list; 817 int error = 0; 818 819 INIT_DEBUGOUT("em_if_attach_pre: begin"); 820 dev = iflib_get_dev(ctx); 821 sc = iflib_get_softc(ctx); 822 823 sc->ctx = sc->osdep.ctx = ctx; 824 sc->dev = sc->osdep.dev = dev; 825 scctx = sc->shared = iflib_get_softc_ctx(ctx); 826 sc->media = iflib_get_media(ctx); 827 hw = &sc->hw; 828 829 sc->tx_process_limit = scctx->isc_ntxd[0]; 830 831 /* Determine hardware and mac info */ 832 em_identify_hardware(ctx); 833 834 /* SYSCTL stuff */ 835 ctx_list = device_get_sysctl_ctx(dev); 836 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 837 838 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 839 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 840 em_sysctl_nvm_info, "I", "NVM Information"); 841 842 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 843 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 844 em_sysctl_print_fw_version, "A", 845 "Prints FW/NVM Versions"); 846 847 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 848 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 849 em_sysctl_debug_info, "I", "Debug Information"); 850 851 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 852 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 853 em_set_flowcntl, "I", "Flow Control"); 854 855 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 856 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 857 em_get_regs, "A", "Dump Registers"); 858 859 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 860 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 861 em_get_rs, "I", "Dump RS indexes"); 862 863 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 864 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 865 if (bootverbose) 866 device_printf(dev, "attach_pre capping queues at %d\n", 867 scctx->isc_ntxqsets_max); 868 869 if (hw->mac.type >= igb_mac_min) { 870 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 871 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 872 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 873 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 874 scctx->isc_txrx = &igb_txrx; 875 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 876 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 877 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 878 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 879 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 880 CSUM_IP6_TCP | CSUM_IP6_UDP; 881 if (hw->mac.type != e1000_82575) 882 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 883 /* 884 ** Some new devices, as with ixgbe, now may 885 ** use a different BAR, so we need to keep 886 ** track of which is used. 887 */ 888 scctx->isc_msix_bar = pci_msix_table_bar(dev); 889 } else if (hw->mac.type >= em_mac_min) { 890 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 891 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 892 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 893 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 894 scctx->isc_txrx = &em_txrx; 895 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 896 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 897 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 898 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 899 /* 900 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 901 * by default as we don't have workarounds for all associated 902 * silicon errata. E. g., with several MACs such as 82573E, 903 * TSO only works at Gigabit speed and otherwise can cause the 904 * hardware to hang (which also would be next to impossible to 905 * work around given that already queued TSO-using descriptors 906 * would need to be flushed and vlan(4) reconfigured at runtime 907 * in case of a link speed change). Moreover, MACs like 82579 908 * still can hang at Gigabit even with all publicly documented 909 * TSO workarounds implemented. Generally, the penality of 910 * these workarounds is rather high and may involve copying 911 * mbuf data around so advantages of TSO lapse. Still, TSO may 912 * work for a few MACs of this class - at least when sticking 913 * with Gigabit - in which case users may enable TSO manually. 914 */ 915 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 916 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 917 /* 918 * We support MSI-X with 82574 only, but indicate to iflib(4) 919 * that it shall give MSI at least a try with other devices. 920 */ 921 if (hw->mac.type == e1000_82574) { 922 scctx->isc_msix_bar = pci_msix_table_bar(dev); 923 } else { 924 scctx->isc_msix_bar = -1; 925 scctx->isc_disable_msix = 1; 926 } 927 } else { 928 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 929 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 930 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 931 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 932 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 933 scctx->isc_txrx = &lem_txrx; 934 scctx->isc_capabilities = LEM_CAPS; 935 if (hw->mac.type < e1000_82543) 936 scctx->isc_capabilities &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 937 /* 82541ER doesn't do HW tagging */ 938 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM) 939 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 940 /* INTx only */ 941 scctx->isc_msix_bar = 0; 942 scctx->isc_capenable = scctx->isc_capabilities; 943 } 944 945 /* Setup PCI resources */ 946 if (em_allocate_pci_resources(ctx)) { 947 device_printf(dev, "Allocation of PCI resources failed\n"); 948 error = ENXIO; 949 goto err_pci; 950 } 951 952 /* 953 ** For ICH8 and family we need to 954 ** map the flash memory, and this 955 ** must happen after the MAC is 956 ** identified 957 */ 958 if ((hw->mac.type == e1000_ich8lan) || 959 (hw->mac.type == e1000_ich9lan) || 960 (hw->mac.type == e1000_ich10lan) || 961 (hw->mac.type == e1000_pchlan) || 962 (hw->mac.type == e1000_pch2lan) || 963 (hw->mac.type == e1000_pch_lpt)) { 964 int rid = EM_BAR_TYPE_FLASH; 965 sc->flash = bus_alloc_resource_any(dev, 966 SYS_RES_MEMORY, &rid, RF_ACTIVE); 967 if (sc->flash == NULL) { 968 device_printf(dev, "Mapping of Flash failed\n"); 969 error = ENXIO; 970 goto err_pci; 971 } 972 /* This is used in the shared code */ 973 hw->flash_address = (u8 *)sc->flash; 974 sc->osdep.flash_bus_space_tag = 975 rman_get_bustag(sc->flash); 976 sc->osdep.flash_bus_space_handle = 977 rman_get_bushandle(sc->flash); 978 } 979 /* 980 ** In the new SPT device flash is not a 981 ** separate BAR, rather it is also in BAR0, 982 ** so use the same tag and an offset handle for the 983 ** FLASH read/write macros in the shared code. 984 */ 985 else if (hw->mac.type >= e1000_pch_spt) { 986 sc->osdep.flash_bus_space_tag = 987 sc->osdep.mem_bus_space_tag; 988 sc->osdep.flash_bus_space_handle = 989 sc->osdep.mem_bus_space_handle 990 + E1000_FLASH_BASE_ADDR; 991 } 992 993 /* Do Shared Code initialization */ 994 error = e1000_setup_init_funcs(hw, true); 995 if (error) { 996 device_printf(dev, "Setup of Shared code failed, error %d\n", 997 error); 998 error = ENXIO; 999 goto err_pci; 1000 } 1001 1002 em_setup_msix(ctx); 1003 e1000_get_bus_info(hw); 1004 1005 /* Set up some sysctls for the tunable interrupt delays */ 1006 em_add_int_delay_sysctl(sc, "rx_int_delay", 1007 "receive interrupt delay in usecs", &sc->rx_int_delay, 1008 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1009 em_add_int_delay_sysctl(sc, "tx_int_delay", 1010 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1011 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1012 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1013 "receive interrupt delay limit in usecs", 1014 &sc->rx_abs_int_delay, 1015 E1000_REGISTER(hw, E1000_RADV), 1016 em_rx_abs_int_delay_dflt); 1017 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1018 "transmit interrupt delay limit in usecs", 1019 &sc->tx_abs_int_delay, 1020 E1000_REGISTER(hw, E1000_TADV), 1021 em_tx_abs_int_delay_dflt); 1022 em_add_int_delay_sysctl(sc, "itr", 1023 "interrupt delay limit in usecs/4", 1024 &sc->tx_itr, 1025 E1000_REGISTER(hw, E1000_ITR), 1026 DEFAULT_ITR); 1027 1028 hw->mac.autoneg = DO_AUTO_NEG; 1029 hw->phy.autoneg_wait_to_complete = false; 1030 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1031 1032 if (hw->mac.type < em_mac_min) { 1033 e1000_init_script_state_82541(hw, true); 1034 e1000_set_tbi_compatibility_82543(hw, true); 1035 } 1036 /* Copper options */ 1037 if (hw->phy.media_type == e1000_media_type_copper) { 1038 hw->phy.mdix = AUTO_ALL_MODES; 1039 hw->phy.disable_polarity_correction = false; 1040 hw->phy.ms_type = EM_MASTER_SLAVE; 1041 } 1042 1043 /* 1044 * Set the frame limits assuming 1045 * standard ethernet sized frames. 1046 */ 1047 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1048 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1049 1050 /* 1051 * This controls when hardware reports transmit completion 1052 * status. 1053 */ 1054 hw->mac.report_tx_early = 1; 1055 1056 /* Allocate multicast array memory. */ 1057 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1058 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1059 if (sc->mta == NULL) { 1060 device_printf(dev, "Can not allocate multicast setup array\n"); 1061 error = ENOMEM; 1062 goto err_late; 1063 } 1064 1065 /* Check SOL/IDER usage */ 1066 if (e1000_check_reset_block(hw)) 1067 device_printf(dev, "PHY reset is blocked" 1068 " due to SOL/IDER session.\n"); 1069 1070 /* Sysctl for setting Energy Efficient Ethernet */ 1071 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1072 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1073 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1074 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1075 1076 /* 1077 ** Start from a known state, this is 1078 ** important in reading the nvm and 1079 ** mac from that. 1080 */ 1081 e1000_reset_hw(hw); 1082 1083 /* Make sure we have a good EEPROM before we read from it */ 1084 if (e1000_validate_nvm_checksum(hw) < 0) { 1085 /* 1086 ** Some PCI-E parts fail the first check due to 1087 ** the link being in sleep state, call it again, 1088 ** if it fails a second time its a real issue. 1089 */ 1090 if (e1000_validate_nvm_checksum(hw) < 0) { 1091 device_printf(dev, 1092 "The EEPROM Checksum Is Not Valid\n"); 1093 error = EIO; 1094 goto err_late; 1095 } 1096 } 1097 1098 /* Copy the permanent MAC address out of the EEPROM */ 1099 if (e1000_read_mac_addr(hw) < 0) { 1100 device_printf(dev, "EEPROM read error while reading MAC" 1101 " address\n"); 1102 error = EIO; 1103 goto err_late; 1104 } 1105 1106 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1107 if (sc->vf_ifp) { 1108 ether_gen_addr(iflib_get_ifp(ctx), 1109 (struct ether_addr *)hw->mac.addr); 1110 } else { 1111 device_printf(dev, "Invalid MAC address\n"); 1112 error = EIO; 1113 goto err_late; 1114 } 1115 } 1116 1117 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1118 em_fw_version_locked(ctx); 1119 1120 em_print_fw_version(sc); 1121 1122 /* 1123 * Get Wake-on-Lan and Management info for later use 1124 */ 1125 em_get_wakeup(ctx); 1126 1127 /* Enable only WOL MAGIC by default */ 1128 scctx->isc_capenable &= ~IFCAP_WOL; 1129 if (sc->wol != 0) 1130 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1131 1132 iflib_set_mac(ctx, hw->mac.addr); 1133 1134 return (0); 1135 1136 err_late: 1137 em_release_hw_control(sc); 1138 err_pci: 1139 em_free_pci_resources(ctx); 1140 free(sc->mta, M_DEVBUF); 1141 1142 return (error); 1143 } 1144 1145 static int 1146 em_if_attach_post(if_ctx_t ctx) 1147 { 1148 struct e1000_softc *sc = iflib_get_softc(ctx); 1149 struct e1000_hw *hw = &sc->hw; 1150 int error = 0; 1151 1152 /* Setup OS specific network interface */ 1153 error = em_setup_interface(ctx); 1154 if (error != 0) { 1155 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1156 goto err_late; 1157 } 1158 1159 em_reset(ctx); 1160 1161 /* Initialize statistics */ 1162 em_update_stats_counters(sc); 1163 hw->mac.get_link_status = 1; 1164 em_if_update_admin_status(ctx); 1165 em_add_hw_stats(sc); 1166 1167 /* Non-AMT based hardware can now take control from firmware */ 1168 if (sc->has_manage && !sc->has_amt) 1169 em_get_hw_control(sc); 1170 1171 INIT_DEBUGOUT("em_if_attach_post: end"); 1172 1173 return (0); 1174 1175 err_late: 1176 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1177 return (error); 1178 } 1179 1180 /********************************************************************* 1181 * Device removal routine 1182 * 1183 * The detach entry point is called when the driver is being removed. 1184 * This routine stops the adapter and deallocates all the resources 1185 * that were allocated for driver operation. 1186 * 1187 * return 0 on success, positive on failure 1188 *********************************************************************/ 1189 static int 1190 em_if_detach(if_ctx_t ctx) 1191 { 1192 struct e1000_softc *sc = iflib_get_softc(ctx); 1193 1194 INIT_DEBUGOUT("em_if_detach: begin"); 1195 1196 e1000_phy_hw_reset(&sc->hw); 1197 1198 em_release_manageability(sc); 1199 em_release_hw_control(sc); 1200 em_free_pci_resources(ctx); 1201 free(sc->mta, M_DEVBUF); 1202 sc->mta = NULL; 1203 1204 return (0); 1205 } 1206 1207 /********************************************************************* 1208 * 1209 * Shutdown entry point 1210 * 1211 **********************************************************************/ 1212 1213 static int 1214 em_if_shutdown(if_ctx_t ctx) 1215 { 1216 return em_if_suspend(ctx); 1217 } 1218 1219 /* 1220 * Suspend/resume device methods. 1221 */ 1222 static int 1223 em_if_suspend(if_ctx_t ctx) 1224 { 1225 struct e1000_softc *sc = iflib_get_softc(ctx); 1226 1227 em_release_manageability(sc); 1228 em_release_hw_control(sc); 1229 em_enable_wakeup(ctx); 1230 return (0); 1231 } 1232 1233 static int 1234 em_if_resume(if_ctx_t ctx) 1235 { 1236 struct e1000_softc *sc = iflib_get_softc(ctx); 1237 1238 if (sc->hw.mac.type == e1000_pch2lan) 1239 e1000_resume_workarounds_pchlan(&sc->hw); 1240 em_if_init(ctx); 1241 em_init_manageability(sc); 1242 1243 return(0); 1244 } 1245 1246 static int 1247 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1248 { 1249 int max_frame_size; 1250 struct e1000_softc *sc = iflib_get_softc(ctx); 1251 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1252 1253 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1254 1255 switch (sc->hw.mac.type) { 1256 case e1000_82571: 1257 case e1000_82572: 1258 case e1000_ich9lan: 1259 case e1000_ich10lan: 1260 case e1000_pch2lan: 1261 case e1000_pch_lpt: 1262 case e1000_pch_spt: 1263 case e1000_pch_cnp: 1264 case e1000_pch_tgp: 1265 case e1000_pch_adp: 1266 case e1000_pch_mtp: 1267 case e1000_pch_ptp: 1268 case e1000_82574: 1269 case e1000_82583: 1270 case e1000_80003es2lan: 1271 /* 9K Jumbo Frame size */ 1272 max_frame_size = 9234; 1273 break; 1274 case e1000_pchlan: 1275 max_frame_size = 4096; 1276 break; 1277 case e1000_82542: 1278 case e1000_ich8lan: 1279 /* Adapters that do not support jumbo frames */ 1280 max_frame_size = ETHER_MAX_LEN; 1281 break; 1282 default: 1283 if (sc->hw.mac.type >= igb_mac_min) 1284 max_frame_size = 9234; 1285 else /* lem */ 1286 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1287 } 1288 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1289 return (EINVAL); 1290 } 1291 1292 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1293 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1294 return (0); 1295 } 1296 1297 /********************************************************************* 1298 * Init entry point 1299 * 1300 * This routine is used in two ways. It is used by the stack as 1301 * init entry point in network interface structure. It is also used 1302 * by the driver as a hw/sw initialization routine to get to a 1303 * consistent state. 1304 * 1305 **********************************************************************/ 1306 static void 1307 em_if_init(if_ctx_t ctx) 1308 { 1309 struct e1000_softc *sc = iflib_get_softc(ctx); 1310 if_softc_ctx_t scctx = sc->shared; 1311 if_t ifp = iflib_get_ifp(ctx); 1312 struct em_tx_queue *tx_que; 1313 int i; 1314 1315 INIT_DEBUGOUT("em_if_init: begin"); 1316 1317 /* Get the latest mac address, User can use a LAA */ 1318 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1319 ETHER_ADDR_LEN); 1320 1321 /* Put the address into the Receive Address Array */ 1322 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1323 1324 /* 1325 * With the 82571 adapter, RAR[0] may be overwritten 1326 * when the other port is reset, we make a duplicate 1327 * in RAR[14] for that eventuality, this assures 1328 * the interface continues to function. 1329 */ 1330 if (sc->hw.mac.type == e1000_82571) { 1331 e1000_set_laa_state_82571(&sc->hw, true); 1332 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1333 E1000_RAR_ENTRIES - 1); 1334 } 1335 1336 1337 /* Initialize the hardware */ 1338 em_reset(ctx); 1339 em_if_update_admin_status(ctx); 1340 1341 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1342 struct tx_ring *txr = &tx_que->txr; 1343 1344 txr->tx_rs_cidx = txr->tx_rs_pidx; 1345 1346 /* Initialize the last processed descriptor to be the end of 1347 * the ring, rather than the start, so that we avoid an 1348 * off-by-one error when calculating how many descriptors are 1349 * done in the credits_update function. 1350 */ 1351 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1352 } 1353 1354 /* Setup VLAN support, basic and offload if available */ 1355 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1356 1357 /* Clear bad data from Rx FIFOs */ 1358 if (sc->hw.mac.type >= igb_mac_min) 1359 e1000_rx_fifo_flush_base(&sc->hw); 1360 1361 /* Configure for OS presence */ 1362 em_init_manageability(sc); 1363 1364 /* Prepare transmit descriptors and buffers */ 1365 em_initialize_transmit_unit(ctx); 1366 1367 /* Setup Multicast table */ 1368 em_if_multi_set(ctx); 1369 1370 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1371 em_initialize_receive_unit(ctx); 1372 1373 /* Set up VLAN support and filter */ 1374 em_setup_vlan_hw_support(ctx); 1375 1376 /* Don't lose promiscuous settings */ 1377 em_if_set_promisc(ctx, if_getflags(ifp)); 1378 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1379 1380 /* MSI-X configuration for 82574 */ 1381 if (sc->hw.mac.type == e1000_82574) { 1382 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1383 1384 tmp |= E1000_CTRL_EXT_PBA_CLR; 1385 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1386 /* Set the IVAR - interrupt vector routing. */ 1387 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1388 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1389 igb_configure_queues(sc); 1390 1391 /* this clears any pending interrupts */ 1392 E1000_READ_REG(&sc->hw, E1000_ICR); 1393 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1394 1395 /* AMT based hardware can now take control from firmware */ 1396 if (sc->has_manage && sc->has_amt) 1397 em_get_hw_control(sc); 1398 1399 /* Set Energy Efficient Ethernet */ 1400 if (sc->hw.mac.type >= igb_mac_min && 1401 sc->hw.phy.media_type == e1000_media_type_copper) { 1402 if (sc->hw.mac.type == e1000_i354) 1403 e1000_set_eee_i354(&sc->hw, true, true); 1404 else 1405 e1000_set_eee_i350(&sc->hw, true, true); 1406 } 1407 } 1408 1409 /********************************************************************* 1410 * 1411 * Fast Legacy/MSI Combined Interrupt Service routine 1412 * 1413 *********************************************************************/ 1414 int 1415 em_intr(void *arg) 1416 { 1417 struct e1000_softc *sc = arg; 1418 if_ctx_t ctx = sc->ctx; 1419 u32 reg_icr; 1420 1421 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1422 1423 /* Hot eject? */ 1424 if (reg_icr == 0xffffffff) 1425 return FILTER_STRAY; 1426 1427 /* Definitely not our interrupt. */ 1428 if (reg_icr == 0x0) 1429 return FILTER_STRAY; 1430 1431 /* 1432 * Starting with the 82571 chip, bit 31 should be used to 1433 * determine whether the interrupt belongs to us. 1434 */ 1435 if (sc->hw.mac.type >= e1000_82571 && 1436 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1437 return FILTER_STRAY; 1438 1439 /* 1440 * Only MSI-X interrupts have one-shot behavior by taking advantage 1441 * of the EIAC register. Thus, explicitly disable interrupts. This 1442 * also works around the MSI message reordering errata on certain 1443 * systems. 1444 */ 1445 IFDI_INTR_DISABLE(ctx); 1446 1447 /* Link status change */ 1448 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1449 em_handle_link(ctx); 1450 1451 if (reg_icr & E1000_ICR_RXO) 1452 sc->rx_overruns++; 1453 1454 return (FILTER_SCHEDULE_THREAD); 1455 } 1456 1457 static int 1458 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1459 { 1460 struct e1000_softc *sc = iflib_get_softc(ctx); 1461 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1462 1463 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1464 return (0); 1465 } 1466 1467 static int 1468 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1469 { 1470 struct e1000_softc *sc = iflib_get_softc(ctx); 1471 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1472 1473 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1474 return (0); 1475 } 1476 1477 static int 1478 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1479 { 1480 struct e1000_softc *sc = iflib_get_softc(ctx); 1481 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1482 1483 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1484 return (0); 1485 } 1486 1487 static int 1488 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1489 { 1490 struct e1000_softc *sc = iflib_get_softc(ctx); 1491 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1492 1493 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1494 return (0); 1495 } 1496 1497 /********************************************************************* 1498 * 1499 * MSI-X RX Interrupt Service routine 1500 * 1501 **********************************************************************/ 1502 static int 1503 em_msix_que(void *arg) 1504 { 1505 struct em_rx_queue *que = arg; 1506 1507 ++que->irqs; 1508 1509 return (FILTER_SCHEDULE_THREAD); 1510 } 1511 1512 /********************************************************************* 1513 * 1514 * MSI-X Link Fast Interrupt Service routine 1515 * 1516 **********************************************************************/ 1517 static int 1518 em_msix_link(void *arg) 1519 { 1520 struct e1000_softc *sc = arg; 1521 u32 reg_icr; 1522 1523 ++sc->link_irq; 1524 MPASS(sc->hw.back != NULL); 1525 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1526 1527 if (reg_icr & E1000_ICR_RXO) 1528 sc->rx_overruns++; 1529 1530 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1531 em_handle_link(sc->ctx); 1532 1533 /* Re-arm unconditionally */ 1534 if (sc->hw.mac.type >= igb_mac_min) { 1535 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1536 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1537 } else if (sc->hw.mac.type == e1000_82574) { 1538 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1539 E1000_IMS_OTHER); 1540 /* 1541 * Because we must read the ICR for this interrupt it may 1542 * clear other causes using autoclear, for this reason we 1543 * simply create a soft interrupt for all these vectors. 1544 */ 1545 if (reg_icr) 1546 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1547 } else 1548 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1549 1550 return (FILTER_HANDLED); 1551 } 1552 1553 static void 1554 em_handle_link(void *context) 1555 { 1556 if_ctx_t ctx = context; 1557 struct e1000_softc *sc = iflib_get_softc(ctx); 1558 1559 sc->hw.mac.get_link_status = 1; 1560 iflib_admin_intr_deferred(ctx); 1561 } 1562 1563 /********************************************************************* 1564 * 1565 * Media Ioctl callback 1566 * 1567 * This routine is called whenever the user queries the status of 1568 * the interface using ifconfig. 1569 * 1570 **********************************************************************/ 1571 static void 1572 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1573 { 1574 struct e1000_softc *sc = iflib_get_softc(ctx); 1575 u_char fiber_type = IFM_1000_SX; 1576 1577 INIT_DEBUGOUT("em_if_media_status: begin"); 1578 1579 iflib_admin_intr_deferred(ctx); 1580 1581 ifmr->ifm_status = IFM_AVALID; 1582 ifmr->ifm_active = IFM_ETHER; 1583 1584 if (!sc->link_active) { 1585 return; 1586 } 1587 1588 ifmr->ifm_status |= IFM_ACTIVE; 1589 1590 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1591 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1592 if (sc->hw.mac.type == e1000_82545) 1593 fiber_type = IFM_1000_LX; 1594 ifmr->ifm_active |= fiber_type | IFM_FDX; 1595 } else { 1596 switch (sc->link_speed) { 1597 case 10: 1598 ifmr->ifm_active |= IFM_10_T; 1599 break; 1600 case 100: 1601 ifmr->ifm_active |= IFM_100_TX; 1602 break; 1603 case 1000: 1604 ifmr->ifm_active |= IFM_1000_T; 1605 break; 1606 } 1607 if (sc->link_duplex == FULL_DUPLEX) 1608 ifmr->ifm_active |= IFM_FDX; 1609 else 1610 ifmr->ifm_active |= IFM_HDX; 1611 } 1612 } 1613 1614 /********************************************************************* 1615 * 1616 * Media Ioctl callback 1617 * 1618 * This routine is called when the user changes speed/duplex using 1619 * media/mediopt option with ifconfig. 1620 * 1621 **********************************************************************/ 1622 static int 1623 em_if_media_change(if_ctx_t ctx) 1624 { 1625 struct e1000_softc *sc = iflib_get_softc(ctx); 1626 struct ifmedia *ifm = iflib_get_media(ctx); 1627 1628 INIT_DEBUGOUT("em_if_media_change: begin"); 1629 1630 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1631 return (EINVAL); 1632 1633 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1634 case IFM_AUTO: 1635 sc->hw.mac.autoneg = DO_AUTO_NEG; 1636 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1637 break; 1638 case IFM_1000_LX: 1639 case IFM_1000_SX: 1640 case IFM_1000_T: 1641 sc->hw.mac.autoneg = DO_AUTO_NEG; 1642 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1643 break; 1644 case IFM_100_TX: 1645 sc->hw.mac.autoneg = false; 1646 sc->hw.phy.autoneg_advertised = 0; 1647 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1648 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1649 else 1650 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1651 break; 1652 case IFM_10_T: 1653 sc->hw.mac.autoneg = false; 1654 sc->hw.phy.autoneg_advertised = 0; 1655 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1656 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1657 else 1658 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1659 break; 1660 default: 1661 device_printf(sc->dev, "Unsupported media type\n"); 1662 } 1663 1664 em_if_init(ctx); 1665 1666 return (0); 1667 } 1668 1669 static int 1670 em_if_set_promisc(if_ctx_t ctx, int flags) 1671 { 1672 struct e1000_softc *sc = iflib_get_softc(ctx); 1673 if_t ifp = iflib_get_ifp(ctx); 1674 u32 reg_rctl; 1675 int mcnt = 0; 1676 1677 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1678 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1679 if (flags & IFF_ALLMULTI) 1680 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1681 else 1682 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1683 1684 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1685 reg_rctl &= (~E1000_RCTL_MPE); 1686 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1687 1688 if (flags & IFF_PROMISC) { 1689 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1690 em_if_vlan_filter_disable(sc); 1691 /* Turn this on if you want to see bad packets */ 1692 if (em_debug_sbp) 1693 reg_rctl |= E1000_RCTL_SBP; 1694 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1695 } else { 1696 if (flags & IFF_ALLMULTI) { 1697 reg_rctl |= E1000_RCTL_MPE; 1698 reg_rctl &= ~E1000_RCTL_UPE; 1699 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1700 } 1701 if (em_if_vlan_filter_used(ctx)) 1702 em_if_vlan_filter_enable(sc); 1703 } 1704 return (0); 1705 } 1706 1707 static u_int 1708 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1709 { 1710 u8 *mta = arg; 1711 1712 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1713 return (0); 1714 1715 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1716 1717 return (1); 1718 } 1719 1720 /********************************************************************* 1721 * Multicast Update 1722 * 1723 * This routine is called whenever multicast address list is updated. 1724 * 1725 **********************************************************************/ 1726 static void 1727 em_if_multi_set(if_ctx_t ctx) 1728 { 1729 struct e1000_softc *sc = iflib_get_softc(ctx); 1730 if_t ifp = iflib_get_ifp(ctx); 1731 u8 *mta; /* Multicast array memory */ 1732 u32 reg_rctl = 0; 1733 int mcnt = 0; 1734 1735 IOCTL_DEBUGOUT("em_set_multi: begin"); 1736 1737 mta = sc->mta; 1738 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1739 1740 if (sc->hw.mac.type == e1000_82542 && 1741 sc->hw.revision_id == E1000_REVISION_2) { 1742 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1743 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1744 e1000_pci_clear_mwi(&sc->hw); 1745 reg_rctl |= E1000_RCTL_RST; 1746 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1747 msec_delay(5); 1748 } 1749 1750 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1751 1752 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1753 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1754 1755 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1756 1757 if (if_getflags(ifp) & IFF_PROMISC) 1758 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1759 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1760 if_getflags(ifp) & IFF_ALLMULTI) { 1761 reg_rctl |= E1000_RCTL_MPE; 1762 reg_rctl &= ~E1000_RCTL_UPE; 1763 } else 1764 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1765 1766 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1767 1768 if (sc->hw.mac.type == e1000_82542 && 1769 sc->hw.revision_id == E1000_REVISION_2) { 1770 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1771 reg_rctl &= ~E1000_RCTL_RST; 1772 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1773 msec_delay(5); 1774 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1775 e1000_pci_set_mwi(&sc->hw); 1776 } 1777 } 1778 1779 /********************************************************************* 1780 * Timer routine 1781 * 1782 * This routine schedules em_if_update_admin_status() to check for 1783 * link status and to gather statistics as well as to perform some 1784 * controller-specific hardware patting. 1785 * 1786 **********************************************************************/ 1787 static void 1788 em_if_timer(if_ctx_t ctx, uint16_t qid) 1789 { 1790 1791 if (qid != 0) 1792 return; 1793 1794 iflib_admin_intr_deferred(ctx); 1795 } 1796 1797 static void 1798 em_if_update_admin_status(if_ctx_t ctx) 1799 { 1800 struct e1000_softc *sc = iflib_get_softc(ctx); 1801 struct e1000_hw *hw = &sc->hw; 1802 device_t dev = iflib_get_dev(ctx); 1803 u32 link_check, thstat, ctrl; 1804 1805 link_check = thstat = ctrl = 0; 1806 /* Get the cached link value or read phy for real */ 1807 switch (hw->phy.media_type) { 1808 case e1000_media_type_copper: 1809 if (hw->mac.get_link_status) { 1810 if (hw->mac.type == e1000_pch_spt) 1811 msec_delay(50); 1812 /* Do the work to read phy */ 1813 e1000_check_for_link(hw); 1814 link_check = !hw->mac.get_link_status; 1815 if (link_check) /* ESB2 fix */ 1816 e1000_cfg_on_link_up(hw); 1817 } else { 1818 link_check = true; 1819 } 1820 break; 1821 case e1000_media_type_fiber: 1822 e1000_check_for_link(hw); 1823 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1824 E1000_STATUS_LU); 1825 break; 1826 case e1000_media_type_internal_serdes: 1827 e1000_check_for_link(hw); 1828 link_check = hw->mac.serdes_has_link; 1829 break; 1830 /* VF device is type_unknown */ 1831 case e1000_media_type_unknown: 1832 e1000_check_for_link(hw); 1833 link_check = !hw->mac.get_link_status; 1834 /* FALLTHROUGH */ 1835 default: 1836 break; 1837 } 1838 1839 /* Check for thermal downshift or shutdown */ 1840 if (hw->mac.type == e1000_i350) { 1841 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1842 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1843 } 1844 1845 /* Now check for a transition */ 1846 if (link_check && (sc->link_active == 0)) { 1847 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1848 &sc->link_duplex); 1849 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1850 if ((sc->link_speed != SPEED_1000) && 1851 ((hw->mac.type == e1000_82571) || 1852 (hw->mac.type == e1000_82572))) { 1853 int tarc0; 1854 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1855 tarc0 &= ~TARC_SPEED_MODE_BIT; 1856 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1857 } 1858 if (bootverbose) 1859 device_printf(dev, "Link is up %d Mbps %s\n", 1860 sc->link_speed, 1861 ((sc->link_duplex == FULL_DUPLEX) ? 1862 "Full Duplex" : "Half Duplex")); 1863 sc->link_active = 1; 1864 sc->smartspeed = 0; 1865 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1866 E1000_CTRL_EXT_LINK_MODE_GMII && 1867 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1868 device_printf(dev, "Link: thermal downshift\n"); 1869 /* Delay Link Up for Phy update */ 1870 if (((hw->mac.type == e1000_i210) || 1871 (hw->mac.type == e1000_i211)) && 1872 (hw->phy.id == I210_I_PHY_ID)) 1873 msec_delay(I210_LINK_DELAY); 1874 /* Reset if the media type changed. */ 1875 if (hw->dev_spec._82575.media_changed && 1876 hw->mac.type >= igb_mac_min) { 1877 hw->dev_spec._82575.media_changed = false; 1878 sc->flags |= IGB_MEDIA_RESET; 1879 em_reset(ctx); 1880 } 1881 iflib_link_state_change(ctx, LINK_STATE_UP, 1882 IF_Mbps(sc->link_speed)); 1883 } else if (!link_check && (sc->link_active == 1)) { 1884 sc->link_speed = 0; 1885 sc->link_duplex = 0; 1886 sc->link_active = 0; 1887 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1888 } 1889 em_update_stats_counters(sc); 1890 1891 /* Reset LAA into RAR[0] on 82571 */ 1892 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1893 e1000_rar_set(hw, hw->mac.addr, 0); 1894 1895 if (hw->mac.type < em_mac_min) 1896 lem_smartspeed(sc); 1897 } 1898 1899 static void 1900 em_if_watchdog_reset(if_ctx_t ctx) 1901 { 1902 struct e1000_softc *sc = iflib_get_softc(ctx); 1903 1904 /* 1905 * Just count the event; iflib(4) will already trigger a 1906 * sufficient reset of the controller. 1907 */ 1908 sc->watchdog_events++; 1909 } 1910 1911 /********************************************************************* 1912 * 1913 * This routine disables all traffic on the adapter by issuing a 1914 * global reset on the MAC. 1915 * 1916 **********************************************************************/ 1917 static void 1918 em_if_stop(if_ctx_t ctx) 1919 { 1920 struct e1000_softc *sc = iflib_get_softc(ctx); 1921 1922 INIT_DEBUGOUT("em_if_stop: begin"); 1923 1924 /* I219 needs special flushing to avoid hangs */ 1925 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 1926 em_flush_desc_rings(sc); 1927 1928 e1000_reset_hw(&sc->hw); 1929 if (sc->hw.mac.type >= e1000_82544) 1930 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1931 1932 e1000_led_off(&sc->hw); 1933 e1000_cleanup_led(&sc->hw); 1934 } 1935 1936 /********************************************************************* 1937 * 1938 * Determine hardware revision. 1939 * 1940 **********************************************************************/ 1941 static void 1942 em_identify_hardware(if_ctx_t ctx) 1943 { 1944 device_t dev = iflib_get_dev(ctx); 1945 struct e1000_softc *sc = iflib_get_softc(ctx); 1946 1947 /* Make sure our PCI config space has the necessary stuff set */ 1948 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1949 1950 /* Save off the information about this board */ 1951 sc->hw.vendor_id = pci_get_vendor(dev); 1952 sc->hw.device_id = pci_get_device(dev); 1953 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1954 sc->hw.subsystem_vendor_id = 1955 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1956 sc->hw.subsystem_device_id = 1957 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1958 1959 /* Do Shared Code Init and Setup */ 1960 if (e1000_set_mac_type(&sc->hw)) { 1961 device_printf(dev, "Setup init failure\n"); 1962 return; 1963 } 1964 1965 /* Are we a VF device? */ 1966 if ((sc->hw.mac.type == e1000_vfadapt) || 1967 (sc->hw.mac.type == e1000_vfadapt_i350)) 1968 sc->vf_ifp = 1; 1969 else 1970 sc->vf_ifp = 0; 1971 } 1972 1973 static int 1974 em_allocate_pci_resources(if_ctx_t ctx) 1975 { 1976 struct e1000_softc *sc = iflib_get_softc(ctx); 1977 device_t dev = iflib_get_dev(ctx); 1978 int rid, val; 1979 1980 rid = PCIR_BAR(0); 1981 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1982 &rid, RF_ACTIVE); 1983 if (sc->memory == NULL) { 1984 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1985 return (ENXIO); 1986 } 1987 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 1988 sc->osdep.mem_bus_space_handle = 1989 rman_get_bushandle(sc->memory); 1990 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 1991 1992 /* Only older adapters use IO mapping */ 1993 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 1994 /* Figure our where our IO BAR is ? */ 1995 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1996 val = pci_read_config(dev, rid, 4); 1997 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1998 break; 1999 } 2000 rid += 4; 2001 /* check for 64bit BAR */ 2002 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2003 rid += 4; 2004 } 2005 if (rid >= PCIR_CIS) { 2006 device_printf(dev, "Unable to locate IO BAR\n"); 2007 return (ENXIO); 2008 } 2009 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2010 &rid, RF_ACTIVE); 2011 if (sc->ioport == NULL) { 2012 device_printf(dev, "Unable to allocate bus resource: " 2013 "ioport\n"); 2014 return (ENXIO); 2015 } 2016 sc->hw.io_base = 0; 2017 sc->osdep.io_bus_space_tag = 2018 rman_get_bustag(sc->ioport); 2019 sc->osdep.io_bus_space_handle = 2020 rman_get_bushandle(sc->ioport); 2021 } 2022 2023 sc->hw.back = &sc->osdep; 2024 2025 return (0); 2026 } 2027 2028 /********************************************************************* 2029 * 2030 * Set up the MSI-X Interrupt handlers 2031 * 2032 **********************************************************************/ 2033 static int 2034 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2035 { 2036 struct e1000_softc *sc = iflib_get_softc(ctx); 2037 struct em_rx_queue *rx_que = sc->rx_queues; 2038 struct em_tx_queue *tx_que = sc->tx_queues; 2039 int error, rid, i, vector = 0, rx_vectors; 2040 char buf[16]; 2041 2042 /* First set up ring resources */ 2043 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2044 rid = vector + 1; 2045 snprintf(buf, sizeof(buf), "rxq%d", i); 2046 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2047 if (error) { 2048 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2049 sc->rx_num_queues = i + 1; 2050 goto fail; 2051 } 2052 2053 rx_que->msix = vector; 2054 2055 /* 2056 * Set the bit to enable interrupt 2057 * in E1000_IMS -- bits 20 and 21 2058 * are for RX0 and RX1, note this has 2059 * NOTHING to do with the MSI-X vector 2060 */ 2061 if (sc->hw.mac.type == e1000_82574) { 2062 rx_que->eims = 1 << (20 + i); 2063 sc->ims |= rx_que->eims; 2064 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2065 } else if (sc->hw.mac.type == e1000_82575) 2066 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2067 else 2068 rx_que->eims = 1 << vector; 2069 } 2070 rx_vectors = vector; 2071 2072 vector = 0; 2073 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2074 snprintf(buf, sizeof(buf), "txq%d", i); 2075 tx_que = &sc->tx_queues[i]; 2076 iflib_softirq_alloc_generic(ctx, 2077 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2078 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2079 2080 tx_que->msix = (vector % sc->rx_num_queues); 2081 2082 /* 2083 * Set the bit to enable interrupt 2084 * in E1000_IMS -- bits 22 and 23 2085 * are for TX0 and TX1, note this has 2086 * NOTHING to do with the MSI-X vector 2087 */ 2088 if (sc->hw.mac.type == e1000_82574) { 2089 tx_que->eims = 1 << (22 + i); 2090 sc->ims |= tx_que->eims; 2091 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2092 } else if (sc->hw.mac.type == e1000_82575) { 2093 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2094 } else { 2095 tx_que->eims = 1 << i; 2096 } 2097 } 2098 2099 /* Link interrupt */ 2100 rid = rx_vectors + 1; 2101 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2102 2103 if (error) { 2104 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2105 goto fail; 2106 } 2107 sc->linkvec = rx_vectors; 2108 if (sc->hw.mac.type < igb_mac_min) { 2109 sc->ivars |= (8 | rx_vectors) << 16; 2110 sc->ivars |= 0x80000000; 2111 /* Enable the "Other" interrupt type for link status change */ 2112 sc->ims |= E1000_IMS_OTHER; 2113 } 2114 2115 return (0); 2116 fail: 2117 iflib_irq_free(ctx, &sc->irq); 2118 rx_que = sc->rx_queues; 2119 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2120 iflib_irq_free(ctx, &rx_que->que_irq); 2121 return (error); 2122 } 2123 2124 static void 2125 igb_configure_queues(struct e1000_softc *sc) 2126 { 2127 struct e1000_hw *hw = &sc->hw; 2128 struct em_rx_queue *rx_que; 2129 struct em_tx_queue *tx_que; 2130 u32 tmp, ivar = 0, newitr = 0; 2131 2132 /* First turn on RSS capability */ 2133 if (hw->mac.type != e1000_82575) 2134 E1000_WRITE_REG(hw, E1000_GPIE, 2135 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2136 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2137 2138 /* Turn on MSI-X */ 2139 switch (hw->mac.type) { 2140 case e1000_82580: 2141 case e1000_i350: 2142 case e1000_i354: 2143 case e1000_i210: 2144 case e1000_i211: 2145 case e1000_vfadapt: 2146 case e1000_vfadapt_i350: 2147 /* RX entries */ 2148 for (int i = 0; i < sc->rx_num_queues; i++) { 2149 u32 index = i >> 1; 2150 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2151 rx_que = &sc->rx_queues[i]; 2152 if (i & 1) { 2153 ivar &= 0xFF00FFFF; 2154 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2155 } else { 2156 ivar &= 0xFFFFFF00; 2157 ivar |= rx_que->msix | E1000_IVAR_VALID; 2158 } 2159 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2160 } 2161 /* TX entries */ 2162 for (int i = 0; i < sc->tx_num_queues; i++) { 2163 u32 index = i >> 1; 2164 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2165 tx_que = &sc->tx_queues[i]; 2166 if (i & 1) { 2167 ivar &= 0x00FFFFFF; 2168 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2169 } else { 2170 ivar &= 0xFFFF00FF; 2171 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2172 } 2173 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2174 sc->que_mask |= tx_que->eims; 2175 } 2176 2177 /* And for the link interrupt */ 2178 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2179 sc->link_mask = 1 << sc->linkvec; 2180 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2181 break; 2182 case e1000_82576: 2183 /* RX entries */ 2184 for (int i = 0; i < sc->rx_num_queues; i++) { 2185 u32 index = i & 0x7; /* Each IVAR has two entries */ 2186 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2187 rx_que = &sc->rx_queues[i]; 2188 if (i < 8) { 2189 ivar &= 0xFFFFFF00; 2190 ivar |= rx_que->msix | E1000_IVAR_VALID; 2191 } else { 2192 ivar &= 0xFF00FFFF; 2193 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2194 } 2195 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2196 sc->que_mask |= rx_que->eims; 2197 } 2198 /* TX entries */ 2199 for (int i = 0; i < sc->tx_num_queues; i++) { 2200 u32 index = i & 0x7; /* Each IVAR has two entries */ 2201 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2202 tx_que = &sc->tx_queues[i]; 2203 if (i < 8) { 2204 ivar &= 0xFFFF00FF; 2205 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2206 } else { 2207 ivar &= 0x00FFFFFF; 2208 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2209 } 2210 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2211 sc->que_mask |= tx_que->eims; 2212 } 2213 2214 /* And for the link interrupt */ 2215 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2216 sc->link_mask = 1 << sc->linkvec; 2217 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2218 break; 2219 2220 case e1000_82575: 2221 /* enable MSI-X support*/ 2222 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2223 tmp |= E1000_CTRL_EXT_PBA_CLR; 2224 /* Auto-Mask interrupts upon ICR read. */ 2225 tmp |= E1000_CTRL_EXT_EIAME; 2226 tmp |= E1000_CTRL_EXT_IRCA; 2227 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2228 2229 /* Queues */ 2230 for (int i = 0; i < sc->rx_num_queues; i++) { 2231 rx_que = &sc->rx_queues[i]; 2232 tmp = E1000_EICR_RX_QUEUE0 << i; 2233 tmp |= E1000_EICR_TX_QUEUE0 << i; 2234 rx_que->eims = tmp; 2235 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2236 i, rx_que->eims); 2237 sc->que_mask |= rx_que->eims; 2238 } 2239 2240 /* Link */ 2241 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2242 E1000_EIMS_OTHER); 2243 sc->link_mask |= E1000_EIMS_OTHER; 2244 default: 2245 break; 2246 } 2247 2248 /* Set the starting interrupt rate */ 2249 if (em_max_interrupt_rate > 0) 2250 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2251 2252 if (hw->mac.type == e1000_82575) 2253 newitr |= newitr << 16; 2254 else 2255 newitr |= E1000_EITR_CNT_IGNR; 2256 2257 for (int i = 0; i < sc->rx_num_queues; i++) { 2258 rx_que = &sc->rx_queues[i]; 2259 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2260 } 2261 2262 return; 2263 } 2264 2265 static void 2266 em_free_pci_resources(if_ctx_t ctx) 2267 { 2268 struct e1000_softc *sc = iflib_get_softc(ctx); 2269 struct em_rx_queue *que = sc->rx_queues; 2270 device_t dev = iflib_get_dev(ctx); 2271 2272 /* Release all MSI-X queue resources */ 2273 if (sc->intr_type == IFLIB_INTR_MSIX) 2274 iflib_irq_free(ctx, &sc->irq); 2275 2276 if (que != NULL) { 2277 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2278 iflib_irq_free(ctx, &que->que_irq); 2279 } 2280 } 2281 2282 if (sc->memory != NULL) { 2283 bus_release_resource(dev, SYS_RES_MEMORY, 2284 rman_get_rid(sc->memory), sc->memory); 2285 sc->memory = NULL; 2286 } 2287 2288 if (sc->flash != NULL) { 2289 bus_release_resource(dev, SYS_RES_MEMORY, 2290 rman_get_rid(sc->flash), sc->flash); 2291 sc->flash = NULL; 2292 } 2293 2294 if (sc->ioport != NULL) { 2295 bus_release_resource(dev, SYS_RES_IOPORT, 2296 rman_get_rid(sc->ioport), sc->ioport); 2297 sc->ioport = NULL; 2298 } 2299 } 2300 2301 /* Set up MSI or MSI-X */ 2302 static int 2303 em_setup_msix(if_ctx_t ctx) 2304 { 2305 struct e1000_softc *sc = iflib_get_softc(ctx); 2306 2307 if (sc->hw.mac.type == e1000_82574) { 2308 em_enable_vectors_82574(ctx); 2309 } 2310 return (0); 2311 } 2312 2313 /********************************************************************* 2314 * 2315 * Workaround for SmartSpeed on 82541 and 82547 controllers 2316 * 2317 **********************************************************************/ 2318 static void 2319 lem_smartspeed(struct e1000_softc *sc) 2320 { 2321 u16 phy_tmp; 2322 2323 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2324 sc->hw.mac.autoneg == 0 || 2325 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2326 return; 2327 2328 if (sc->smartspeed == 0) { 2329 /* If Master/Slave config fault is asserted twice, 2330 * we assume back-to-back */ 2331 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2332 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2333 return; 2334 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2335 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2336 e1000_read_phy_reg(&sc->hw, 2337 PHY_1000T_CTRL, &phy_tmp); 2338 if(phy_tmp & CR_1000T_MS_ENABLE) { 2339 phy_tmp &= ~CR_1000T_MS_ENABLE; 2340 e1000_write_phy_reg(&sc->hw, 2341 PHY_1000T_CTRL, phy_tmp); 2342 sc->smartspeed++; 2343 if(sc->hw.mac.autoneg && 2344 !e1000_copper_link_autoneg(&sc->hw) && 2345 !e1000_read_phy_reg(&sc->hw, 2346 PHY_CONTROL, &phy_tmp)) { 2347 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2348 MII_CR_RESTART_AUTO_NEG); 2349 e1000_write_phy_reg(&sc->hw, 2350 PHY_CONTROL, phy_tmp); 2351 } 2352 } 2353 } 2354 return; 2355 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2356 /* If still no link, perhaps using 2/3 pair cable */ 2357 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2358 phy_tmp |= CR_1000T_MS_ENABLE; 2359 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2360 if(sc->hw.mac.autoneg && 2361 !e1000_copper_link_autoneg(&sc->hw) && 2362 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2363 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2364 MII_CR_RESTART_AUTO_NEG); 2365 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2366 } 2367 } 2368 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2369 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2370 sc->smartspeed = 0; 2371 } 2372 2373 /********************************************************************* 2374 * 2375 * Initialize the DMA Coalescing feature 2376 * 2377 **********************************************************************/ 2378 static void 2379 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2380 { 2381 device_t dev = sc->dev; 2382 struct e1000_hw *hw = &sc->hw; 2383 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2384 u16 hwm; 2385 u16 max_frame_size; 2386 2387 if (hw->mac.type == e1000_i211) 2388 return; 2389 2390 max_frame_size = sc->shared->isc_max_frame_size; 2391 if (hw->mac.type > e1000_82580) { 2392 2393 if (sc->dmac == 0) { /* Disabling it */ 2394 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2395 return; 2396 } else 2397 device_printf(dev, "DMA Coalescing enabled\n"); 2398 2399 /* Set starting threshold */ 2400 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2401 2402 hwm = 64 * pba - max_frame_size / 16; 2403 if (hwm < 64 * (pba - 6)) 2404 hwm = 64 * (pba - 6); 2405 reg = E1000_READ_REG(hw, E1000_FCRTC); 2406 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2407 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2408 & E1000_FCRTC_RTH_COAL_MASK); 2409 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2410 2411 2412 dmac = pba - max_frame_size / 512; 2413 if (dmac < pba - 10) 2414 dmac = pba - 10; 2415 reg = E1000_READ_REG(hw, E1000_DMACR); 2416 reg &= ~E1000_DMACR_DMACTHR_MASK; 2417 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2418 & E1000_DMACR_DMACTHR_MASK); 2419 2420 /* transition to L0x or L1 if available..*/ 2421 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2422 2423 /* Check if status is 2.5Gb backplane connection 2424 * before configuration of watchdog timer, which is 2425 * in msec values in 12.8usec intervals 2426 * watchdog timer= msec values in 32usec intervals 2427 * for non 2.5Gb connection 2428 */ 2429 if (hw->mac.type == e1000_i354) { 2430 int status = E1000_READ_REG(hw, E1000_STATUS); 2431 if ((status & E1000_STATUS_2P5_SKU) && 2432 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2433 reg |= ((sc->dmac * 5) >> 6); 2434 else 2435 reg |= (sc->dmac >> 5); 2436 } else { 2437 reg |= (sc->dmac >> 5); 2438 } 2439 2440 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2441 2442 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2443 2444 /* Set the interval before transition */ 2445 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2446 if (hw->mac.type == e1000_i350) 2447 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2448 /* 2449 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2450 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2451 */ 2452 if (hw->mac.type == e1000_i354) { 2453 int status = E1000_READ_REG(hw, E1000_STATUS); 2454 if ((status & E1000_STATUS_2P5_SKU) && 2455 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2456 reg |= 0xA; 2457 else 2458 reg |= 0x4; 2459 } else { 2460 reg |= 0x4; 2461 } 2462 2463 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2464 2465 /* free space in tx packet buffer to wake from DMA coal */ 2466 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2467 (2 * max_frame_size)) >> 6); 2468 2469 /* make low power state decision controlled by DMA coal */ 2470 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2471 reg &= ~E1000_PCIEMISC_LX_DECISION; 2472 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2473 2474 } else if (hw->mac.type == e1000_82580) { 2475 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2476 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2477 reg & ~E1000_PCIEMISC_LX_DECISION); 2478 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2479 } 2480 } 2481 /********************************************************************* 2482 * The 3 following flush routines are used as a workaround in the 2483 * I219 client parts and only for them. 2484 * 2485 * em_flush_tx_ring - remove all descriptors from the tx_ring 2486 * 2487 * We want to clear all pending descriptors from the TX ring. 2488 * zeroing happens when the HW reads the regs. We assign the ring itself as 2489 * the data of the next descriptor. We don't care about the data we are about 2490 * to reset the HW. 2491 **********************************************************************/ 2492 static void 2493 em_flush_tx_ring(struct e1000_softc *sc) 2494 { 2495 struct e1000_hw *hw = &sc->hw; 2496 struct tx_ring *txr = &sc->tx_queues->txr; 2497 struct e1000_tx_desc *txd; 2498 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2499 u16 size = 512; 2500 2501 tctl = E1000_READ_REG(hw, E1000_TCTL); 2502 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2503 2504 txd = &txr->tx_base[txr->tx_cidx_processed]; 2505 2506 /* Just use the ring as a dummy buffer addr */ 2507 txd->buffer_addr = txr->tx_paddr; 2508 txd->lower.data = htole32(txd_lower | size); 2509 txd->upper.data = 0; 2510 2511 /* flush descriptors to memory before notifying the HW */ 2512 wmb(); 2513 2514 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2515 mb(); 2516 usec_delay(250); 2517 } 2518 2519 /********************************************************************* 2520 * em_flush_rx_ring - remove all descriptors from the rx_ring 2521 * 2522 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2523 **********************************************************************/ 2524 static void 2525 em_flush_rx_ring(struct e1000_softc *sc) 2526 { 2527 struct e1000_hw *hw = &sc->hw; 2528 u32 rctl, rxdctl; 2529 2530 rctl = E1000_READ_REG(hw, E1000_RCTL); 2531 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2532 E1000_WRITE_FLUSH(hw); 2533 usec_delay(150); 2534 2535 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2536 /* zero the lower 14 bits (prefetch and host thresholds) */ 2537 rxdctl &= 0xffffc000; 2538 /* 2539 * update thresholds: prefetch threshold to 31, host threshold to 1 2540 * and make sure the granularity is "descriptors" and not "cache lines" 2541 */ 2542 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2543 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2544 2545 /* momentarily enable the RX ring for the changes to take effect */ 2546 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2547 E1000_WRITE_FLUSH(hw); 2548 usec_delay(150); 2549 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2550 } 2551 2552 /********************************************************************* 2553 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2554 * 2555 * In I219, the descriptor rings must be emptied before resetting the HW 2556 * or before changing the device state to D3 during runtime (runtime PM). 2557 * 2558 * Failure to do this will cause the HW to enter a unit hang state which can 2559 * only be released by PCI reset on the device 2560 * 2561 **********************************************************************/ 2562 static void 2563 em_flush_desc_rings(struct e1000_softc *sc) 2564 { 2565 struct e1000_hw *hw = &sc->hw; 2566 device_t dev = sc->dev; 2567 u16 hang_state; 2568 u32 fext_nvm11, tdlen; 2569 2570 /* First, disable MULR fix in FEXTNVM11 */ 2571 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2572 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2573 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2574 2575 /* do nothing if we're not in faulty state, or if the queue is empty */ 2576 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2577 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2578 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2579 return; 2580 em_flush_tx_ring(sc); 2581 2582 /* recheck, maybe the fault is caused by the rx ring */ 2583 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2584 if (hang_state & FLUSH_DESC_REQUIRED) 2585 em_flush_rx_ring(sc); 2586 } 2587 2588 2589 /********************************************************************* 2590 * 2591 * Initialize the hardware to a configuration as specified by the 2592 * sc structure. 2593 * 2594 **********************************************************************/ 2595 static void 2596 em_reset(if_ctx_t ctx) 2597 { 2598 device_t dev = iflib_get_dev(ctx); 2599 struct e1000_softc *sc = iflib_get_softc(ctx); 2600 if_t ifp = iflib_get_ifp(ctx); 2601 struct e1000_hw *hw = &sc->hw; 2602 u32 rx_buffer_size; 2603 u32 pba; 2604 2605 INIT_DEBUGOUT("em_reset: begin"); 2606 /* Let the firmware know the OS is in control */ 2607 em_get_hw_control(sc); 2608 2609 /* Set up smart power down as default off on newer adapters. */ 2610 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2611 hw->mac.type == e1000_82572)) { 2612 u16 phy_tmp = 0; 2613 2614 /* Speed up time to link by disabling smart power down. */ 2615 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2616 phy_tmp &= ~IGP02E1000_PM_SPD; 2617 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2618 } 2619 2620 /* 2621 * Packet Buffer Allocation (PBA) 2622 * Writing PBA sets the receive portion of the buffer 2623 * the remainder is used for the transmit buffer. 2624 */ 2625 switch (hw->mac.type) { 2626 /* 82547: Total Packet Buffer is 40K */ 2627 case e1000_82547: 2628 case e1000_82547_rev_2: 2629 if (hw->mac.max_frame_size > 8192) 2630 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2631 else 2632 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2633 break; 2634 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2635 case e1000_82571: 2636 case e1000_82572: 2637 case e1000_80003es2lan: 2638 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2639 break; 2640 /* 82573: Total Packet Buffer is 32K */ 2641 case e1000_82573: 2642 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2643 break; 2644 case e1000_82574: 2645 case e1000_82583: 2646 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2647 break; 2648 case e1000_ich8lan: 2649 pba = E1000_PBA_8K; 2650 break; 2651 case e1000_ich9lan: 2652 case e1000_ich10lan: 2653 /* Boost Receive side for jumbo frames */ 2654 if (hw->mac.max_frame_size > 4096) 2655 pba = E1000_PBA_14K; 2656 else 2657 pba = E1000_PBA_10K; 2658 break; 2659 case e1000_pchlan: 2660 case e1000_pch2lan: 2661 case e1000_pch_lpt: 2662 case e1000_pch_spt: 2663 case e1000_pch_cnp: 2664 case e1000_pch_tgp: 2665 case e1000_pch_adp: 2666 case e1000_pch_mtp: 2667 case e1000_pch_ptp: 2668 pba = E1000_PBA_26K; 2669 break; 2670 case e1000_82575: 2671 pba = E1000_PBA_32K; 2672 break; 2673 case e1000_82576: 2674 case e1000_vfadapt: 2675 pba = E1000_READ_REG(hw, E1000_RXPBS); 2676 pba &= E1000_RXPBS_SIZE_MASK_82576; 2677 break; 2678 case e1000_82580: 2679 case e1000_i350: 2680 case e1000_i354: 2681 case e1000_vfadapt_i350: 2682 pba = E1000_READ_REG(hw, E1000_RXPBS); 2683 pba = e1000_rxpbs_adjust_82580(pba); 2684 break; 2685 case e1000_i210: 2686 case e1000_i211: 2687 pba = E1000_PBA_34K; 2688 break; 2689 default: 2690 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2691 if (hw->mac.max_frame_size > 8192) 2692 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2693 else 2694 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2695 } 2696 2697 /* Special needs in case of Jumbo frames */ 2698 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2699 u32 tx_space, min_tx, min_rx; 2700 pba = E1000_READ_REG(hw, E1000_PBA); 2701 tx_space = pba >> 16; 2702 pba &= 0xffff; 2703 min_tx = (hw->mac.max_frame_size + 2704 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2705 min_tx = roundup2(min_tx, 1024); 2706 min_tx >>= 10; 2707 min_rx = hw->mac.max_frame_size; 2708 min_rx = roundup2(min_rx, 1024); 2709 min_rx >>= 10; 2710 if (tx_space < min_tx && 2711 ((min_tx - tx_space) < pba)) { 2712 pba = pba - (min_tx - tx_space); 2713 /* 2714 * if short on rx space, rx wins 2715 * and must trump tx adjustment 2716 */ 2717 if (pba < min_rx) 2718 pba = min_rx; 2719 } 2720 E1000_WRITE_REG(hw, E1000_PBA, pba); 2721 } 2722 2723 if (hw->mac.type < igb_mac_min) 2724 E1000_WRITE_REG(hw, E1000_PBA, pba); 2725 2726 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2727 2728 /* 2729 * These parameters control the automatic generation (Tx) and 2730 * response (Rx) to Ethernet PAUSE frames. 2731 * - High water mark should allow for at least two frames to be 2732 * received after sending an XOFF. 2733 * - Low water mark works best when it is very near the high water mark. 2734 * This allows the receiver to restart by sending XON when it has 2735 * drained a bit. Here we use an arbitrary value of 1500 which will 2736 * restart after one full frame is pulled from the buffer. There 2737 * could be several smaller frames in the buffer and if so they will 2738 * not trigger the XON until their total number reduces the buffer 2739 * by 1500. 2740 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2741 */ 2742 rx_buffer_size = (pba & 0xffff) << 10; 2743 hw->fc.high_water = rx_buffer_size - 2744 roundup2(hw->mac.max_frame_size, 1024); 2745 hw->fc.low_water = hw->fc.high_water - 1500; 2746 2747 if (sc->fc) /* locally set flow control value? */ 2748 hw->fc.requested_mode = sc->fc; 2749 else 2750 hw->fc.requested_mode = e1000_fc_full; 2751 2752 if (hw->mac.type == e1000_80003es2lan) 2753 hw->fc.pause_time = 0xFFFF; 2754 else 2755 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2756 2757 hw->fc.send_xon = true; 2758 2759 /* Device specific overrides/settings */ 2760 switch (hw->mac.type) { 2761 case e1000_pchlan: 2762 /* Workaround: no TX flow ctrl for PCH */ 2763 hw->fc.requested_mode = e1000_fc_rx_pause; 2764 hw->fc.pause_time = 0xFFFF; /* override */ 2765 if (if_getmtu(ifp) > ETHERMTU) { 2766 hw->fc.high_water = 0x3500; 2767 hw->fc.low_water = 0x1500; 2768 } else { 2769 hw->fc.high_water = 0x5000; 2770 hw->fc.low_water = 0x3000; 2771 } 2772 hw->fc.refresh_time = 0x1000; 2773 break; 2774 case e1000_pch2lan: 2775 case e1000_pch_lpt: 2776 case e1000_pch_spt: 2777 case e1000_pch_cnp: 2778 case e1000_pch_tgp: 2779 case e1000_pch_adp: 2780 case e1000_pch_mtp: 2781 case e1000_pch_ptp: 2782 hw->fc.high_water = 0x5C20; 2783 hw->fc.low_water = 0x5048; 2784 hw->fc.pause_time = 0x0650; 2785 hw->fc.refresh_time = 0x0400; 2786 /* Jumbos need adjusted PBA */ 2787 if (if_getmtu(ifp) > ETHERMTU) 2788 E1000_WRITE_REG(hw, E1000_PBA, 12); 2789 else 2790 E1000_WRITE_REG(hw, E1000_PBA, 26); 2791 break; 2792 case e1000_82575: 2793 case e1000_82576: 2794 /* 8-byte granularity */ 2795 hw->fc.low_water = hw->fc.high_water - 8; 2796 break; 2797 case e1000_82580: 2798 case e1000_i350: 2799 case e1000_i354: 2800 case e1000_i210: 2801 case e1000_i211: 2802 case e1000_vfadapt: 2803 case e1000_vfadapt_i350: 2804 /* 16-byte granularity */ 2805 hw->fc.low_water = hw->fc.high_water - 16; 2806 break; 2807 case e1000_ich9lan: 2808 case e1000_ich10lan: 2809 if (if_getmtu(ifp) > ETHERMTU) { 2810 hw->fc.high_water = 0x2800; 2811 hw->fc.low_water = hw->fc.high_water - 8; 2812 break; 2813 } 2814 /* FALLTHROUGH */ 2815 default: 2816 if (hw->mac.type == e1000_80003es2lan) 2817 hw->fc.pause_time = 0xFFFF; 2818 break; 2819 } 2820 2821 /* I219 needs some special flushing to avoid hangs */ 2822 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2823 em_flush_desc_rings(sc); 2824 2825 /* Issue a global reset */ 2826 e1000_reset_hw(hw); 2827 if (hw->mac.type >= igb_mac_min) { 2828 E1000_WRITE_REG(hw, E1000_WUC, 0); 2829 } else { 2830 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2831 em_disable_aspm(sc); 2832 } 2833 if (sc->flags & IGB_MEDIA_RESET) { 2834 e1000_setup_init_funcs(hw, true); 2835 e1000_get_bus_info(hw); 2836 sc->flags &= ~IGB_MEDIA_RESET; 2837 } 2838 /* and a re-init */ 2839 if (e1000_init_hw(hw) < 0) { 2840 device_printf(dev, "Hardware Initialization Failed\n"); 2841 return; 2842 } 2843 if (hw->mac.type >= igb_mac_min) 2844 igb_init_dmac(sc, pba); 2845 2846 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2847 e1000_get_phy_info(hw); 2848 e1000_check_for_link(hw); 2849 } 2850 2851 /* 2852 * Initialise the RSS mapping for NICs that support multiple transmit/ 2853 * receive rings. 2854 */ 2855 2856 #define RSSKEYLEN 10 2857 static void 2858 em_initialize_rss_mapping(struct e1000_softc *sc) 2859 { 2860 uint8_t rss_key[4 * RSSKEYLEN]; 2861 uint32_t reta = 0; 2862 struct e1000_hw *hw = &sc->hw; 2863 int i; 2864 2865 /* 2866 * Configure RSS key 2867 */ 2868 arc4rand(rss_key, sizeof(rss_key), 0); 2869 for (i = 0; i < RSSKEYLEN; ++i) { 2870 uint32_t rssrk = 0; 2871 2872 rssrk = EM_RSSRK_VAL(rss_key, i); 2873 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2874 } 2875 2876 /* 2877 * Configure RSS redirect table in following fashion: 2878 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2879 */ 2880 for (i = 0; i < sizeof(reta); ++i) { 2881 uint32_t q; 2882 2883 q = (i % sc->rx_num_queues) << 7; 2884 reta |= q << (8 * i); 2885 } 2886 2887 for (i = 0; i < 32; ++i) 2888 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2889 2890 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2891 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2892 E1000_MRQC_RSS_FIELD_IPV4 | 2893 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2894 E1000_MRQC_RSS_FIELD_IPV6_EX | 2895 E1000_MRQC_RSS_FIELD_IPV6); 2896 } 2897 2898 static void 2899 igb_initialize_rss_mapping(struct e1000_softc *sc) 2900 { 2901 struct e1000_hw *hw = &sc->hw; 2902 int i; 2903 int queue_id; 2904 u32 reta; 2905 u32 rss_key[10], mrqc, shift = 0; 2906 2907 /* XXX? */ 2908 if (hw->mac.type == e1000_82575) 2909 shift = 6; 2910 2911 /* 2912 * The redirection table controls which destination 2913 * queue each bucket redirects traffic to. 2914 * Each DWORD represents four queues, with the LSB 2915 * being the first queue in the DWORD. 2916 * 2917 * This just allocates buckets to queues using round-robin 2918 * allocation. 2919 * 2920 * NOTE: It Just Happens to line up with the default 2921 * RSS allocation method. 2922 */ 2923 2924 /* Warning FM follows */ 2925 reta = 0; 2926 for (i = 0; i < 128; i++) { 2927 #ifdef RSS 2928 queue_id = rss_get_indirection_to_bucket(i); 2929 /* 2930 * If we have more queues than buckets, we'll 2931 * end up mapping buckets to a subset of the 2932 * queues. 2933 * 2934 * If we have more buckets than queues, we'll 2935 * end up instead assigning multiple buckets 2936 * to queues. 2937 * 2938 * Both are suboptimal, but we need to handle 2939 * the case so we don't go out of bounds 2940 * indexing arrays and such. 2941 */ 2942 queue_id = queue_id % sc->rx_num_queues; 2943 #else 2944 queue_id = (i % sc->rx_num_queues); 2945 #endif 2946 /* Adjust if required */ 2947 queue_id = queue_id << shift; 2948 2949 /* 2950 * The low 8 bits are for hash value (n+0); 2951 * The next 8 bits are for hash value (n+1), etc. 2952 */ 2953 reta = reta >> 8; 2954 reta = reta | ( ((uint32_t) queue_id) << 24); 2955 if ((i & 3) == 3) { 2956 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2957 reta = 0; 2958 } 2959 } 2960 2961 /* Now fill in hash table */ 2962 2963 /* 2964 * MRQC: Multiple Receive Queues Command 2965 * Set queuing to RSS control, number depends on the device. 2966 */ 2967 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2968 2969 #ifdef RSS 2970 /* XXX ew typecasting */ 2971 rss_getkey((uint8_t *) &rss_key); 2972 #else 2973 arc4rand(&rss_key, sizeof(rss_key), 0); 2974 #endif 2975 for (i = 0; i < 10; i++) 2976 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2977 2978 /* 2979 * Configure the RSS fields to hash upon. 2980 */ 2981 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2982 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2983 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2984 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2985 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2986 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2987 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2988 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2989 2990 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2991 } 2992 2993 /********************************************************************* 2994 * 2995 * Setup networking device structure and register interface media. 2996 * 2997 **********************************************************************/ 2998 static int 2999 em_setup_interface(if_ctx_t ctx) 3000 { 3001 if_t ifp = iflib_get_ifp(ctx); 3002 struct e1000_softc *sc = iflib_get_softc(ctx); 3003 if_softc_ctx_t scctx = sc->shared; 3004 3005 INIT_DEBUGOUT("em_setup_interface: begin"); 3006 3007 /* Single Queue */ 3008 if (sc->tx_num_queues == 1) { 3009 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3010 if_setsendqready(ifp); 3011 } 3012 3013 /* 3014 * Specify the media types supported by this adapter and register 3015 * callbacks to update media and link information 3016 */ 3017 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3018 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3019 u_char fiber_type = IFM_1000_SX; /* default type */ 3020 3021 if (sc->hw.mac.type == e1000_82545) 3022 fiber_type = IFM_1000_LX; 3023 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3024 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3025 } else { 3026 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3027 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3028 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3029 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3030 if (sc->hw.phy.type != e1000_phy_ife) { 3031 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3032 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3033 } 3034 } 3035 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3036 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3037 return (0); 3038 } 3039 3040 static int 3041 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3042 { 3043 struct e1000_softc *sc = iflib_get_softc(ctx); 3044 if_softc_ctx_t scctx = sc->shared; 3045 int error = E1000_SUCCESS; 3046 struct em_tx_queue *que; 3047 int i, j; 3048 3049 MPASS(sc->tx_num_queues > 0); 3050 MPASS(sc->tx_num_queues == ntxqsets); 3051 3052 /* First allocate the top level queue structs */ 3053 if (!(sc->tx_queues = 3054 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3055 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3056 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3057 return(ENOMEM); 3058 } 3059 3060 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3061 /* Set up some basics */ 3062 3063 struct tx_ring *txr = &que->txr; 3064 txr->sc = que->sc = sc; 3065 que->me = txr->me = i; 3066 3067 /* Allocate report status array */ 3068 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3069 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3070 error = ENOMEM; 3071 goto fail; 3072 } 3073 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3074 txr->tx_rsq[j] = QIDX_INVALID; 3075 /* get the virtual and physical address of the hardware queues */ 3076 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3077 txr->tx_paddr = paddrs[i*ntxqs]; 3078 } 3079 3080 if (bootverbose) 3081 device_printf(iflib_get_dev(ctx), 3082 "allocated for %d tx_queues\n", sc->tx_num_queues); 3083 return (0); 3084 fail: 3085 em_if_queues_free(ctx); 3086 return (error); 3087 } 3088 3089 static int 3090 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3091 { 3092 struct e1000_softc *sc = iflib_get_softc(ctx); 3093 int error = E1000_SUCCESS; 3094 struct em_rx_queue *que; 3095 int i; 3096 3097 MPASS(sc->rx_num_queues > 0); 3098 MPASS(sc->rx_num_queues == nrxqsets); 3099 3100 /* First allocate the top level queue structs */ 3101 if (!(sc->rx_queues = 3102 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3103 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3104 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3105 error = ENOMEM; 3106 goto fail; 3107 } 3108 3109 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3110 /* Set up some basics */ 3111 struct rx_ring *rxr = &que->rxr; 3112 rxr->sc = que->sc = sc; 3113 rxr->que = que; 3114 que->me = rxr->me = i; 3115 3116 /* get the virtual and physical address of the hardware queues */ 3117 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3118 rxr->rx_paddr = paddrs[i*nrxqs]; 3119 } 3120 3121 if (bootverbose) 3122 device_printf(iflib_get_dev(ctx), 3123 "allocated for %d rx_queues\n", sc->rx_num_queues); 3124 3125 return (0); 3126 fail: 3127 em_if_queues_free(ctx); 3128 return (error); 3129 } 3130 3131 static void 3132 em_if_queues_free(if_ctx_t ctx) 3133 { 3134 struct e1000_softc *sc = iflib_get_softc(ctx); 3135 struct em_tx_queue *tx_que = sc->tx_queues; 3136 struct em_rx_queue *rx_que = sc->rx_queues; 3137 3138 if (tx_que != NULL) { 3139 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3140 struct tx_ring *txr = &tx_que->txr; 3141 if (txr->tx_rsq == NULL) 3142 break; 3143 3144 free(txr->tx_rsq, M_DEVBUF); 3145 txr->tx_rsq = NULL; 3146 } 3147 free(sc->tx_queues, M_DEVBUF); 3148 sc->tx_queues = NULL; 3149 } 3150 3151 if (rx_que != NULL) { 3152 free(sc->rx_queues, M_DEVBUF); 3153 sc->rx_queues = NULL; 3154 } 3155 } 3156 3157 /********************************************************************* 3158 * 3159 * Enable transmit unit. 3160 * 3161 **********************************************************************/ 3162 static void 3163 em_initialize_transmit_unit(if_ctx_t ctx) 3164 { 3165 struct e1000_softc *sc = iflib_get_softc(ctx); 3166 if_softc_ctx_t scctx = sc->shared; 3167 struct em_tx_queue *que; 3168 struct tx_ring *txr; 3169 struct e1000_hw *hw = &sc->hw; 3170 u32 tctl, txdctl = 0, tarc, tipg = 0; 3171 3172 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3173 3174 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3175 u64 bus_addr; 3176 caddr_t offp, endp; 3177 3178 que = &sc->tx_queues[i]; 3179 txr = &que->txr; 3180 bus_addr = txr->tx_paddr; 3181 3182 /* Clear checksum offload context. */ 3183 offp = (caddr_t)&txr->csum_flags; 3184 endp = (caddr_t)(txr + 1); 3185 bzero(offp, endp - offp); 3186 3187 /* Base and Len of TX Ring */ 3188 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3189 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3190 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3191 (u32)(bus_addr >> 32)); 3192 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3193 (u32)bus_addr); 3194 /* Init the HEAD/TAIL indices */ 3195 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3196 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3197 3198 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3199 E1000_READ_REG(hw, E1000_TDBAL(i)), 3200 E1000_READ_REG(hw, E1000_TDLEN(i))); 3201 3202 txdctl = 0; /* clear txdctl */ 3203 txdctl |= 0x1f; /* PTHRESH */ 3204 txdctl |= 1 << 8; /* HTHRESH */ 3205 txdctl |= 1 << 16;/* WTHRESH */ 3206 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3207 txdctl |= E1000_TXDCTL_GRAN; 3208 txdctl |= 1 << 25; /* LWTHRESH */ 3209 3210 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3211 } 3212 3213 /* Set the default values for the Tx Inter Packet Gap timer */ 3214 switch (hw->mac.type) { 3215 case e1000_80003es2lan: 3216 tipg = DEFAULT_82543_TIPG_IPGR1; 3217 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3218 E1000_TIPG_IPGR2_SHIFT; 3219 break; 3220 case e1000_82542: 3221 tipg = DEFAULT_82542_TIPG_IPGT; 3222 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3223 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3224 break; 3225 default: 3226 if (hw->phy.media_type == e1000_media_type_fiber || 3227 hw->phy.media_type == e1000_media_type_internal_serdes) 3228 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3229 else 3230 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3231 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3232 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3233 } 3234 3235 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3236 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3237 3238 if(hw->mac.type >= e1000_82540) 3239 E1000_WRITE_REG(hw, E1000_TADV, 3240 sc->tx_abs_int_delay.value); 3241 3242 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3243 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3244 tarc |= TARC_SPEED_MODE_BIT; 3245 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3246 } else if (hw->mac.type == e1000_80003es2lan) { 3247 /* errata: program both queues to unweighted RR */ 3248 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3249 tarc |= 1; 3250 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3251 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3252 tarc |= 1; 3253 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3254 } else if (hw->mac.type == e1000_82574) { 3255 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3256 tarc |= TARC_ERRATA_BIT; 3257 if ( sc->tx_num_queues > 1) { 3258 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3259 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3260 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3261 } else 3262 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3263 } 3264 3265 if (sc->tx_int_delay.value > 0) 3266 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3267 3268 /* Program the Transmit Control Register */ 3269 tctl = E1000_READ_REG(hw, E1000_TCTL); 3270 tctl &= ~E1000_TCTL_CT; 3271 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3272 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3273 3274 if (hw->mac.type >= e1000_82571) 3275 tctl |= E1000_TCTL_MULR; 3276 3277 /* This write will effectively turn on the transmit unit. */ 3278 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3279 3280 /* SPT and KBL errata workarounds */ 3281 if (hw->mac.type == e1000_pch_spt) { 3282 u32 reg; 3283 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3284 reg |= E1000_RCTL_RDMTS_HEX; 3285 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3286 /* i218-i219 Specification Update 1.5.4.5 */ 3287 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3288 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3289 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3290 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3291 } 3292 } 3293 3294 /********************************************************************* 3295 * 3296 * Enable receive unit. 3297 * 3298 **********************************************************************/ 3299 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3300 3301 static void 3302 em_initialize_receive_unit(if_ctx_t ctx) 3303 { 3304 struct e1000_softc *sc = iflib_get_softc(ctx); 3305 if_softc_ctx_t scctx = sc->shared; 3306 if_t ifp = iflib_get_ifp(ctx); 3307 struct e1000_hw *hw = &sc->hw; 3308 struct em_rx_queue *que; 3309 int i; 3310 uint32_t rctl, rxcsum; 3311 3312 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3313 3314 /* 3315 * Make sure receives are disabled while setting 3316 * up the descriptor ring 3317 */ 3318 rctl = E1000_READ_REG(hw, E1000_RCTL); 3319 /* Do not disable if ever enabled on this hardware */ 3320 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3321 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3322 3323 /* Setup the Receive Control Register */ 3324 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3325 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3326 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3327 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3328 3329 /* Do not store bad packets */ 3330 rctl &= ~E1000_RCTL_SBP; 3331 3332 /* Enable Long Packet receive */ 3333 if (if_getmtu(ifp) > ETHERMTU) 3334 rctl |= E1000_RCTL_LPE; 3335 else 3336 rctl &= ~E1000_RCTL_LPE; 3337 3338 /* Strip the CRC */ 3339 if (!em_disable_crc_stripping) 3340 rctl |= E1000_RCTL_SECRC; 3341 3342 if (hw->mac.type >= e1000_82540) { 3343 E1000_WRITE_REG(hw, E1000_RADV, 3344 sc->rx_abs_int_delay.value); 3345 3346 /* 3347 * Set the interrupt throttling rate. Value is calculated 3348 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3349 */ 3350 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3351 } 3352 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3353 3354 if (hw->mac.type >= em_mac_min) { 3355 uint32_t rfctl; 3356 /* Use extended rx descriptor formats */ 3357 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3358 rfctl |= E1000_RFCTL_EXTEN; 3359 3360 /* 3361 * When using MSI-X interrupts we need to throttle 3362 * using the EITR register (82574 only) 3363 */ 3364 if (hw->mac.type == e1000_82574) { 3365 for (int i = 0; i < 4; i++) 3366 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3367 DEFAULT_ITR); 3368 /* Disable accelerated acknowledge */ 3369 rfctl |= E1000_RFCTL_ACK_DIS; 3370 } 3371 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3372 } 3373 3374 /* Set up L3 and L4 csum Rx descriptor offloads */ 3375 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3376 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3377 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3378 if (hw->mac.type > e1000_82575) 3379 rxcsum |= E1000_RXCSUM_CRCOFL; 3380 else if (hw->mac.type < em_mac_min && 3381 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3382 rxcsum |= E1000_RXCSUM_IPV6OFL; 3383 } else { 3384 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3385 if (hw->mac.type > e1000_82575) 3386 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3387 else if (hw->mac.type < em_mac_min) 3388 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3389 } 3390 3391 if (sc->rx_num_queues > 1) { 3392 /* RSS hash needed in the Rx descriptor */ 3393 rxcsum |= E1000_RXCSUM_PCSD; 3394 3395 if (hw->mac.type >= igb_mac_min) 3396 igb_initialize_rss_mapping(sc); 3397 else 3398 em_initialize_rss_mapping(sc); 3399 } 3400 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3401 3402 /* 3403 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3404 * long latencies are observed, like Lenovo X60. This 3405 * change eliminates the problem, but since having positive 3406 * values in RDTR is a known source of problems on other 3407 * platforms another solution is being sought. 3408 */ 3409 if (hw->mac.type == e1000_82573) 3410 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3411 3412 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3413 struct rx_ring *rxr = &que->rxr; 3414 /* Setup the Base and Length of the Rx Descriptor Ring */ 3415 u64 bus_addr = rxr->rx_paddr; 3416 #if 0 3417 u32 rdt = sc->rx_num_queues -1; /* default */ 3418 #endif 3419 3420 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3421 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3422 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3423 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3424 /* Setup the Head and Tail Descriptor Pointers */ 3425 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3426 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3427 } 3428 3429 /* 3430 * Set PTHRESH for improved jumbo performance 3431 * According to 10.2.5.11 of Intel 82574 Datasheet, 3432 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3433 * Only write to RXDCTL(1) if there is a need for different 3434 * settings. 3435 */ 3436 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3437 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3438 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3439 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3440 } else if (hw->mac.type == e1000_82574) { 3441 for (int i = 0; i < sc->rx_num_queues; i++) { 3442 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3443 rxdctl |= 0x20; /* PTHRESH */ 3444 rxdctl |= 4 << 8; /* HTHRESH */ 3445 rxdctl |= 4 << 16;/* WTHRESH */ 3446 rxdctl |= 1 << 24; /* Switch to granularity */ 3447 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3448 } 3449 } else if (hw->mac.type >= igb_mac_min) { 3450 u32 psize, srrctl = 0; 3451 3452 if (if_getmtu(ifp) > ETHERMTU) { 3453 psize = scctx->isc_max_frame_size; 3454 /* are we on a vlan? */ 3455 if (if_vlantrunkinuse(ifp)) 3456 psize += VLAN_TAG_SIZE; 3457 3458 if (sc->vf_ifp) 3459 e1000_rlpml_set_vf(hw, psize); 3460 else 3461 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3462 } 3463 3464 /* Set maximum packet buffer len */ 3465 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3466 E1000_SRRCTL_BSIZEPKT_SHIFT; 3467 3468 /* 3469 * If TX flow control is disabled and there's >1 queue defined, 3470 * enable DROP. 3471 * 3472 * This drops frames rather than hanging the RX MAC for all queues. 3473 */ 3474 if ((sc->rx_num_queues > 1) && 3475 (sc->fc == e1000_fc_none || 3476 sc->fc == e1000_fc_rx_pause)) { 3477 srrctl |= E1000_SRRCTL_DROP_EN; 3478 } 3479 /* Setup the Base and Length of the Rx Descriptor Rings */ 3480 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3481 struct rx_ring *rxr = &que->rxr; 3482 u64 bus_addr = rxr->rx_paddr; 3483 u32 rxdctl; 3484 3485 #ifdef notyet 3486 /* Configure for header split? -- ignore for now */ 3487 rxr->hdr_split = igb_header_split; 3488 #else 3489 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3490 #endif 3491 3492 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3493 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3494 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3495 (uint32_t)(bus_addr >> 32)); 3496 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3497 (uint32_t)bus_addr); 3498 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3499 /* Enable this Queue */ 3500 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3501 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3502 rxdctl &= 0xFFF00000; 3503 rxdctl |= IGB_RX_PTHRESH; 3504 rxdctl |= IGB_RX_HTHRESH << 8; 3505 rxdctl |= IGB_RX_WTHRESH << 16; 3506 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3507 } 3508 } else if (hw->mac.type >= e1000_pch2lan) { 3509 if (if_getmtu(ifp) > ETHERMTU) 3510 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3511 else 3512 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3513 } 3514 3515 /* Make sure VLAN Filters are off */ 3516 rctl &= ~E1000_RCTL_VFE; 3517 3518 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3519 if (hw->mac.type < igb_mac_min) { 3520 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3521 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3522 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3523 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3524 else if (sc->rx_mbuf_sz > 8192) 3525 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3526 else { 3527 rctl |= E1000_RCTL_SZ_2048; 3528 rctl &= ~E1000_RCTL_BSEX; 3529 } 3530 } else 3531 rctl |= E1000_RCTL_SZ_2048; 3532 3533 /* 3534 * rctl bits 11:10 are as follows 3535 * lem: reserved 3536 * em: DTYPE 3537 * igb: reserved 3538 * and should be 00 on all of the above 3539 */ 3540 rctl &= ~0x00000C00; 3541 3542 /* Write out the settings */ 3543 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3544 3545 return; 3546 } 3547 3548 static void 3549 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3550 { 3551 struct e1000_softc *sc = iflib_get_softc(ctx); 3552 u32 index, bit; 3553 3554 index = (vtag >> 5) & 0x7F; 3555 bit = vtag & 0x1F; 3556 sc->shadow_vfta[index] |= (1 << bit); 3557 ++sc->num_vlans; 3558 em_if_vlan_filter_write(sc); 3559 } 3560 3561 static void 3562 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3563 { 3564 struct e1000_softc *sc = iflib_get_softc(ctx); 3565 u32 index, bit; 3566 3567 index = (vtag >> 5) & 0x7F; 3568 bit = vtag & 0x1F; 3569 sc->shadow_vfta[index] &= ~(1 << bit); 3570 --sc->num_vlans; 3571 em_if_vlan_filter_write(sc); 3572 } 3573 3574 static bool 3575 em_if_vlan_filter_capable(if_ctx_t ctx) 3576 { 3577 if_t ifp = iflib_get_ifp(ctx); 3578 3579 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3580 !em_disable_crc_stripping) 3581 return (true); 3582 3583 return (false); 3584 } 3585 3586 static bool 3587 em_if_vlan_filter_used(if_ctx_t ctx) 3588 { 3589 struct e1000_softc *sc = iflib_get_softc(ctx); 3590 3591 if (!em_if_vlan_filter_capable(ctx)) 3592 return (false); 3593 3594 for (int i = 0; i < EM_VFTA_SIZE; i++) 3595 if (sc->shadow_vfta[i] != 0) 3596 return (true); 3597 3598 return (false); 3599 } 3600 3601 static void 3602 em_if_vlan_filter_enable(struct e1000_softc *sc) 3603 { 3604 struct e1000_hw *hw = &sc->hw; 3605 u32 reg; 3606 3607 reg = E1000_READ_REG(hw, E1000_RCTL); 3608 reg &= ~E1000_RCTL_CFIEN; 3609 reg |= E1000_RCTL_VFE; 3610 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3611 } 3612 3613 static void 3614 em_if_vlan_filter_disable(struct e1000_softc *sc) 3615 { 3616 struct e1000_hw *hw = &sc->hw; 3617 u32 reg; 3618 3619 reg = E1000_READ_REG(hw, E1000_RCTL); 3620 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3621 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3622 } 3623 3624 static void 3625 em_if_vlan_filter_write(struct e1000_softc *sc) 3626 { 3627 struct e1000_hw *hw = &sc->hw; 3628 3629 if (sc->vf_ifp) 3630 return; 3631 3632 /* Disable interrupts for lem-class devices during the filter change */ 3633 if (hw->mac.type < em_mac_min) 3634 em_if_intr_disable(sc->ctx); 3635 3636 for (int i = 0; i < EM_VFTA_SIZE; i++) 3637 if (sc->shadow_vfta[i] != 0) { 3638 /* XXXKB: incomplete VF support, we return early above */ 3639 if (sc->vf_ifp) 3640 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3641 else 3642 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3643 } 3644 3645 /* Re-enable interrupts for lem-class devices */ 3646 if (hw->mac.type < em_mac_min) 3647 em_if_intr_enable(sc->ctx); 3648 } 3649 3650 static void 3651 em_setup_vlan_hw_support(if_ctx_t ctx) 3652 { 3653 struct e1000_softc *sc = iflib_get_softc(ctx); 3654 struct e1000_hw *hw = &sc->hw; 3655 if_t ifp = iflib_get_ifp(ctx); 3656 u32 reg; 3657 3658 /* XXXKB: Return early if we are a VF until VF decap and filter management 3659 * is ready and tested. 3660 */ 3661 if (sc->vf_ifp) 3662 return; 3663 3664 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3665 !em_disable_crc_stripping) { 3666 reg = E1000_READ_REG(hw, E1000_CTRL); 3667 reg |= E1000_CTRL_VME; 3668 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3669 } else { 3670 reg = E1000_READ_REG(hw, E1000_CTRL); 3671 reg &= ~E1000_CTRL_VME; 3672 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3673 } 3674 3675 /* If we aren't doing HW filtering, we're done */ 3676 if (!em_if_vlan_filter_capable(ctx)) { 3677 em_if_vlan_filter_disable(sc); 3678 return; 3679 } 3680 3681 /* 3682 * A soft reset zero's out the VFTA, so 3683 * we need to repopulate it now. 3684 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3685 * traffic through. This will write the entire table. 3686 */ 3687 em_if_vlan_register(ctx, 0); 3688 3689 /* Enable the Filter Table */ 3690 em_if_vlan_filter_enable(sc); 3691 } 3692 3693 static void 3694 em_if_intr_enable(if_ctx_t ctx) 3695 { 3696 struct e1000_softc *sc = iflib_get_softc(ctx); 3697 struct e1000_hw *hw = &sc->hw; 3698 u32 ims_mask = IMS_ENABLE_MASK; 3699 3700 if (sc->intr_type == IFLIB_INTR_MSIX) { 3701 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3702 ims_mask |= sc->ims; 3703 } 3704 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3705 E1000_WRITE_FLUSH(hw); 3706 } 3707 3708 static void 3709 em_if_intr_disable(if_ctx_t ctx) 3710 { 3711 struct e1000_softc *sc = iflib_get_softc(ctx); 3712 struct e1000_hw *hw = &sc->hw; 3713 3714 if (sc->intr_type == IFLIB_INTR_MSIX) 3715 E1000_WRITE_REG(hw, EM_EIAC, 0); 3716 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3717 E1000_WRITE_FLUSH(hw); 3718 } 3719 3720 static void 3721 igb_if_intr_enable(if_ctx_t ctx) 3722 { 3723 struct e1000_softc *sc = iflib_get_softc(ctx); 3724 struct e1000_hw *hw = &sc->hw; 3725 u32 mask; 3726 3727 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3728 mask = (sc->que_mask | sc->link_mask); 3729 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3730 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3731 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3732 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3733 } else 3734 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3735 E1000_WRITE_FLUSH(hw); 3736 } 3737 3738 static void 3739 igb_if_intr_disable(if_ctx_t ctx) 3740 { 3741 struct e1000_softc *sc = iflib_get_softc(ctx); 3742 struct e1000_hw *hw = &sc->hw; 3743 3744 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3745 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3746 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3747 } 3748 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3749 E1000_WRITE_FLUSH(hw); 3750 } 3751 3752 /* 3753 * Bit of a misnomer, what this really means is 3754 * to enable OS management of the system... aka 3755 * to disable special hardware management features 3756 */ 3757 static void 3758 em_init_manageability(struct e1000_softc *sc) 3759 { 3760 /* A shared code workaround */ 3761 #define E1000_82542_MANC2H E1000_MANC2H 3762 if (sc->has_manage) { 3763 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3764 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3765 3766 /* disable hardware interception of ARP */ 3767 manc &= ~(E1000_MANC_ARP_EN); 3768 3769 /* enable receiving management packets to the host */ 3770 manc |= E1000_MANC_EN_MNG2HOST; 3771 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3772 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3773 manc2h |= E1000_MNG2HOST_PORT_623; 3774 manc2h |= E1000_MNG2HOST_PORT_664; 3775 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3776 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3777 } 3778 } 3779 3780 /* 3781 * Give control back to hardware management 3782 * controller if there is one. 3783 */ 3784 static void 3785 em_release_manageability(struct e1000_softc *sc) 3786 { 3787 if (sc->has_manage) { 3788 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3789 3790 /* re-enable hardware interception of ARP */ 3791 manc |= E1000_MANC_ARP_EN; 3792 manc &= ~E1000_MANC_EN_MNG2HOST; 3793 3794 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3795 } 3796 } 3797 3798 /* 3799 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3800 * For ASF and Pass Through versions of f/w this means 3801 * that the driver is loaded. For AMT version type f/w 3802 * this means that the network i/f is open. 3803 */ 3804 static void 3805 em_get_hw_control(struct e1000_softc *sc) 3806 { 3807 u32 ctrl_ext, swsm; 3808 3809 if (sc->vf_ifp) 3810 return; 3811 3812 if (sc->hw.mac.type == e1000_82573) { 3813 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3814 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3815 swsm | E1000_SWSM_DRV_LOAD); 3816 return; 3817 } 3818 /* else */ 3819 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3820 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3821 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3822 } 3823 3824 /* 3825 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3826 * For ASF and Pass Through versions of f/w this means that 3827 * the driver is no longer loaded. For AMT versions of the 3828 * f/w this means that the network i/f is closed. 3829 */ 3830 static void 3831 em_release_hw_control(struct e1000_softc *sc) 3832 { 3833 u32 ctrl_ext, swsm; 3834 3835 if (!sc->has_manage) 3836 return; 3837 3838 if (sc->hw.mac.type == e1000_82573) { 3839 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3840 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3841 swsm & ~E1000_SWSM_DRV_LOAD); 3842 return; 3843 } 3844 /* else */ 3845 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3846 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3847 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3848 return; 3849 } 3850 3851 static int 3852 em_is_valid_ether_addr(u8 *addr) 3853 { 3854 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3855 3856 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3857 return (false); 3858 } 3859 3860 return (true); 3861 } 3862 3863 /* 3864 ** Parse the interface capabilities with regard 3865 ** to both system management and wake-on-lan for 3866 ** later use. 3867 */ 3868 static void 3869 em_get_wakeup(if_ctx_t ctx) 3870 { 3871 struct e1000_softc *sc = iflib_get_softc(ctx); 3872 device_t dev = iflib_get_dev(ctx); 3873 u16 eeprom_data = 0, device_id, apme_mask; 3874 3875 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3876 apme_mask = EM_EEPROM_APME; 3877 3878 switch (sc->hw.mac.type) { 3879 case e1000_82542: 3880 case e1000_82543: 3881 break; 3882 case e1000_82544: 3883 e1000_read_nvm(&sc->hw, 3884 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3885 apme_mask = EM_82544_APME; 3886 break; 3887 case e1000_82546: 3888 case e1000_82546_rev_3: 3889 if (sc->hw.bus.func == 1) { 3890 e1000_read_nvm(&sc->hw, 3891 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3892 break; 3893 } else 3894 e1000_read_nvm(&sc->hw, 3895 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3896 break; 3897 case e1000_82573: 3898 case e1000_82583: 3899 sc->has_amt = true; 3900 /* FALLTHROUGH */ 3901 case e1000_82571: 3902 case e1000_82572: 3903 case e1000_80003es2lan: 3904 if (sc->hw.bus.func == 1) { 3905 e1000_read_nvm(&sc->hw, 3906 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3907 break; 3908 } else 3909 e1000_read_nvm(&sc->hw, 3910 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3911 break; 3912 case e1000_ich8lan: 3913 case e1000_ich9lan: 3914 case e1000_ich10lan: 3915 case e1000_pchlan: 3916 case e1000_pch2lan: 3917 case e1000_pch_lpt: 3918 case e1000_pch_spt: 3919 case e1000_82575: /* listing all igb devices */ 3920 case e1000_82576: 3921 case e1000_82580: 3922 case e1000_i350: 3923 case e1000_i354: 3924 case e1000_i210: 3925 case e1000_i211: 3926 case e1000_vfadapt: 3927 case e1000_vfadapt_i350: 3928 apme_mask = E1000_WUC_APME; 3929 sc->has_amt = true; 3930 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 3931 break; 3932 default: 3933 e1000_read_nvm(&sc->hw, 3934 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3935 break; 3936 } 3937 if (eeprom_data & apme_mask) 3938 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3939 /* 3940 * We have the eeprom settings, now apply the special cases 3941 * where the eeprom may be wrong or the board won't support 3942 * wake on lan on a particular port 3943 */ 3944 device_id = pci_get_device(dev); 3945 switch (device_id) { 3946 case E1000_DEV_ID_82546GB_PCIE: 3947 sc->wol = 0; 3948 break; 3949 case E1000_DEV_ID_82546EB_FIBER: 3950 case E1000_DEV_ID_82546GB_FIBER: 3951 /* Wake events only supported on port A for dual fiber 3952 * regardless of eeprom setting */ 3953 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3954 E1000_STATUS_FUNC_1) 3955 sc->wol = 0; 3956 break; 3957 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3958 /* if quad port adapter, disable WoL on all but port A */ 3959 if (global_quad_port_a != 0) 3960 sc->wol = 0; 3961 /* Reset for multiple quad port adapters */ 3962 if (++global_quad_port_a == 4) 3963 global_quad_port_a = 0; 3964 break; 3965 case E1000_DEV_ID_82571EB_FIBER: 3966 /* Wake events only supported on port A for dual fiber 3967 * regardless of eeprom setting */ 3968 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3969 E1000_STATUS_FUNC_1) 3970 sc->wol = 0; 3971 break; 3972 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3973 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3974 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3975 /* if quad port adapter, disable WoL on all but port A */ 3976 if (global_quad_port_a != 0) 3977 sc->wol = 0; 3978 /* Reset for multiple quad port adapters */ 3979 if (++global_quad_port_a == 4) 3980 global_quad_port_a = 0; 3981 break; 3982 } 3983 return; 3984 } 3985 3986 3987 /* 3988 * Enable PCI Wake On Lan capability 3989 */ 3990 static void 3991 em_enable_wakeup(if_ctx_t ctx) 3992 { 3993 struct e1000_softc *sc = iflib_get_softc(ctx); 3994 device_t dev = iflib_get_dev(ctx); 3995 if_t ifp = iflib_get_ifp(ctx); 3996 int error = 0; 3997 u32 pmc, ctrl, ctrl_ext, rctl; 3998 u16 status; 3999 4000 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4001 return; 4002 4003 /* 4004 * Determine type of Wakeup: note that wol 4005 * is set with all bits on by default. 4006 */ 4007 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4008 sc->wol &= ~E1000_WUFC_MAG; 4009 4010 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4011 sc->wol &= ~E1000_WUFC_EX; 4012 4013 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4014 sc->wol &= ~E1000_WUFC_MC; 4015 else { 4016 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4017 rctl |= E1000_RCTL_MPE; 4018 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4019 } 4020 4021 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4022 goto pme; 4023 4024 /* Advertise the wakeup capability */ 4025 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4026 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4027 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4028 4029 /* Keep the laser running on Fiber adapters */ 4030 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4031 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4032 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4033 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4034 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4035 } 4036 4037 if ((sc->hw.mac.type == e1000_ich8lan) || 4038 (sc->hw.mac.type == e1000_pchlan) || 4039 (sc->hw.mac.type == e1000_ich9lan) || 4040 (sc->hw.mac.type == e1000_ich10lan)) 4041 e1000_suspend_workarounds_ich8lan(&sc->hw); 4042 4043 if ( sc->hw.mac.type >= e1000_pchlan) { 4044 error = em_enable_phy_wakeup(sc); 4045 if (error) 4046 goto pme; 4047 } else { 4048 /* Enable wakeup by the MAC */ 4049 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4050 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4051 } 4052 4053 if (sc->hw.phy.type == e1000_phy_igp_3) 4054 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4055 4056 pme: 4057 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4058 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4059 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4060 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4061 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4062 4063 return; 4064 } 4065 4066 /* 4067 * WOL in the newer chipset interfaces (pchlan) 4068 * require thing to be copied into the phy 4069 */ 4070 static int 4071 em_enable_phy_wakeup(struct e1000_softc *sc) 4072 { 4073 struct e1000_hw *hw = &sc->hw; 4074 u32 mreg, ret = 0; 4075 u16 preg; 4076 4077 /* copy MAC RARs to PHY RARs */ 4078 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4079 4080 /* copy MAC MTA to PHY MTA */ 4081 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4082 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4083 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4084 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4085 (u16)((mreg >> 16) & 0xFFFF)); 4086 } 4087 4088 /* configure PHY Rx Control register */ 4089 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4090 mreg = E1000_READ_REG(hw, E1000_RCTL); 4091 if (mreg & E1000_RCTL_UPE) 4092 preg |= BM_RCTL_UPE; 4093 if (mreg & E1000_RCTL_MPE) 4094 preg |= BM_RCTL_MPE; 4095 preg &= ~(BM_RCTL_MO_MASK); 4096 if (mreg & E1000_RCTL_MO_3) 4097 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4098 << BM_RCTL_MO_SHIFT); 4099 if (mreg & E1000_RCTL_BAM) 4100 preg |= BM_RCTL_BAM; 4101 if (mreg & E1000_RCTL_PMCF) 4102 preg |= BM_RCTL_PMCF; 4103 mreg = E1000_READ_REG(hw, E1000_CTRL); 4104 if (mreg & E1000_CTRL_RFCE) 4105 preg |= BM_RCTL_RFCE; 4106 e1000_write_phy_reg(hw, BM_RCTL, preg); 4107 4108 /* enable PHY wakeup in MAC register */ 4109 E1000_WRITE_REG(hw, E1000_WUC, 4110 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4111 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4112 4113 /* configure and enable PHY wakeup in PHY registers */ 4114 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4115 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4116 4117 /* activate PHY wakeup */ 4118 ret = hw->phy.ops.acquire(hw); 4119 if (ret) { 4120 printf("Could not acquire PHY\n"); 4121 return ret; 4122 } 4123 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4124 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4125 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4126 if (ret) { 4127 printf("Could not read PHY page 769\n"); 4128 goto out; 4129 } 4130 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4131 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4132 if (ret) 4133 printf("Could not set PHY Host Wakeup bit\n"); 4134 out: 4135 hw->phy.ops.release(hw); 4136 4137 return ret; 4138 } 4139 4140 static void 4141 em_if_led_func(if_ctx_t ctx, int onoff) 4142 { 4143 struct e1000_softc *sc = iflib_get_softc(ctx); 4144 4145 if (onoff) { 4146 e1000_setup_led(&sc->hw); 4147 e1000_led_on(&sc->hw); 4148 } else { 4149 e1000_led_off(&sc->hw); 4150 e1000_cleanup_led(&sc->hw); 4151 } 4152 } 4153 4154 /* 4155 * Disable the L0S and L1 LINK states 4156 */ 4157 static void 4158 em_disable_aspm(struct e1000_softc *sc) 4159 { 4160 int base, reg; 4161 u16 link_cap,link_ctrl; 4162 device_t dev = sc->dev; 4163 4164 switch (sc->hw.mac.type) { 4165 case e1000_82573: 4166 case e1000_82574: 4167 case e1000_82583: 4168 break; 4169 default: 4170 return; 4171 } 4172 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4173 return; 4174 reg = base + PCIER_LINK_CAP; 4175 link_cap = pci_read_config(dev, reg, 2); 4176 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4177 return; 4178 reg = base + PCIER_LINK_CTL; 4179 link_ctrl = pci_read_config(dev, reg, 2); 4180 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4181 pci_write_config(dev, reg, link_ctrl, 2); 4182 return; 4183 } 4184 4185 /********************************************************************** 4186 * 4187 * Update the board statistics counters. 4188 * 4189 **********************************************************************/ 4190 static void 4191 em_update_stats_counters(struct e1000_softc *sc) 4192 { 4193 u64 prev_xoffrxc = sc->stats.xoffrxc; 4194 4195 if(sc->hw.phy.media_type == e1000_media_type_copper || 4196 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4197 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4198 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4199 } 4200 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4201 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4202 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4203 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4204 4205 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4206 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4207 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4208 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4209 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4210 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4211 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4212 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4213 /* 4214 ** For watchdog management we need to know if we have been 4215 ** paused during the last interval, so capture that here. 4216 */ 4217 if (sc->stats.xoffrxc != prev_xoffrxc) 4218 sc->shared->isc_pause_frames = 1; 4219 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4220 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4221 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4222 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4223 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4224 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4225 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4226 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4227 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4228 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4229 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4230 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4231 4232 /* For the 64-bit byte counters the low dword must be read first. */ 4233 /* Both registers clear on the read of the high dword */ 4234 4235 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4236 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4237 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4238 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4239 4240 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4241 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4242 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4243 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4244 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4245 4246 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4247 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4248 4249 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4250 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4251 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4252 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4253 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4254 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4255 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4256 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4257 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4258 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4259 4260 /* Interrupt Counts */ 4261 4262 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4263 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4264 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4265 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4266 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4267 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4268 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4269 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4270 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4271 4272 if (sc->hw.mac.type >= e1000_82543) { 4273 sc->stats.algnerrc += 4274 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4275 sc->stats.rxerrc += 4276 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4277 sc->stats.tncrs += 4278 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4279 sc->stats.cexterr += 4280 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4281 sc->stats.tsctc += 4282 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4283 sc->stats.tsctfc += 4284 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4285 } 4286 } 4287 4288 static uint64_t 4289 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4290 { 4291 struct e1000_softc *sc = iflib_get_softc(ctx); 4292 if_t ifp = iflib_get_ifp(ctx); 4293 4294 switch (cnt) { 4295 case IFCOUNTER_COLLISIONS: 4296 return (sc->stats.colc); 4297 case IFCOUNTER_IERRORS: 4298 return (sc->dropped_pkts + sc->stats.rxerrc + 4299 sc->stats.crcerrs + sc->stats.algnerrc + 4300 sc->stats.ruc + sc->stats.roc + 4301 sc->stats.mpc + sc->stats.cexterr); 4302 case IFCOUNTER_OERRORS: 4303 return (sc->stats.ecol + sc->stats.latecol + 4304 sc->watchdog_events); 4305 default: 4306 return (if_get_counter_default(ifp, cnt)); 4307 } 4308 } 4309 4310 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4311 * @ctx: iflib context 4312 * @event: event code to check 4313 * 4314 * Defaults to returning true for unknown events. 4315 * 4316 * @returns true if iflib needs to reinit the interface 4317 */ 4318 static bool 4319 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4320 { 4321 switch (event) { 4322 case IFLIB_RESTART_VLAN_CONFIG: 4323 return (false); 4324 default: 4325 return (true); 4326 } 4327 } 4328 4329 /* Export a single 32-bit register via a read-only sysctl. */ 4330 static int 4331 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4332 { 4333 struct e1000_softc *sc; 4334 u_int val; 4335 4336 sc = oidp->oid_arg1; 4337 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4338 return (sysctl_handle_int(oidp, &val, 0, req)); 4339 } 4340 4341 /* 4342 * Add sysctl variables, one per statistic, to the system. 4343 */ 4344 static void 4345 em_add_hw_stats(struct e1000_softc *sc) 4346 { 4347 device_t dev = iflib_get_dev(sc->ctx); 4348 struct em_tx_queue *tx_que = sc->tx_queues; 4349 struct em_rx_queue *rx_que = sc->rx_queues; 4350 4351 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4352 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4353 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4354 struct e1000_hw_stats *stats = &sc->stats; 4355 4356 struct sysctl_oid *stat_node, *queue_node, *int_node; 4357 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4358 4359 #define QUEUE_NAME_LEN 32 4360 char namebuf[QUEUE_NAME_LEN]; 4361 4362 /* Driver Statistics */ 4363 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4364 CTLFLAG_RD, &sc->dropped_pkts, 4365 "Driver dropped packets"); 4366 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4367 CTLFLAG_RD, &sc->link_irq, 4368 "Link MSI-X IRQ Handled"); 4369 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4370 CTLFLAG_RD, &sc->rx_overruns, 4371 "RX overruns"); 4372 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4373 CTLFLAG_RD, &sc->watchdog_events, 4374 "Watchdog timeouts"); 4375 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4376 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4377 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4378 "Device Control Register"); 4379 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4380 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4381 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4382 "Receiver Control Register"); 4383 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4384 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4385 "Flow Control High Watermark"); 4386 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4387 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4388 "Flow Control Low Watermark"); 4389 4390 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4391 struct tx_ring *txr = &tx_que->txr; 4392 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4393 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4394 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4395 queue_list = SYSCTL_CHILDREN(queue_node); 4396 4397 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4398 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4399 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4400 "Transmit Descriptor Head"); 4401 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4402 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4403 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4404 "Transmit Descriptor Tail"); 4405 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4406 CTLFLAG_RD, &txr->tx_irq, 4407 "Queue MSI-X Transmit Interrupts"); 4408 } 4409 4410 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4411 struct rx_ring *rxr = &rx_que->rxr; 4412 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4413 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4414 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4415 queue_list = SYSCTL_CHILDREN(queue_node); 4416 4417 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4418 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4419 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4420 "Receive Descriptor Head"); 4421 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4422 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4423 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4424 "Receive Descriptor Tail"); 4425 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4426 CTLFLAG_RD, &rxr->rx_irq, 4427 "Queue MSI-X Receive Interrupts"); 4428 } 4429 4430 /* MAC stats get their own sub node */ 4431 4432 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4433 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4434 stat_list = SYSCTL_CHILDREN(stat_node); 4435 4436 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4437 CTLFLAG_RD, &stats->ecol, 4438 "Excessive collisions"); 4439 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4440 CTLFLAG_RD, &stats->scc, 4441 "Single collisions"); 4442 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4443 CTLFLAG_RD, &stats->mcc, 4444 "Multiple collisions"); 4445 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4446 CTLFLAG_RD, &stats->latecol, 4447 "Late collisions"); 4448 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4449 CTLFLAG_RD, &stats->colc, 4450 "Collision Count"); 4451 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4452 CTLFLAG_RD, &sc->stats.symerrs, 4453 "Symbol Errors"); 4454 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4455 CTLFLAG_RD, &sc->stats.sec, 4456 "Sequence Errors"); 4457 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4458 CTLFLAG_RD, &sc->stats.dc, 4459 "Defer Count"); 4460 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4461 CTLFLAG_RD, &sc->stats.mpc, 4462 "Missed Packets"); 4463 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4464 CTLFLAG_RD, &sc->stats.rnbc, 4465 "Receive No Buffers"); 4466 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4467 CTLFLAG_RD, &sc->stats.ruc, 4468 "Receive Undersize"); 4469 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4470 CTLFLAG_RD, &sc->stats.rfc, 4471 "Fragmented Packets Received "); 4472 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4473 CTLFLAG_RD, &sc->stats.roc, 4474 "Oversized Packets Received"); 4475 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4476 CTLFLAG_RD, &sc->stats.rjc, 4477 "Recevied Jabber"); 4478 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4479 CTLFLAG_RD, &sc->stats.rxerrc, 4480 "Receive Errors"); 4481 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4482 CTLFLAG_RD, &sc->stats.crcerrs, 4483 "CRC errors"); 4484 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4485 CTLFLAG_RD, &sc->stats.algnerrc, 4486 "Alignment Errors"); 4487 /* On 82575 these are collision counts */ 4488 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4489 CTLFLAG_RD, &sc->stats.cexterr, 4490 "Collision/Carrier extension errors"); 4491 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4492 CTLFLAG_RD, &sc->stats.xonrxc, 4493 "XON Received"); 4494 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4495 CTLFLAG_RD, &sc->stats.xontxc, 4496 "XON Transmitted"); 4497 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4498 CTLFLAG_RD, &sc->stats.xoffrxc, 4499 "XOFF Received"); 4500 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4501 CTLFLAG_RD, &sc->stats.xofftxc, 4502 "XOFF Transmitted"); 4503 4504 /* Packet Reception Stats */ 4505 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4506 CTLFLAG_RD, &sc->stats.tpr, 4507 "Total Packets Received "); 4508 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4509 CTLFLAG_RD, &sc->stats.gprc, 4510 "Good Packets Received"); 4511 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4512 CTLFLAG_RD, &sc->stats.bprc, 4513 "Broadcast Packets Received"); 4514 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4515 CTLFLAG_RD, &sc->stats.mprc, 4516 "Multicast Packets Received"); 4517 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4518 CTLFLAG_RD, &sc->stats.prc64, 4519 "64 byte frames received "); 4520 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4521 CTLFLAG_RD, &sc->stats.prc127, 4522 "65-127 byte frames received"); 4523 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4524 CTLFLAG_RD, &sc->stats.prc255, 4525 "128-255 byte frames received"); 4526 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4527 CTLFLAG_RD, &sc->stats.prc511, 4528 "256-511 byte frames received"); 4529 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4530 CTLFLAG_RD, &sc->stats.prc1023, 4531 "512-1023 byte frames received"); 4532 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4533 CTLFLAG_RD, &sc->stats.prc1522, 4534 "1023-1522 byte frames received"); 4535 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4536 CTLFLAG_RD, &sc->stats.gorc, 4537 "Good Octets Received"); 4538 4539 /* Packet Transmission Stats */ 4540 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4541 CTLFLAG_RD, &sc->stats.gotc, 4542 "Good Octets Transmitted"); 4543 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4544 CTLFLAG_RD, &sc->stats.tpt, 4545 "Total Packets Transmitted"); 4546 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4547 CTLFLAG_RD, &sc->stats.gptc, 4548 "Good Packets Transmitted"); 4549 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4550 CTLFLAG_RD, &sc->stats.bptc, 4551 "Broadcast Packets Transmitted"); 4552 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4553 CTLFLAG_RD, &sc->stats.mptc, 4554 "Multicast Packets Transmitted"); 4555 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4556 CTLFLAG_RD, &sc->stats.ptc64, 4557 "64 byte frames transmitted "); 4558 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4559 CTLFLAG_RD, &sc->stats.ptc127, 4560 "65-127 byte frames transmitted"); 4561 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4562 CTLFLAG_RD, &sc->stats.ptc255, 4563 "128-255 byte frames transmitted"); 4564 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4565 CTLFLAG_RD, &sc->stats.ptc511, 4566 "256-511 byte frames transmitted"); 4567 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4568 CTLFLAG_RD, &sc->stats.ptc1023, 4569 "512-1023 byte frames transmitted"); 4570 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4571 CTLFLAG_RD, &sc->stats.ptc1522, 4572 "1024-1522 byte frames transmitted"); 4573 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4574 CTLFLAG_RD, &sc->stats.tsctc, 4575 "TSO Contexts Transmitted"); 4576 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4577 CTLFLAG_RD, &sc->stats.tsctfc, 4578 "TSO Contexts Failed"); 4579 4580 4581 /* Interrupt Stats */ 4582 4583 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4584 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4585 int_list = SYSCTL_CHILDREN(int_node); 4586 4587 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4588 CTLFLAG_RD, &sc->stats.iac, 4589 "Interrupt Assertion Count"); 4590 4591 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4592 CTLFLAG_RD, &sc->stats.icrxptc, 4593 "Interrupt Cause Rx Pkt Timer Expire Count"); 4594 4595 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4596 CTLFLAG_RD, &sc->stats.icrxatc, 4597 "Interrupt Cause Rx Abs Timer Expire Count"); 4598 4599 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4600 CTLFLAG_RD, &sc->stats.ictxptc, 4601 "Interrupt Cause Tx Pkt Timer Expire Count"); 4602 4603 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4604 CTLFLAG_RD, &sc->stats.ictxatc, 4605 "Interrupt Cause Tx Abs Timer Expire Count"); 4606 4607 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4608 CTLFLAG_RD, &sc->stats.ictxqec, 4609 "Interrupt Cause Tx Queue Empty Count"); 4610 4611 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4612 CTLFLAG_RD, &sc->stats.ictxqmtc, 4613 "Interrupt Cause Tx Queue Min Thresh Count"); 4614 4615 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4616 CTLFLAG_RD, &sc->stats.icrxdmtc, 4617 "Interrupt Cause Rx Desc Min Thresh Count"); 4618 4619 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4620 CTLFLAG_RD, &sc->stats.icrxoc, 4621 "Interrupt Cause Receiver Overrun Count"); 4622 } 4623 4624 static void 4625 em_fw_version_locked(if_ctx_t ctx) 4626 { 4627 struct e1000_softc *sc = iflib_get_softc(ctx); 4628 struct e1000_hw *hw = &sc->hw; 4629 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4630 uint16_t eep = 0; 4631 4632 /* 4633 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4634 * NVM locking model, so we do it in em_if_attach_pre() and store the 4635 * info in the softc 4636 */ 4637 ASSERT_CTX_LOCK_HELD(hw); 4638 4639 *fw_ver = (struct e1000_fw_version){0}; 4640 4641 if (hw->mac.type >= igb_mac_min) { 4642 /* 4643 * Use the Shared Code for igb(4) 4644 */ 4645 e1000_get_fw_version(hw, fw_ver); 4646 } else { 4647 /* 4648 * Otherwise, EEPROM version should be present on (almost?) all 4649 * devices here 4650 */ 4651 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4652 INIT_DEBUGOUT("can't get EEPROM version"); 4653 return; 4654 } 4655 4656 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4657 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4658 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4659 } 4660 } 4661 4662 static void 4663 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4664 { 4665 const char *space = ""; 4666 4667 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4668 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4669 fw_ver->eep_minor, fw_ver->eep_build); 4670 space = " "; 4671 } 4672 4673 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4674 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4675 space, fw_ver->invm_major, fw_ver->invm_minor, 4676 fw_ver->invm_img_type); 4677 space = " "; 4678 } 4679 4680 if (fw_ver->or_valid) { 4681 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4682 space, fw_ver->or_major, fw_ver->or_build, 4683 fw_ver->or_patch); 4684 space = " "; 4685 } 4686 4687 if (fw_ver->etrack_id) 4688 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4689 } 4690 4691 static void 4692 em_print_fw_version(struct e1000_softc *sc ) 4693 { 4694 device_t dev = sc->dev; 4695 struct sbuf *buf; 4696 int error = 0; 4697 4698 buf = sbuf_new_auto(); 4699 if (!buf) { 4700 device_printf(dev, "Could not allocate sbuf for output.\n"); 4701 return; 4702 } 4703 4704 em_sbuf_fw_version(&sc->fw_ver, buf); 4705 4706 error = sbuf_finish(buf); 4707 if (error) 4708 device_printf(dev, "Error finishing sbuf: %d\n", error); 4709 else if (sbuf_len(buf)) 4710 device_printf(dev, "%s\n", sbuf_data(buf)); 4711 4712 sbuf_delete(buf); 4713 } 4714 4715 static int 4716 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4717 { 4718 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4719 device_t dev = sc->dev; 4720 struct sbuf *buf; 4721 int error = 0; 4722 4723 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4724 if (!buf) { 4725 device_printf(dev, "Could not allocate sbuf for output.\n"); 4726 return (ENOMEM); 4727 } 4728 4729 em_sbuf_fw_version(&sc->fw_ver, buf); 4730 4731 error = sbuf_finish(buf); 4732 if (error) 4733 device_printf(dev, "Error finishing sbuf: %d\n", error); 4734 4735 sbuf_delete(buf); 4736 4737 return (0); 4738 } 4739 4740 /********************************************************************** 4741 * 4742 * This routine provides a way to dump out the adapter eeprom, 4743 * often a useful debug/service tool. This only dumps the first 4744 * 32 words, stuff that matters is in that extent. 4745 * 4746 **********************************************************************/ 4747 static int 4748 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4749 { 4750 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4751 int error; 4752 int result; 4753 4754 result = -1; 4755 error = sysctl_handle_int(oidp, &result, 0, req); 4756 4757 if (error || !req->newptr) 4758 return (error); 4759 4760 /* 4761 * This value will cause a hex dump of the 4762 * first 32 16-bit words of the EEPROM to 4763 * the screen. 4764 */ 4765 if (result == 1) 4766 em_print_nvm_info(sc); 4767 4768 return (error); 4769 } 4770 4771 static void 4772 em_print_nvm_info(struct e1000_softc *sc) 4773 { 4774 struct e1000_hw *hw = &sc->hw; 4775 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4776 u16 eeprom_data; 4777 int i, j, row = 0; 4778 4779 /* Its a bit crude, but it gets the job done */ 4780 printf("\nInterface EEPROM Dump:\n"); 4781 printf("Offset\n0x0000 "); 4782 4783 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4784 sx_xlock(iflib_ctx_lock); 4785 ASSERT_CTX_LOCK_HELD(hw); 4786 for (i = 0, j = 0; i < 32; i++, j++) { 4787 if (j == 8) { /* Make the offset block */ 4788 j = 0; ++row; 4789 printf("\n0x00%x0 ",row); 4790 } 4791 e1000_read_nvm(hw, i, 1, &eeprom_data); 4792 printf("%04x ", eeprom_data); 4793 } 4794 sx_xunlock(iflib_ctx_lock); 4795 printf("\n"); 4796 } 4797 4798 static int 4799 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4800 { 4801 struct em_int_delay_info *info; 4802 struct e1000_softc *sc; 4803 u32 regval; 4804 int error, usecs, ticks; 4805 4806 info = (struct em_int_delay_info *) arg1; 4807 usecs = info->value; 4808 error = sysctl_handle_int(oidp, &usecs, 0, req); 4809 if (error != 0 || req->newptr == NULL) 4810 return (error); 4811 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4812 return (EINVAL); 4813 info->value = usecs; 4814 ticks = EM_USECS_TO_TICKS(usecs); 4815 if (info->offset == E1000_ITR) /* units are 256ns here */ 4816 ticks *= 4; 4817 4818 sc = info->sc; 4819 4820 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4821 regval = (regval & ~0xffff) | (ticks & 0xffff); 4822 /* Handle a few special cases. */ 4823 switch (info->offset) { 4824 case E1000_RDTR: 4825 break; 4826 case E1000_TIDV: 4827 if (ticks == 0) { 4828 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4829 /* Don't write 0 into the TIDV register. */ 4830 regval++; 4831 } else 4832 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4833 break; 4834 } 4835 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4836 return (0); 4837 } 4838 4839 static void 4840 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4841 const char *description, struct em_int_delay_info *info, 4842 int offset, int value) 4843 { 4844 info->sc = sc; 4845 info->offset = offset; 4846 info->value = value; 4847 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4848 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4849 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4850 info, 0, em_sysctl_int_delay, "I", description); 4851 } 4852 4853 /* 4854 * Set flow control using sysctl: 4855 * Flow control values: 4856 * 0 - off 4857 * 1 - rx pause 4858 * 2 - tx pause 4859 * 3 - full 4860 */ 4861 static int 4862 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4863 { 4864 int error; 4865 static int input = 3; /* default is full */ 4866 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4867 4868 error = sysctl_handle_int(oidp, &input, 0, req); 4869 4870 if ((error) || (req->newptr == NULL)) 4871 return (error); 4872 4873 if (input == sc->fc) /* no change? */ 4874 return (error); 4875 4876 switch (input) { 4877 case e1000_fc_rx_pause: 4878 case e1000_fc_tx_pause: 4879 case e1000_fc_full: 4880 case e1000_fc_none: 4881 sc->hw.fc.requested_mode = input; 4882 sc->fc = input; 4883 break; 4884 default: 4885 /* Do nothing */ 4886 return (error); 4887 } 4888 4889 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4890 e1000_force_mac_fc(&sc->hw); 4891 return (error); 4892 } 4893 4894 /* 4895 * Manage Energy Efficient Ethernet: 4896 * Control values: 4897 * 0/1 - enabled/disabled 4898 */ 4899 static int 4900 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4901 { 4902 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4903 int error, value; 4904 4905 value = sc->hw.dev_spec.ich8lan.eee_disable; 4906 error = sysctl_handle_int(oidp, &value, 0, req); 4907 if (error || req->newptr == NULL) 4908 return (error); 4909 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4910 em_if_init(sc->ctx); 4911 4912 return (0); 4913 } 4914 4915 static int 4916 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4917 { 4918 struct e1000_softc *sc; 4919 int error; 4920 int result; 4921 4922 result = -1; 4923 error = sysctl_handle_int(oidp, &result, 0, req); 4924 4925 if (error || !req->newptr) 4926 return (error); 4927 4928 if (result == 1) { 4929 sc = (struct e1000_softc *) arg1; 4930 em_print_debug_info(sc); 4931 } 4932 4933 return (error); 4934 } 4935 4936 static int 4937 em_get_rs(SYSCTL_HANDLER_ARGS) 4938 { 4939 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4940 int error; 4941 int result; 4942 4943 result = 0; 4944 error = sysctl_handle_int(oidp, &result, 0, req); 4945 4946 if (error || !req->newptr || result != 1) 4947 return (error); 4948 em_dump_rs(sc); 4949 4950 return (error); 4951 } 4952 4953 static void 4954 em_if_debug(if_ctx_t ctx) 4955 { 4956 em_dump_rs(iflib_get_softc(ctx)); 4957 } 4958 4959 /* 4960 * This routine is meant to be fluid, add whatever is 4961 * needed for debugging a problem. -jfv 4962 */ 4963 static void 4964 em_print_debug_info(struct e1000_softc *sc) 4965 { 4966 device_t dev = iflib_get_dev(sc->ctx); 4967 if_t ifp = iflib_get_ifp(sc->ctx); 4968 struct tx_ring *txr = &sc->tx_queues->txr; 4969 struct rx_ring *rxr = &sc->rx_queues->rxr; 4970 4971 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4972 printf("Interface is RUNNING "); 4973 else 4974 printf("Interface is NOT RUNNING\n"); 4975 4976 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4977 printf("and INACTIVE\n"); 4978 else 4979 printf("and ACTIVE\n"); 4980 4981 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 4982 device_printf(dev, "TX Queue %d ------\n", i); 4983 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4984 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 4985 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 4986 4987 } 4988 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 4989 device_printf(dev, "RX Queue %d ------\n", j); 4990 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4991 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 4992 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 4993 } 4994 } 4995 4996 /* 4997 * 82574 only: 4998 * Write a new value to the EEPROM increasing the number of MSI-X 4999 * vectors from 3 to 5, for proper multiqueue support. 5000 */ 5001 static void 5002 em_enable_vectors_82574(if_ctx_t ctx) 5003 { 5004 struct e1000_softc *sc = iflib_get_softc(ctx); 5005 struct e1000_hw *hw = &sc->hw; 5006 device_t dev = iflib_get_dev(ctx); 5007 u16 edata; 5008 5009 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5010 if (bootverbose) 5011 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5012 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5013 device_printf(dev, "Writing to eeprom: increasing " 5014 "reported MSI-X vectors from 3 to 5...\n"); 5015 edata &= ~(EM_NVM_MSIX_N_MASK); 5016 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5017 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5018 e1000_update_nvm_checksum(hw); 5019 device_printf(dev, "Writing to eeprom: done\n"); 5020 } 5021 } 5022