1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) PRO/1000 Network Connection"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) PRO/1000 Network Connection"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) PRO/1000 Network Connection"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) PRO/1000 Network Connection"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) PRO/1000 Network Connection"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) PRO/1000 Network Connection"), 183 /* required last entry */ 184 PVID_END 185 }; 186 187 static pci_vendor_info_t igb_vendor_info_array[] = 188 { 189 /* Intel(R) PRO/1000 Network Connection - igb */ 190 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 216 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 217 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 218 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 219 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 220 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 221 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 222 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 223 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 224 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 225 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 226 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 227 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 228 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 229 /* required last entry */ 230 PVID_END 231 }; 232 233 /********************************************************************* 234 * Function prototypes 235 *********************************************************************/ 236 static void *em_register(device_t dev); 237 static void *igb_register(device_t dev); 238 static int em_if_attach_pre(if_ctx_t ctx); 239 static int em_if_attach_post(if_ctx_t ctx); 240 static int em_if_detach(if_ctx_t ctx); 241 static int em_if_shutdown(if_ctx_t ctx); 242 static int em_if_suspend(if_ctx_t ctx); 243 static int em_if_resume(if_ctx_t ctx); 244 245 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 246 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 247 static void em_if_queues_free(if_ctx_t ctx); 248 249 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 250 static void em_if_init(if_ctx_t ctx); 251 static void em_if_stop(if_ctx_t ctx); 252 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 253 static int em_if_media_change(if_ctx_t ctx); 254 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 255 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 256 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 257 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 258 static void em_if_watchdog_reset(if_ctx_t ctx); 259 static bool em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 260 261 static void em_identify_hardware(if_ctx_t ctx); 262 static int em_allocate_pci_resources(if_ctx_t ctx); 263 static void em_free_pci_resources(if_ctx_t ctx); 264 static void em_reset(if_ctx_t ctx); 265 static int em_setup_interface(if_ctx_t ctx); 266 static int em_setup_msix(if_ctx_t ctx); 267 268 static void em_initialize_transmit_unit(if_ctx_t ctx); 269 static void em_initialize_receive_unit(if_ctx_t ctx); 270 271 static void em_if_intr_enable(if_ctx_t ctx); 272 static void em_if_intr_disable(if_ctx_t ctx); 273 static void igb_if_intr_enable(if_ctx_t ctx); 274 static void igb_if_intr_disable(if_ctx_t ctx); 275 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 276 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 277 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 278 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 279 static void em_if_multi_set(if_ctx_t ctx); 280 static void em_if_update_admin_status(if_ctx_t ctx); 281 static void em_if_debug(if_ctx_t ctx); 282 static void em_update_stats_counters(struct adapter *); 283 static void em_add_hw_stats(struct adapter *adapter); 284 static int em_if_set_promisc(if_ctx_t ctx, int flags); 285 static void em_setup_vlan_hw_support(struct adapter *); 286 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 287 static void em_print_nvm_info(struct adapter *); 288 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 289 static int em_get_rs(SYSCTL_HANDLER_ARGS); 290 static void em_print_debug_info(struct adapter *); 291 static int em_is_valid_ether_addr(u8 *); 292 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 293 static void em_add_int_delay_sysctl(struct adapter *, const char *, 294 const char *, struct em_int_delay_info *, int, int); 295 /* Management and WOL Support */ 296 static void em_init_manageability(struct adapter *); 297 static void em_release_manageability(struct adapter *); 298 static void em_get_hw_control(struct adapter *); 299 static void em_release_hw_control(struct adapter *); 300 static void em_get_wakeup(if_ctx_t ctx); 301 static void em_enable_wakeup(if_ctx_t ctx); 302 static int em_enable_phy_wakeup(struct adapter *); 303 static void em_disable_aspm(struct adapter *); 304 305 int em_intr(void *arg); 306 static void em_disable_promisc(if_ctx_t ctx); 307 308 /* MSI-X handlers */ 309 static int em_if_msix_intr_assign(if_ctx_t, int); 310 static int em_msix_link(void *); 311 static void em_handle_link(void *context); 312 313 static void em_enable_vectors_82574(if_ctx_t); 314 315 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 316 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 317 static void em_if_led_func(if_ctx_t ctx, int onoff); 318 319 static int em_get_regs(SYSCTL_HANDLER_ARGS); 320 321 static void lem_smartspeed(struct adapter *adapter); 322 static void igb_configure_queues(struct adapter *adapter); 323 324 325 /********************************************************************* 326 * FreeBSD Device Interface Entry Points 327 *********************************************************************/ 328 static device_method_t em_methods[] = { 329 /* Device interface */ 330 DEVMETHOD(device_register, em_register), 331 DEVMETHOD(device_probe, iflib_device_probe), 332 DEVMETHOD(device_attach, iflib_device_attach), 333 DEVMETHOD(device_detach, iflib_device_detach), 334 DEVMETHOD(device_shutdown, iflib_device_shutdown), 335 DEVMETHOD(device_suspend, iflib_device_suspend), 336 DEVMETHOD(device_resume, iflib_device_resume), 337 DEVMETHOD_END 338 }; 339 340 static device_method_t igb_methods[] = { 341 /* Device interface */ 342 DEVMETHOD(device_register, igb_register), 343 DEVMETHOD(device_probe, iflib_device_probe), 344 DEVMETHOD(device_attach, iflib_device_attach), 345 DEVMETHOD(device_detach, iflib_device_detach), 346 DEVMETHOD(device_shutdown, iflib_device_shutdown), 347 DEVMETHOD(device_suspend, iflib_device_suspend), 348 DEVMETHOD(device_resume, iflib_device_resume), 349 DEVMETHOD_END 350 }; 351 352 353 static driver_t em_driver = { 354 "em", em_methods, sizeof(struct adapter), 355 }; 356 357 static devclass_t em_devclass; 358 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 359 360 MODULE_DEPEND(em, pci, 1, 1, 1); 361 MODULE_DEPEND(em, ether, 1, 1, 1); 362 MODULE_DEPEND(em, iflib, 1, 1, 1); 363 364 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 365 366 static driver_t igb_driver = { 367 "igb", igb_methods, sizeof(struct adapter), 368 }; 369 370 static devclass_t igb_devclass; 371 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 372 373 MODULE_DEPEND(igb, pci, 1, 1, 1); 374 MODULE_DEPEND(igb, ether, 1, 1, 1); 375 MODULE_DEPEND(igb, iflib, 1, 1, 1); 376 377 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 378 379 static device_method_t em_if_methods[] = { 380 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 381 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 382 DEVMETHOD(ifdi_detach, em_if_detach), 383 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 384 DEVMETHOD(ifdi_suspend, em_if_suspend), 385 DEVMETHOD(ifdi_resume, em_if_resume), 386 DEVMETHOD(ifdi_init, em_if_init), 387 DEVMETHOD(ifdi_stop, em_if_stop), 388 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 389 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 390 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 391 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 392 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 393 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 394 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 395 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 396 DEVMETHOD(ifdi_media_status, em_if_media_status), 397 DEVMETHOD(ifdi_media_change, em_if_media_change), 398 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 399 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 400 DEVMETHOD(ifdi_timer, em_if_timer), 401 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 402 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 403 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 404 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 405 DEVMETHOD(ifdi_led_func, em_if_led_func), 406 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 407 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 408 DEVMETHOD(ifdi_debug, em_if_debug), 409 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 410 DEVMETHOD_END 411 }; 412 413 static driver_t em_if_driver = { 414 "em_if", em_if_methods, sizeof(struct adapter) 415 }; 416 417 static device_method_t igb_if_methods[] = { 418 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 419 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 420 DEVMETHOD(ifdi_detach, em_if_detach), 421 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 422 DEVMETHOD(ifdi_suspend, em_if_suspend), 423 DEVMETHOD(ifdi_resume, em_if_resume), 424 DEVMETHOD(ifdi_init, em_if_init), 425 DEVMETHOD(ifdi_stop, em_if_stop), 426 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 427 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 428 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 429 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 430 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 431 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 432 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 433 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 434 DEVMETHOD(ifdi_media_status, em_if_media_status), 435 DEVMETHOD(ifdi_media_change, em_if_media_change), 436 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 437 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 438 DEVMETHOD(ifdi_timer, em_if_timer), 439 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 440 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 441 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 442 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 443 DEVMETHOD(ifdi_led_func, em_if_led_func), 444 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 445 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 446 DEVMETHOD(ifdi_debug, em_if_debug), 447 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 448 DEVMETHOD_END 449 }; 450 451 static driver_t igb_if_driver = { 452 "igb_if", igb_if_methods, sizeof(struct adapter) 453 }; 454 455 /********************************************************************* 456 * Tunable default values. 457 *********************************************************************/ 458 459 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 460 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 461 462 #define MAX_INTS_PER_SEC 8000 463 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 464 465 /* Allow common code without TSO */ 466 #ifndef CSUM_TSO 467 #define CSUM_TSO 0 468 #endif 469 470 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 471 "EM driver parameters"); 472 473 static int em_disable_crc_stripping = 0; 474 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 475 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 476 477 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 478 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 479 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 480 0, "Default transmit interrupt delay in usecs"); 481 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 482 0, "Default receive interrupt delay in usecs"); 483 484 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 485 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 486 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 487 &em_tx_abs_int_delay_dflt, 0, 488 "Default transmit interrupt delay limit in usecs"); 489 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 490 &em_rx_abs_int_delay_dflt, 0, 491 "Default receive interrupt delay limit in usecs"); 492 493 static int em_smart_pwr_down = FALSE; 494 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 495 0, "Set to true to leave smart power down enabled on newer adapters"); 496 497 /* Controls whether promiscuous also shows bad packets */ 498 static int em_debug_sbp = TRUE; 499 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 500 "Show bad packets in promiscuous mode"); 501 502 /* How many packets rxeof tries to clean at a time */ 503 static int em_rx_process_limit = 100; 504 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 505 &em_rx_process_limit, 0, 506 "Maximum number of received packets to process " 507 "at a time, -1 means unlimited"); 508 509 /* Energy efficient ethernet - default to OFF */ 510 static int eee_setting = 1; 511 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 512 "Enable Energy Efficient Ethernet"); 513 514 /* 515 ** Tuneable Interrupt rate 516 */ 517 static int em_max_interrupt_rate = 8000; 518 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 519 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 520 521 522 523 /* Global used in WOL setup with multiport cards */ 524 static int global_quad_port_a = 0; 525 526 extern struct if_txrx igb_txrx; 527 extern struct if_txrx em_txrx; 528 extern struct if_txrx lem_txrx; 529 530 static struct if_shared_ctx em_sctx_init = { 531 .isc_magic = IFLIB_MAGIC, 532 .isc_q_align = PAGE_SIZE, 533 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 534 .isc_tx_maxsegsize = PAGE_SIZE, 535 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 536 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 537 .isc_rx_maxsize = MJUM9BYTES, 538 .isc_rx_nsegments = 1, 539 .isc_rx_maxsegsize = MJUM9BYTES, 540 .isc_nfl = 1, 541 .isc_nrxqs = 1, 542 .isc_ntxqs = 1, 543 .isc_admin_intrcnt = 1, 544 .isc_vendor_info = em_vendor_info_array, 545 .isc_driver_version = em_driver_version, 546 .isc_driver = &em_if_driver, 547 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 548 549 .isc_nrxd_min = {EM_MIN_RXD}, 550 .isc_ntxd_min = {EM_MIN_TXD}, 551 .isc_nrxd_max = {EM_MAX_RXD}, 552 .isc_ntxd_max = {EM_MAX_TXD}, 553 .isc_nrxd_default = {EM_DEFAULT_RXD}, 554 .isc_ntxd_default = {EM_DEFAULT_TXD}, 555 }; 556 557 if_shared_ctx_t em_sctx = &em_sctx_init; 558 559 static struct if_shared_ctx igb_sctx_init = { 560 .isc_magic = IFLIB_MAGIC, 561 .isc_q_align = PAGE_SIZE, 562 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 563 .isc_tx_maxsegsize = PAGE_SIZE, 564 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 565 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 566 .isc_rx_maxsize = MJUM9BYTES, 567 .isc_rx_nsegments = 1, 568 .isc_rx_maxsegsize = MJUM9BYTES, 569 .isc_nfl = 1, 570 .isc_nrxqs = 1, 571 .isc_ntxqs = 1, 572 .isc_admin_intrcnt = 1, 573 .isc_vendor_info = igb_vendor_info_array, 574 .isc_driver_version = em_driver_version, 575 .isc_driver = &igb_if_driver, 576 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 577 578 .isc_nrxd_min = {EM_MIN_RXD}, 579 .isc_ntxd_min = {EM_MIN_TXD}, 580 .isc_nrxd_max = {IGB_MAX_RXD}, 581 .isc_ntxd_max = {IGB_MAX_TXD}, 582 .isc_nrxd_default = {EM_DEFAULT_RXD}, 583 .isc_ntxd_default = {EM_DEFAULT_TXD}, 584 }; 585 586 if_shared_ctx_t igb_sctx = &igb_sctx_init; 587 588 /***************************************************************** 589 * 590 * Dump Registers 591 * 592 ****************************************************************/ 593 #define IGB_REGS_LEN 739 594 595 static int em_get_regs(SYSCTL_HANDLER_ARGS) 596 { 597 struct adapter *adapter = (struct adapter *)arg1; 598 struct e1000_hw *hw = &adapter->hw; 599 struct sbuf *sb; 600 u32 *regs_buff; 601 int rc; 602 603 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 604 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 605 606 rc = sysctl_wire_old_buffer(req, 0); 607 MPASS(rc == 0); 608 if (rc != 0) { 609 free(regs_buff, M_DEVBUF); 610 return (rc); 611 } 612 613 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 614 MPASS(sb != NULL); 615 if (sb == NULL) { 616 free(regs_buff, M_DEVBUF); 617 return (ENOMEM); 618 } 619 620 /* General Registers */ 621 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 622 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 623 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 624 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 625 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 626 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 627 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 628 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 629 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 630 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 631 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 632 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 633 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 634 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 635 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 636 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 637 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 638 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 639 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 640 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 641 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 642 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 643 644 sbuf_printf(sb, "General Registers\n"); 645 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 646 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 647 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 648 649 sbuf_printf(sb, "Interrupt Registers\n"); 650 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 651 652 sbuf_printf(sb, "RX Registers\n"); 653 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 654 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 655 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 656 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 657 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 658 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 659 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 660 661 sbuf_printf(sb, "TX Registers\n"); 662 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 663 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 664 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 665 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 666 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 667 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 668 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 669 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 670 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 671 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 672 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 673 674 free(regs_buff, M_DEVBUF); 675 676 #ifdef DUMP_DESCS 677 { 678 if_softc_ctx_t scctx = adapter->shared; 679 struct rx_ring *rxr = &rx_que->rxr; 680 struct tx_ring *txr = &tx_que->txr; 681 int ntxd = scctx->isc_ntxd[0]; 682 int nrxd = scctx->isc_nrxd[0]; 683 int j; 684 685 for (j = 0; j < nrxd; j++) { 686 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 687 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 688 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 689 } 690 691 for (j = 0; j < min(ntxd, 256); j++) { 692 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 693 694 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 695 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 696 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 697 698 } 699 } 700 #endif 701 702 rc = sbuf_finish(sb); 703 sbuf_delete(sb); 704 return(rc); 705 } 706 707 static void * 708 em_register(device_t dev) 709 { 710 return (em_sctx); 711 } 712 713 static void * 714 igb_register(device_t dev) 715 { 716 return (igb_sctx); 717 } 718 719 static int 720 em_set_num_queues(if_ctx_t ctx) 721 { 722 struct adapter *adapter = iflib_get_softc(ctx); 723 int maxqueues; 724 725 /* Sanity check based on HW */ 726 switch (adapter->hw.mac.type) { 727 case e1000_82576: 728 case e1000_82580: 729 case e1000_i350: 730 case e1000_i354: 731 maxqueues = 8; 732 break; 733 case e1000_i210: 734 case e1000_82575: 735 maxqueues = 4; 736 break; 737 case e1000_i211: 738 case e1000_82574: 739 maxqueues = 2; 740 break; 741 default: 742 maxqueues = 1; 743 break; 744 } 745 746 return (maxqueues); 747 } 748 749 #define LEM_CAPS \ 750 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 751 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 752 753 #define EM_CAPS \ 754 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 755 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 756 IFCAP_LRO | IFCAP_VLAN_HWTSO 757 758 #define IGB_CAPS \ 759 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 760 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 761 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 762 IFCAP_TSO6 763 764 /********************************************************************* 765 * Device initialization routine 766 * 767 * The attach entry point is called when the driver is being loaded. 768 * This routine identifies the type of hardware, allocates all resources 769 * and initializes the hardware. 770 * 771 * return 0 on success, positive on failure 772 *********************************************************************/ 773 static int 774 em_if_attach_pre(if_ctx_t ctx) 775 { 776 struct adapter *adapter; 777 if_softc_ctx_t scctx; 778 device_t dev; 779 struct e1000_hw *hw; 780 int error = 0; 781 782 INIT_DEBUGOUT("em_if_attach_pre: begin"); 783 dev = iflib_get_dev(ctx); 784 adapter = iflib_get_softc(ctx); 785 786 adapter->ctx = adapter->osdep.ctx = ctx; 787 adapter->dev = adapter->osdep.dev = dev; 788 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 789 adapter->media = iflib_get_media(ctx); 790 hw = &adapter->hw; 791 792 adapter->tx_process_limit = scctx->isc_ntxd[0]; 793 794 /* SYSCTL stuff */ 795 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 796 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 797 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 798 adapter, 0, em_sysctl_nvm_info, "I", "NVM Information"); 799 800 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 801 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 802 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 803 adapter, 0, em_sysctl_debug_info, "I", "Debug Information"); 804 805 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 806 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 807 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 808 adapter, 0, em_set_flowcntl, "I", "Flow Control"); 809 810 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 811 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 812 OID_AUTO, "reg_dump", 813 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 814 em_get_regs, "A", "Dump Registers"); 815 816 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 817 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 818 OID_AUTO, "rs_dump", 819 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 820 em_get_rs, "I", "Dump RS indexes"); 821 822 /* Determine hardware and mac info */ 823 em_identify_hardware(ctx); 824 825 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 826 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 827 if (bootverbose) 828 device_printf(dev, "attach_pre capping queues at %d\n", 829 scctx->isc_ntxqsets_max); 830 831 if (adapter->hw.mac.type >= igb_mac_min) { 832 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 833 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 834 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 835 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 836 scctx->isc_txrx = &igb_txrx; 837 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 838 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 839 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 840 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 841 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 842 CSUM_IP6_TCP | CSUM_IP6_UDP; 843 if (adapter->hw.mac.type != e1000_82575) 844 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 845 /* 846 ** Some new devices, as with ixgbe, now may 847 ** use a different BAR, so we need to keep 848 ** track of which is used. 849 */ 850 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 851 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 852 scctx->isc_msix_bar += 4; 853 } else if (adapter->hw.mac.type >= em_mac_min) { 854 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 855 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 856 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 857 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 858 scctx->isc_txrx = &em_txrx; 859 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 860 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 861 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 862 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 863 /* 864 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 865 * by default as we don't have workarounds for all associated 866 * silicon errata. E. g., with several MACs such as 82573E, 867 * TSO only works at Gigabit speed and otherwise can cause the 868 * hardware to hang (which also would be next to impossible to 869 * work around given that already queued TSO-using descriptors 870 * would need to be flushed and vlan(4) reconfigured at runtime 871 * in case of a link speed change). Moreover, MACs like 82579 872 * still can hang at Gigabit even with all publicly documented 873 * TSO workarounds implemented. Generally, the penality of 874 * these workarounds is rather high and may involve copying 875 * mbuf data around so advantages of TSO lapse. Still, TSO may 876 * work for a few MACs of this class - at least when sticking 877 * with Gigabit - in which case users may enable TSO manually. 878 */ 879 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 880 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 881 /* 882 * We support MSI-X with 82574 only, but indicate to iflib(4) 883 * that it shall give MSI at least a try with other devices. 884 */ 885 if (adapter->hw.mac.type == e1000_82574) { 886 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 887 } else { 888 scctx->isc_msix_bar = -1; 889 scctx->isc_disable_msix = 1; 890 } 891 } else { 892 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 893 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 894 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 895 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 896 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 897 scctx->isc_txrx = &lem_txrx; 898 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 899 if (adapter->hw.mac.type < e1000_82543) 900 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 901 /* INTx only */ 902 scctx->isc_msix_bar = 0; 903 } 904 905 /* Setup PCI resources */ 906 if (em_allocate_pci_resources(ctx)) { 907 device_printf(dev, "Allocation of PCI resources failed\n"); 908 error = ENXIO; 909 goto err_pci; 910 } 911 912 /* 913 ** For ICH8 and family we need to 914 ** map the flash memory, and this 915 ** must happen after the MAC is 916 ** identified 917 */ 918 if ((hw->mac.type == e1000_ich8lan) || 919 (hw->mac.type == e1000_ich9lan) || 920 (hw->mac.type == e1000_ich10lan) || 921 (hw->mac.type == e1000_pchlan) || 922 (hw->mac.type == e1000_pch2lan) || 923 (hw->mac.type == e1000_pch_lpt)) { 924 int rid = EM_BAR_TYPE_FLASH; 925 adapter->flash = bus_alloc_resource_any(dev, 926 SYS_RES_MEMORY, &rid, RF_ACTIVE); 927 if (adapter->flash == NULL) { 928 device_printf(dev, "Mapping of Flash failed\n"); 929 error = ENXIO; 930 goto err_pci; 931 } 932 /* This is used in the shared code */ 933 hw->flash_address = (u8 *)adapter->flash; 934 adapter->osdep.flash_bus_space_tag = 935 rman_get_bustag(adapter->flash); 936 adapter->osdep.flash_bus_space_handle = 937 rman_get_bushandle(adapter->flash); 938 } 939 /* 940 ** In the new SPT device flash is not a 941 ** separate BAR, rather it is also in BAR0, 942 ** so use the same tag and an offset handle for the 943 ** FLASH read/write macros in the shared code. 944 */ 945 else if (hw->mac.type >= e1000_pch_spt) { 946 adapter->osdep.flash_bus_space_tag = 947 adapter->osdep.mem_bus_space_tag; 948 adapter->osdep.flash_bus_space_handle = 949 adapter->osdep.mem_bus_space_handle 950 + E1000_FLASH_BASE_ADDR; 951 } 952 953 /* Do Shared Code initialization */ 954 error = e1000_setup_init_funcs(hw, TRUE); 955 if (error) { 956 device_printf(dev, "Setup of Shared code failed, error %d\n", 957 error); 958 error = ENXIO; 959 goto err_pci; 960 } 961 962 em_setup_msix(ctx); 963 e1000_get_bus_info(hw); 964 965 /* Set up some sysctls for the tunable interrupt delays */ 966 em_add_int_delay_sysctl(adapter, "rx_int_delay", 967 "receive interrupt delay in usecs", &adapter->rx_int_delay, 968 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 969 em_add_int_delay_sysctl(adapter, "tx_int_delay", 970 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 971 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 972 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 973 "receive interrupt delay limit in usecs", 974 &adapter->rx_abs_int_delay, 975 E1000_REGISTER(hw, E1000_RADV), 976 em_rx_abs_int_delay_dflt); 977 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 978 "transmit interrupt delay limit in usecs", 979 &adapter->tx_abs_int_delay, 980 E1000_REGISTER(hw, E1000_TADV), 981 em_tx_abs_int_delay_dflt); 982 em_add_int_delay_sysctl(adapter, "itr", 983 "interrupt delay limit in usecs/4", 984 &adapter->tx_itr, 985 E1000_REGISTER(hw, E1000_ITR), 986 DEFAULT_ITR); 987 988 hw->mac.autoneg = DO_AUTO_NEG; 989 hw->phy.autoneg_wait_to_complete = FALSE; 990 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 991 992 if (adapter->hw.mac.type < em_mac_min) { 993 e1000_init_script_state_82541(&adapter->hw, TRUE); 994 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 995 } 996 /* Copper options */ 997 if (hw->phy.media_type == e1000_media_type_copper) { 998 hw->phy.mdix = AUTO_ALL_MODES; 999 hw->phy.disable_polarity_correction = FALSE; 1000 hw->phy.ms_type = EM_MASTER_SLAVE; 1001 } 1002 1003 /* 1004 * Set the frame limits assuming 1005 * standard ethernet sized frames. 1006 */ 1007 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1008 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1009 1010 /* 1011 * This controls when hardware reports transmit completion 1012 * status. 1013 */ 1014 hw->mac.report_tx_early = 1; 1015 1016 /* Allocate multicast array memory. */ 1017 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1018 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1019 if (adapter->mta == NULL) { 1020 device_printf(dev, "Can not allocate multicast setup array\n"); 1021 error = ENOMEM; 1022 goto err_late; 1023 } 1024 1025 /* Check SOL/IDER usage */ 1026 if (e1000_check_reset_block(hw)) 1027 device_printf(dev, "PHY reset is blocked" 1028 " due to SOL/IDER session.\n"); 1029 1030 /* Sysctl for setting Energy Efficient Ethernet */ 1031 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1032 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1033 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1034 OID_AUTO, "eee_control", 1035 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1036 adapter, 0, em_sysctl_eee, "I", 1037 "Disable Energy Efficient Ethernet"); 1038 1039 /* 1040 ** Start from a known state, this is 1041 ** important in reading the nvm and 1042 ** mac from that. 1043 */ 1044 e1000_reset_hw(hw); 1045 1046 /* Make sure we have a good EEPROM before we read from it */ 1047 if (e1000_validate_nvm_checksum(hw) < 0) { 1048 /* 1049 ** Some PCI-E parts fail the first check due to 1050 ** the link being in sleep state, call it again, 1051 ** if it fails a second time its a real issue. 1052 */ 1053 if (e1000_validate_nvm_checksum(hw) < 0) { 1054 device_printf(dev, 1055 "The EEPROM Checksum Is Not Valid\n"); 1056 error = EIO; 1057 goto err_late; 1058 } 1059 } 1060 1061 /* Copy the permanent MAC address out of the EEPROM */ 1062 if (e1000_read_mac_addr(hw) < 0) { 1063 device_printf(dev, "EEPROM read error while reading MAC" 1064 " address\n"); 1065 error = EIO; 1066 goto err_late; 1067 } 1068 1069 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1070 device_printf(dev, "Invalid MAC address\n"); 1071 error = EIO; 1072 goto err_late; 1073 } 1074 1075 /* Disable ULP support */ 1076 e1000_disable_ulp_lpt_lp(hw, TRUE); 1077 1078 /* 1079 * Get Wake-on-Lan and Management info for later use 1080 */ 1081 em_get_wakeup(ctx); 1082 1083 /* Enable only WOL MAGIC by default */ 1084 scctx->isc_capenable &= ~IFCAP_WOL; 1085 if (adapter->wol != 0) 1086 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1087 1088 iflib_set_mac(ctx, hw->mac.addr); 1089 1090 return (0); 1091 1092 err_late: 1093 em_release_hw_control(adapter); 1094 err_pci: 1095 em_free_pci_resources(ctx); 1096 free(adapter->mta, M_DEVBUF); 1097 1098 return (error); 1099 } 1100 1101 static int 1102 em_if_attach_post(if_ctx_t ctx) 1103 { 1104 struct adapter *adapter = iflib_get_softc(ctx); 1105 struct e1000_hw *hw = &adapter->hw; 1106 int error = 0; 1107 1108 /* Setup OS specific network interface */ 1109 error = em_setup_interface(ctx); 1110 if (error != 0) { 1111 goto err_late; 1112 } 1113 1114 em_reset(ctx); 1115 1116 /* Initialize statistics */ 1117 em_update_stats_counters(adapter); 1118 hw->mac.get_link_status = 1; 1119 em_if_update_admin_status(ctx); 1120 em_add_hw_stats(adapter); 1121 1122 /* Non-AMT based hardware can now take control from firmware */ 1123 if (adapter->has_manage && !adapter->has_amt) 1124 em_get_hw_control(adapter); 1125 1126 INIT_DEBUGOUT("em_if_attach_post: end"); 1127 1128 return (error); 1129 1130 err_late: 1131 em_release_hw_control(adapter); 1132 em_free_pci_resources(ctx); 1133 em_if_queues_free(ctx); 1134 free(adapter->mta, M_DEVBUF); 1135 1136 return (error); 1137 } 1138 1139 /********************************************************************* 1140 * Device removal routine 1141 * 1142 * The detach entry point is called when the driver is being removed. 1143 * This routine stops the adapter and deallocates all the resources 1144 * that were allocated for driver operation. 1145 * 1146 * return 0 on success, positive on failure 1147 *********************************************************************/ 1148 static int 1149 em_if_detach(if_ctx_t ctx) 1150 { 1151 struct adapter *adapter = iflib_get_softc(ctx); 1152 1153 INIT_DEBUGOUT("em_if_detach: begin"); 1154 1155 e1000_phy_hw_reset(&adapter->hw); 1156 1157 em_release_manageability(adapter); 1158 em_release_hw_control(adapter); 1159 em_free_pci_resources(ctx); 1160 1161 return (0); 1162 } 1163 1164 /********************************************************************* 1165 * 1166 * Shutdown entry point 1167 * 1168 **********************************************************************/ 1169 1170 static int 1171 em_if_shutdown(if_ctx_t ctx) 1172 { 1173 return em_if_suspend(ctx); 1174 } 1175 1176 /* 1177 * Suspend/resume device methods. 1178 */ 1179 static int 1180 em_if_suspend(if_ctx_t ctx) 1181 { 1182 struct adapter *adapter = iflib_get_softc(ctx); 1183 1184 em_release_manageability(adapter); 1185 em_release_hw_control(adapter); 1186 em_enable_wakeup(ctx); 1187 return (0); 1188 } 1189 1190 static int 1191 em_if_resume(if_ctx_t ctx) 1192 { 1193 struct adapter *adapter = iflib_get_softc(ctx); 1194 1195 if (adapter->hw.mac.type == e1000_pch2lan) 1196 e1000_resume_workarounds_pchlan(&adapter->hw); 1197 em_if_init(ctx); 1198 em_init_manageability(adapter); 1199 1200 return(0); 1201 } 1202 1203 static int 1204 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1205 { 1206 int max_frame_size; 1207 struct adapter *adapter = iflib_get_softc(ctx); 1208 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1209 1210 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1211 1212 switch (adapter->hw.mac.type) { 1213 case e1000_82571: 1214 case e1000_82572: 1215 case e1000_ich9lan: 1216 case e1000_ich10lan: 1217 case e1000_pch2lan: 1218 case e1000_pch_lpt: 1219 case e1000_pch_spt: 1220 case e1000_pch_cnp: 1221 case e1000_82574: 1222 case e1000_82583: 1223 case e1000_80003es2lan: 1224 /* 9K Jumbo Frame size */ 1225 max_frame_size = 9234; 1226 break; 1227 case e1000_pchlan: 1228 max_frame_size = 4096; 1229 break; 1230 case e1000_82542: 1231 case e1000_ich8lan: 1232 /* Adapters that do not support jumbo frames */ 1233 max_frame_size = ETHER_MAX_LEN; 1234 break; 1235 default: 1236 if (adapter->hw.mac.type >= igb_mac_min) 1237 max_frame_size = 9234; 1238 else /* lem */ 1239 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1240 } 1241 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1242 return (EINVAL); 1243 } 1244 1245 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1246 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1247 return (0); 1248 } 1249 1250 /********************************************************************* 1251 * Init entry point 1252 * 1253 * This routine is used in two ways. It is used by the stack as 1254 * init entry point in network interface structure. It is also used 1255 * by the driver as a hw/sw initialization routine to get to a 1256 * consistent state. 1257 * 1258 **********************************************************************/ 1259 static void 1260 em_if_init(if_ctx_t ctx) 1261 { 1262 struct adapter *adapter = iflib_get_softc(ctx); 1263 if_softc_ctx_t scctx = adapter->shared; 1264 struct ifnet *ifp = iflib_get_ifp(ctx); 1265 struct em_tx_queue *tx_que; 1266 int i; 1267 1268 INIT_DEBUGOUT("em_if_init: begin"); 1269 1270 /* Get the latest mac address, User can use a LAA */ 1271 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1272 ETHER_ADDR_LEN); 1273 1274 /* Put the address into the Receive Address Array */ 1275 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1276 1277 /* 1278 * With the 82571 adapter, RAR[0] may be overwritten 1279 * when the other port is reset, we make a duplicate 1280 * in RAR[14] for that eventuality, this assures 1281 * the interface continues to function. 1282 */ 1283 if (adapter->hw.mac.type == e1000_82571) { 1284 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1285 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1286 E1000_RAR_ENTRIES - 1); 1287 } 1288 1289 1290 /* Initialize the hardware */ 1291 em_reset(ctx); 1292 em_if_update_admin_status(ctx); 1293 1294 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1295 struct tx_ring *txr = &tx_que->txr; 1296 1297 txr->tx_rs_cidx = txr->tx_rs_pidx; 1298 1299 /* Initialize the last processed descriptor to be the end of 1300 * the ring, rather than the start, so that we avoid an 1301 * off-by-one error when calculating how many descriptors are 1302 * done in the credits_update function. 1303 */ 1304 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1305 } 1306 1307 /* Setup VLAN support, basic and offload if available */ 1308 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1309 1310 /* Clear bad data from Rx FIFOs */ 1311 if (adapter->hw.mac.type >= igb_mac_min) 1312 e1000_rx_fifo_flush_82575(&adapter->hw); 1313 1314 /* Configure for OS presence */ 1315 em_init_manageability(adapter); 1316 1317 /* Prepare transmit descriptors and buffers */ 1318 em_initialize_transmit_unit(ctx); 1319 1320 /* Setup Multicast table */ 1321 em_if_multi_set(ctx); 1322 1323 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1324 em_initialize_receive_unit(ctx); 1325 1326 /* Use real VLAN Filter support? */ 1327 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1328 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1329 /* Use real VLAN Filter support */ 1330 em_setup_vlan_hw_support(adapter); 1331 else { 1332 u32 ctrl; 1333 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1334 ctrl |= E1000_CTRL_VME; 1335 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1336 } 1337 } 1338 1339 /* Don't lose promiscuous settings */ 1340 em_if_set_promisc(ctx, IFF_PROMISC); 1341 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1342 1343 /* MSI-X configuration for 82574 */ 1344 if (adapter->hw.mac.type == e1000_82574) { 1345 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1346 1347 tmp |= E1000_CTRL_EXT_PBA_CLR; 1348 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1349 /* Set the IVAR - interrupt vector routing. */ 1350 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1351 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1352 igb_configure_queues(adapter); 1353 1354 /* this clears any pending interrupts */ 1355 E1000_READ_REG(&adapter->hw, E1000_ICR); 1356 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1357 1358 /* AMT based hardware can now take control from firmware */ 1359 if (adapter->has_manage && adapter->has_amt) 1360 em_get_hw_control(adapter); 1361 1362 /* Set Energy Efficient Ethernet */ 1363 if (adapter->hw.mac.type >= igb_mac_min && 1364 adapter->hw.phy.media_type == e1000_media_type_copper) { 1365 if (adapter->hw.mac.type == e1000_i354) 1366 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1367 else 1368 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1369 } 1370 } 1371 1372 /********************************************************************* 1373 * 1374 * Fast Legacy/MSI Combined Interrupt Service routine 1375 * 1376 *********************************************************************/ 1377 int 1378 em_intr(void *arg) 1379 { 1380 struct adapter *adapter = arg; 1381 if_ctx_t ctx = adapter->ctx; 1382 u32 reg_icr; 1383 1384 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1385 1386 /* Hot eject? */ 1387 if (reg_icr == 0xffffffff) 1388 return FILTER_STRAY; 1389 1390 /* Definitely not our interrupt. */ 1391 if (reg_icr == 0x0) 1392 return FILTER_STRAY; 1393 1394 /* 1395 * Starting with the 82571 chip, bit 31 should be used to 1396 * determine whether the interrupt belongs to us. 1397 */ 1398 if (adapter->hw.mac.type >= e1000_82571 && 1399 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1400 return FILTER_STRAY; 1401 1402 /* 1403 * Only MSI-X interrupts have one-shot behavior by taking advantage 1404 * of the EIAC register. Thus, explicitly disable interrupts. This 1405 * also works around the MSI message reordering errata on certain 1406 * systems. 1407 */ 1408 IFDI_INTR_DISABLE(ctx); 1409 1410 /* Link status change */ 1411 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1412 em_handle_link(ctx); 1413 1414 if (reg_icr & E1000_ICR_RXO) 1415 adapter->rx_overruns++; 1416 1417 return (FILTER_SCHEDULE_THREAD); 1418 } 1419 1420 static int 1421 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1422 { 1423 struct adapter *adapter = iflib_get_softc(ctx); 1424 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1425 1426 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1427 return (0); 1428 } 1429 1430 static int 1431 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1432 { 1433 struct adapter *adapter = iflib_get_softc(ctx); 1434 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1435 1436 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1437 return (0); 1438 } 1439 1440 static int 1441 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1442 { 1443 struct adapter *adapter = iflib_get_softc(ctx); 1444 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1445 1446 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1447 return (0); 1448 } 1449 1450 static int 1451 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1452 { 1453 struct adapter *adapter = iflib_get_softc(ctx); 1454 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1455 1456 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1457 return (0); 1458 } 1459 1460 /********************************************************************* 1461 * 1462 * MSI-X RX Interrupt Service routine 1463 * 1464 **********************************************************************/ 1465 static int 1466 em_msix_que(void *arg) 1467 { 1468 struct em_rx_queue *que = arg; 1469 1470 ++que->irqs; 1471 1472 return (FILTER_SCHEDULE_THREAD); 1473 } 1474 1475 /********************************************************************* 1476 * 1477 * MSI-X Link Fast Interrupt Service routine 1478 * 1479 **********************************************************************/ 1480 static int 1481 em_msix_link(void *arg) 1482 { 1483 struct adapter *adapter = arg; 1484 u32 reg_icr; 1485 1486 ++adapter->link_irq; 1487 MPASS(adapter->hw.back != NULL); 1488 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1489 1490 if (reg_icr & E1000_ICR_RXO) 1491 adapter->rx_overruns++; 1492 1493 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1494 em_handle_link(adapter->ctx); 1495 } else if (adapter->hw.mac.type == e1000_82574) { 1496 /* Only re-arm 82574 if em_if_update_admin_status() won't. */ 1497 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | 1498 E1000_IMS_LSC); 1499 } 1500 1501 if (adapter->hw.mac.type == e1000_82574) { 1502 /* 1503 * Because we must read the ICR for this interrupt it may 1504 * clear other causes using autoclear, for this reason we 1505 * simply create a soft interrupt for all these vectors. 1506 */ 1507 if (reg_icr) 1508 E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims); 1509 } else { 1510 /* Re-arm unconditionally */ 1511 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1512 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1513 } 1514 1515 return (FILTER_HANDLED); 1516 } 1517 1518 static void 1519 em_handle_link(void *context) 1520 { 1521 if_ctx_t ctx = context; 1522 struct adapter *adapter = iflib_get_softc(ctx); 1523 1524 adapter->hw.mac.get_link_status = 1; 1525 iflib_admin_intr_deferred(ctx); 1526 } 1527 1528 /********************************************************************* 1529 * 1530 * Media Ioctl callback 1531 * 1532 * This routine is called whenever the user queries the status of 1533 * the interface using ifconfig. 1534 * 1535 **********************************************************************/ 1536 static void 1537 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1538 { 1539 struct adapter *adapter = iflib_get_softc(ctx); 1540 u_char fiber_type = IFM_1000_SX; 1541 1542 INIT_DEBUGOUT("em_if_media_status: begin"); 1543 1544 iflib_admin_intr_deferred(ctx); 1545 1546 ifmr->ifm_status = IFM_AVALID; 1547 ifmr->ifm_active = IFM_ETHER; 1548 1549 if (!adapter->link_active) { 1550 return; 1551 } 1552 1553 ifmr->ifm_status |= IFM_ACTIVE; 1554 1555 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1556 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1557 if (adapter->hw.mac.type == e1000_82545) 1558 fiber_type = IFM_1000_LX; 1559 ifmr->ifm_active |= fiber_type | IFM_FDX; 1560 } else { 1561 switch (adapter->link_speed) { 1562 case 10: 1563 ifmr->ifm_active |= IFM_10_T; 1564 break; 1565 case 100: 1566 ifmr->ifm_active |= IFM_100_TX; 1567 break; 1568 case 1000: 1569 ifmr->ifm_active |= IFM_1000_T; 1570 break; 1571 } 1572 if (adapter->link_duplex == FULL_DUPLEX) 1573 ifmr->ifm_active |= IFM_FDX; 1574 else 1575 ifmr->ifm_active |= IFM_HDX; 1576 } 1577 } 1578 1579 /********************************************************************* 1580 * 1581 * Media Ioctl callback 1582 * 1583 * This routine is called when the user changes speed/duplex using 1584 * media/mediopt option with ifconfig. 1585 * 1586 **********************************************************************/ 1587 static int 1588 em_if_media_change(if_ctx_t ctx) 1589 { 1590 struct adapter *adapter = iflib_get_softc(ctx); 1591 struct ifmedia *ifm = iflib_get_media(ctx); 1592 1593 INIT_DEBUGOUT("em_if_media_change: begin"); 1594 1595 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1596 return (EINVAL); 1597 1598 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1599 case IFM_AUTO: 1600 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1601 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1602 break; 1603 case IFM_1000_LX: 1604 case IFM_1000_SX: 1605 case IFM_1000_T: 1606 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1607 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1608 break; 1609 case IFM_100_TX: 1610 adapter->hw.mac.autoneg = FALSE; 1611 adapter->hw.phy.autoneg_advertised = 0; 1612 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1613 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1614 else 1615 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1616 break; 1617 case IFM_10_T: 1618 adapter->hw.mac.autoneg = FALSE; 1619 adapter->hw.phy.autoneg_advertised = 0; 1620 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1621 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1622 else 1623 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1624 break; 1625 default: 1626 device_printf(adapter->dev, "Unsupported media type\n"); 1627 } 1628 1629 em_if_init(ctx); 1630 1631 return (0); 1632 } 1633 1634 static int 1635 em_if_set_promisc(if_ctx_t ctx, int flags) 1636 { 1637 struct adapter *adapter = iflib_get_softc(ctx); 1638 u32 reg_rctl; 1639 1640 em_disable_promisc(ctx); 1641 1642 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1643 1644 if (flags & IFF_PROMISC) { 1645 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1646 /* Turn this on if you want to see bad packets */ 1647 if (em_debug_sbp) 1648 reg_rctl |= E1000_RCTL_SBP; 1649 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1650 } else if (flags & IFF_ALLMULTI) { 1651 reg_rctl |= E1000_RCTL_MPE; 1652 reg_rctl &= ~E1000_RCTL_UPE; 1653 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1654 } 1655 return (0); 1656 } 1657 1658 static void 1659 em_disable_promisc(if_ctx_t ctx) 1660 { 1661 struct adapter *adapter = iflib_get_softc(ctx); 1662 struct ifnet *ifp = iflib_get_ifp(ctx); 1663 u32 reg_rctl; 1664 int mcnt = 0; 1665 1666 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1667 reg_rctl &= (~E1000_RCTL_UPE); 1668 if (if_getflags(ifp) & IFF_ALLMULTI) 1669 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1670 else 1671 mcnt = if_llmaddr_count(ifp); 1672 /* Don't disable if in MAX groups */ 1673 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1674 reg_rctl &= (~E1000_RCTL_MPE); 1675 reg_rctl &= (~E1000_RCTL_SBP); 1676 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1677 } 1678 1679 1680 static u_int 1681 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1682 { 1683 u8 *mta = arg; 1684 1685 if (cnt == MAX_NUM_MULTICAST_ADDRESSES) 1686 return (1); 1687 1688 bcopy(LLADDR(sdl), &mta[cnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1689 1690 return (1); 1691 } 1692 1693 /********************************************************************* 1694 * Multicast Update 1695 * 1696 * This routine is called whenever multicast address list is updated. 1697 * 1698 **********************************************************************/ 1699 1700 static void 1701 em_if_multi_set(if_ctx_t ctx) 1702 { 1703 struct adapter *adapter = iflib_get_softc(ctx); 1704 struct ifnet *ifp = iflib_get_ifp(ctx); 1705 u32 reg_rctl = 0; 1706 u8 *mta; /* Multicast array memory */ 1707 int mcnt = 0; 1708 1709 IOCTL_DEBUGOUT("em_set_multi: begin"); 1710 1711 mta = adapter->mta; 1712 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1713 1714 if (adapter->hw.mac.type == e1000_82542 && 1715 adapter->hw.revision_id == E1000_REVISION_2) { 1716 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1717 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1718 e1000_pci_clear_mwi(&adapter->hw); 1719 reg_rctl |= E1000_RCTL_RST; 1720 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1721 msec_delay(5); 1722 } 1723 1724 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1725 1726 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1727 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1728 reg_rctl |= E1000_RCTL_MPE; 1729 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1730 } else 1731 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1732 1733 if (adapter->hw.mac.type == e1000_82542 && 1734 adapter->hw.revision_id == E1000_REVISION_2) { 1735 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1736 reg_rctl &= ~E1000_RCTL_RST; 1737 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1738 msec_delay(5); 1739 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1740 e1000_pci_set_mwi(&adapter->hw); 1741 } 1742 } 1743 1744 /********************************************************************* 1745 * Timer routine 1746 * 1747 * This routine schedules em_if_update_admin_status() to check for 1748 * link status and to gather statistics as well as to perform some 1749 * controller-specific hardware patting. 1750 * 1751 **********************************************************************/ 1752 static void 1753 em_if_timer(if_ctx_t ctx, uint16_t qid) 1754 { 1755 1756 if (qid != 0) 1757 return; 1758 1759 iflib_admin_intr_deferred(ctx); 1760 } 1761 1762 static void 1763 em_if_update_admin_status(if_ctx_t ctx) 1764 { 1765 struct adapter *adapter = iflib_get_softc(ctx); 1766 struct e1000_hw *hw = &adapter->hw; 1767 device_t dev = iflib_get_dev(ctx); 1768 u32 link_check, thstat, ctrl; 1769 1770 link_check = thstat = ctrl = 0; 1771 /* Get the cached link value or read phy for real */ 1772 switch (hw->phy.media_type) { 1773 case e1000_media_type_copper: 1774 if (hw->mac.get_link_status) { 1775 if (hw->mac.type == e1000_pch_spt) 1776 msec_delay(50); 1777 /* Do the work to read phy */ 1778 e1000_check_for_link(hw); 1779 link_check = !hw->mac.get_link_status; 1780 if (link_check) /* ESB2 fix */ 1781 e1000_cfg_on_link_up(hw); 1782 } else { 1783 link_check = TRUE; 1784 } 1785 break; 1786 case e1000_media_type_fiber: 1787 e1000_check_for_link(hw); 1788 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1789 E1000_STATUS_LU); 1790 break; 1791 case e1000_media_type_internal_serdes: 1792 e1000_check_for_link(hw); 1793 link_check = adapter->hw.mac.serdes_has_link; 1794 break; 1795 /* VF device is type_unknown */ 1796 case e1000_media_type_unknown: 1797 e1000_check_for_link(hw); 1798 link_check = !hw->mac.get_link_status; 1799 /* FALLTHROUGH */ 1800 default: 1801 break; 1802 } 1803 1804 /* Check for thermal downshift or shutdown */ 1805 if (hw->mac.type == e1000_i350) { 1806 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1807 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1808 } 1809 1810 /* Now check for a transition */ 1811 if (link_check && (adapter->link_active == 0)) { 1812 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1813 &adapter->link_duplex); 1814 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1815 if ((adapter->link_speed != SPEED_1000) && 1816 ((hw->mac.type == e1000_82571) || 1817 (hw->mac.type == e1000_82572))) { 1818 int tarc0; 1819 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1820 tarc0 &= ~TARC_SPEED_MODE_BIT; 1821 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1822 } 1823 if (bootverbose) 1824 device_printf(dev, "Link is up %d Mbps %s\n", 1825 adapter->link_speed, 1826 ((adapter->link_duplex == FULL_DUPLEX) ? 1827 "Full Duplex" : "Half Duplex")); 1828 adapter->link_active = 1; 1829 adapter->smartspeed = 0; 1830 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1831 E1000_CTRL_EXT_LINK_MODE_GMII && 1832 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1833 device_printf(dev, "Link: thermal downshift\n"); 1834 /* Delay Link Up for Phy update */ 1835 if (((hw->mac.type == e1000_i210) || 1836 (hw->mac.type == e1000_i211)) && 1837 (hw->phy.id == I210_I_PHY_ID)) 1838 msec_delay(I210_LINK_DELAY); 1839 /* Reset if the media type changed. */ 1840 if ((hw->dev_spec._82575.media_changed) && 1841 (adapter->hw.mac.type >= igb_mac_min)) { 1842 hw->dev_spec._82575.media_changed = false; 1843 adapter->flags |= IGB_MEDIA_RESET; 1844 em_reset(ctx); 1845 } 1846 iflib_link_state_change(ctx, LINK_STATE_UP, 1847 IF_Mbps(adapter->link_speed)); 1848 } else if (!link_check && (adapter->link_active == 1)) { 1849 adapter->link_speed = 0; 1850 adapter->link_duplex = 0; 1851 adapter->link_active = 0; 1852 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1853 } 1854 em_update_stats_counters(adapter); 1855 1856 /* Reset LAA into RAR[0] on 82571 */ 1857 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1858 e1000_rar_set(hw, hw->mac.addr, 0); 1859 1860 if (hw->mac.type < em_mac_min) 1861 lem_smartspeed(adapter); 1862 else if (hw->mac.type == e1000_82574 && 1863 adapter->intr_type == IFLIB_INTR_MSIX) 1864 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | 1865 E1000_IMS_LSC); 1866 } 1867 1868 static void 1869 em_if_watchdog_reset(if_ctx_t ctx) 1870 { 1871 struct adapter *adapter = iflib_get_softc(ctx); 1872 1873 /* 1874 * Just count the event; iflib(4) will already trigger a 1875 * sufficient reset of the controller. 1876 */ 1877 adapter->watchdog_events++; 1878 } 1879 1880 /********************************************************************* 1881 * 1882 * This routine disables all traffic on the adapter by issuing a 1883 * global reset on the MAC. 1884 * 1885 **********************************************************************/ 1886 static void 1887 em_if_stop(if_ctx_t ctx) 1888 { 1889 struct adapter *adapter = iflib_get_softc(ctx); 1890 1891 INIT_DEBUGOUT("em_if_stop: begin"); 1892 1893 e1000_reset_hw(&adapter->hw); 1894 if (adapter->hw.mac.type >= e1000_82544) 1895 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1896 1897 e1000_led_off(&adapter->hw); 1898 e1000_cleanup_led(&adapter->hw); 1899 } 1900 1901 /********************************************************************* 1902 * 1903 * Determine hardware revision. 1904 * 1905 **********************************************************************/ 1906 static void 1907 em_identify_hardware(if_ctx_t ctx) 1908 { 1909 device_t dev = iflib_get_dev(ctx); 1910 struct adapter *adapter = iflib_get_softc(ctx); 1911 1912 /* Make sure our PCI config space has the necessary stuff set */ 1913 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1914 1915 /* Save off the information about this board */ 1916 adapter->hw.vendor_id = pci_get_vendor(dev); 1917 adapter->hw.device_id = pci_get_device(dev); 1918 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1919 adapter->hw.subsystem_vendor_id = 1920 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1921 adapter->hw.subsystem_device_id = 1922 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1923 1924 /* Do Shared Code Init and Setup */ 1925 if (e1000_set_mac_type(&adapter->hw)) { 1926 device_printf(dev, "Setup init failure\n"); 1927 return; 1928 } 1929 } 1930 1931 static int 1932 em_allocate_pci_resources(if_ctx_t ctx) 1933 { 1934 struct adapter *adapter = iflib_get_softc(ctx); 1935 device_t dev = iflib_get_dev(ctx); 1936 int rid, val; 1937 1938 rid = PCIR_BAR(0); 1939 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1940 &rid, RF_ACTIVE); 1941 if (adapter->memory == NULL) { 1942 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1943 return (ENXIO); 1944 } 1945 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1946 adapter->osdep.mem_bus_space_handle = 1947 rman_get_bushandle(adapter->memory); 1948 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1949 1950 /* Only older adapters use IO mapping */ 1951 if (adapter->hw.mac.type < em_mac_min && 1952 adapter->hw.mac.type > e1000_82543) { 1953 /* Figure our where our IO BAR is ? */ 1954 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1955 val = pci_read_config(dev, rid, 4); 1956 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1957 break; 1958 } 1959 rid += 4; 1960 /* check for 64bit BAR */ 1961 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1962 rid += 4; 1963 } 1964 if (rid >= PCIR_CIS) { 1965 device_printf(dev, "Unable to locate IO BAR\n"); 1966 return (ENXIO); 1967 } 1968 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1969 &rid, RF_ACTIVE); 1970 if (adapter->ioport == NULL) { 1971 device_printf(dev, "Unable to allocate bus resource: " 1972 "ioport\n"); 1973 return (ENXIO); 1974 } 1975 adapter->hw.io_base = 0; 1976 adapter->osdep.io_bus_space_tag = 1977 rman_get_bustag(adapter->ioport); 1978 adapter->osdep.io_bus_space_handle = 1979 rman_get_bushandle(adapter->ioport); 1980 } 1981 1982 adapter->hw.back = &adapter->osdep; 1983 1984 return (0); 1985 } 1986 1987 /********************************************************************* 1988 * 1989 * Set up the MSI-X Interrupt handlers 1990 * 1991 **********************************************************************/ 1992 static int 1993 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1994 { 1995 struct adapter *adapter = iflib_get_softc(ctx); 1996 struct em_rx_queue *rx_que = adapter->rx_queues; 1997 struct em_tx_queue *tx_que = adapter->tx_queues; 1998 int error, rid, i, vector = 0, rx_vectors; 1999 char buf[16]; 2000 2001 /* First set up ring resources */ 2002 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 2003 rid = vector + 1; 2004 snprintf(buf, sizeof(buf), "rxq%d", i); 2005 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2006 if (error) { 2007 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2008 adapter->rx_num_queues = i + 1; 2009 goto fail; 2010 } 2011 2012 rx_que->msix = vector; 2013 2014 /* 2015 * Set the bit to enable interrupt 2016 * in E1000_IMS -- bits 20 and 21 2017 * are for RX0 and RX1, note this has 2018 * NOTHING to do with the MSI-X vector 2019 */ 2020 if (adapter->hw.mac.type == e1000_82574) { 2021 rx_que->eims = 1 << (20 + i); 2022 adapter->ims |= rx_que->eims; 2023 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 2024 } else if (adapter->hw.mac.type == e1000_82575) 2025 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2026 else 2027 rx_que->eims = 1 << vector; 2028 } 2029 rx_vectors = vector; 2030 2031 vector = 0; 2032 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 2033 snprintf(buf, sizeof(buf), "txq%d", i); 2034 tx_que = &adapter->tx_queues[i]; 2035 iflib_softirq_alloc_generic(ctx, 2036 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 2037 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2038 2039 tx_que->msix = (vector % adapter->rx_num_queues); 2040 2041 /* 2042 * Set the bit to enable interrupt 2043 * in E1000_IMS -- bits 22 and 23 2044 * are for TX0 and TX1, note this has 2045 * NOTHING to do with the MSI-X vector 2046 */ 2047 if (adapter->hw.mac.type == e1000_82574) { 2048 tx_que->eims = 1 << (22 + i); 2049 adapter->ims |= tx_que->eims; 2050 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2051 } else if (adapter->hw.mac.type == e1000_82575) { 2052 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2053 } else { 2054 tx_que->eims = 1 << i; 2055 } 2056 } 2057 2058 /* Link interrupt */ 2059 rid = rx_vectors + 1; 2060 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2061 2062 if (error) { 2063 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2064 goto fail; 2065 } 2066 adapter->linkvec = rx_vectors; 2067 if (adapter->hw.mac.type < igb_mac_min) { 2068 adapter->ivars |= (8 | rx_vectors) << 16; 2069 adapter->ivars |= 0x80000000; 2070 } 2071 return (0); 2072 fail: 2073 iflib_irq_free(ctx, &adapter->irq); 2074 rx_que = adapter->rx_queues; 2075 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2076 iflib_irq_free(ctx, &rx_que->que_irq); 2077 return (error); 2078 } 2079 2080 static void 2081 igb_configure_queues(struct adapter *adapter) 2082 { 2083 struct e1000_hw *hw = &adapter->hw; 2084 struct em_rx_queue *rx_que; 2085 struct em_tx_queue *tx_que; 2086 u32 tmp, ivar = 0, newitr = 0; 2087 2088 /* First turn on RSS capability */ 2089 if (adapter->hw.mac.type != e1000_82575) 2090 E1000_WRITE_REG(hw, E1000_GPIE, 2091 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2092 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2093 2094 /* Turn on MSI-X */ 2095 switch (adapter->hw.mac.type) { 2096 case e1000_82580: 2097 case e1000_i350: 2098 case e1000_i354: 2099 case e1000_i210: 2100 case e1000_i211: 2101 case e1000_vfadapt: 2102 case e1000_vfadapt_i350: 2103 /* RX entries */ 2104 for (int i = 0; i < adapter->rx_num_queues; i++) { 2105 u32 index = i >> 1; 2106 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2107 rx_que = &adapter->rx_queues[i]; 2108 if (i & 1) { 2109 ivar &= 0xFF00FFFF; 2110 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2111 } else { 2112 ivar &= 0xFFFFFF00; 2113 ivar |= rx_que->msix | E1000_IVAR_VALID; 2114 } 2115 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2116 } 2117 /* TX entries */ 2118 for (int i = 0; i < adapter->tx_num_queues; i++) { 2119 u32 index = i >> 1; 2120 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2121 tx_que = &adapter->tx_queues[i]; 2122 if (i & 1) { 2123 ivar &= 0x00FFFFFF; 2124 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2125 } else { 2126 ivar &= 0xFFFF00FF; 2127 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2128 } 2129 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2130 adapter->que_mask |= tx_que->eims; 2131 } 2132 2133 /* And for the link interrupt */ 2134 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2135 adapter->link_mask = 1 << adapter->linkvec; 2136 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2137 break; 2138 case e1000_82576: 2139 /* RX entries */ 2140 for (int i = 0; i < adapter->rx_num_queues; i++) { 2141 u32 index = i & 0x7; /* Each IVAR has two entries */ 2142 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2143 rx_que = &adapter->rx_queues[i]; 2144 if (i < 8) { 2145 ivar &= 0xFFFFFF00; 2146 ivar |= rx_que->msix | E1000_IVAR_VALID; 2147 } else { 2148 ivar &= 0xFF00FFFF; 2149 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2150 } 2151 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2152 adapter->que_mask |= rx_que->eims; 2153 } 2154 /* TX entries */ 2155 for (int i = 0; i < adapter->tx_num_queues; i++) { 2156 u32 index = i & 0x7; /* Each IVAR has two entries */ 2157 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2158 tx_que = &adapter->tx_queues[i]; 2159 if (i < 8) { 2160 ivar &= 0xFFFF00FF; 2161 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2162 } else { 2163 ivar &= 0x00FFFFFF; 2164 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2165 } 2166 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2167 adapter->que_mask |= tx_que->eims; 2168 } 2169 2170 /* And for the link interrupt */ 2171 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2172 adapter->link_mask = 1 << adapter->linkvec; 2173 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2174 break; 2175 2176 case e1000_82575: 2177 /* enable MSI-X support*/ 2178 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2179 tmp |= E1000_CTRL_EXT_PBA_CLR; 2180 /* Auto-Mask interrupts upon ICR read. */ 2181 tmp |= E1000_CTRL_EXT_EIAME; 2182 tmp |= E1000_CTRL_EXT_IRCA; 2183 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2184 2185 /* Queues */ 2186 for (int i = 0; i < adapter->rx_num_queues; i++) { 2187 rx_que = &adapter->rx_queues[i]; 2188 tmp = E1000_EICR_RX_QUEUE0 << i; 2189 tmp |= E1000_EICR_TX_QUEUE0 << i; 2190 rx_que->eims = tmp; 2191 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2192 i, rx_que->eims); 2193 adapter->que_mask |= rx_que->eims; 2194 } 2195 2196 /* Link */ 2197 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2198 E1000_EIMS_OTHER); 2199 adapter->link_mask |= E1000_EIMS_OTHER; 2200 default: 2201 break; 2202 } 2203 2204 /* Set the starting interrupt rate */ 2205 if (em_max_interrupt_rate > 0) 2206 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2207 2208 if (hw->mac.type == e1000_82575) 2209 newitr |= newitr << 16; 2210 else 2211 newitr |= E1000_EITR_CNT_IGNR; 2212 2213 for (int i = 0; i < adapter->rx_num_queues; i++) { 2214 rx_que = &adapter->rx_queues[i]; 2215 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2216 } 2217 2218 return; 2219 } 2220 2221 static void 2222 em_free_pci_resources(if_ctx_t ctx) 2223 { 2224 struct adapter *adapter = iflib_get_softc(ctx); 2225 struct em_rx_queue *que = adapter->rx_queues; 2226 device_t dev = iflib_get_dev(ctx); 2227 2228 /* Release all MSI-X queue resources */ 2229 if (adapter->intr_type == IFLIB_INTR_MSIX) 2230 iflib_irq_free(ctx, &adapter->irq); 2231 2232 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2233 iflib_irq_free(ctx, &que->que_irq); 2234 } 2235 2236 if (adapter->memory != NULL) { 2237 bus_release_resource(dev, SYS_RES_MEMORY, 2238 rman_get_rid(adapter->memory), adapter->memory); 2239 adapter->memory = NULL; 2240 } 2241 2242 if (adapter->flash != NULL) { 2243 bus_release_resource(dev, SYS_RES_MEMORY, 2244 rman_get_rid(adapter->flash), adapter->flash); 2245 adapter->flash = NULL; 2246 } 2247 2248 if (adapter->ioport != NULL) { 2249 bus_release_resource(dev, SYS_RES_IOPORT, 2250 rman_get_rid(adapter->ioport), adapter->ioport); 2251 adapter->ioport = NULL; 2252 } 2253 } 2254 2255 /* Set up MSI or MSI-X */ 2256 static int 2257 em_setup_msix(if_ctx_t ctx) 2258 { 2259 struct adapter *adapter = iflib_get_softc(ctx); 2260 2261 if (adapter->hw.mac.type == e1000_82574) { 2262 em_enable_vectors_82574(ctx); 2263 } 2264 return (0); 2265 } 2266 2267 /********************************************************************* 2268 * 2269 * Workaround for SmartSpeed on 82541 and 82547 controllers 2270 * 2271 **********************************************************************/ 2272 static void 2273 lem_smartspeed(struct adapter *adapter) 2274 { 2275 u16 phy_tmp; 2276 2277 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2278 adapter->hw.mac.autoneg == 0 || 2279 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2280 return; 2281 2282 if (adapter->smartspeed == 0) { 2283 /* If Master/Slave config fault is asserted twice, 2284 * we assume back-to-back */ 2285 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2286 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2287 return; 2288 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2289 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2290 e1000_read_phy_reg(&adapter->hw, 2291 PHY_1000T_CTRL, &phy_tmp); 2292 if(phy_tmp & CR_1000T_MS_ENABLE) { 2293 phy_tmp &= ~CR_1000T_MS_ENABLE; 2294 e1000_write_phy_reg(&adapter->hw, 2295 PHY_1000T_CTRL, phy_tmp); 2296 adapter->smartspeed++; 2297 if(adapter->hw.mac.autoneg && 2298 !e1000_copper_link_autoneg(&adapter->hw) && 2299 !e1000_read_phy_reg(&adapter->hw, 2300 PHY_CONTROL, &phy_tmp)) { 2301 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2302 MII_CR_RESTART_AUTO_NEG); 2303 e1000_write_phy_reg(&adapter->hw, 2304 PHY_CONTROL, phy_tmp); 2305 } 2306 } 2307 } 2308 return; 2309 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2310 /* If still no link, perhaps using 2/3 pair cable */ 2311 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2312 phy_tmp |= CR_1000T_MS_ENABLE; 2313 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2314 if(adapter->hw.mac.autoneg && 2315 !e1000_copper_link_autoneg(&adapter->hw) && 2316 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2317 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2318 MII_CR_RESTART_AUTO_NEG); 2319 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2320 } 2321 } 2322 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2323 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2324 adapter->smartspeed = 0; 2325 } 2326 2327 /********************************************************************* 2328 * 2329 * Initialize the DMA Coalescing feature 2330 * 2331 **********************************************************************/ 2332 static void 2333 igb_init_dmac(struct adapter *adapter, u32 pba) 2334 { 2335 device_t dev = adapter->dev; 2336 struct e1000_hw *hw = &adapter->hw; 2337 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2338 u16 hwm; 2339 u16 max_frame_size; 2340 2341 if (hw->mac.type == e1000_i211) 2342 return; 2343 2344 max_frame_size = adapter->shared->isc_max_frame_size; 2345 if (hw->mac.type > e1000_82580) { 2346 2347 if (adapter->dmac == 0) { /* Disabling it */ 2348 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2349 return; 2350 } else 2351 device_printf(dev, "DMA Coalescing enabled\n"); 2352 2353 /* Set starting threshold */ 2354 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2355 2356 hwm = 64 * pba - max_frame_size / 16; 2357 if (hwm < 64 * (pba - 6)) 2358 hwm = 64 * (pba - 6); 2359 reg = E1000_READ_REG(hw, E1000_FCRTC); 2360 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2361 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2362 & E1000_FCRTC_RTH_COAL_MASK); 2363 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2364 2365 2366 dmac = pba - max_frame_size / 512; 2367 if (dmac < pba - 10) 2368 dmac = pba - 10; 2369 reg = E1000_READ_REG(hw, E1000_DMACR); 2370 reg &= ~E1000_DMACR_DMACTHR_MASK; 2371 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2372 & E1000_DMACR_DMACTHR_MASK); 2373 2374 /* transition to L0x or L1 if available..*/ 2375 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2376 2377 /* Check if status is 2.5Gb backplane connection 2378 * before configuration of watchdog timer, which is 2379 * in msec values in 12.8usec intervals 2380 * watchdog timer= msec values in 32usec intervals 2381 * for non 2.5Gb connection 2382 */ 2383 if (hw->mac.type == e1000_i354) { 2384 int status = E1000_READ_REG(hw, E1000_STATUS); 2385 if ((status & E1000_STATUS_2P5_SKU) && 2386 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2387 reg |= ((adapter->dmac * 5) >> 6); 2388 else 2389 reg |= (adapter->dmac >> 5); 2390 } else { 2391 reg |= (adapter->dmac >> 5); 2392 } 2393 2394 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2395 2396 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2397 2398 /* Set the interval before transition */ 2399 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2400 if (hw->mac.type == e1000_i350) 2401 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2402 /* 2403 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2404 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2405 */ 2406 if (hw->mac.type == e1000_i354) { 2407 int status = E1000_READ_REG(hw, E1000_STATUS); 2408 if ((status & E1000_STATUS_2P5_SKU) && 2409 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2410 reg |= 0xA; 2411 else 2412 reg |= 0x4; 2413 } else { 2414 reg |= 0x4; 2415 } 2416 2417 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2418 2419 /* free space in tx packet buffer to wake from DMA coal */ 2420 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2421 (2 * max_frame_size)) >> 6); 2422 2423 /* make low power state decision controlled by DMA coal */ 2424 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2425 reg &= ~E1000_PCIEMISC_LX_DECISION; 2426 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2427 2428 } else if (hw->mac.type == e1000_82580) { 2429 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2430 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2431 reg & ~E1000_PCIEMISC_LX_DECISION); 2432 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2433 } 2434 } 2435 2436 /********************************************************************* 2437 * 2438 * Initialize the hardware to a configuration as specified by the 2439 * adapter structure. 2440 * 2441 **********************************************************************/ 2442 static void 2443 em_reset(if_ctx_t ctx) 2444 { 2445 device_t dev = iflib_get_dev(ctx); 2446 struct adapter *adapter = iflib_get_softc(ctx); 2447 struct ifnet *ifp = iflib_get_ifp(ctx); 2448 struct e1000_hw *hw = &adapter->hw; 2449 u16 rx_buffer_size; 2450 u32 pba; 2451 2452 INIT_DEBUGOUT("em_reset: begin"); 2453 /* Let the firmware know the OS is in control */ 2454 em_get_hw_control(adapter); 2455 2456 /* Set up smart power down as default off on newer adapters. */ 2457 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2458 hw->mac.type == e1000_82572)) { 2459 u16 phy_tmp = 0; 2460 2461 /* Speed up time to link by disabling smart power down. */ 2462 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2463 phy_tmp &= ~IGP02E1000_PM_SPD; 2464 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2465 } 2466 2467 /* 2468 * Packet Buffer Allocation (PBA) 2469 * Writing PBA sets the receive portion of the buffer 2470 * the remainder is used for the transmit buffer. 2471 */ 2472 switch (hw->mac.type) { 2473 /* Total Packet Buffer on these is 48K */ 2474 case e1000_82571: 2475 case e1000_82572: 2476 case e1000_80003es2lan: 2477 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2478 break; 2479 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2480 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2481 break; 2482 case e1000_82574: 2483 case e1000_82583: 2484 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2485 break; 2486 case e1000_ich8lan: 2487 pba = E1000_PBA_8K; 2488 break; 2489 case e1000_ich9lan: 2490 case e1000_ich10lan: 2491 /* Boost Receive side for jumbo frames */ 2492 if (adapter->hw.mac.max_frame_size > 4096) 2493 pba = E1000_PBA_14K; 2494 else 2495 pba = E1000_PBA_10K; 2496 break; 2497 case e1000_pchlan: 2498 case e1000_pch2lan: 2499 case e1000_pch_lpt: 2500 case e1000_pch_spt: 2501 case e1000_pch_cnp: 2502 pba = E1000_PBA_26K; 2503 break; 2504 case e1000_82575: 2505 pba = E1000_PBA_32K; 2506 break; 2507 case e1000_82576: 2508 case e1000_vfadapt: 2509 pba = E1000_READ_REG(hw, E1000_RXPBS); 2510 pba &= E1000_RXPBS_SIZE_MASK_82576; 2511 break; 2512 case e1000_82580: 2513 case e1000_i350: 2514 case e1000_i354: 2515 case e1000_vfadapt_i350: 2516 pba = E1000_READ_REG(hw, E1000_RXPBS); 2517 pba = e1000_rxpbs_adjust_82580(pba); 2518 break; 2519 case e1000_i210: 2520 case e1000_i211: 2521 pba = E1000_PBA_34K; 2522 break; 2523 default: 2524 if (adapter->hw.mac.max_frame_size > 8192) 2525 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2526 else 2527 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2528 } 2529 2530 /* Special needs in case of Jumbo frames */ 2531 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2532 u32 tx_space, min_tx, min_rx; 2533 pba = E1000_READ_REG(hw, E1000_PBA); 2534 tx_space = pba >> 16; 2535 pba &= 0xffff; 2536 min_tx = (adapter->hw.mac.max_frame_size + 2537 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2538 min_tx = roundup2(min_tx, 1024); 2539 min_tx >>= 10; 2540 min_rx = adapter->hw.mac.max_frame_size; 2541 min_rx = roundup2(min_rx, 1024); 2542 min_rx >>= 10; 2543 if (tx_space < min_tx && 2544 ((min_tx - tx_space) < pba)) { 2545 pba = pba - (min_tx - tx_space); 2546 /* 2547 * if short on rx space, rx wins 2548 * and must trump tx adjustment 2549 */ 2550 if (pba < min_rx) 2551 pba = min_rx; 2552 } 2553 E1000_WRITE_REG(hw, E1000_PBA, pba); 2554 } 2555 2556 if (hw->mac.type < igb_mac_min) 2557 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2558 2559 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2560 2561 /* 2562 * These parameters control the automatic generation (Tx) and 2563 * response (Rx) to Ethernet PAUSE frames. 2564 * - High water mark should allow for at least two frames to be 2565 * received after sending an XOFF. 2566 * - Low water mark works best when it is very near the high water mark. 2567 * This allows the receiver to restart by sending XON when it has 2568 * drained a bit. Here we use an arbitrary value of 1500 which will 2569 * restart after one full frame is pulled from the buffer. There 2570 * could be several smaller frames in the buffer and if so they will 2571 * not trigger the XON until their total number reduces the buffer 2572 * by 1500. 2573 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2574 */ 2575 rx_buffer_size = (pba & 0xffff) << 10; 2576 hw->fc.high_water = rx_buffer_size - 2577 roundup2(adapter->hw.mac.max_frame_size, 1024); 2578 hw->fc.low_water = hw->fc.high_water - 1500; 2579 2580 if (adapter->fc) /* locally set flow control value? */ 2581 hw->fc.requested_mode = adapter->fc; 2582 else 2583 hw->fc.requested_mode = e1000_fc_full; 2584 2585 if (hw->mac.type == e1000_80003es2lan) 2586 hw->fc.pause_time = 0xFFFF; 2587 else 2588 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2589 2590 hw->fc.send_xon = TRUE; 2591 2592 /* Device specific overrides/settings */ 2593 switch (hw->mac.type) { 2594 case e1000_pchlan: 2595 /* Workaround: no TX flow ctrl for PCH */ 2596 hw->fc.requested_mode = e1000_fc_rx_pause; 2597 hw->fc.pause_time = 0xFFFF; /* override */ 2598 if (if_getmtu(ifp) > ETHERMTU) { 2599 hw->fc.high_water = 0x3500; 2600 hw->fc.low_water = 0x1500; 2601 } else { 2602 hw->fc.high_water = 0x5000; 2603 hw->fc.low_water = 0x3000; 2604 } 2605 hw->fc.refresh_time = 0x1000; 2606 break; 2607 case e1000_pch2lan: 2608 case e1000_pch_lpt: 2609 case e1000_pch_spt: 2610 case e1000_pch_cnp: 2611 hw->fc.high_water = 0x5C20; 2612 hw->fc.low_water = 0x5048; 2613 hw->fc.pause_time = 0x0650; 2614 hw->fc.refresh_time = 0x0400; 2615 /* Jumbos need adjusted PBA */ 2616 if (if_getmtu(ifp) > ETHERMTU) 2617 E1000_WRITE_REG(hw, E1000_PBA, 12); 2618 else 2619 E1000_WRITE_REG(hw, E1000_PBA, 26); 2620 break; 2621 case e1000_82575: 2622 case e1000_82576: 2623 /* 8-byte granularity */ 2624 hw->fc.low_water = hw->fc.high_water - 8; 2625 break; 2626 case e1000_82580: 2627 case e1000_i350: 2628 case e1000_i354: 2629 case e1000_i210: 2630 case e1000_i211: 2631 case e1000_vfadapt: 2632 case e1000_vfadapt_i350: 2633 /* 16-byte granularity */ 2634 hw->fc.low_water = hw->fc.high_water - 16; 2635 break; 2636 case e1000_ich9lan: 2637 case e1000_ich10lan: 2638 if (if_getmtu(ifp) > ETHERMTU) { 2639 hw->fc.high_water = 0x2800; 2640 hw->fc.low_water = hw->fc.high_water - 8; 2641 break; 2642 } 2643 /* FALLTHROUGH */ 2644 default: 2645 if (hw->mac.type == e1000_80003es2lan) 2646 hw->fc.pause_time = 0xFFFF; 2647 break; 2648 } 2649 2650 /* Issue a global reset */ 2651 e1000_reset_hw(hw); 2652 if (adapter->hw.mac.type >= igb_mac_min) { 2653 E1000_WRITE_REG(hw, E1000_WUC, 0); 2654 } else { 2655 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2656 em_disable_aspm(adapter); 2657 } 2658 if (adapter->flags & IGB_MEDIA_RESET) { 2659 e1000_setup_init_funcs(hw, TRUE); 2660 e1000_get_bus_info(hw); 2661 adapter->flags &= ~IGB_MEDIA_RESET; 2662 } 2663 /* and a re-init */ 2664 if (e1000_init_hw(hw) < 0) { 2665 device_printf(dev, "Hardware Initialization Failed\n"); 2666 return; 2667 } 2668 if (adapter->hw.mac.type >= igb_mac_min) 2669 igb_init_dmac(adapter, pba); 2670 2671 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2672 e1000_get_phy_info(hw); 2673 e1000_check_for_link(hw); 2674 } 2675 2676 /* 2677 * Initialise the RSS mapping for NICs that support multiple transmit/ 2678 * receive rings. 2679 */ 2680 2681 #define RSSKEYLEN 10 2682 static void 2683 em_initialize_rss_mapping(struct adapter *adapter) 2684 { 2685 uint8_t rss_key[4 * RSSKEYLEN]; 2686 uint32_t reta = 0; 2687 struct e1000_hw *hw = &adapter->hw; 2688 int i; 2689 2690 /* 2691 * Configure RSS key 2692 */ 2693 arc4rand(rss_key, sizeof(rss_key), 0); 2694 for (i = 0; i < RSSKEYLEN; ++i) { 2695 uint32_t rssrk = 0; 2696 2697 rssrk = EM_RSSRK_VAL(rss_key, i); 2698 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2699 } 2700 2701 /* 2702 * Configure RSS redirect table in following fashion: 2703 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2704 */ 2705 for (i = 0; i < sizeof(reta); ++i) { 2706 uint32_t q; 2707 2708 q = (i % adapter->rx_num_queues) << 7; 2709 reta |= q << (8 * i); 2710 } 2711 2712 for (i = 0; i < 32; ++i) 2713 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2714 2715 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2716 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2717 E1000_MRQC_RSS_FIELD_IPV4 | 2718 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2719 E1000_MRQC_RSS_FIELD_IPV6_EX | 2720 E1000_MRQC_RSS_FIELD_IPV6); 2721 } 2722 2723 static void 2724 igb_initialize_rss_mapping(struct adapter *adapter) 2725 { 2726 struct e1000_hw *hw = &adapter->hw; 2727 int i; 2728 int queue_id; 2729 u32 reta; 2730 u32 rss_key[10], mrqc, shift = 0; 2731 2732 /* XXX? */ 2733 if (adapter->hw.mac.type == e1000_82575) 2734 shift = 6; 2735 2736 /* 2737 * The redirection table controls which destination 2738 * queue each bucket redirects traffic to. 2739 * Each DWORD represents four queues, with the LSB 2740 * being the first queue in the DWORD. 2741 * 2742 * This just allocates buckets to queues using round-robin 2743 * allocation. 2744 * 2745 * NOTE: It Just Happens to line up with the default 2746 * RSS allocation method. 2747 */ 2748 2749 /* Warning FM follows */ 2750 reta = 0; 2751 for (i = 0; i < 128; i++) { 2752 #ifdef RSS 2753 queue_id = rss_get_indirection_to_bucket(i); 2754 /* 2755 * If we have more queues than buckets, we'll 2756 * end up mapping buckets to a subset of the 2757 * queues. 2758 * 2759 * If we have more buckets than queues, we'll 2760 * end up instead assigning multiple buckets 2761 * to queues. 2762 * 2763 * Both are suboptimal, but we need to handle 2764 * the case so we don't go out of bounds 2765 * indexing arrays and such. 2766 */ 2767 queue_id = queue_id % adapter->rx_num_queues; 2768 #else 2769 queue_id = (i % adapter->rx_num_queues); 2770 #endif 2771 /* Adjust if required */ 2772 queue_id = queue_id << shift; 2773 2774 /* 2775 * The low 8 bits are for hash value (n+0); 2776 * The next 8 bits are for hash value (n+1), etc. 2777 */ 2778 reta = reta >> 8; 2779 reta = reta | ( ((uint32_t) queue_id) << 24); 2780 if ((i & 3) == 3) { 2781 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2782 reta = 0; 2783 } 2784 } 2785 2786 /* Now fill in hash table */ 2787 2788 /* 2789 * MRQC: Multiple Receive Queues Command 2790 * Set queuing to RSS control, number depends on the device. 2791 */ 2792 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2793 2794 #ifdef RSS 2795 /* XXX ew typecasting */ 2796 rss_getkey((uint8_t *) &rss_key); 2797 #else 2798 arc4rand(&rss_key, sizeof(rss_key), 0); 2799 #endif 2800 for (i = 0; i < 10; i++) 2801 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2802 2803 /* 2804 * Configure the RSS fields to hash upon. 2805 */ 2806 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2807 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2808 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2809 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2810 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2811 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2812 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2813 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2814 2815 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2816 } 2817 2818 /********************************************************************* 2819 * 2820 * Setup networking device structure and register interface media. 2821 * 2822 **********************************************************************/ 2823 static int 2824 em_setup_interface(if_ctx_t ctx) 2825 { 2826 struct ifnet *ifp = iflib_get_ifp(ctx); 2827 struct adapter *adapter = iflib_get_softc(ctx); 2828 if_softc_ctx_t scctx = adapter->shared; 2829 2830 INIT_DEBUGOUT("em_setup_interface: begin"); 2831 2832 /* Single Queue */ 2833 if (adapter->tx_num_queues == 1) { 2834 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2835 if_setsendqready(ifp); 2836 } 2837 2838 /* 2839 * Specify the media types supported by this adapter and register 2840 * callbacks to update media and link information 2841 */ 2842 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2843 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2844 u_char fiber_type = IFM_1000_SX; /* default type */ 2845 2846 if (adapter->hw.mac.type == e1000_82545) 2847 fiber_type = IFM_1000_LX; 2848 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2849 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2850 } else { 2851 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2852 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2853 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2854 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2855 if (adapter->hw.phy.type != e1000_phy_ife) { 2856 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2857 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2858 } 2859 } 2860 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2861 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2862 return (0); 2863 } 2864 2865 static int 2866 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2867 { 2868 struct adapter *adapter = iflib_get_softc(ctx); 2869 if_softc_ctx_t scctx = adapter->shared; 2870 int error = E1000_SUCCESS; 2871 struct em_tx_queue *que; 2872 int i, j; 2873 2874 MPASS(adapter->tx_num_queues > 0); 2875 MPASS(adapter->tx_num_queues == ntxqsets); 2876 2877 /* First allocate the top level queue structs */ 2878 if (!(adapter->tx_queues = 2879 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2880 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2881 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2882 return(ENOMEM); 2883 } 2884 2885 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2886 /* Set up some basics */ 2887 2888 struct tx_ring *txr = &que->txr; 2889 txr->adapter = que->adapter = adapter; 2890 que->me = txr->me = i; 2891 2892 /* Allocate report status array */ 2893 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2894 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2895 error = ENOMEM; 2896 goto fail; 2897 } 2898 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2899 txr->tx_rsq[j] = QIDX_INVALID; 2900 /* get the virtual and physical address of the hardware queues */ 2901 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2902 txr->tx_paddr = paddrs[i*ntxqs]; 2903 } 2904 2905 if (bootverbose) 2906 device_printf(iflib_get_dev(ctx), 2907 "allocated for %d tx_queues\n", adapter->tx_num_queues); 2908 return (0); 2909 fail: 2910 em_if_queues_free(ctx); 2911 return (error); 2912 } 2913 2914 static int 2915 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2916 { 2917 struct adapter *adapter = iflib_get_softc(ctx); 2918 int error = E1000_SUCCESS; 2919 struct em_rx_queue *que; 2920 int i; 2921 2922 MPASS(adapter->rx_num_queues > 0); 2923 MPASS(adapter->rx_num_queues == nrxqsets); 2924 2925 /* First allocate the top level queue structs */ 2926 if (!(adapter->rx_queues = 2927 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2928 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2929 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2930 error = ENOMEM; 2931 goto fail; 2932 } 2933 2934 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2935 /* Set up some basics */ 2936 struct rx_ring *rxr = &que->rxr; 2937 rxr->adapter = que->adapter = adapter; 2938 rxr->que = que; 2939 que->me = rxr->me = i; 2940 2941 /* get the virtual and physical address of the hardware queues */ 2942 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2943 rxr->rx_paddr = paddrs[i*nrxqs]; 2944 } 2945 2946 if (bootverbose) 2947 device_printf(iflib_get_dev(ctx), 2948 "allocated for %d rx_queues\n", adapter->rx_num_queues); 2949 2950 return (0); 2951 fail: 2952 em_if_queues_free(ctx); 2953 return (error); 2954 } 2955 2956 static void 2957 em_if_queues_free(if_ctx_t ctx) 2958 { 2959 struct adapter *adapter = iflib_get_softc(ctx); 2960 struct em_tx_queue *tx_que = adapter->tx_queues; 2961 struct em_rx_queue *rx_que = adapter->rx_queues; 2962 2963 if (tx_que != NULL) { 2964 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2965 struct tx_ring *txr = &tx_que->txr; 2966 if (txr->tx_rsq == NULL) 2967 break; 2968 2969 free(txr->tx_rsq, M_DEVBUF); 2970 txr->tx_rsq = NULL; 2971 } 2972 free(adapter->tx_queues, M_DEVBUF); 2973 adapter->tx_queues = NULL; 2974 } 2975 2976 if (rx_que != NULL) { 2977 free(adapter->rx_queues, M_DEVBUF); 2978 adapter->rx_queues = NULL; 2979 } 2980 2981 em_release_hw_control(adapter); 2982 2983 if (adapter->mta != NULL) { 2984 free(adapter->mta, M_DEVBUF); 2985 } 2986 } 2987 2988 /********************************************************************* 2989 * 2990 * Enable transmit unit. 2991 * 2992 **********************************************************************/ 2993 static void 2994 em_initialize_transmit_unit(if_ctx_t ctx) 2995 { 2996 struct adapter *adapter = iflib_get_softc(ctx); 2997 if_softc_ctx_t scctx = adapter->shared; 2998 struct em_tx_queue *que; 2999 struct tx_ring *txr; 3000 struct e1000_hw *hw = &adapter->hw; 3001 u32 tctl, txdctl = 0, tarc, tipg = 0; 3002 3003 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3004 3005 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 3006 u64 bus_addr; 3007 caddr_t offp, endp; 3008 3009 que = &adapter->tx_queues[i]; 3010 txr = &que->txr; 3011 bus_addr = txr->tx_paddr; 3012 3013 /* Clear checksum offload context. */ 3014 offp = (caddr_t)&txr->csum_flags; 3015 endp = (caddr_t)(txr + 1); 3016 bzero(offp, endp - offp); 3017 3018 /* Base and Len of TX Ring */ 3019 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3020 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3021 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3022 (u32)(bus_addr >> 32)); 3023 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3024 (u32)bus_addr); 3025 /* Init the HEAD/TAIL indices */ 3026 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3027 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3028 3029 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3030 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 3031 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 3032 3033 txdctl = 0; /* clear txdctl */ 3034 txdctl |= 0x1f; /* PTHRESH */ 3035 txdctl |= 1 << 8; /* HTHRESH */ 3036 txdctl |= 1 << 16;/* WTHRESH */ 3037 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3038 txdctl |= E1000_TXDCTL_GRAN; 3039 txdctl |= 1 << 25; /* LWTHRESH */ 3040 3041 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3042 } 3043 3044 /* Set the default values for the Tx Inter Packet Gap timer */ 3045 switch (adapter->hw.mac.type) { 3046 case e1000_80003es2lan: 3047 tipg = DEFAULT_82543_TIPG_IPGR1; 3048 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3049 E1000_TIPG_IPGR2_SHIFT; 3050 break; 3051 case e1000_82542: 3052 tipg = DEFAULT_82542_TIPG_IPGT; 3053 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3054 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3055 break; 3056 default: 3057 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3058 (adapter->hw.phy.media_type == 3059 e1000_media_type_internal_serdes)) 3060 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3061 else 3062 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3063 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3064 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3065 } 3066 3067 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3068 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3069 3070 if(adapter->hw.mac.type >= e1000_82540) 3071 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3072 adapter->tx_abs_int_delay.value); 3073 3074 if ((adapter->hw.mac.type == e1000_82571) || 3075 (adapter->hw.mac.type == e1000_82572)) { 3076 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3077 tarc |= TARC_SPEED_MODE_BIT; 3078 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3079 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3080 /* errata: program both queues to unweighted RR */ 3081 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3082 tarc |= 1; 3083 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3084 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3085 tarc |= 1; 3086 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3087 } else if (adapter->hw.mac.type == e1000_82574) { 3088 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3089 tarc |= TARC_ERRATA_BIT; 3090 if ( adapter->tx_num_queues > 1) { 3091 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3092 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3093 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3094 } else 3095 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3096 } 3097 3098 if (adapter->tx_int_delay.value > 0) 3099 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3100 3101 /* Program the Transmit Control Register */ 3102 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3103 tctl &= ~E1000_TCTL_CT; 3104 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3105 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3106 3107 if (adapter->hw.mac.type >= e1000_82571) 3108 tctl |= E1000_TCTL_MULR; 3109 3110 /* This write will effectively turn on the transmit unit. */ 3111 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3112 3113 /* SPT and KBL errata workarounds */ 3114 if (hw->mac.type == e1000_pch_spt) { 3115 u32 reg; 3116 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3117 reg |= E1000_RCTL_RDMTS_HEX; 3118 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3119 /* i218-i219 Specification Update 1.5.4.5 */ 3120 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3121 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3122 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3123 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3124 } 3125 } 3126 3127 /********************************************************************* 3128 * 3129 * Enable receive unit. 3130 * 3131 **********************************************************************/ 3132 3133 static void 3134 em_initialize_receive_unit(if_ctx_t ctx) 3135 { 3136 struct adapter *adapter = iflib_get_softc(ctx); 3137 if_softc_ctx_t scctx = adapter->shared; 3138 struct ifnet *ifp = iflib_get_ifp(ctx); 3139 struct e1000_hw *hw = &adapter->hw; 3140 struct em_rx_queue *que; 3141 int i; 3142 u32 rctl, rxcsum, rfctl; 3143 3144 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3145 3146 /* 3147 * Make sure receives are disabled while setting 3148 * up the descriptor ring 3149 */ 3150 rctl = E1000_READ_REG(hw, E1000_RCTL); 3151 /* Do not disable if ever enabled on this hardware */ 3152 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3153 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3154 3155 /* Setup the Receive Control Register */ 3156 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3157 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3158 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3159 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3160 3161 /* Do not store bad packets */ 3162 rctl &= ~E1000_RCTL_SBP; 3163 3164 /* Enable Long Packet receive */ 3165 if (if_getmtu(ifp) > ETHERMTU) 3166 rctl |= E1000_RCTL_LPE; 3167 else 3168 rctl &= ~E1000_RCTL_LPE; 3169 3170 /* Strip the CRC */ 3171 if (!em_disable_crc_stripping) 3172 rctl |= E1000_RCTL_SECRC; 3173 3174 if (adapter->hw.mac.type >= e1000_82540) { 3175 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3176 adapter->rx_abs_int_delay.value); 3177 3178 /* 3179 * Set the interrupt throttling rate. Value is calculated 3180 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3181 */ 3182 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3183 } 3184 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3185 adapter->rx_int_delay.value); 3186 3187 /* Use extended rx descriptor formats */ 3188 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3189 rfctl |= E1000_RFCTL_EXTEN; 3190 /* 3191 * When using MSI-X interrupts we need to throttle 3192 * using the EITR register (82574 only) 3193 */ 3194 if (hw->mac.type == e1000_82574) { 3195 for (int i = 0; i < 4; i++) 3196 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3197 DEFAULT_ITR); 3198 /* Disable accelerated acknowledge */ 3199 rfctl |= E1000_RFCTL_ACK_DIS; 3200 } 3201 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3202 3203 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3204 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3205 adapter->hw.mac.type >= e1000_82543) { 3206 if (adapter->tx_num_queues > 1) { 3207 if (adapter->hw.mac.type >= igb_mac_min) { 3208 rxcsum |= E1000_RXCSUM_PCSD; 3209 if (hw->mac.type != e1000_82575) 3210 rxcsum |= E1000_RXCSUM_CRCOFL; 3211 } else 3212 rxcsum |= E1000_RXCSUM_TUOFL | 3213 E1000_RXCSUM_IPOFL | 3214 E1000_RXCSUM_PCSD; 3215 } else { 3216 if (adapter->hw.mac.type >= igb_mac_min) 3217 rxcsum |= E1000_RXCSUM_IPPCSE; 3218 else 3219 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3220 if (adapter->hw.mac.type > e1000_82575) 3221 rxcsum |= E1000_RXCSUM_CRCOFL; 3222 } 3223 } else 3224 rxcsum &= ~E1000_RXCSUM_TUOFL; 3225 3226 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3227 3228 if (adapter->rx_num_queues > 1) { 3229 if (adapter->hw.mac.type >= igb_mac_min) 3230 igb_initialize_rss_mapping(adapter); 3231 else 3232 em_initialize_rss_mapping(adapter); 3233 } 3234 3235 /* 3236 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3237 * long latencies are observed, like Lenovo X60. This 3238 * change eliminates the problem, but since having positive 3239 * values in RDTR is a known source of problems on other 3240 * platforms another solution is being sought. 3241 */ 3242 if (hw->mac.type == e1000_82573) 3243 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3244 3245 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3246 struct rx_ring *rxr = &que->rxr; 3247 /* Setup the Base and Length of the Rx Descriptor Ring */ 3248 u64 bus_addr = rxr->rx_paddr; 3249 #if 0 3250 u32 rdt = adapter->rx_num_queues -1; /* default */ 3251 #endif 3252 3253 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3254 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3255 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3256 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3257 /* Setup the Head and Tail Descriptor Pointers */ 3258 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3259 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3260 } 3261 3262 /* 3263 * Set PTHRESH for improved jumbo performance 3264 * According to 10.2.5.11 of Intel 82574 Datasheet, 3265 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3266 * Only write to RXDCTL(1) if there is a need for different 3267 * settings. 3268 */ 3269 3270 if (((adapter->hw.mac.type == e1000_ich9lan) || 3271 (adapter->hw.mac.type == e1000_pch2lan) || 3272 (adapter->hw.mac.type == e1000_ich10lan)) && 3273 (if_getmtu(ifp) > ETHERMTU)) { 3274 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3275 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3276 } else if (adapter->hw.mac.type == e1000_82574) { 3277 for (int i = 0; i < adapter->rx_num_queues; i++) { 3278 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3279 rxdctl |= 0x20; /* PTHRESH */ 3280 rxdctl |= 4 << 8; /* HTHRESH */ 3281 rxdctl |= 4 << 16;/* WTHRESH */ 3282 rxdctl |= 1 << 24; /* Switch to granularity */ 3283 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3284 } 3285 } else if (adapter->hw.mac.type >= igb_mac_min) { 3286 u32 psize, srrctl = 0; 3287 3288 if (if_getmtu(ifp) > ETHERMTU) { 3289 /* Set maximum packet len */ 3290 if (adapter->rx_mbuf_sz <= 4096) { 3291 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3292 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3293 } else if (adapter->rx_mbuf_sz > 4096) { 3294 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3295 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3296 } 3297 psize = scctx->isc_max_frame_size; 3298 /* are we on a vlan? */ 3299 if (ifp->if_vlantrunk != NULL) 3300 psize += VLAN_TAG_SIZE; 3301 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3302 } else { 3303 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3304 rctl |= E1000_RCTL_SZ_2048; 3305 } 3306 3307 /* 3308 * If TX flow control is disabled and there's >1 queue defined, 3309 * enable DROP. 3310 * 3311 * This drops frames rather than hanging the RX MAC for all queues. 3312 */ 3313 if ((adapter->rx_num_queues > 1) && 3314 (adapter->fc == e1000_fc_none || 3315 adapter->fc == e1000_fc_rx_pause)) { 3316 srrctl |= E1000_SRRCTL_DROP_EN; 3317 } 3318 /* Setup the Base and Length of the Rx Descriptor Rings */ 3319 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3320 struct rx_ring *rxr = &que->rxr; 3321 u64 bus_addr = rxr->rx_paddr; 3322 u32 rxdctl; 3323 3324 #ifdef notyet 3325 /* Configure for header split? -- ignore for now */ 3326 rxr->hdr_split = igb_header_split; 3327 #else 3328 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3329 #endif 3330 3331 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3332 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3333 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3334 (uint32_t)(bus_addr >> 32)); 3335 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3336 (uint32_t)bus_addr); 3337 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3338 /* Enable this Queue */ 3339 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3340 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3341 rxdctl &= 0xFFF00000; 3342 rxdctl |= IGB_RX_PTHRESH; 3343 rxdctl |= IGB_RX_HTHRESH << 8; 3344 rxdctl |= IGB_RX_WTHRESH << 16; 3345 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3346 } 3347 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3348 if (if_getmtu(ifp) > ETHERMTU) 3349 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3350 else 3351 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3352 } 3353 3354 /* Make sure VLAN Filters are off */ 3355 rctl &= ~E1000_RCTL_VFE; 3356 3357 if (adapter->hw.mac.type < igb_mac_min) { 3358 if (adapter->rx_mbuf_sz == MCLBYTES) 3359 rctl |= E1000_RCTL_SZ_2048; 3360 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3361 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3362 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3363 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3364 3365 /* ensure we clear use DTYPE of 00 here */ 3366 rctl &= ~0x00000C00; 3367 } 3368 3369 /* Write out the settings */ 3370 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3371 3372 return; 3373 } 3374 3375 static void 3376 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3377 { 3378 struct adapter *adapter = iflib_get_softc(ctx); 3379 u32 index, bit; 3380 3381 index = (vtag >> 5) & 0x7F; 3382 bit = vtag & 0x1F; 3383 adapter->shadow_vfta[index] |= (1 << bit); 3384 ++adapter->num_vlans; 3385 } 3386 3387 static void 3388 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3389 { 3390 struct adapter *adapter = iflib_get_softc(ctx); 3391 u32 index, bit; 3392 3393 index = (vtag >> 5) & 0x7F; 3394 bit = vtag & 0x1F; 3395 adapter->shadow_vfta[index] &= ~(1 << bit); 3396 --adapter->num_vlans; 3397 } 3398 3399 static void 3400 em_setup_vlan_hw_support(struct adapter *adapter) 3401 { 3402 struct e1000_hw *hw = &adapter->hw; 3403 u32 reg; 3404 3405 /* 3406 * We get here thru init_locked, meaning 3407 * a soft reset, this has already cleared 3408 * the VFTA and other state, so if there 3409 * have been no vlan's registered do nothing. 3410 */ 3411 if (adapter->num_vlans == 0) 3412 return; 3413 3414 /* 3415 * A soft reset zero's out the VFTA, so 3416 * we need to repopulate it now. 3417 */ 3418 for (int i = 0; i < EM_VFTA_SIZE; i++) 3419 if (adapter->shadow_vfta[i] != 0) 3420 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3421 i, adapter->shadow_vfta[i]); 3422 3423 reg = E1000_READ_REG(hw, E1000_CTRL); 3424 reg |= E1000_CTRL_VME; 3425 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3426 3427 /* Enable the Filter Table */ 3428 reg = E1000_READ_REG(hw, E1000_RCTL); 3429 reg &= ~E1000_RCTL_CFIEN; 3430 reg |= E1000_RCTL_VFE; 3431 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3432 } 3433 3434 static void 3435 em_if_intr_enable(if_ctx_t ctx) 3436 { 3437 struct adapter *adapter = iflib_get_softc(ctx); 3438 struct e1000_hw *hw = &adapter->hw; 3439 u32 ims_mask = IMS_ENABLE_MASK; 3440 3441 if (hw->mac.type == e1000_82574) { 3442 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3443 ims_mask |= adapter->ims; 3444 } 3445 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3446 } 3447 3448 static void 3449 em_if_intr_disable(if_ctx_t ctx) 3450 { 3451 struct adapter *adapter = iflib_get_softc(ctx); 3452 struct e1000_hw *hw = &adapter->hw; 3453 3454 if (hw->mac.type == e1000_82574) 3455 E1000_WRITE_REG(hw, EM_EIAC, 0); 3456 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3457 } 3458 3459 static void 3460 igb_if_intr_enable(if_ctx_t ctx) 3461 { 3462 struct adapter *adapter = iflib_get_softc(ctx); 3463 struct e1000_hw *hw = &adapter->hw; 3464 u32 mask; 3465 3466 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3467 mask = (adapter->que_mask | adapter->link_mask); 3468 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3469 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3470 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3471 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3472 } else 3473 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3474 E1000_WRITE_FLUSH(hw); 3475 } 3476 3477 static void 3478 igb_if_intr_disable(if_ctx_t ctx) 3479 { 3480 struct adapter *adapter = iflib_get_softc(ctx); 3481 struct e1000_hw *hw = &adapter->hw; 3482 3483 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3484 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3485 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3486 } 3487 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3488 E1000_WRITE_FLUSH(hw); 3489 } 3490 3491 /* 3492 * Bit of a misnomer, what this really means is 3493 * to enable OS management of the system... aka 3494 * to disable special hardware management features 3495 */ 3496 static void 3497 em_init_manageability(struct adapter *adapter) 3498 { 3499 /* A shared code workaround */ 3500 #define E1000_82542_MANC2H E1000_MANC2H 3501 if (adapter->has_manage) { 3502 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3503 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3504 3505 /* disable hardware interception of ARP */ 3506 manc &= ~(E1000_MANC_ARP_EN); 3507 3508 /* enable receiving management packets to the host */ 3509 manc |= E1000_MANC_EN_MNG2HOST; 3510 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3511 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3512 manc2h |= E1000_MNG2HOST_PORT_623; 3513 manc2h |= E1000_MNG2HOST_PORT_664; 3514 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3515 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3516 } 3517 } 3518 3519 /* 3520 * Give control back to hardware management 3521 * controller if there is one. 3522 */ 3523 static void 3524 em_release_manageability(struct adapter *adapter) 3525 { 3526 if (adapter->has_manage) { 3527 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3528 3529 /* re-enable hardware interception of ARP */ 3530 manc |= E1000_MANC_ARP_EN; 3531 manc &= ~E1000_MANC_EN_MNG2HOST; 3532 3533 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3534 } 3535 } 3536 3537 /* 3538 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3539 * For ASF and Pass Through versions of f/w this means 3540 * that the driver is loaded. For AMT version type f/w 3541 * this means that the network i/f is open. 3542 */ 3543 static void 3544 em_get_hw_control(struct adapter *adapter) 3545 { 3546 u32 ctrl_ext, swsm; 3547 3548 if (adapter->vf_ifp) 3549 return; 3550 3551 if (adapter->hw.mac.type == e1000_82573) { 3552 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3553 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3554 swsm | E1000_SWSM_DRV_LOAD); 3555 return; 3556 } 3557 /* else */ 3558 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3559 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3560 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3561 } 3562 3563 /* 3564 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3565 * For ASF and Pass Through versions of f/w this means that 3566 * the driver is no longer loaded. For AMT versions of the 3567 * f/w this means that the network i/f is closed. 3568 */ 3569 static void 3570 em_release_hw_control(struct adapter *adapter) 3571 { 3572 u32 ctrl_ext, swsm; 3573 3574 if (!adapter->has_manage) 3575 return; 3576 3577 if (adapter->hw.mac.type == e1000_82573) { 3578 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3579 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3580 swsm & ~E1000_SWSM_DRV_LOAD); 3581 return; 3582 } 3583 /* else */ 3584 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3585 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3586 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3587 return; 3588 } 3589 3590 static int 3591 em_is_valid_ether_addr(u8 *addr) 3592 { 3593 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3594 3595 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3596 return (FALSE); 3597 } 3598 3599 return (TRUE); 3600 } 3601 3602 /* 3603 ** Parse the interface capabilities with regard 3604 ** to both system management and wake-on-lan for 3605 ** later use. 3606 */ 3607 static void 3608 em_get_wakeup(if_ctx_t ctx) 3609 { 3610 struct adapter *adapter = iflib_get_softc(ctx); 3611 device_t dev = iflib_get_dev(ctx); 3612 u16 eeprom_data = 0, device_id, apme_mask; 3613 3614 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3615 apme_mask = EM_EEPROM_APME; 3616 3617 switch (adapter->hw.mac.type) { 3618 case e1000_82542: 3619 case e1000_82543: 3620 break; 3621 case e1000_82544: 3622 e1000_read_nvm(&adapter->hw, 3623 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3624 apme_mask = EM_82544_APME; 3625 break; 3626 case e1000_82546: 3627 case e1000_82546_rev_3: 3628 if (adapter->hw.bus.func == 1) { 3629 e1000_read_nvm(&adapter->hw, 3630 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3631 break; 3632 } else 3633 e1000_read_nvm(&adapter->hw, 3634 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3635 break; 3636 case e1000_82573: 3637 case e1000_82583: 3638 adapter->has_amt = TRUE; 3639 /* FALLTHROUGH */ 3640 case e1000_82571: 3641 case e1000_82572: 3642 case e1000_80003es2lan: 3643 if (adapter->hw.bus.func == 1) { 3644 e1000_read_nvm(&adapter->hw, 3645 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3646 break; 3647 } else 3648 e1000_read_nvm(&adapter->hw, 3649 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3650 break; 3651 case e1000_ich8lan: 3652 case e1000_ich9lan: 3653 case e1000_ich10lan: 3654 case e1000_pchlan: 3655 case e1000_pch2lan: 3656 case e1000_pch_lpt: 3657 case e1000_pch_spt: 3658 case e1000_82575: /* listing all igb devices */ 3659 case e1000_82576: 3660 case e1000_82580: 3661 case e1000_i350: 3662 case e1000_i354: 3663 case e1000_i210: 3664 case e1000_i211: 3665 case e1000_vfadapt: 3666 case e1000_vfadapt_i350: 3667 apme_mask = E1000_WUC_APME; 3668 adapter->has_amt = TRUE; 3669 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3670 break; 3671 default: 3672 e1000_read_nvm(&adapter->hw, 3673 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3674 break; 3675 } 3676 if (eeprom_data & apme_mask) 3677 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3678 /* 3679 * We have the eeprom settings, now apply the special cases 3680 * where the eeprom may be wrong or the board won't support 3681 * wake on lan on a particular port 3682 */ 3683 device_id = pci_get_device(dev); 3684 switch (device_id) { 3685 case E1000_DEV_ID_82546GB_PCIE: 3686 adapter->wol = 0; 3687 break; 3688 case E1000_DEV_ID_82546EB_FIBER: 3689 case E1000_DEV_ID_82546GB_FIBER: 3690 /* Wake events only supported on port A for dual fiber 3691 * regardless of eeprom setting */ 3692 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3693 E1000_STATUS_FUNC_1) 3694 adapter->wol = 0; 3695 break; 3696 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3697 /* if quad port adapter, disable WoL on all but port A */ 3698 if (global_quad_port_a != 0) 3699 adapter->wol = 0; 3700 /* Reset for multiple quad port adapters */ 3701 if (++global_quad_port_a == 4) 3702 global_quad_port_a = 0; 3703 break; 3704 case E1000_DEV_ID_82571EB_FIBER: 3705 /* Wake events only supported on port A for dual fiber 3706 * regardless of eeprom setting */ 3707 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3708 E1000_STATUS_FUNC_1) 3709 adapter->wol = 0; 3710 break; 3711 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3712 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3713 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3714 /* if quad port adapter, disable WoL on all but port A */ 3715 if (global_quad_port_a != 0) 3716 adapter->wol = 0; 3717 /* Reset for multiple quad port adapters */ 3718 if (++global_quad_port_a == 4) 3719 global_quad_port_a = 0; 3720 break; 3721 } 3722 return; 3723 } 3724 3725 3726 /* 3727 * Enable PCI Wake On Lan capability 3728 */ 3729 static void 3730 em_enable_wakeup(if_ctx_t ctx) 3731 { 3732 struct adapter *adapter = iflib_get_softc(ctx); 3733 device_t dev = iflib_get_dev(ctx); 3734 if_t ifp = iflib_get_ifp(ctx); 3735 int error = 0; 3736 u32 pmc, ctrl, ctrl_ext, rctl; 3737 u16 status; 3738 3739 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3740 return; 3741 3742 /* 3743 * Determine type of Wakeup: note that wol 3744 * is set with all bits on by default. 3745 */ 3746 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3747 adapter->wol &= ~E1000_WUFC_MAG; 3748 3749 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3750 adapter->wol &= ~E1000_WUFC_EX; 3751 3752 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3753 adapter->wol &= ~E1000_WUFC_MC; 3754 else { 3755 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3756 rctl |= E1000_RCTL_MPE; 3757 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3758 } 3759 3760 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3761 goto pme; 3762 3763 /* Advertise the wakeup capability */ 3764 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3765 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3766 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3767 3768 /* Keep the laser running on Fiber adapters */ 3769 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3770 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3771 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3772 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3773 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3774 } 3775 3776 if ((adapter->hw.mac.type == e1000_ich8lan) || 3777 (adapter->hw.mac.type == e1000_pchlan) || 3778 (adapter->hw.mac.type == e1000_ich9lan) || 3779 (adapter->hw.mac.type == e1000_ich10lan)) 3780 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3781 3782 if ( adapter->hw.mac.type >= e1000_pchlan) { 3783 error = em_enable_phy_wakeup(adapter); 3784 if (error) 3785 goto pme; 3786 } else { 3787 /* Enable wakeup by the MAC */ 3788 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3789 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3790 } 3791 3792 if (adapter->hw.phy.type == e1000_phy_igp_3) 3793 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3794 3795 pme: 3796 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3797 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3798 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3799 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3800 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3801 3802 return; 3803 } 3804 3805 /* 3806 * WOL in the newer chipset interfaces (pchlan) 3807 * require thing to be copied into the phy 3808 */ 3809 static int 3810 em_enable_phy_wakeup(struct adapter *adapter) 3811 { 3812 struct e1000_hw *hw = &adapter->hw; 3813 u32 mreg, ret = 0; 3814 u16 preg; 3815 3816 /* copy MAC RARs to PHY RARs */ 3817 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3818 3819 /* copy MAC MTA to PHY MTA */ 3820 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3821 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3822 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3823 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3824 (u16)((mreg >> 16) & 0xFFFF)); 3825 } 3826 3827 /* configure PHY Rx Control register */ 3828 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3829 mreg = E1000_READ_REG(hw, E1000_RCTL); 3830 if (mreg & E1000_RCTL_UPE) 3831 preg |= BM_RCTL_UPE; 3832 if (mreg & E1000_RCTL_MPE) 3833 preg |= BM_RCTL_MPE; 3834 preg &= ~(BM_RCTL_MO_MASK); 3835 if (mreg & E1000_RCTL_MO_3) 3836 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3837 << BM_RCTL_MO_SHIFT); 3838 if (mreg & E1000_RCTL_BAM) 3839 preg |= BM_RCTL_BAM; 3840 if (mreg & E1000_RCTL_PMCF) 3841 preg |= BM_RCTL_PMCF; 3842 mreg = E1000_READ_REG(hw, E1000_CTRL); 3843 if (mreg & E1000_CTRL_RFCE) 3844 preg |= BM_RCTL_RFCE; 3845 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3846 3847 /* enable PHY wakeup in MAC register */ 3848 E1000_WRITE_REG(hw, E1000_WUC, 3849 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3850 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3851 3852 /* configure and enable PHY wakeup in PHY registers */ 3853 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3854 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3855 3856 /* activate PHY wakeup */ 3857 ret = hw->phy.ops.acquire(hw); 3858 if (ret) { 3859 printf("Could not acquire PHY\n"); 3860 return ret; 3861 } 3862 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3863 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3864 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3865 if (ret) { 3866 printf("Could not read PHY page 769\n"); 3867 goto out; 3868 } 3869 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3870 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3871 if (ret) 3872 printf("Could not set PHY Host Wakeup bit\n"); 3873 out: 3874 hw->phy.ops.release(hw); 3875 3876 return ret; 3877 } 3878 3879 static void 3880 em_if_led_func(if_ctx_t ctx, int onoff) 3881 { 3882 struct adapter *adapter = iflib_get_softc(ctx); 3883 3884 if (onoff) { 3885 e1000_setup_led(&adapter->hw); 3886 e1000_led_on(&adapter->hw); 3887 } else { 3888 e1000_led_off(&adapter->hw); 3889 e1000_cleanup_led(&adapter->hw); 3890 } 3891 } 3892 3893 /* 3894 * Disable the L0S and L1 LINK states 3895 */ 3896 static void 3897 em_disable_aspm(struct adapter *adapter) 3898 { 3899 int base, reg; 3900 u16 link_cap,link_ctrl; 3901 device_t dev = adapter->dev; 3902 3903 switch (adapter->hw.mac.type) { 3904 case e1000_82573: 3905 case e1000_82574: 3906 case e1000_82583: 3907 break; 3908 default: 3909 return; 3910 } 3911 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3912 return; 3913 reg = base + PCIER_LINK_CAP; 3914 link_cap = pci_read_config(dev, reg, 2); 3915 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3916 return; 3917 reg = base + PCIER_LINK_CTL; 3918 link_ctrl = pci_read_config(dev, reg, 2); 3919 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3920 pci_write_config(dev, reg, link_ctrl, 2); 3921 return; 3922 } 3923 3924 /********************************************************************** 3925 * 3926 * Update the board statistics counters. 3927 * 3928 **********************************************************************/ 3929 static void 3930 em_update_stats_counters(struct adapter *adapter) 3931 { 3932 u64 prev_xoffrxc = adapter->stats.xoffrxc; 3933 3934 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3935 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3936 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3937 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3938 } 3939 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3940 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3941 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3942 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3943 3944 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3945 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3946 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3947 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3948 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3949 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3950 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3951 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3952 /* 3953 ** For watchdog management we need to know if we have been 3954 ** paused during the last interval, so capture that here. 3955 */ 3956 if (adapter->stats.xoffrxc != prev_xoffrxc) 3957 adapter->shared->isc_pause_frames = 1; 3958 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3959 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3960 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3961 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3962 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3963 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3964 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3965 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3966 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3967 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3968 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3969 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3970 3971 /* For the 64-bit byte counters the low dword must be read first. */ 3972 /* Both registers clear on the read of the high dword */ 3973 3974 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3975 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3976 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3977 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3978 3979 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3980 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3981 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3982 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3983 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3984 3985 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3986 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3987 3988 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3989 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3990 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3991 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3992 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3993 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3994 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3995 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3996 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3997 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3998 3999 /* Interrupt Counts */ 4000 4001 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 4002 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 4003 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 4004 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 4005 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 4006 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 4007 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 4008 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 4009 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 4010 4011 if (adapter->hw.mac.type >= e1000_82543) { 4012 adapter->stats.algnerrc += 4013 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4014 adapter->stats.rxerrc += 4015 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4016 adapter->stats.tncrs += 4017 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4018 adapter->stats.cexterr += 4019 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4020 adapter->stats.tsctc += 4021 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4022 adapter->stats.tsctfc += 4023 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4024 } 4025 } 4026 4027 static uint64_t 4028 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4029 { 4030 struct adapter *adapter = iflib_get_softc(ctx); 4031 struct ifnet *ifp = iflib_get_ifp(ctx); 4032 4033 switch (cnt) { 4034 case IFCOUNTER_COLLISIONS: 4035 return (adapter->stats.colc); 4036 case IFCOUNTER_IERRORS: 4037 return (adapter->dropped_pkts + adapter->stats.rxerrc + 4038 adapter->stats.crcerrs + adapter->stats.algnerrc + 4039 adapter->stats.ruc + adapter->stats.roc + 4040 adapter->stats.mpc + adapter->stats.cexterr); 4041 case IFCOUNTER_OERRORS: 4042 return (adapter->stats.ecol + adapter->stats.latecol + 4043 adapter->watchdog_events); 4044 default: 4045 return (if_get_counter_default(ifp, cnt)); 4046 } 4047 } 4048 4049 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4050 * @ctx: iflib context 4051 * @event: event code to check 4052 * 4053 * Defaults to returning true for unknown events. 4054 * 4055 * @returns true if iflib needs to reinit the interface 4056 */ 4057 static bool 4058 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4059 { 4060 switch (event) { 4061 case IFLIB_RESTART_VLAN_CONFIG: 4062 return (false); 4063 default: 4064 return (true); 4065 } 4066 } 4067 4068 /* Export a single 32-bit register via a read-only sysctl. */ 4069 static int 4070 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4071 { 4072 struct adapter *adapter; 4073 u_int val; 4074 4075 adapter = oidp->oid_arg1; 4076 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 4077 return (sysctl_handle_int(oidp, &val, 0, req)); 4078 } 4079 4080 /* 4081 * Add sysctl variables, one per statistic, to the system. 4082 */ 4083 static void 4084 em_add_hw_stats(struct adapter *adapter) 4085 { 4086 device_t dev = iflib_get_dev(adapter->ctx); 4087 struct em_tx_queue *tx_que = adapter->tx_queues; 4088 struct em_rx_queue *rx_que = adapter->rx_queues; 4089 4090 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4091 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4092 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4093 struct e1000_hw_stats *stats = &adapter->stats; 4094 4095 struct sysctl_oid *stat_node, *queue_node, *int_node; 4096 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4097 4098 #define QUEUE_NAME_LEN 32 4099 char namebuf[QUEUE_NAME_LEN]; 4100 4101 /* Driver Statistics */ 4102 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4103 CTLFLAG_RD, &adapter->dropped_pkts, 4104 "Driver dropped packets"); 4105 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4106 CTLFLAG_RD, &adapter->link_irq, 4107 "Link MSI-X IRQ Handled"); 4108 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4109 CTLFLAG_RD, &adapter->rx_overruns, 4110 "RX overruns"); 4111 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4112 CTLFLAG_RD, &adapter->watchdog_events, 4113 "Watchdog timeouts"); 4114 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4115 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4116 adapter, E1000_CTRL, em_sysctl_reg_handler, "IU", 4117 "Device Control Register"); 4118 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4119 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4120 adapter, E1000_RCTL, em_sysctl_reg_handler, "IU", 4121 "Receiver Control Register"); 4122 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4123 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4124 "Flow Control High Watermark"); 4125 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4126 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4127 "Flow Control Low Watermark"); 4128 4129 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4130 struct tx_ring *txr = &tx_que->txr; 4131 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4132 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4133 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4134 queue_list = SYSCTL_CHILDREN(queue_node); 4135 4136 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4137 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4138 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4139 "Transmit Descriptor Head"); 4140 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4141 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4142 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4143 "Transmit Descriptor Tail"); 4144 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4145 CTLFLAG_RD, &txr->tx_irq, 4146 "Queue MSI-X Transmit Interrupts"); 4147 } 4148 4149 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4150 struct rx_ring *rxr = &rx_que->rxr; 4151 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4152 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4153 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4154 queue_list = SYSCTL_CHILDREN(queue_node); 4155 4156 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4157 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4158 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4159 "Receive Descriptor Head"); 4160 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4161 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4162 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4163 "Receive Descriptor Tail"); 4164 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4165 CTLFLAG_RD, &rxr->rx_irq, 4166 "Queue MSI-X Receive Interrupts"); 4167 } 4168 4169 /* MAC stats get their own sub node */ 4170 4171 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4172 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4173 stat_list = SYSCTL_CHILDREN(stat_node); 4174 4175 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4176 CTLFLAG_RD, &stats->ecol, 4177 "Excessive collisions"); 4178 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4179 CTLFLAG_RD, &stats->scc, 4180 "Single collisions"); 4181 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4182 CTLFLAG_RD, &stats->mcc, 4183 "Multiple collisions"); 4184 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4185 CTLFLAG_RD, &stats->latecol, 4186 "Late collisions"); 4187 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4188 CTLFLAG_RD, &stats->colc, 4189 "Collision Count"); 4190 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4191 CTLFLAG_RD, &adapter->stats.symerrs, 4192 "Symbol Errors"); 4193 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4194 CTLFLAG_RD, &adapter->stats.sec, 4195 "Sequence Errors"); 4196 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4197 CTLFLAG_RD, &adapter->stats.dc, 4198 "Defer Count"); 4199 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4200 CTLFLAG_RD, &adapter->stats.mpc, 4201 "Missed Packets"); 4202 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4203 CTLFLAG_RD, &adapter->stats.rnbc, 4204 "Receive No Buffers"); 4205 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4206 CTLFLAG_RD, &adapter->stats.ruc, 4207 "Receive Undersize"); 4208 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4209 CTLFLAG_RD, &adapter->stats.rfc, 4210 "Fragmented Packets Received "); 4211 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4212 CTLFLAG_RD, &adapter->stats.roc, 4213 "Oversized Packets Received"); 4214 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4215 CTLFLAG_RD, &adapter->stats.rjc, 4216 "Recevied Jabber"); 4217 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4218 CTLFLAG_RD, &adapter->stats.rxerrc, 4219 "Receive Errors"); 4220 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4221 CTLFLAG_RD, &adapter->stats.crcerrs, 4222 "CRC errors"); 4223 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4224 CTLFLAG_RD, &adapter->stats.algnerrc, 4225 "Alignment Errors"); 4226 /* On 82575 these are collision counts */ 4227 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4228 CTLFLAG_RD, &adapter->stats.cexterr, 4229 "Collision/Carrier extension errors"); 4230 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4231 CTLFLAG_RD, &adapter->stats.xonrxc, 4232 "XON Received"); 4233 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4234 CTLFLAG_RD, &adapter->stats.xontxc, 4235 "XON Transmitted"); 4236 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4237 CTLFLAG_RD, &adapter->stats.xoffrxc, 4238 "XOFF Received"); 4239 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4240 CTLFLAG_RD, &adapter->stats.xofftxc, 4241 "XOFF Transmitted"); 4242 4243 /* Packet Reception Stats */ 4244 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4245 CTLFLAG_RD, &adapter->stats.tpr, 4246 "Total Packets Received "); 4247 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4248 CTLFLAG_RD, &adapter->stats.gprc, 4249 "Good Packets Received"); 4250 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4251 CTLFLAG_RD, &adapter->stats.bprc, 4252 "Broadcast Packets Received"); 4253 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4254 CTLFLAG_RD, &adapter->stats.mprc, 4255 "Multicast Packets Received"); 4256 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4257 CTLFLAG_RD, &adapter->stats.prc64, 4258 "64 byte frames received "); 4259 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4260 CTLFLAG_RD, &adapter->stats.prc127, 4261 "65-127 byte frames received"); 4262 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4263 CTLFLAG_RD, &adapter->stats.prc255, 4264 "128-255 byte frames received"); 4265 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4266 CTLFLAG_RD, &adapter->stats.prc511, 4267 "256-511 byte frames received"); 4268 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4269 CTLFLAG_RD, &adapter->stats.prc1023, 4270 "512-1023 byte frames received"); 4271 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4272 CTLFLAG_RD, &adapter->stats.prc1522, 4273 "1023-1522 byte frames received"); 4274 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4275 CTLFLAG_RD, &adapter->stats.gorc, 4276 "Good Octets Received"); 4277 4278 /* Packet Transmission Stats */ 4279 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4280 CTLFLAG_RD, &adapter->stats.gotc, 4281 "Good Octets Transmitted"); 4282 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4283 CTLFLAG_RD, &adapter->stats.tpt, 4284 "Total Packets Transmitted"); 4285 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4286 CTLFLAG_RD, &adapter->stats.gptc, 4287 "Good Packets Transmitted"); 4288 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4289 CTLFLAG_RD, &adapter->stats.bptc, 4290 "Broadcast Packets Transmitted"); 4291 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4292 CTLFLAG_RD, &adapter->stats.mptc, 4293 "Multicast Packets Transmitted"); 4294 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4295 CTLFLAG_RD, &adapter->stats.ptc64, 4296 "64 byte frames transmitted "); 4297 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4298 CTLFLAG_RD, &adapter->stats.ptc127, 4299 "65-127 byte frames transmitted"); 4300 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4301 CTLFLAG_RD, &adapter->stats.ptc255, 4302 "128-255 byte frames transmitted"); 4303 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4304 CTLFLAG_RD, &adapter->stats.ptc511, 4305 "256-511 byte frames transmitted"); 4306 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4307 CTLFLAG_RD, &adapter->stats.ptc1023, 4308 "512-1023 byte frames transmitted"); 4309 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4310 CTLFLAG_RD, &adapter->stats.ptc1522, 4311 "1024-1522 byte frames transmitted"); 4312 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4313 CTLFLAG_RD, &adapter->stats.tsctc, 4314 "TSO Contexts Transmitted"); 4315 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4316 CTLFLAG_RD, &adapter->stats.tsctfc, 4317 "TSO Contexts Failed"); 4318 4319 4320 /* Interrupt Stats */ 4321 4322 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4323 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4324 int_list = SYSCTL_CHILDREN(int_node); 4325 4326 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4327 CTLFLAG_RD, &adapter->stats.iac, 4328 "Interrupt Assertion Count"); 4329 4330 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4331 CTLFLAG_RD, &adapter->stats.icrxptc, 4332 "Interrupt Cause Rx Pkt Timer Expire Count"); 4333 4334 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4335 CTLFLAG_RD, &adapter->stats.icrxatc, 4336 "Interrupt Cause Rx Abs Timer Expire Count"); 4337 4338 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4339 CTLFLAG_RD, &adapter->stats.ictxptc, 4340 "Interrupt Cause Tx Pkt Timer Expire Count"); 4341 4342 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4343 CTLFLAG_RD, &adapter->stats.ictxatc, 4344 "Interrupt Cause Tx Abs Timer Expire Count"); 4345 4346 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4347 CTLFLAG_RD, &adapter->stats.ictxqec, 4348 "Interrupt Cause Tx Queue Empty Count"); 4349 4350 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4351 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4352 "Interrupt Cause Tx Queue Min Thresh Count"); 4353 4354 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4355 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4356 "Interrupt Cause Rx Desc Min Thresh Count"); 4357 4358 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4359 CTLFLAG_RD, &adapter->stats.icrxoc, 4360 "Interrupt Cause Receiver Overrun Count"); 4361 } 4362 4363 /********************************************************************** 4364 * 4365 * This routine provides a way to dump out the adapter eeprom, 4366 * often a useful debug/service tool. This only dumps the first 4367 * 32 words, stuff that matters is in that extent. 4368 * 4369 **********************************************************************/ 4370 static int 4371 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4372 { 4373 struct adapter *adapter = (struct adapter *)arg1; 4374 int error; 4375 int result; 4376 4377 result = -1; 4378 error = sysctl_handle_int(oidp, &result, 0, req); 4379 4380 if (error || !req->newptr) 4381 return (error); 4382 4383 /* 4384 * This value will cause a hex dump of the 4385 * first 32 16-bit words of the EEPROM to 4386 * the screen. 4387 */ 4388 if (result == 1) 4389 em_print_nvm_info(adapter); 4390 4391 return (error); 4392 } 4393 4394 static void 4395 em_print_nvm_info(struct adapter *adapter) 4396 { 4397 u16 eeprom_data; 4398 int i, j, row = 0; 4399 4400 /* Its a bit crude, but it gets the job done */ 4401 printf("\nInterface EEPROM Dump:\n"); 4402 printf("Offset\n0x0000 "); 4403 for (i = 0, j = 0; i < 32; i++, j++) { 4404 if (j == 8) { /* Make the offset block */ 4405 j = 0; ++row; 4406 printf("\n0x00%x0 ",row); 4407 } 4408 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4409 printf("%04x ", eeprom_data); 4410 } 4411 printf("\n"); 4412 } 4413 4414 static int 4415 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4416 { 4417 struct em_int_delay_info *info; 4418 struct adapter *adapter; 4419 u32 regval; 4420 int error, usecs, ticks; 4421 4422 info = (struct em_int_delay_info *) arg1; 4423 usecs = info->value; 4424 error = sysctl_handle_int(oidp, &usecs, 0, req); 4425 if (error != 0 || req->newptr == NULL) 4426 return (error); 4427 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4428 return (EINVAL); 4429 info->value = usecs; 4430 ticks = EM_USECS_TO_TICKS(usecs); 4431 if (info->offset == E1000_ITR) /* units are 256ns here */ 4432 ticks *= 4; 4433 4434 adapter = info->adapter; 4435 4436 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4437 regval = (regval & ~0xffff) | (ticks & 0xffff); 4438 /* Handle a few special cases. */ 4439 switch (info->offset) { 4440 case E1000_RDTR: 4441 break; 4442 case E1000_TIDV: 4443 if (ticks == 0) { 4444 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4445 /* Don't write 0 into the TIDV register. */ 4446 regval++; 4447 } else 4448 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4449 break; 4450 } 4451 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4452 return (0); 4453 } 4454 4455 static void 4456 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4457 const char *description, struct em_int_delay_info *info, 4458 int offset, int value) 4459 { 4460 info->adapter = adapter; 4461 info->offset = offset; 4462 info->value = value; 4463 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4464 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4465 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4466 info, 0, em_sysctl_int_delay, "I", description); 4467 } 4468 4469 /* 4470 * Set flow control using sysctl: 4471 * Flow control values: 4472 * 0 - off 4473 * 1 - rx pause 4474 * 2 - tx pause 4475 * 3 - full 4476 */ 4477 static int 4478 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4479 { 4480 int error; 4481 static int input = 3; /* default is full */ 4482 struct adapter *adapter = (struct adapter *) arg1; 4483 4484 error = sysctl_handle_int(oidp, &input, 0, req); 4485 4486 if ((error) || (req->newptr == NULL)) 4487 return (error); 4488 4489 if (input == adapter->fc) /* no change? */ 4490 return (error); 4491 4492 switch (input) { 4493 case e1000_fc_rx_pause: 4494 case e1000_fc_tx_pause: 4495 case e1000_fc_full: 4496 case e1000_fc_none: 4497 adapter->hw.fc.requested_mode = input; 4498 adapter->fc = input; 4499 break; 4500 default: 4501 /* Do nothing */ 4502 return (error); 4503 } 4504 4505 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4506 e1000_force_mac_fc(&adapter->hw); 4507 return (error); 4508 } 4509 4510 /* 4511 * Manage Energy Efficient Ethernet: 4512 * Control values: 4513 * 0/1 - enabled/disabled 4514 */ 4515 static int 4516 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4517 { 4518 struct adapter *adapter = (struct adapter *) arg1; 4519 int error, value; 4520 4521 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4522 error = sysctl_handle_int(oidp, &value, 0, req); 4523 if (error || req->newptr == NULL) 4524 return (error); 4525 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4526 em_if_init(adapter->ctx); 4527 4528 return (0); 4529 } 4530 4531 static int 4532 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4533 { 4534 struct adapter *adapter; 4535 int error; 4536 int result; 4537 4538 result = -1; 4539 error = sysctl_handle_int(oidp, &result, 0, req); 4540 4541 if (error || !req->newptr) 4542 return (error); 4543 4544 if (result == 1) { 4545 adapter = (struct adapter *) arg1; 4546 em_print_debug_info(adapter); 4547 } 4548 4549 return (error); 4550 } 4551 4552 static int 4553 em_get_rs(SYSCTL_HANDLER_ARGS) 4554 { 4555 struct adapter *adapter = (struct adapter *) arg1; 4556 int error; 4557 int result; 4558 4559 result = 0; 4560 error = sysctl_handle_int(oidp, &result, 0, req); 4561 4562 if (error || !req->newptr || result != 1) 4563 return (error); 4564 em_dump_rs(adapter); 4565 4566 return (error); 4567 } 4568 4569 static void 4570 em_if_debug(if_ctx_t ctx) 4571 { 4572 em_dump_rs(iflib_get_softc(ctx)); 4573 } 4574 4575 /* 4576 * This routine is meant to be fluid, add whatever is 4577 * needed for debugging a problem. -jfv 4578 */ 4579 static void 4580 em_print_debug_info(struct adapter *adapter) 4581 { 4582 device_t dev = iflib_get_dev(adapter->ctx); 4583 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4584 struct tx_ring *txr = &adapter->tx_queues->txr; 4585 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4586 4587 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4588 printf("Interface is RUNNING "); 4589 else 4590 printf("Interface is NOT RUNNING\n"); 4591 4592 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4593 printf("and INACTIVE\n"); 4594 else 4595 printf("and ACTIVE\n"); 4596 4597 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4598 device_printf(dev, "TX Queue %d ------\n", i); 4599 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4600 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4601 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4602 4603 } 4604 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4605 device_printf(dev, "RX Queue %d ------\n", j); 4606 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4607 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4608 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4609 } 4610 } 4611 4612 /* 4613 * 82574 only: 4614 * Write a new value to the EEPROM increasing the number of MSI-X 4615 * vectors from 3 to 5, for proper multiqueue support. 4616 */ 4617 static void 4618 em_enable_vectors_82574(if_ctx_t ctx) 4619 { 4620 struct adapter *adapter = iflib_get_softc(ctx); 4621 struct e1000_hw *hw = &adapter->hw; 4622 device_t dev = iflib_get_dev(ctx); 4623 u16 edata; 4624 4625 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4626 if (bootverbose) 4627 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4628 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4629 device_printf(dev, "Writing to eeprom: increasing " 4630 "reported MSI-X vectors from 3 to 5...\n"); 4631 edata &= ~(EM_NVM_MSIX_N_MASK); 4632 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4633 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4634 e1000_update_nvm_checksum(hw); 4635 device_printf(dev, "Writing to eeprom: done\n"); 4636 } 4637 } 4638