1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 36 #ifndef _EM_H_DEFINED_ 37 #define _EM_H_DEFINED_ 38 39 40 /* Tunables */ 41 42 /* 43 * EM_TXD: Maximum number of Transmit Descriptors 44 * Valid Range: 80-256 for 82542 and 82543-based adapters 45 * 80-4096 for others 46 * Default Value: 256 47 * This value is the number of transmit descriptors allocated by the driver. 48 * Increasing this value allows the driver to queue more transmits. Each 49 * descriptor is 16 bytes. 50 * Since TDLEN should be multiple of 128bytes, the number of transmit 51 * desscriptors should meet the following condition. 52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 53 */ 54 #define EM_MIN_TXD 80 55 #define EM_MAX_TXD 4096 56 #define EM_DEFAULT_TXD 1024 57 58 /* 59 * EM_RXD - Maximum number of receive Descriptors 60 * Valid Range: 80-256 for 82542 and 82543-based adapters 61 * 80-4096 for others 62 * Default Value: 256 63 * This value is the number of receive descriptors allocated by the driver. 64 * Increasing this value allows the driver to buffer more incoming packets. 65 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 66 * descriptor. The maximum MTU size is 16110. 67 * Since TDLEN should be multiple of 128bytes, the number of transmit 68 * desscriptors should meet the following condition. 69 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 70 */ 71 #define EM_MIN_RXD 80 72 #define EM_MAX_RXD 4096 73 #define EM_DEFAULT_RXD 1024 74 75 /* 76 * EM_TIDV - Transmit Interrupt Delay Value 77 * Valid Range: 0-65535 (0=off) 78 * Default Value: 64 79 * This value delays the generation of transmit interrupts in units of 80 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 81 * efficiency if properly tuned for specific network traffic. If the 82 * system is reporting dropped transmits, this value may be set too high 83 * causing the driver to run out of available transmit descriptors. 84 */ 85 #define EM_TIDV 64 86 87 /* 88 * EM_TADV - Transmit Absolute Interrupt Delay Value 89 * (Not valid for 82542/82543/82544) 90 * Valid Range: 0-65535 (0=off) 91 * Default Value: 64 92 * This value, in units of 1.024 microseconds, limits the delay in which a 93 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 94 * this value ensures that an interrupt is generated after the initial 95 * packet is sent on the wire within the set amount of time. Proper tuning, 96 * along with EM_TIDV, may improve traffic throughput in specific 97 * network conditions. 98 */ 99 #define EM_TADV 64 100 101 /* 102 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 103 * Valid Range: 0-65535 (0=off) 104 * Default Value: 0 105 * This value delays the generation of receive interrupts in units of 1.024 106 * microseconds. Receive interrupt reduction can improve CPU efficiency if 107 * properly tuned for specific network traffic. Increasing this value adds 108 * extra latency to frame reception and can end up decreasing the throughput 109 * of TCP traffic. If the system is reporting dropped receives, this value 110 * may be set too high, causing the driver to run out of available receive 111 * descriptors. 112 * 113 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 114 * may hang (stop transmitting) under certain network conditions. 115 * If this occurs a WATCHDOG message is logged in the system 116 * event log. In addition, the controller is automatically reset, 117 * restoring the network connection. To eliminate the potential 118 * for the hang ensure that EM_RDTR is set to 0. 119 */ 120 #define EM_RDTR 0 121 122 /* 123 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 124 * Valid Range: 0-65535 (0=off) 125 * Default Value: 64 126 * This value, in units of 1.024 microseconds, limits the delay in which a 127 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 128 * this value ensures that an interrupt is generated after the initial 129 * packet is received within the set amount of time. Proper tuning, 130 * along with EM_RDTR, may improve traffic throughput in specific network 131 * conditions. 132 */ 133 #define EM_RADV 64 134 135 /* 136 * This parameter controls the max duration of transmit watchdog. 137 */ 138 #define EM_WATCHDOG (10 * hz) 139 140 /* 141 * This parameter controls when the driver calls the routine to reclaim 142 * transmit descriptors. 143 */ 144 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 145 146 /* 147 * This parameter controls whether or not autonegotation is enabled. 148 * 0 - Disable autonegotiation 149 * 1 - Enable autonegotiation 150 */ 151 #define DO_AUTO_NEG 1 152 153 /* 154 * This parameter control whether or not the driver will wait for 155 * autonegotiation to complete. 156 * 1 - Wait for autonegotiation to complete 157 * 0 - Don't wait for autonegotiation to complete 158 */ 159 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 160 161 /* Tunables -- End */ 162 163 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 164 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 165 ADVERTISE_1000_FULL) 166 167 #define AUTO_ALL_MODES 0 168 169 /* PHY master/slave setting */ 170 #define EM_MASTER_SLAVE e1000_ms_hw_default 171 172 /* 173 * Micellaneous constants 174 */ 175 #define EM_VENDOR_ID 0x8086 176 #define EM_FLASH 0x0014 177 178 #define EM_JUMBO_PBA 0x00000028 179 #define EM_DEFAULT_PBA 0x00000030 180 #define EM_SMARTSPEED_DOWNSHIFT 3 181 #define EM_SMARTSPEED_MAX 15 182 #define EM_MAX_LOOP 10 183 184 #define MAX_NUM_MULTICAST_ADDRESSES 128 185 #define PCI_ANY_ID (~0U) 186 #define ETHER_ALIGN 2 187 #define EM_FC_PAUSE_TIME 0x0680 188 #define EM_EEPROM_APME 0x400; 189 #define EM_82544_APME 0x0004; 190 191 /* 192 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 193 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 194 * also optimize cache line size effect. H/W supports up to cache line size 128. 195 */ 196 #define EM_DBA_ALIGN 128 197 198 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 199 200 /* PCI Config defines */ 201 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 202 #define EM_BAR_TYPE_MASK 0x00000001 203 #define EM_BAR_TYPE_MMEM 0x00000000 204 #define EM_BAR_TYPE_FLASH 0x0014 205 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 206 #define EM_BAR_MEM_TYPE_MASK 0x00000006 207 #define EM_BAR_MEM_TYPE_32BIT 0x00000000 208 #define EM_BAR_MEM_TYPE_64BIT 0x00000004 209 #define EM_MSIX_BAR 3 /* On 82575 */ 210 211 /* Defines for printing debug information */ 212 #define DEBUG_INIT 0 213 #define DEBUG_IOCTL 0 214 #define DEBUG_HW 0 215 216 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 217 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 218 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 219 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 220 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 221 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 222 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 223 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 224 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 225 226 #define EM_MAX_SCATTER 32 227 #define EM_VFTA_SIZE 128 228 #define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 229 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 230 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 231 #define EM_MSIX_LINK 0x01000000 /* For 82574 use */ 232 #define ETH_ZLEN 60 233 #define ETH_ADDR_LEN 6 234 #define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 235 236 /* 237 * 82574 has a nonstandard address for EIAC 238 * and since its only used in MSIX, and in 239 * the em driver only 82574 uses MSIX we can 240 * solve it just using this define. 241 */ 242 #define EM_EIAC 0x000DC 243 244 /* 245 * Bus dma allocation structure used by 246 * e1000_dma_malloc and e1000_dma_free. 247 */ 248 struct em_dma_alloc { 249 bus_addr_t dma_paddr; 250 caddr_t dma_vaddr; 251 bus_dma_tag_t dma_tag; 252 bus_dmamap_t dma_map; 253 bus_dma_segment_t dma_seg; 254 int dma_nseg; 255 }; 256 257 struct adapter; 258 259 struct em_int_delay_info { 260 struct adapter *adapter; /* Back-pointer to the adapter struct */ 261 int offset; /* Register offset to read/write */ 262 int value; /* Current value in usecs */ 263 }; 264 265 /* 266 * The transmit ring, one per tx queue 267 */ 268 struct tx_ring { 269 struct adapter *adapter; 270 struct mtx tx_mtx; 271 char mtx_name[16]; 272 u32 me; 273 u32 msix; 274 u32 ims; 275 bool watchdog_check; 276 int watchdog_time; 277 struct em_dma_alloc txdma; 278 struct e1000_tx_desc *tx_base; 279 struct task tx_task; 280 struct taskqueue *tq; 281 u32 next_avail_desc; 282 u32 next_to_clean; 283 struct em_buffer *tx_buffers; 284 volatile u16 tx_avail; 285 u32 tx_tso; /* last tx was tso */ 286 u16 last_hw_offload; 287 #if __FreeBSD_version >= 800000 288 struct buf_ring *br; 289 #endif 290 /* Interrupt resources */ 291 bus_dma_tag_t txtag; 292 void *tag; 293 struct resource *res; 294 unsigned long tx_irq; 295 unsigned long no_desc_avail; 296 }; 297 298 /* 299 * The Receive ring, one per rx queue 300 */ 301 struct rx_ring { 302 struct adapter *adapter; 303 u32 me; 304 u32 msix; 305 u32 ims; 306 struct mtx rx_mtx; 307 char mtx_name[16]; 308 u32 payload; 309 struct task rx_task; 310 struct taskqueue *tq; 311 struct e1000_rx_desc *rx_base; 312 struct em_dma_alloc rxdma; 313 u32 next_to_refresh; 314 u32 next_to_check; 315 struct em_buffer *rx_buffers; 316 struct mbuf *fmp; 317 struct mbuf *lmp; 318 319 /* Interrupt resources */ 320 void *tag; 321 struct resource *res; 322 bus_dma_tag_t rxtag; 323 bus_dmamap_t rx_sparemap; 324 325 /* Soft stats */ 326 unsigned long rx_irq; 327 unsigned long rx_packets; 328 unsigned long rx_bytes; 329 }; 330 331 332 /* Our adapter structure */ 333 struct adapter { 334 struct ifnet *ifp; 335 struct e1000_hw hw; 336 337 /* FreeBSD operating-system-specific structures. */ 338 struct e1000_osdep osdep; 339 struct device *dev; 340 struct cdev *led_dev; 341 342 struct resource *memory; 343 struct resource *flash; 344 struct resource *msix_mem; 345 346 struct resource *res; 347 void *tag; 348 u32 linkvec; 349 u32 ivars; 350 351 struct ifmedia media; 352 struct callout timer; 353 int msix; 354 int if_flags; 355 int max_frame_size; 356 int min_frame_size; 357 struct mtx core_mtx; 358 int em_insert_vlan_header; 359 u32 ims; 360 bool in_detach; 361 362 /* Task for FAST handling */ 363 struct task link_task; 364 struct task que_task; 365 struct taskqueue *tq; /* private task queue */ 366 367 eventhandler_tag vlan_attach; 368 eventhandler_tag vlan_detach; 369 370 u16 num_vlans; 371 u16 num_queues; 372 373 /* 374 * Transmit rings: 375 * Allocated at run time, an array of rings. 376 */ 377 struct tx_ring *tx_rings; 378 int num_tx_desc; 379 u32 txd_cmd; 380 381 /* 382 * Receive rings: 383 * Allocated at run time, an array of rings. 384 */ 385 struct rx_ring *rx_rings; 386 int num_rx_desc; 387 u32 rx_process_limit; 388 389 /* Management and WOL features */ 390 u32 wol; 391 bool has_manage; 392 bool has_amt; 393 394 /* Info about the board itself */ 395 uint8_t link_active; 396 uint16_t link_speed; 397 uint16_t link_duplex; 398 uint32_t smartspeed; 399 struct em_int_delay_info tx_int_delay; 400 struct em_int_delay_info tx_abs_int_delay; 401 struct em_int_delay_info rx_int_delay; 402 struct em_int_delay_info rx_abs_int_delay; 403 404 /* Misc stats maintained by the driver */ 405 unsigned long dropped_pkts; 406 unsigned long mbuf_alloc_failed; 407 unsigned long mbuf_cluster_failed; 408 unsigned long no_tx_map_avail; 409 unsigned long no_tx_dma_setup; 410 unsigned long rx_overruns; 411 unsigned long watchdog_events; 412 unsigned long link_irq; 413 414 struct e1000_hw_stats stats; 415 }; 416 417 /******************************************************************************** 418 * vendor_info_array 419 * 420 * This array contains the list of Subvendor/Subdevice IDs on which the driver 421 * should load. 422 * 423 ********************************************************************************/ 424 typedef struct _em_vendor_info_t { 425 unsigned int vendor_id; 426 unsigned int device_id; 427 unsigned int subvendor_id; 428 unsigned int subdevice_id; 429 unsigned int index; 430 } em_vendor_info_t; 431 432 struct em_buffer { 433 int next_eop; /* Index of the desc to watch */ 434 struct mbuf *m_head; 435 bus_dmamap_t map; /* bus_dma map for packet */ 436 }; 437 438 #define EM_CORE_LOCK_INIT(_sc, _name) \ 439 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 440 #define EM_TX_LOCK_INIT(_sc, _name) \ 441 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 442 #define EM_RX_LOCK_INIT(_sc, _name) \ 443 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 444 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 445 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 446 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 447 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 448 #define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 449 #define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 450 #define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 451 #define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 452 #define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 453 #define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 454 #define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 455 #define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 456 #define EM_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 457 458 #endif /* _EM_H_DEFINED_ */ 459