1 /****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 36 #ifndef _EM_H_DEFINED_ 37 #define _EM_H_DEFINED_ 38 39 /* Tunables */ 40 41 /* 42 * EM_TXD: Maximum number of Transmit Descriptors 43 * Valid Range: 80-256 for 82542 and 82543-based adapters 44 * 80-4096 for others 45 * Default Value: 256 46 * This value is the number of transmit descriptors allocated by the driver. 47 * Increasing this value allows the driver to queue more transmits. Each 48 * descriptor is 16 bytes. 49 * Since TDLEN should be multiple of 128bytes, the number of transmit 50 * desscriptors should meet the following condition. 51 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 52 */ 53 #define EM_MIN_TXD 80 54 #define EM_MAX_TXD_82543 256 55 #define EM_MAX_TXD 4096 56 #define EM_DEFAULT_TXD EM_MAX_TXD_82543 57 58 /* 59 * EM_RXD - Maximum number of receive Descriptors 60 * Valid Range: 80-256 for 82542 and 82543-based adapters 61 * 80-4096 for others 62 * Default Value: 256 63 * This value is the number of receive descriptors allocated by the driver. 64 * Increasing this value allows the driver to buffer more incoming packets. 65 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 66 * descriptor. The maximum MTU size is 16110. 67 * Since TDLEN should be multiple of 128bytes, the number of transmit 68 * desscriptors should meet the following condition. 69 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 70 */ 71 #define EM_MIN_RXD 80 72 #define EM_MAX_RXD_82543 256 73 #define EM_MAX_RXD 4096 74 #define EM_DEFAULT_RXD EM_MAX_RXD_82543 75 76 /* 77 * EM_TIDV - Transmit Interrupt Delay Value 78 * Valid Range: 0-65535 (0=off) 79 * Default Value: 64 80 * This value delays the generation of transmit interrupts in units of 81 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 82 * efficiency if properly tuned for specific network traffic. If the 83 * system is reporting dropped transmits, this value may be set too high 84 * causing the driver to run out of available transmit descriptors. 85 */ 86 #define EM_TIDV 64 87 88 /* 89 * EM_TADV - Transmit Absolute Interrupt Delay Value 90 * (Not valid for 82542/82543/82544) 91 * Valid Range: 0-65535 (0=off) 92 * Default Value: 64 93 * This value, in units of 1.024 microseconds, limits the delay in which a 94 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 95 * this value ensures that an interrupt is generated after the initial 96 * packet is sent on the wire within the set amount of time. Proper tuning, 97 * along with EM_TIDV, may improve traffic throughput in specific 98 * network conditions. 99 */ 100 #define EM_TADV 64 101 102 /* 103 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 104 * Valid Range: 0-65535 (0=off) 105 * Default Value: 0 106 * This value delays the generation of receive interrupts in units of 1.024 107 * microseconds. Receive interrupt reduction can improve CPU efficiency if 108 * properly tuned for specific network traffic. Increasing this value adds 109 * extra latency to frame reception and can end up decreasing the throughput 110 * of TCP traffic. If the system is reporting dropped receives, this value 111 * may be set too high, causing the driver to run out of available receive 112 * descriptors. 113 * 114 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 115 * may hang (stop transmitting) under certain network conditions. 116 * If this occurs a WATCHDOG message is logged in the system 117 * event log. In addition, the controller is automatically reset, 118 * restoring the network connection. To eliminate the potential 119 * for the hang ensure that EM_RDTR is set to 0. 120 */ 121 #define EM_RDTR 0 122 123 /* 124 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 125 * Valid Range: 0-65535 (0=off) 126 * Default Value: 64 127 * This value, in units of 1.024 microseconds, limits the delay in which a 128 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 129 * this value ensures that an interrupt is generated after the initial 130 * packet is received within the set amount of time. Proper tuning, 131 * along with EM_RDTR, may improve traffic throughput in specific network 132 * conditions. 133 */ 134 #define EM_RADV 64 135 136 /* 137 * This parameter controls the duration of transmit watchdog timer. 138 */ 139 #define EM_TX_TIMEOUT 5 140 141 /* 142 * This parameter controls when the driver calls the routine to reclaim 143 * transmit descriptors. 144 */ 145 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 146 #define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 147 148 /* 149 * This parameter controls whether or not autonegotation is enabled. 150 * 0 - Disable autonegotiation 151 * 1 - Enable autonegotiation 152 */ 153 #define DO_AUTO_NEG 1 154 155 /* 156 * This parameter control whether or not the driver will wait for 157 * autonegotiation to complete. 158 * 1 - Wait for autonegotiation to complete 159 * 0 - Don't wait for autonegotiation to complete 160 */ 161 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 162 163 /* Tunables -- End */ 164 165 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 166 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 167 ADVERTISE_1000_FULL) 168 169 #define AUTO_ALL_MODES 0 170 171 /* PHY master/slave setting */ 172 #define EM_MASTER_SLAVE e1000_ms_hw_default 173 174 /* 175 * Micellaneous constants 176 */ 177 #define EM_VENDOR_ID 0x8086 178 #define EM_FLASH 0x0014 179 180 #define EM_JUMBO_PBA 0x00000028 181 #define EM_DEFAULT_PBA 0x00000030 182 #define EM_SMARTSPEED_DOWNSHIFT 3 183 #define EM_SMARTSPEED_MAX 15 184 #define EM_MAX_INTR 10 185 186 #define MAX_NUM_MULTICAST_ADDRESSES 128 187 #define PCI_ANY_ID (~0U) 188 #define ETHER_ALIGN 2 189 #define EM_FC_PAUSE_TIME 0x0680 190 #define EM_EEPROM_APME 0x400; 191 192 /* Code compatilbility between 6 and 7 */ 193 #ifndef ETHER_BPF_MTAP 194 #define ETHER_BPF_MTAP BPF_MTAP 195 #endif 196 197 /* 198 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 199 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 200 * also optimize cache line size effect. H/W supports up to cache line size 128. 201 */ 202 #define EM_DBA_ALIGN 128 203 204 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 205 206 /* PCI Config defines */ 207 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 208 #define EM_BAR_TYPE_MASK 0x00000001 209 #define EM_BAR_TYPE_MMEM 0x00000000 210 #define EM_BAR_TYPE_IO 0x00000001 211 #define EM_BAR_TYPE_FLASH 0x0014 212 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 213 #define EM_BAR_MEM_TYPE_MASK 0x00000006 214 #define EM_BAR_MEM_TYPE_32BIT 0x00000000 215 #define EM_BAR_MEM_TYPE_64BIT 0x00000004 216 #define EM_MSIX_BAR 3 /* On 82575 */ 217 218 /* Defines for printing debug information */ 219 #define DEBUG_INIT 0 220 #define DEBUG_IOCTL 0 221 #define DEBUG_HW 0 222 223 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 224 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 225 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 226 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 227 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 228 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 229 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 230 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 231 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 232 233 #define EM_MAX_SCATTER 64 234 #define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 235 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 236 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 237 #define ETH_ZLEN 60 238 #define ETH_ADDR_LEN 6 239 #define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 240 241 /* 242 * 82574 has a nonstandard address for EIAC 243 * and since its only used in MSIX, and in 244 * the em driver only 82574 uses MSIX we can 245 * solve it just using this define. 246 */ 247 #define EM_EIAC 0x000DC 248 249 /* Used in for 82547 10Mb Half workaround */ 250 #define EM_PBA_BYTES_SHIFT 0xA 251 #define EM_TX_HEAD_ADDR_SHIFT 7 252 #define EM_PBA_TX_MASK 0xFFFF0000 253 #define EM_FIFO_HDR 0x10 254 #define EM_82547_PKT_THRESH 0x3e0 255 256 #ifdef EM_TIMESYNC 257 /* Precision Time Sync (IEEE 1588) defines */ 258 #define ETHERTYPE_IEEE1588 0x88F7 259 #define PICOSECS_PER_TICK 20833 260 #define TSYNC_PORT 319 /* UDP port for the protocol */ 261 262 /* TIMESYNC IOCTL defines */ 263 #define EM_TIMESYNC_READTS _IOWR('i', 127, struct em_tsync_read) 264 265 /* Used in the READTS IOCTL */ 266 struct em_tsync_read { 267 int read_current_time; 268 struct timespec system_time; 269 u64 network_time; 270 u64 rx_stamp; 271 u64 tx_stamp; 272 u16 seqid; 273 unsigned char srcid[6]; 274 int rx_valid; 275 int tx_valid; 276 }; 277 278 #endif /* EM_TIMESYNC */ 279 280 struct adapter; 281 282 struct em_int_delay_info { 283 struct adapter *adapter; /* Back-pointer to the adapter struct */ 284 int offset; /* Register offset to read/write */ 285 int value; /* Current value in usecs */ 286 }; 287 288 /* 289 * Bus dma allocation structure used by 290 * e1000_dma_malloc and e1000_dma_free. 291 */ 292 struct em_dma_alloc { 293 bus_addr_t dma_paddr; 294 caddr_t dma_vaddr; 295 bus_dma_tag_t dma_tag; 296 bus_dmamap_t dma_map; 297 bus_dma_segment_t dma_seg; 298 int dma_nseg; 299 }; 300 301 /* Our adapter structure */ 302 struct adapter { 303 struct ifnet *ifp; 304 struct e1000_hw hw; 305 306 /* FreeBSD operating-system-specific structures. */ 307 struct e1000_osdep osdep; 308 struct device *dev; 309 310 struct resource *memory; 311 struct resource *flash; 312 struct resource *msix; 313 314 struct resource *ioport; 315 int io_rid; 316 317 /* 82574 uses 3 int vectors */ 318 struct resource *res[3]; 319 void *tag[3]; 320 int rid[3]; 321 322 struct ifmedia media; 323 struct callout timer; 324 struct callout tx_fifo_timer; 325 int watchdog_timer; 326 int msi; 327 int if_flags; 328 int max_frame_size; 329 int min_frame_size; 330 struct mtx core_mtx; 331 struct mtx tx_mtx; 332 struct mtx rx_mtx; 333 int em_insert_vlan_header; 334 335 /* Task for FAST handling */ 336 struct task link_task; 337 struct task rxtx_task; 338 struct task rx_task; 339 struct task tx_task; 340 struct taskqueue *tq; /* private task queue */ 341 342 eventhandler_tag vlan_attach; 343 eventhandler_tag vlan_detach; 344 345 /* Management and WOL features */ 346 int wol; 347 int has_manage; 348 349 /* Info about the board itself */ 350 uint8_t link_active; 351 uint16_t link_speed; 352 uint16_t link_duplex; 353 uint32_t smartspeed; 354 struct em_int_delay_info tx_int_delay; 355 struct em_int_delay_info tx_abs_int_delay; 356 struct em_int_delay_info rx_int_delay; 357 struct em_int_delay_info rx_abs_int_delay; 358 359 /* 360 * Transmit definitions 361 * 362 * We have an array of num_tx_desc descriptors (handled 363 * by the controller) paired with an array of tx_buffers 364 * (at tx_buffer_area). 365 * The index of the next available descriptor is next_avail_tx_desc. 366 * The number of remaining tx_desc is num_tx_desc_avail. 367 */ 368 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 369 struct e1000_tx_desc *tx_desc_base; 370 uint32_t next_avail_tx_desc; 371 uint32_t next_tx_to_clean; 372 volatile uint16_t num_tx_desc_avail; 373 uint16_t num_tx_desc; 374 uint32_t txd_cmd; 375 struct em_buffer *tx_buffer_area; 376 bus_dma_tag_t txtag; /* dma tag for tx */ 377 uint32_t tx_tso; /* last tx was tso */ 378 379 /* 380 * Receive definitions 381 * 382 * we have an array of num_rx_desc rx_desc (handled by the 383 * controller), and paired with an array of rx_buffers 384 * (at rx_buffer_area). 385 * The next pair to check on receive is at offset next_rx_desc_to_check 386 */ 387 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 388 struct e1000_rx_desc *rx_desc_base; 389 uint32_t next_rx_desc_to_check; 390 uint32_t rx_buffer_len; 391 uint16_t num_rx_desc; 392 int rx_process_limit; 393 struct em_buffer *rx_buffer_area; 394 bus_dma_tag_t rxtag; 395 bus_dmamap_t rx_sparemap; 396 397 /* 398 * First/last mbuf pointers, for 399 * collecting multisegment RX packets. 400 */ 401 struct mbuf *fmp; 402 struct mbuf *lmp; 403 404 /* Misc stats maintained by the driver */ 405 unsigned long dropped_pkts; 406 unsigned long mbuf_alloc_failed; 407 unsigned long mbuf_cluster_failed; 408 unsigned long no_tx_desc_avail1; 409 unsigned long no_tx_desc_avail2; 410 unsigned long no_tx_map_avail; 411 unsigned long no_tx_dma_setup; 412 unsigned long watchdog_events; 413 unsigned long rx_overruns; 414 unsigned long rx_irq; 415 unsigned long tx_irq; 416 unsigned long link_irq; 417 418 /* 82547 workaround */ 419 uint32_t tx_fifo_size; 420 uint32_t tx_fifo_head; 421 uint32_t tx_fifo_head_addr; 422 uint64_t tx_fifo_reset_cnt; 423 uint64_t tx_fifo_wrk_cnt; 424 uint32_t tx_head_addr; 425 426 /* For 82544 PCIX Workaround */ 427 boolean_t pcix_82544; 428 boolean_t in_detach; 429 430 #ifdef EM_TIMESYNC 431 u64 last_stamp; 432 u64 last_sec; 433 u32 last_ns; 434 #endif 435 436 struct e1000_hw_stats stats; 437 }; 438 439 /* ****************************************************************************** 440 * vendor_info_array 441 * 442 * This array contains the list of Subvendor/Subdevice IDs on which the driver 443 * should load. 444 * 445 * ******************************************************************************/ 446 typedef struct _em_vendor_info_t { 447 unsigned int vendor_id; 448 unsigned int device_id; 449 unsigned int subvendor_id; 450 unsigned int subdevice_id; 451 unsigned int index; 452 } em_vendor_info_t; 453 454 455 struct em_buffer { 456 int next_eop; /* Index of the desc to watch */ 457 struct mbuf *m_head; 458 bus_dmamap_t map; /* bus_dma map for packet */ 459 }; 460 461 /* For 82544 PCIX Workaround */ 462 typedef struct _ADDRESS_LENGTH_PAIR 463 { 464 uint64_t address; 465 uint32_t length; 466 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 467 468 typedef struct _DESCRIPTOR_PAIR 469 { 470 ADDRESS_LENGTH_PAIR descriptor[4]; 471 uint32_t elements; 472 } DESC_ARRAY, *PDESC_ARRAY; 473 474 #define EM_CORE_LOCK_INIT(_sc, _name) \ 475 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 476 #define EM_TX_LOCK_INIT(_sc, _name) \ 477 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 478 #define EM_RX_LOCK_INIT(_sc, _name) \ 479 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 480 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 481 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 482 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 483 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 484 #define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 485 #define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 486 #define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 487 #define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 488 #define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 489 #define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 490 #define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 491 492 #endif /* _EM_H_DEFINED_ */ 493