1 /* $FreeBSD$ */ 2 #include "if_em.h" 3 4 #ifdef RSS 5 #include <net/rss_config.h> 6 #include <netinet/in_rss.h> 7 #endif 8 9 #ifdef VERBOSE_DEBUG 10 #define DPRINTF device_printf 11 #else 12 #define DPRINTF(...) 13 #endif 14 15 /********************************************************************* 16 * Local Function prototypes 17 *********************************************************************/ 18 static int igb_isc_txd_encap(void *arg, if_pkt_info_t pi); 19 static void igb_isc_txd_flush(void *arg, uint16_t txqid, uint32_t pidx); 20 static int igb_isc_txd_credits_update(void *arg, uint16_t txqid, uint32_t cidx, bool clear); 21 22 static void igb_isc_rxd_refill(void *arg, uint16_t rxqid, uint8_t flid __unused, 23 uint32_t pidx, uint64_t *paddrs, caddr_t *vaddrs __unused, uint16_t count, uint16_t buf_len __unused); 24 static void igb_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, uint32_t pidx); 25 static int igb_isc_rxd_available(void *arg, uint16_t rxqid, uint32_t idx, 26 int budget); 27 static int igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri); 28 29 static int igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status); 30 static int igb_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status); 31 32 static void igb_rx_checksum(u32 staterr, if_rxd_info_t ri, u32 ptype); 33 static int igb_determine_rsstype(u16 pkt_info); 34 35 extern void igb_if_enable_intr(if_ctx_t ctx); 36 extern int em_intr(void *arg); 37 38 struct if_txrx igb_txrx = { 39 igb_isc_txd_encap, 40 igb_isc_txd_flush, 41 igb_isc_txd_credits_update, 42 igb_isc_rxd_available, 43 igb_isc_rxd_pkt_get, 44 igb_isc_rxd_refill, 45 igb_isc_rxd_flush, 46 em_intr 47 }; 48 49 extern if_shared_ctx_t em_sctx; 50 51 /********************************************************************** 52 * 53 * Setup work for hardware segmentation offload (TSO) on 54 * adapters using advanced tx descriptors 55 * 56 **********************************************************************/ 57 static int 58 igb_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status) 59 { 60 struct e1000_adv_tx_context_desc *TXD; 61 struct adapter *adapter = txr->adapter; 62 u32 type_tucmd_mlhl = 0, vlan_macip_lens = 0; 63 u32 mss_l4len_idx = 0; 64 u32 paylen; 65 66 switch(pi->ipi_etype) { 67 case ETHERTYPE_IPV6: 68 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 69 break; 70 case ETHERTYPE_IP: 71 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 72 /* Tell transmit desc to also do IPv4 checksum. */ 73 *olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 74 break; 75 default: 76 panic("%s: CSUM_TSO but no supported IP version (0x%04x)", 77 __func__, ntohs(pi->ipi_etype)); 78 break; 79 } 80 81 TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 82 83 /* This is used in the transmit desc in encap */ 84 paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen; 85 86 /* VLAN MACLEN IPLEN */ 87 if (pi->ipi_mflags & M_VLANTAG) { 88 vlan_macip_lens |= (pi->ipi_vtag << E1000_ADVTXD_VLAN_SHIFT); 89 } 90 91 vlan_macip_lens |= pi->ipi_ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 92 vlan_macip_lens |= pi->ipi_ip_hlen; 93 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 94 95 /* ADV DTYPE TUCMD */ 96 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 97 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 98 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 99 100 /* MSS L4LEN IDX */ 101 mss_l4len_idx |= (pi->ipi_tso_segsz << E1000_ADVTXD_MSS_SHIFT); 102 mss_l4len_idx |= (pi->ipi_tcp_hlen << E1000_ADVTXD_L4LEN_SHIFT); 103 /* 82575 needs the queue index added */ 104 if (adapter->hw.mac.type == e1000_82575) 105 mss_l4len_idx |= txr->me << 4; 106 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 107 108 TXD->seqnum_seed = htole32(0); 109 *cmd_type_len |= E1000_ADVTXD_DCMD_TSE; 110 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 111 *olinfo_status |= paylen << E1000_ADVTXD_PAYLEN_SHIFT; 112 113 return (1); 114 } 115 116 /********************************************************************* 117 * 118 * Advanced Context Descriptor setup for VLAN, CSUM or TSO 119 * 120 **********************************************************************/ 121 static int 122 igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status) 123 { 124 struct e1000_adv_tx_context_desc *TXD; 125 struct adapter *adapter = txr->adapter; 126 u32 vlan_macip_lens, type_tucmd_mlhl; 127 u32 mss_l4len_idx; 128 mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0; 129 int offload = TRUE; 130 131 /* First check if TSO is to be used */ 132 if (pi->ipi_csum_flags & CSUM_TSO) 133 return (igb_tso_setup(txr, pi, cmd_type_len, olinfo_status)); 134 135 /* Indicate the whole packet as payload when not doing TSO */ 136 *olinfo_status |= pi->ipi_len << E1000_ADVTXD_PAYLEN_SHIFT; 137 138 /* Now ready a context descriptor */ 139 TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 140 141 /* 142 ** In advanced descriptors the vlan tag must 143 ** be placed into the context descriptor. Hence 144 ** we need to make one even if not doing offloads. 145 */ 146 if (pi->ipi_mflags & M_VLANTAG) { 147 vlan_macip_lens |= (pi->ipi_vtag << E1000_ADVTXD_VLAN_SHIFT); 148 } else if ((pi->ipi_csum_flags & CSUM_OFFLOAD) == 0) { 149 return (0); 150 } 151 152 /* Set the ether header length */ 153 vlan_macip_lens |= pi->ipi_ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 154 155 switch(pi->ipi_etype) { 156 case ETHERTYPE_IP: 157 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 158 break; 159 case ETHERTYPE_IPV6: 160 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 161 break; 162 default: 163 offload = FALSE; 164 break; 165 } 166 167 vlan_macip_lens |= pi->ipi_ip_hlen; 168 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 169 170 switch (pi->ipi_ipproto) { 171 case IPPROTO_TCP: 172 #if __FreeBSD_version >= 1000000 173 if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)) 174 #else 175 if (pi->ipi_csum_flags & CSUM_TCP) 176 #endif 177 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 178 break; 179 case IPPROTO_UDP: 180 #if __FreeBSD_version >= 1000000 181 if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP)) 182 #else 183 if (pi->ipi_csum_flags & CSUM_UDP) 184 #endif 185 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP; 186 break; 187 188 #if __FreeBSD_version >= 800000 189 case IPPROTO_SCTP: 190 #if __FreeBSD_version >= 1000000 191 if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP)) 192 #else 193 if (pi->ipi_csum_flags & CSUM_SCTP) 194 #endif 195 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP; 196 break; 197 #endif 198 default: 199 offload = FALSE; 200 break; 201 } 202 203 if (offload) /* For the TX descriptor setup */ 204 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 205 206 /* 82575 needs the queue index added */ 207 if (adapter->hw.mac.type == e1000_82575) 208 mss_l4len_idx = txr->me << 4; 209 210 /* Now copy bits into descriptor */ 211 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 212 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 213 TXD->seqnum_seed = htole32(0); 214 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 215 216 return (1); 217 } 218 219 static int 220 igb_isc_txd_encap(void *arg, if_pkt_info_t pi) 221 { 222 struct adapter *sc = arg; 223 if_softc_ctx_t scctx = sc->shared; 224 struct em_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx]; 225 struct tx_ring *txr = &que->txr; 226 int nsegs = pi->ipi_nsegs; 227 bus_dma_segment_t *segs = pi->ipi_segs; 228 struct em_txbuffer *txbuf; 229 union e1000_adv_tx_desc *txd = NULL; 230 231 int i, j, first, pidx_last; 232 u32 olinfo_status, cmd_type_len; 233 234 pidx_last = olinfo_status = 0; 235 /* Basic descriptor defines */ 236 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | 237 E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT); 238 239 if (pi->ipi_mflags & M_VLANTAG) 240 cmd_type_len |= E1000_ADVTXD_DCMD_VLE; 241 242 first = i = pi->ipi_pidx; 243 244 /* Consume the first descriptor */ 245 i += igb_tx_ctx_setup(txr, pi, &cmd_type_len, &olinfo_status); 246 if (i == scctx->isc_ntxd[0]) 247 i = 0; 248 249 /* 82575 needs the queue index added */ 250 if (sc->hw.mac.type == e1000_82575) 251 olinfo_status |= txr->me << 4; 252 253 for (j = 0; j < nsegs; j++) { 254 bus_size_t seglen; 255 bus_addr_t segaddr; 256 257 txbuf = &txr->tx_buffers[i]; 258 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i]; 259 seglen = segs[j].ds_len; 260 segaddr = htole64(segs[j].ds_addr); 261 262 txd->read.buffer_addr = segaddr; 263 txd->read.cmd_type_len = htole32(E1000_TXD_CMD_IFCS | 264 cmd_type_len | seglen); 265 txd->read.olinfo_status = htole32(olinfo_status); 266 pidx_last = i; 267 if (++i == scctx->isc_ntxd[0]) { 268 i = 0; 269 } 270 } 271 272 txd->read.cmd_type_len |= 273 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 274 275 /* Set the EOP descriptor that will be marked done */ 276 txbuf = &txr->tx_buffers[first]; 277 txbuf->eop = pidx_last; 278 279 pi->ipi_new_pidx = i; 280 281 return (0); 282 } 283 284 static void 285 igb_isc_txd_flush(void *arg, uint16_t txqid, uint32_t pidx) 286 { 287 struct adapter *adapter = arg; 288 struct em_tx_queue *que = &adapter->tx_queues[txqid]; 289 struct tx_ring *txr = &que->txr; 290 291 E1000_WRITE_REG(&adapter->hw, E1000_TDT(txr->me), pidx); 292 } 293 294 static int 295 igb_isc_txd_credits_update(void *arg, uint16_t txqid, uint32_t cidx_init, bool clear) 296 { 297 struct adapter *adapter = arg; 298 if_softc_ctx_t scctx = adapter->shared; 299 struct em_tx_queue *que = &adapter->tx_queues[txqid]; 300 struct tx_ring *txr = &que->txr; 301 302 u32 cidx, ntxd, processed = 0; 303 304 struct em_txbuffer *buf; 305 union e1000_adv_tx_desc *txd, *eop; 306 int limit; 307 308 cidx = cidx_init; 309 310 buf = &txr->tx_buffers[cidx]; 311 txd = (union e1000_adv_tx_desc *)&txr->tx_base[cidx]; 312 ntxd = scctx->isc_ntxd[0]; 313 limit = adapter->tx_process_limit; 314 315 do { 316 if (buf->eop == -1) /* No work */ 317 break; 318 319 eop = (union e1000_adv_tx_desc *)&txr->tx_base[buf->eop]; 320 if ((eop->wb.status & E1000_TXD_STAT_DD) == 0) 321 break; /* I/O not complete */ 322 323 if (clear) 324 buf->eop = -1; /* clear indicate processed */ 325 326 /* We clean the range if multi segment */ 327 while (txd != eop) { 328 ++txd; 329 ++buf; 330 /* wrap the ring? */ 331 if (++cidx == scctx->isc_ntxd[0]) { 332 cidx = 0; 333 buf = txr->tx_buffers; 334 txd = (union e1000_adv_tx_desc *)txr->tx_base; 335 } 336 337 buf = &txr->tx_buffers[cidx]; 338 if (clear) 339 buf->eop = -1; 340 processed++; 341 } 342 processed++; 343 344 /* Try the next packet */ 345 txd++; 346 buf++; 347 348 /* reset with a wrap */ 349 if (++cidx == scctx->isc_ntxd[0]) { 350 cidx = 0; 351 buf = txr->tx_buffers; 352 txd = (union e1000_adv_tx_desc *)txr->tx_base; 353 } 354 prefetch(txd); 355 prefetch(txd+1); 356 } while (__predict_true(--limit) && cidx != cidx_init); 357 358 return (processed); 359 } 360 361 static void 362 igb_isc_rxd_refill(void *arg, uint16_t rxqid, uint8_t flid __unused, 363 uint32_t pidx, uint64_t *paddrs, caddr_t *vaddrs __unused, 364 uint16_t count, uint16_t buf_len __unused) 365 { 366 struct adapter *sc = arg; 367 if_softc_ctx_t scctx = sc->shared; 368 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 369 union e1000_adv_rx_desc *rxd; 370 struct rx_ring *rxr = &que->rxr; 371 int i; 372 uint32_t next_pidx; 373 374 for (i = 0, next_pidx = pidx; i < count; i++) { 375 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[next_pidx]; 376 377 rxd->read.pkt_addr = htole64(paddrs[i]); 378 if (++next_pidx == scctx->isc_nrxd[0]) 379 next_pidx = 0; 380 } 381 } 382 383 static void 384 igb_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, uint32_t pidx) 385 { 386 struct adapter *sc = arg; 387 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 388 struct rx_ring *rxr = &que->rxr; 389 390 E1000_WRITE_REG(&sc->hw, E1000_RDT(rxr->me), pidx); 391 } 392 393 static int 394 igb_isc_rxd_available(void *arg, uint16_t rxqid, uint32_t idx, int budget) 395 { 396 struct adapter *sc = arg; 397 if_softc_ctx_t scctx = sc->shared; 398 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 399 struct rx_ring *rxr = &que->rxr; 400 union e1000_adv_rx_desc *rxd; 401 u32 staterr = 0; 402 int cnt, i, iter; 403 404 for (iter = cnt = 0, i = idx; iter < scctx->isc_nrxd[0] && iter <= budget;) { 405 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[i]; 406 staterr = le32toh(rxd->wb.upper.status_error); 407 408 if ((staterr & E1000_RXD_STAT_DD) == 0) 409 break; 410 411 if (++i == scctx->isc_nrxd[0]) { 412 i = 0; 413 } 414 415 if (staterr & E1000_RXD_STAT_EOP) 416 cnt++; 417 iter++; 418 } 419 { 420 struct e1000_hw *hw = &sc->hw; 421 int rdt, rdh; 422 rdt = E1000_READ_REG(hw, E1000_RDT(rxr->me)); 423 rdh = E1000_READ_REG(hw, E1000_RDH(rxr->me)); 424 DPRINTF(iflib_get_dev(sc->ctx), "sidx:%d eidx:%d iter=%d pktcnt=%d RDT=%d RDH=%d\n", idx, i, iter, cnt, rdt, rdh); 425 } 426 return (cnt); 427 } 428 429 /**************************************************************** 430 * Routine sends data which has been dma'ed into host memory 431 * to upper layer. Initialize ri structure. 432 * 433 * Returns 0 upon success, errno on failure 434 ***************************************************************/ 435 436 static int 437 igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri) 438 { 439 struct adapter *adapter = arg; 440 if_softc_ctx_t scctx = adapter->shared; 441 struct em_rx_queue *que = &adapter->rx_queues[ri->iri_qsidx]; 442 struct rx_ring *rxr = &que->rxr; 443 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 444 union e1000_adv_rx_desc *rxd; 445 446 u16 pkt_info, len; 447 u16 vtag = 0; 448 u32 ptype; 449 u32 staterr = 0; 450 bool eop; 451 int i = 0; 452 int cidx = ri->iri_cidx; 453 454 do { 455 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[cidx]; 456 staterr = le32toh(rxd->wb.upper.status_error); 457 pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info); 458 459 MPASS ((staterr & E1000_RXD_STAT_DD) != 0); 460 461 len = le16toh(rxd->wb.upper.length); 462 ptype = le32toh(rxd->wb.lower.lo_dword.data) & IGB_PKTTYPE_MASK; 463 464 ri->iri_len += len; 465 rxr->rx_bytes += ri->iri_len; 466 467 rxd->wb.upper.status_error = 0; 468 eop = ((staterr & E1000_RXD_STAT_EOP) == E1000_RXD_STAT_EOP); 469 470 if (((adapter->hw.mac.type == e1000_i350) || 471 (adapter->hw.mac.type == e1000_i354)) && 472 (staterr & E1000_RXDEXT_STATERR_LB)) 473 vtag = be16toh(rxd->wb.upper.vlan); 474 else 475 vtag = le16toh(rxd->wb.upper.vlan); 476 477 /* Make sure bad packets are discarded */ 478 if (eop && ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) != 0)) { 479 adapter->dropped_pkts++; 480 ++rxr->rx_discarded; 481 return (EBADMSG); 482 } 483 ri->iri_frags[i].irf_flid = 0; 484 ri->iri_frags[i].irf_idx = cidx; 485 ri->iri_frags[i].irf_len = len; 486 487 if (++cidx == scctx->isc_nrxd[0]) 488 cidx = 0; 489 #ifdef notyet 490 if (rxr->hdr_split == TRUE) { 491 ri->iri_frags[i].irf_flid = 1; 492 ri->iri_frags[i].irf_idx = cidx; 493 if (++cidx == scctx->isc_nrxd[0]) 494 cidx = 0; 495 } 496 #endif 497 i++; 498 } while (!eop); 499 500 rxr->rx_packets++; 501 502 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 503 igb_rx_checksum(staterr, ri, ptype); 504 505 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 506 (staterr & E1000_RXD_STAT_VP) != 0) { 507 ri->iri_vtag = vtag; 508 ri->iri_flags |= M_VLANTAG; 509 } 510 ri->iri_flowid = 511 le32toh(rxd->wb.lower.hi_dword.rss); 512 ri->iri_rsstype = igb_determine_rsstype(pkt_info); 513 ri->iri_nfrags = i; 514 515 return (0); 516 } 517 518 /********************************************************************* 519 * 520 * Verify that the hardware indicated that the checksum is valid. 521 * Inform the stack about the status of checksum so that stack 522 * doesn't spend time verifying the checksum. 523 * 524 *********************************************************************/ 525 static void 526 igb_rx_checksum(u32 staterr, if_rxd_info_t ri, u32 ptype) 527 { 528 u16 status = (u16)staterr; 529 u8 errors = (u8) (staterr >> 24); 530 bool sctp = FALSE; 531 532 /* Ignore Checksum bit is set */ 533 if (status & E1000_RXD_STAT_IXSM) { 534 ri->iri_csum_flags = 0; 535 return; 536 } 537 538 if ((ptype & E1000_RXDADV_PKTTYPE_ETQF) == 0 && 539 (ptype & E1000_RXDADV_PKTTYPE_SCTP) != 0) 540 sctp = 1; 541 else 542 sctp = 0; 543 544 if (status & E1000_RXD_STAT_IPCS) { 545 /* Did it pass? */ 546 if (!(errors & E1000_RXD_ERR_IPE)) { 547 /* IP Checksum Good */ 548 ri->iri_csum_flags = CSUM_IP_CHECKED; 549 ri->iri_csum_flags |= CSUM_IP_VALID; 550 } else 551 ri->iri_csum_flags = 0; 552 } 553 554 if (status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) { 555 u64 type = (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 556 #if __FreeBSD_version >= 800000 557 if (sctp) /* reassign */ 558 type = CSUM_SCTP_VALID; 559 #endif 560 /* Did it pass? */ 561 if (!(errors & E1000_RXD_ERR_TCPE)) { 562 ri->iri_csum_flags |= type; 563 if (sctp == 0) 564 ri->iri_csum_data = htons(0xffff); 565 } 566 } 567 return; 568 } 569 570 /******************************************************************** 571 * 572 * Parse the packet type to determine the appropriate hash 573 * 574 ******************************************************************/ 575 static int 576 igb_determine_rsstype(u16 pkt_info) 577 { 578 switch (pkt_info & E1000_RXDADV_RSSTYPE_MASK) { 579 case E1000_RXDADV_RSSTYPE_IPV4_TCP: 580 return M_HASHTYPE_RSS_TCP_IPV4; 581 case E1000_RXDADV_RSSTYPE_IPV4: 582 return M_HASHTYPE_RSS_IPV4; 583 case E1000_RXDADV_RSSTYPE_IPV6_TCP: 584 return M_HASHTYPE_RSS_TCP_IPV6; 585 case E1000_RXDADV_RSSTYPE_IPV6_EX: 586 return M_HASHTYPE_RSS_IPV6_EX; 587 case E1000_RXDADV_RSSTYPE_IPV6: 588 return M_HASHTYPE_RSS_IPV6; 589 case E1000_RXDADV_RSSTYPE_IPV6_TCP_EX: 590 return M_HASHTYPE_RSS_TCP_IPV6_EX; 591 default: 592 return M_HASHTYPE_OPAQUE; 593 } 594 } 595