1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef ENA_H 33 #define ENA_H 34 35 #include "opt_rss.h" 36 37 #include "ena-com/ena_com.h" 38 #include "ena-com/ena_eth_com.h" 39 40 #define ENA_DRV_MODULE_VER_MAJOR 2 41 #define ENA_DRV_MODULE_VER_MINOR 6 42 #define ENA_DRV_MODULE_VER_SUBMINOR 3 43 44 #define ENA_DRV_MODULE_NAME "ena" 45 46 #ifndef ENA_DRV_MODULE_VERSION 47 #define ENA_DRV_MODULE_VERSION \ 48 __XSTRING(ENA_DRV_MODULE_VER_MAJOR) "." \ 49 __XSTRING(ENA_DRV_MODULE_VER_MINOR) "." \ 50 __XSTRING(ENA_DRV_MODULE_VER_SUBMINOR) 51 #endif 52 #define ENA_DEVICE_NAME "Elastic Network Adapter (ENA)" 53 #define ENA_DEVICE_DESC "ENA adapter" 54 55 /* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */ 56 #define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL) 57 58 /* 1 for AENQ + ADMIN */ 59 #define ENA_ADMIN_MSIX_VEC 1 60 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues)) 61 62 #define ENA_REG_BAR 0 63 #define ENA_MEM_BAR 2 64 65 #define ENA_BUS_DMA_SEGS 32 66 67 #define ENA_DEFAULT_BUF_RING_SIZE 4096 68 69 #define ENA_DEFAULT_RING_SIZE 1024 70 #define ENA_MIN_RING_SIZE 256 71 72 /* 73 * Refill Rx queue when number of required descriptors is above 74 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET 75 */ 76 #define ENA_RX_REFILL_THRESH_DIVIDER 8 77 #define ENA_RX_REFILL_THRESH_PACKET 256 78 79 #define ENA_IRQNAME_SIZE 40 80 81 #define ENA_PKT_MAX_BUFS 19 82 83 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 84 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 85 86 #define ENA_HASH_KEY_SIZE 40 87 88 #define ENA_MAX_FRAME_LEN 10000 89 #define ENA_MIN_FRAME_LEN 60 90 91 #define ENA_TX_RESUME_THRESH (ENA_PKT_MAX_BUFS + 2) 92 93 #define ENA_DB_THRESHOLD 64 94 95 #define ENA_TX_COMMIT 32 96 /* 97 * TX budget for cleaning. It should be half of the RX budget to reduce amount 98 * of TCP retransmissions. 99 */ 100 #define ENA_TX_BUDGET 128 101 /* RX cleanup budget. -1 stands for infinity. */ 102 #define ENA_RX_BUDGET 256 103 /* 104 * How many times we can repeat cleanup in the io irq handling routine if the 105 * RX or TX budget was depleted. 106 */ 107 #define ENA_CLEAN_BUDGET 8 108 109 #define ENA_RX_IRQ_INTERVAL 20 110 #define ENA_TX_IRQ_INTERVAL 50 111 112 #define ENA_MIN_MTU 128 113 114 #define ENA_TSO_MAXSIZE 65536 115 116 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 117 118 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 119 120 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 121 122 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 123 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 124 #define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2) 125 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2) 126 127 #define ENA_MGMNT_IRQ_IDX 0 128 #define ENA_IO_IRQ_FIRST_IDX 1 129 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 130 131 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3 132 133 /* 134 * ENA device should send keep alive msg every 1 sec. 135 * We wait for 6 sec just to be on the safe side. 136 */ 137 #define ENA_DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6) 138 139 /* Time in jiffies before concluding the transmitter is hung. */ 140 #define ENA_DEFAULT_TX_CMP_TO (SBT_1S * 5) 141 142 /* Number of queues to check for missing queues per timer tick */ 143 #define ENA_DEFAULT_TX_MONITORED_QUEUES (4) 144 145 /* Max number of timeouted packets before device reset */ 146 #define ENA_DEFAULT_TX_CMP_THRESHOLD (128) 147 148 /* 149 * Supported PCI vendor and devices IDs 150 */ 151 #define PCI_VENDOR_ID_AMAZON 0x1d0f 152 153 #define PCI_DEV_ID_ENA_PF 0x0ec2 154 #define PCI_DEV_ID_ENA_PF_RSERV0 0x1ec2 155 #define PCI_DEV_ID_ENA_VF 0xec20 156 #define PCI_DEV_ID_ENA_VF_RSERV0 0xec21 157 158 /* 159 * Flags indicating current ENA driver state 160 */ 161 enum ena_flags_t { 162 ENA_FLAG_DEVICE_RUNNING, 163 ENA_FLAG_DEV_UP, 164 ENA_FLAG_LINK_UP, 165 ENA_FLAG_MSIX_ENABLED, 166 ENA_FLAG_TRIGGER_RESET, 167 ENA_FLAG_ONGOING_RESET, 168 ENA_FLAG_DEV_UP_BEFORE_RESET, 169 ENA_FLAG_RSS_ACTIVE, 170 ENA_FLAGS_NUMBER = ENA_FLAG_RSS_ACTIVE 171 }; 172 173 BITSET_DEFINE(_ena_state, ENA_FLAGS_NUMBER); 174 typedef struct _ena_state ena_state_t; 175 176 #define ENA_FLAG_ZERO(adapter) \ 177 BIT_ZERO(ENA_FLAGS_NUMBER, &(adapter)->flags) 178 #define ENA_FLAG_ISSET(bit, adapter) \ 179 BIT_ISSET(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags) 180 #define ENA_FLAG_SET_ATOMIC(bit, adapter) \ 181 BIT_SET_ATOMIC(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags) 182 #define ENA_FLAG_CLEAR_ATOMIC(bit, adapter) \ 183 BIT_CLR_ATOMIC(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags) 184 185 struct msix_entry { 186 int entry; 187 int vector; 188 }; 189 190 typedef struct _ena_vendor_info_t { 191 uint16_t vendor_id; 192 uint16_t device_id; 193 unsigned int index; 194 } ena_vendor_info_t; 195 196 struct ena_irq { 197 /* Interrupt resources */ 198 struct resource *res; 199 driver_filter_t *handler; 200 void *data; 201 void *cookie; 202 unsigned int vector; 203 bool requested; 204 #ifdef RSS 205 int cpu; 206 #endif 207 char name[ENA_IRQNAME_SIZE]; 208 }; 209 210 struct ena_que { 211 struct ena_adapter *adapter; 212 struct ena_ring *tx_ring; 213 struct ena_ring *rx_ring; 214 215 struct task cleanup_task; 216 struct taskqueue *cleanup_tq; 217 218 uint32_t id; 219 #ifdef RSS 220 int cpu; 221 cpuset_t cpu_mask; 222 #endif 223 int domain; 224 struct sysctl_oid *oid; 225 }; 226 227 struct ena_calc_queue_size_ctx { 228 struct ena_com_dev_get_features_ctx *get_feat_ctx; 229 struct ena_com_dev *ena_dev; 230 device_t pdev; 231 uint32_t tx_queue_size; 232 uint32_t rx_queue_size; 233 uint32_t max_tx_queue_size; 234 uint32_t max_rx_queue_size; 235 uint16_t max_tx_sgl_size; 236 uint16_t max_rx_sgl_size; 237 }; 238 239 #ifdef DEV_NETMAP 240 struct ena_netmap_tx_info { 241 uint32_t socket_buf_idx[ENA_PKT_MAX_BUFS]; 242 bus_dmamap_t map_seg[ENA_PKT_MAX_BUFS]; 243 unsigned int sockets_used; 244 }; 245 #endif 246 247 struct ena_tx_buffer { 248 struct mbuf *mbuf; 249 /* # of ena desc for this specific mbuf 250 * (includes data desc and metadata desc) */ 251 unsigned int tx_descs; 252 /* # of buffers used by this mbuf */ 253 unsigned int num_of_bufs; 254 255 bus_dmamap_t dmamap; 256 257 /* Used to detect missing tx packets */ 258 struct bintime timestamp; 259 bool print_once; 260 261 #ifdef DEV_NETMAP 262 struct ena_netmap_tx_info nm_info; 263 #endif /* DEV_NETMAP */ 264 265 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 266 } __aligned(CACHE_LINE_SIZE); 267 268 struct ena_rx_buffer { 269 struct mbuf *mbuf; 270 bus_dmamap_t map; 271 struct ena_com_buf ena_buf; 272 #ifdef DEV_NETMAP 273 uint32_t netmap_buf_idx; 274 #endif /* DEV_NETMAP */ 275 } __aligned(CACHE_LINE_SIZE); 276 277 struct ena_stats_tx { 278 counter_u64_t cnt; 279 counter_u64_t bytes; 280 counter_u64_t prepare_ctx_err; 281 counter_u64_t dma_mapping_err; 282 counter_u64_t doorbells; 283 counter_u64_t missing_tx_comp; 284 counter_u64_t bad_req_id; 285 counter_u64_t collapse; 286 counter_u64_t collapse_err; 287 counter_u64_t queue_wakeup; 288 counter_u64_t queue_stop; 289 counter_u64_t llq_buffer_copy; 290 counter_u64_t unmask_interrupt_num; 291 }; 292 293 struct ena_stats_rx { 294 counter_u64_t cnt; 295 counter_u64_t bytes; 296 counter_u64_t refil_partial; 297 counter_u64_t csum_bad; 298 counter_u64_t mjum_alloc_fail; 299 counter_u64_t mbuf_alloc_fail; 300 counter_u64_t dma_mapping_err; 301 counter_u64_t bad_desc_num; 302 counter_u64_t bad_req_id; 303 counter_u64_t empty_rx_ring; 304 counter_u64_t csum_good; 305 }; 306 307 struct ena_ring { 308 /* Holds the empty requests for TX/RX out of order completions */ 309 union { 310 uint16_t *free_tx_ids; 311 uint16_t *free_rx_ids; 312 }; 313 struct ena_com_dev *ena_dev; 314 struct ena_adapter *adapter; 315 struct ena_com_io_cq *ena_com_io_cq; 316 struct ena_com_io_sq *ena_com_io_sq; 317 318 uint16_t qid; 319 320 /* Determines if device will use LLQ or normal mode for TX */ 321 enum ena_admin_placement_policy_type tx_mem_queue_type; 322 union { 323 /* The maximum length the driver can push to the device (For LLQ) */ 324 uint8_t tx_max_header_size; 325 /* The maximum (and default) mbuf size for the Rx descriptor. */ 326 uint16_t rx_mbuf_sz; 327 328 }; 329 330 uint8_t first_interrupt; 331 uint16_t no_interrupt_event_cnt; 332 333 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 334 335 struct ena_que *que; 336 struct lro_ctrl lro; 337 338 uint16_t next_to_use; 339 uint16_t next_to_clean; 340 341 union { 342 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 343 struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */ 344 }; 345 int ring_size; /* number of tx/rx_buffer_info's entries */ 346 347 struct buf_ring *br; /* only for TX */ 348 uint32_t buf_ring_size; 349 350 struct mtx ring_mtx; 351 char mtx_name[16]; 352 353 struct { 354 struct task enqueue_task; 355 struct taskqueue *enqueue_tq; 356 }; 357 358 union { 359 struct ena_stats_tx tx_stats; 360 struct ena_stats_rx rx_stats; 361 }; 362 363 union { 364 int empty_rx_queue; 365 /* For Tx ring to indicate if it's running or not */ 366 bool running; 367 }; 368 369 /* How many packets are sent in one Tx loop, used for doorbells */ 370 uint32_t acum_pkts; 371 372 /* Used for LLQ */ 373 uint8_t *push_buf_intermediate_buf; 374 375 int tx_last_cleanup_ticks; 376 377 #ifdef DEV_NETMAP 378 bool initialized; 379 #endif /* DEV_NETMAP */ 380 } __aligned(CACHE_LINE_SIZE); 381 382 struct ena_stats_dev { 383 counter_u64_t wd_expired; 384 counter_u64_t interface_up; 385 counter_u64_t interface_down; 386 counter_u64_t admin_q_pause; 387 }; 388 389 struct ena_hw_stats { 390 counter_u64_t rx_packets; 391 counter_u64_t tx_packets; 392 393 counter_u64_t rx_bytes; 394 counter_u64_t tx_bytes; 395 396 counter_u64_t rx_drops; 397 counter_u64_t tx_drops; 398 }; 399 400 /* Board specific private data structure */ 401 struct ena_adapter { 402 struct ena_com_dev *ena_dev; 403 404 /* OS defined structs */ 405 if_t ifp; 406 device_t pdev; 407 struct ifmedia media; 408 409 /* OS resources */ 410 struct resource *memory; 411 struct resource *registers; 412 struct resource *msix; 413 int msix_rid; 414 415 /* MSI-X */ 416 struct msix_entry *msix_entries; 417 int msix_vecs; 418 419 /* DMA tags used throughout the driver adapter for Tx and Rx */ 420 bus_dma_tag_t tx_buf_tag; 421 bus_dma_tag_t rx_buf_tag; 422 int dma_width; 423 424 uint32_t max_mtu; 425 426 uint32_t num_io_queues; 427 uint32_t max_num_io_queues; 428 429 uint32_t requested_tx_ring_size; 430 uint32_t requested_rx_ring_size; 431 432 uint32_t max_tx_ring_size; 433 uint32_t max_rx_ring_size; 434 435 uint16_t max_tx_sgl_size; 436 uint16_t max_rx_sgl_size; 437 438 uint32_t tx_offload_cap; 439 440 uint32_t buf_ring_size; 441 442 /* RSS*/ 443 int first_bind; 444 struct ena_indir *rss_indir; 445 446 uint8_t mac_addr[ETHER_ADDR_LEN]; 447 /* mdio and phy*/ 448 449 ena_state_t flags; 450 451 /* Queue will represent one TX and one RX ring */ 452 struct ena_que que[ENA_MAX_NUM_IO_QUEUES] 453 __aligned(CACHE_LINE_SIZE); 454 455 /* TX */ 456 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 457 __aligned(CACHE_LINE_SIZE); 458 459 /* RX */ 460 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 461 __aligned(CACHE_LINE_SIZE); 462 463 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 464 465 /* Timer service */ 466 struct callout timer_service; 467 sbintime_t keep_alive_timestamp; 468 uint32_t next_monitored_tx_qid; 469 struct task reset_task; 470 struct taskqueue *reset_tq; 471 struct task metrics_task; 472 struct taskqueue *metrics_tq; 473 int wd_active; 474 sbintime_t keep_alive_timeout; 475 sbintime_t missing_tx_timeout; 476 uint32_t missing_tx_max_queues; 477 uint32_t missing_tx_threshold; 478 bool disable_meta_caching; 479 480 uint16_t eni_metrics_sample_interval; 481 uint16_t eni_metrics_sample_interval_cnt; 482 483 /* Statistics */ 484 struct ena_stats_dev dev_stats; 485 struct ena_hw_stats hw_stats; 486 struct ena_admin_eni_stats eni_metrics; 487 488 enum ena_regs_reset_reason_types reset_reason; 489 }; 490 491 #define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx) 492 #define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx) 493 #define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx) 494 #define ENA_RING_MTX_ASSERT(_ring) \ 495 mtx_assert(&(_ring)->ring_mtx, MA_OWNED) 496 497 #define ENA_LOCK_INIT() \ 498 sx_init(&ena_global_lock, "ENA global lock") 499 #define ENA_LOCK_DESTROY() sx_destroy(&ena_global_lock) 500 #define ENA_LOCK_LOCK() sx_xlock(&ena_global_lock) 501 #define ENA_LOCK_UNLOCK() sx_unlock(&ena_global_lock) 502 #define ENA_LOCK_ASSERT() sx_assert(&ena_global_lock, SA_XLOCKED) 503 504 #define ENA_TIMER_INIT(_adapter) \ 505 callout_init(&(_adapter)->timer_service, true) 506 #define ENA_TIMER_DRAIN(_adapter) \ 507 callout_drain(&(_adapter)->timer_service) 508 #define ENA_TIMER_RESET(_adapter) \ 509 callout_reset_sbt(&(_adapter)->timer_service, SBT_1S, SBT_1S, \ 510 ena_timer_service, (void*)(_adapter), 0) 511 512 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 513 #define clamp_val(val, lo, hi) clamp_t(__typeof(val), val, lo, hi) 514 515 extern struct sx ena_global_lock; 516 517 int ena_up(struct ena_adapter *adapter); 518 void ena_down(struct ena_adapter *adapter); 519 int ena_restore_device(struct ena_adapter *adapter); 520 void ena_destroy_device(struct ena_adapter *adapter, bool graceful); 521 int ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num); 522 int ena_update_buf_ring_size(struct ena_adapter *adapter, 523 uint32_t new_buf_ring_size); 524 int ena_update_queue_size(struct ena_adapter *adapter, uint32_t new_tx_size, 525 uint32_t new_rx_size); 526 int ena_update_io_queue_nb(struct ena_adapter *adapter, uint32_t new_num); 527 528 static inline int 529 ena_mbuf_count(struct mbuf *mbuf) 530 { 531 int count = 1; 532 533 while ((mbuf = mbuf->m_next) != NULL) 534 ++count; 535 536 return count; 537 } 538 539 static inline void 540 ena_trigger_reset(struct ena_adapter *adapter, 541 enum ena_regs_reset_reason_types reset_reason) 542 { 543 if (likely(!ENA_FLAG_ISSET(ENA_FLAG_TRIGGER_RESET, adapter))) { 544 adapter->reset_reason = reset_reason; 545 ENA_FLAG_SET_ATOMIC(ENA_FLAG_TRIGGER_RESET, adapter); 546 } 547 } 548 549 static inline void 550 ena_ring_tx_doorbell(struct ena_ring *tx_ring) 551 { 552 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 553 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 554 tx_ring->acum_pkts = 0; 555 } 556 557 #endif /* !(ENA_H) */ 558