1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 * 32 */ 33 34 #ifndef ENA_H 35 #define ENA_H 36 37 #include <sys/types.h> 38 39 #include "ena-com/ena_com.h" 40 #include "ena-com/ena_eth_com.h" 41 42 #define DRV_MODULE_VER_MAJOR 2 43 #define DRV_MODULE_VER_MINOR 2 44 #define DRV_MODULE_VER_SUBMINOR 0 45 46 #define DRV_MODULE_NAME "ena" 47 48 #ifndef DRV_MODULE_VERSION 49 #define DRV_MODULE_VERSION \ 50 __XSTRING(DRV_MODULE_VER_MAJOR) "." \ 51 __XSTRING(DRV_MODULE_VER_MINOR) "." \ 52 __XSTRING(DRV_MODULE_VER_SUBMINOR) 53 #endif 54 #define DEVICE_NAME "Elastic Network Adapter (ENA)" 55 #define DEVICE_DESC "ENA adapter" 56 57 /* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */ 58 #define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL) 59 60 /* 1 for AENQ + ADMIN */ 61 #define ENA_ADMIN_MSIX_VEC 1 62 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues)) 63 64 #define ENA_REG_BAR 0 65 #define ENA_MEM_BAR 2 66 67 #define ENA_BUS_DMA_SEGS 32 68 69 #define ENA_DEFAULT_BUF_RING_SIZE 4096 70 71 #define ENA_DEFAULT_RING_SIZE 1024 72 #define ENA_MIN_RING_SIZE 256 73 74 /* 75 * Refill Rx queue when number of required descriptors is above 76 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET 77 */ 78 #define ENA_RX_REFILL_THRESH_DIVIDER 8 79 #define ENA_RX_REFILL_THRESH_PACKET 256 80 81 #define ENA_IRQNAME_SIZE 40 82 83 #define ENA_PKT_MAX_BUFS 19 84 85 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 86 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 87 88 #define ENA_HASH_KEY_SIZE 40 89 90 #define ENA_MAX_FRAME_LEN 10000 91 #define ENA_MIN_FRAME_LEN 60 92 93 #define ENA_TX_RESUME_THRESH (ENA_PKT_MAX_BUFS + 2) 94 95 #define DB_THRESHOLD 64 96 97 #define TX_COMMIT 32 98 /* 99 * TX budget for cleaning. It should be half of the RX budget to reduce amount 100 * of TCP retransmissions. 101 */ 102 #define TX_BUDGET 128 103 /* RX cleanup budget. -1 stands for infinity. */ 104 #define RX_BUDGET 256 105 /* 106 * How many times we can repeat cleanup in the io irq handling routine if the 107 * RX or TX budget was depleted. 108 */ 109 #define CLEAN_BUDGET 8 110 111 #define RX_IRQ_INTERVAL 20 112 #define TX_IRQ_INTERVAL 50 113 114 #define ENA_MIN_MTU 128 115 116 #define ENA_TSO_MAXSIZE 65536 117 118 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 119 120 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 121 122 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 123 124 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 125 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 126 127 #define ENA_MGMNT_IRQ_IDX 0 128 #define ENA_IO_IRQ_FIRST_IDX 1 129 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 130 131 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3 132 133 /* 134 * ENA device should send keep alive msg every 1 sec. 135 * We wait for 6 sec just to be on the safe side. 136 */ 137 #define DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6) 138 139 /* Time in jiffies before concluding the transmitter is hung. */ 140 #define DEFAULT_TX_CMP_TO (SBT_1S * 5) 141 142 /* Number of queues to check for missing queues per timer tick */ 143 #define DEFAULT_TX_MONITORED_QUEUES (4) 144 145 /* Max number of timeouted packets before device reset */ 146 #define DEFAULT_TX_CMP_THRESHOLD (128) 147 148 /* 149 * Supported PCI vendor and devices IDs 150 */ 151 #define PCI_VENDOR_ID_AMAZON 0x1d0f 152 153 #define PCI_DEV_ID_ENA_PF 0x0ec2 154 #define PCI_DEV_ID_ENA_LLQ_PF 0x1ec2 155 #define PCI_DEV_ID_ENA_VF 0xec20 156 #define PCI_DEV_ID_ENA_LLQ_VF 0xec21 157 158 /* 159 * Flags indicating current ENA driver state 160 */ 161 enum ena_flags_t { 162 ENA_FLAG_DEVICE_RUNNING, 163 ENA_FLAG_DEV_UP, 164 ENA_FLAG_LINK_UP, 165 ENA_FLAG_MSIX_ENABLED, 166 ENA_FLAG_TRIGGER_RESET, 167 ENA_FLAG_ONGOING_RESET, 168 ENA_FLAG_DEV_UP_BEFORE_RESET, 169 ENA_FLAG_RSS_ACTIVE, 170 ENA_FLAGS_NUMBER = ENA_FLAG_RSS_ACTIVE 171 }; 172 173 BITSET_DEFINE(_ena_state, ENA_FLAGS_NUMBER); 174 typedef struct _ena_state ena_state_t; 175 176 #define ENA_FLAG_ZERO(adapter) \ 177 BIT_ZERO(ENA_FLAGS_NUMBER, &(adapter)->flags) 178 #define ENA_FLAG_ISSET(bit, adapter) \ 179 BIT_ISSET(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags) 180 #define ENA_FLAG_SET_ATOMIC(bit, adapter) \ 181 BIT_SET_ATOMIC(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags) 182 #define ENA_FLAG_CLEAR_ATOMIC(bit, adapter) \ 183 BIT_CLR_ATOMIC(ENA_FLAGS_NUMBER, (bit), &(adapter)->flags) 184 185 struct msix_entry { 186 int entry; 187 int vector; 188 }; 189 190 typedef struct _ena_vendor_info_t { 191 uint16_t vendor_id; 192 uint16_t device_id; 193 unsigned int index; 194 } ena_vendor_info_t; 195 196 struct ena_irq { 197 /* Interrupt resources */ 198 struct resource *res; 199 driver_filter_t *handler; 200 void *data; 201 void *cookie; 202 unsigned int vector; 203 bool requested; 204 int cpu; 205 char name[ENA_IRQNAME_SIZE]; 206 }; 207 208 struct ena_que { 209 struct ena_adapter *adapter; 210 struct ena_ring *tx_ring; 211 struct ena_ring *rx_ring; 212 213 struct task cleanup_task; 214 struct taskqueue *cleanup_tq; 215 216 uint32_t id; 217 int cpu; 218 }; 219 220 struct ena_calc_queue_size_ctx { 221 struct ena_com_dev_get_features_ctx *get_feat_ctx; 222 struct ena_com_dev *ena_dev; 223 device_t pdev; 224 uint32_t tx_queue_size; 225 uint32_t rx_queue_size; 226 uint32_t max_tx_queue_size; 227 uint32_t max_rx_queue_size; 228 uint16_t max_tx_sgl_size; 229 uint16_t max_rx_sgl_size; 230 }; 231 232 #ifdef DEV_NETMAP 233 struct ena_netmap_tx_info { 234 uint32_t socket_buf_idx[ENA_PKT_MAX_BUFS]; 235 bus_dmamap_t map_seg[ENA_PKT_MAX_BUFS]; 236 unsigned int sockets_used; 237 }; 238 #endif 239 240 struct ena_tx_buffer { 241 struct mbuf *mbuf; 242 /* # of ena desc for this specific mbuf 243 * (includes data desc and metadata desc) */ 244 unsigned int tx_descs; 245 /* # of buffers used by this mbuf */ 246 unsigned int num_of_bufs; 247 248 bus_dmamap_t dmamap; 249 250 /* Used to detect missing tx packets */ 251 struct bintime timestamp; 252 bool print_once; 253 254 #ifdef DEV_NETMAP 255 struct ena_netmap_tx_info nm_info; 256 #endif /* DEV_NETMAP */ 257 258 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 259 } __aligned(CACHE_LINE_SIZE); 260 261 struct ena_rx_buffer { 262 struct mbuf *mbuf; 263 bus_dmamap_t map; 264 struct ena_com_buf ena_buf; 265 #ifdef DEV_NETMAP 266 uint32_t netmap_buf_idx; 267 #endif /* DEV_NETMAP */ 268 } __aligned(CACHE_LINE_SIZE); 269 270 struct ena_stats_tx { 271 counter_u64_t cnt; 272 counter_u64_t bytes; 273 counter_u64_t prepare_ctx_err; 274 counter_u64_t dma_mapping_err; 275 counter_u64_t doorbells; 276 counter_u64_t missing_tx_comp; 277 counter_u64_t bad_req_id; 278 counter_u64_t collapse; 279 counter_u64_t collapse_err; 280 counter_u64_t queue_wakeup; 281 counter_u64_t queue_stop; 282 counter_u64_t llq_buffer_copy; 283 }; 284 285 struct ena_stats_rx { 286 counter_u64_t cnt; 287 counter_u64_t bytes; 288 counter_u64_t refil_partial; 289 counter_u64_t bad_csum; 290 counter_u64_t mjum_alloc_fail; 291 counter_u64_t mbuf_alloc_fail; 292 counter_u64_t dma_mapping_err; 293 counter_u64_t bad_desc_num; 294 counter_u64_t bad_req_id; 295 counter_u64_t empty_rx_ring; 296 }; 297 298 struct ena_ring { 299 /* Holds the empty requests for TX/RX out of order completions */ 300 union { 301 uint16_t *free_tx_ids; 302 uint16_t *free_rx_ids; 303 }; 304 struct ena_com_dev *ena_dev; 305 struct ena_adapter *adapter; 306 struct ena_com_io_cq *ena_com_io_cq; 307 struct ena_com_io_sq *ena_com_io_sq; 308 309 uint16_t qid; 310 311 /* Determines if device will use LLQ or normal mode for TX */ 312 enum ena_admin_placement_policy_type tx_mem_queue_type; 313 union { 314 /* The maximum length the driver can push to the device (For LLQ) */ 315 uint8_t tx_max_header_size; 316 /* The maximum (and default) mbuf size for the Rx descriptor. */ 317 uint16_t rx_mbuf_sz; 318 319 }; 320 321 bool first_interrupt; 322 uint16_t no_interrupt_event_cnt; 323 324 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 325 326 struct ena_que *que; 327 struct lro_ctrl lro; 328 329 uint16_t next_to_use; 330 uint16_t next_to_clean; 331 332 union { 333 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 334 struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */ 335 }; 336 int ring_size; /* number of tx/rx_buffer_info's entries */ 337 338 struct buf_ring *br; /* only for TX */ 339 uint32_t buf_ring_size; 340 341 struct mtx ring_mtx; 342 char mtx_name[16]; 343 344 struct { 345 struct task enqueue_task; 346 struct taskqueue *enqueue_tq; 347 }; 348 349 union { 350 struct ena_stats_tx tx_stats; 351 struct ena_stats_rx rx_stats; 352 }; 353 354 union { 355 int empty_rx_queue; 356 /* For Tx ring to indicate if it's running or not */ 357 bool running; 358 }; 359 360 /* How many packets are sent in one Tx loop, used for doorbells */ 361 uint32_t acum_pkts; 362 363 /* Used for LLQ */ 364 uint8_t *push_buf_intermediate_buf; 365 366 #ifdef DEV_NETMAP 367 bool initialized; 368 #endif /* DEV_NETMAP */ 369 } __aligned(CACHE_LINE_SIZE); 370 371 struct ena_stats_dev { 372 counter_u64_t wd_expired; 373 counter_u64_t interface_up; 374 counter_u64_t interface_down; 375 counter_u64_t admin_q_pause; 376 }; 377 378 struct ena_hw_stats { 379 counter_u64_t rx_packets; 380 counter_u64_t tx_packets; 381 382 counter_u64_t rx_bytes; 383 counter_u64_t tx_bytes; 384 385 counter_u64_t rx_drops; 386 counter_u64_t tx_drops; 387 }; 388 389 /* Board specific private data structure */ 390 struct ena_adapter { 391 struct ena_com_dev *ena_dev; 392 393 /* OS defined structs */ 394 if_t ifp; 395 device_t pdev; 396 struct ifmedia media; 397 398 /* OS resources */ 399 struct resource *memory; 400 struct resource *registers; 401 402 struct sx global_lock; 403 404 /* MSI-X */ 405 struct msix_entry *msix_entries; 406 int msix_vecs; 407 408 /* DMA tags used throughout the driver adapter for Tx and Rx */ 409 bus_dma_tag_t tx_buf_tag; 410 bus_dma_tag_t rx_buf_tag; 411 int dma_width; 412 413 uint32_t max_mtu; 414 415 uint32_t num_io_queues; 416 uint32_t max_num_io_queues; 417 418 uint32_t requested_tx_ring_size; 419 uint32_t requested_rx_ring_size; 420 421 uint32_t max_tx_ring_size; 422 uint32_t max_rx_ring_size; 423 424 uint16_t max_tx_sgl_size; 425 uint16_t max_rx_sgl_size; 426 427 uint32_t tx_offload_cap; 428 429 uint32_t buf_ring_size; 430 431 /* RSS*/ 432 uint8_t rss_ind_tbl[ENA_RX_RSS_TABLE_SIZE]; 433 434 uint8_t mac_addr[ETHER_ADDR_LEN]; 435 /* mdio and phy*/ 436 437 ena_state_t flags; 438 439 /* Queue will represent one TX and one RX ring */ 440 struct ena_que que[ENA_MAX_NUM_IO_QUEUES] 441 __aligned(CACHE_LINE_SIZE); 442 443 /* TX */ 444 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 445 __aligned(CACHE_LINE_SIZE); 446 447 /* RX */ 448 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 449 __aligned(CACHE_LINE_SIZE); 450 451 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 452 453 /* Timer service */ 454 struct callout timer_service; 455 sbintime_t keep_alive_timestamp; 456 uint32_t next_monitored_tx_qid; 457 struct task reset_task; 458 struct taskqueue *reset_tq; 459 int wd_active; 460 sbintime_t keep_alive_timeout; 461 sbintime_t missing_tx_timeout; 462 uint32_t missing_tx_max_queues; 463 uint32_t missing_tx_threshold; 464 bool disable_meta_caching; 465 466 /* Statistics */ 467 struct ena_stats_dev dev_stats; 468 struct ena_hw_stats hw_stats; 469 470 enum ena_regs_reset_reason_types reset_reason; 471 }; 472 473 #define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx) 474 #define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx) 475 #define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx) 476 477 #define ENA_LOCK_INIT(adapter) \ 478 sx_init(&(adapter)->global_lock, "ENA global lock") 479 #define ENA_LOCK_DESTROY(adapter) sx_destroy(&(adapter)->global_lock) 480 #define ENA_LOCK_LOCK(adapter) sx_xlock(&(adapter)->global_lock) 481 #define ENA_LOCK_UNLOCK(adapter) sx_unlock(&(adapter)->global_lock) 482 483 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 484 #define clamp_val(val, lo, hi) clamp_t(__typeof(val), val, lo, hi) 485 486 static inline int ena_mbuf_count(struct mbuf *mbuf) 487 { 488 int count = 1; 489 490 while ((mbuf = mbuf->m_next) != NULL) 491 ++count; 492 493 return count; 494 } 495 496 int ena_up(struct ena_adapter *adapter); 497 void ena_down(struct ena_adapter *adapter); 498 int ena_restore_device(struct ena_adapter *adapter); 499 void ena_destroy_device(struct ena_adapter *adapter, bool graceful); 500 int ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num); 501 int ena_update_buf_ring_size(struct ena_adapter *adapter, 502 uint32_t new_buf_ring_size); 503 int ena_update_queue_size(struct ena_adapter *adapter, uint32_t new_tx_size, 504 uint32_t new_rx_size); 505 int ena_update_io_queue_nb(struct ena_adapter *adapter, uint32_t new_num); 506 507 static inline void 508 ena_trigger_reset(struct ena_adapter *adapter, 509 enum ena_regs_reset_reason_types reset_reason) 510 { 511 if (likely(!ENA_FLAG_ISSET(ENA_FLAG_TRIGGER_RESET, adapter))) { 512 adapter->reset_reason = reset_reason; 513 ENA_FLAG_SET_ATOMIC(ENA_FLAG_TRIGGER_RESET, adapter); 514 } 515 } 516 517 static inline int 518 validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 519 { 520 if (likely(req_id < rx_ring->ring_size)) 521 return (0); 522 523 device_printf(rx_ring->adapter->pdev, "Invalid rx req_id: %hu\n", 524 req_id); 525 counter_u64_add(rx_ring->rx_stats.bad_req_id, 1); 526 527 /* Trigger device reset */ 528 ena_trigger_reset(rx_ring->adapter, ENA_REGS_RESET_INV_RX_REQ_ID); 529 530 return (EFAULT); 531 } 532 533 #endif /* !(ENA_H) */ 534