1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_rss.h" 34 #include "ena.h" 35 #include "ena_datapath.h" 36 #ifdef DEV_NETMAP 37 #include "ena_netmap.h" 38 #endif /* DEV_NETMAP */ 39 40 /********************************************************************* 41 * Static functions prototypes 42 *********************************************************************/ 43 44 static int ena_tx_cleanup(struct ena_ring *); 45 static int ena_rx_cleanup(struct ena_ring *); 46 static inline int validate_tx_req_id(struct ena_ring *, uint16_t); 47 static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *, 48 struct mbuf *); 49 static struct mbuf* ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *, 50 struct ena_com_rx_ctx *, uint16_t *); 51 static inline void ena_rx_checksum(struct ena_ring *, struct ena_com_rx_ctx *, 52 struct mbuf *); 53 static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *, bool); 54 static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, 55 struct mbuf **mbuf); 56 static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **); 57 static void ena_start_xmit(struct ena_ring *); 58 59 /********************************************************************* 60 * Global functions 61 *********************************************************************/ 62 63 void 64 ena_cleanup(void *arg, int pending) 65 { 66 struct ena_que *que = arg; 67 struct ena_adapter *adapter = que->adapter; 68 if_t ifp = adapter->ifp; 69 struct ena_ring *tx_ring; 70 struct ena_ring *rx_ring; 71 struct ena_com_io_cq* io_cq; 72 struct ena_eth_io_intr_reg intr_reg; 73 int qid, ena_qid; 74 int txc, rxc, i; 75 76 if (unlikely((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)) 77 return; 78 79 ena_trace(ENA_DBG, "MSI-X TX/RX routine\n"); 80 81 tx_ring = que->tx_ring; 82 rx_ring = que->rx_ring; 83 qid = que->id; 84 ena_qid = ENA_IO_TXQ_IDX(qid); 85 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 86 87 tx_ring->first_interrupt = true; 88 rx_ring->first_interrupt = true; 89 90 for (i = 0; i < CLEAN_BUDGET; ++i) { 91 rxc = ena_rx_cleanup(rx_ring); 92 txc = ena_tx_cleanup(tx_ring); 93 94 if (unlikely((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)) 95 return; 96 97 if ((txc != TX_BUDGET) && (rxc != RX_BUDGET)) 98 break; 99 } 100 101 /* Signal that work is done and unmask interrupt */ 102 ena_com_update_intr_reg(&intr_reg, 103 RX_IRQ_INTERVAL, 104 TX_IRQ_INTERVAL, 105 true); 106 ena_com_unmask_intr(io_cq, &intr_reg); 107 } 108 109 void 110 ena_deferred_mq_start(void *arg, int pending) 111 { 112 struct ena_ring *tx_ring = (struct ena_ring *)arg; 113 struct ifnet *ifp = tx_ring->adapter->ifp; 114 115 while (!drbr_empty(ifp, tx_ring->br) && 116 tx_ring->running && 117 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 118 ENA_RING_MTX_LOCK(tx_ring); 119 ena_start_xmit(tx_ring); 120 ENA_RING_MTX_UNLOCK(tx_ring); 121 } 122 } 123 124 int 125 ena_mq_start(if_t ifp, struct mbuf *m) 126 { 127 struct ena_adapter *adapter = ifp->if_softc; 128 struct ena_ring *tx_ring; 129 int ret, is_drbr_empty; 130 uint32_t i; 131 132 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) == 0)) 133 return (ENODEV); 134 135 /* Which queue to use */ 136 /* 137 * If everything is setup correctly, it should be the 138 * same bucket that the current CPU we're on is. 139 * It should improve performance. 140 */ 141 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { 142 i = m->m_pkthdr.flowid % adapter->num_io_queues; 143 } else { 144 i = curcpu % adapter->num_io_queues; 145 } 146 tx_ring = &adapter->tx_ring[i]; 147 148 /* Check if drbr is empty before putting packet */ 149 is_drbr_empty = drbr_empty(ifp, tx_ring->br); 150 ret = drbr_enqueue(ifp, tx_ring->br, m); 151 if (unlikely(ret != 0)) { 152 taskqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 153 return (ret); 154 } 155 156 if (is_drbr_empty && (ENA_RING_MTX_TRYLOCK(tx_ring) != 0)) { 157 ena_start_xmit(tx_ring); 158 ENA_RING_MTX_UNLOCK(tx_ring); 159 } else { 160 taskqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 161 } 162 163 return (0); 164 } 165 166 void 167 ena_qflush(if_t ifp) 168 { 169 struct ena_adapter *adapter = ifp->if_softc; 170 struct ena_ring *tx_ring = adapter->tx_ring; 171 int i; 172 173 for(i = 0; i < adapter->num_io_queues; ++i, ++tx_ring) 174 if (!drbr_empty(ifp, tx_ring->br)) { 175 ENA_RING_MTX_LOCK(tx_ring); 176 drbr_flush(ifp, tx_ring->br); 177 ENA_RING_MTX_UNLOCK(tx_ring); 178 } 179 180 if_qflush(ifp); 181 } 182 183 /********************************************************************* 184 * Static functions 185 *********************************************************************/ 186 187 static inline int 188 validate_tx_req_id(struct ena_ring *tx_ring, uint16_t req_id) 189 { 190 struct ena_adapter *adapter = tx_ring->adapter; 191 struct ena_tx_buffer *tx_info = NULL; 192 193 if (likely(req_id < tx_ring->ring_size)) { 194 tx_info = &tx_ring->tx_buffer_info[req_id]; 195 if (tx_info->mbuf != NULL) 196 return (0); 197 device_printf(adapter->pdev, 198 "tx_info doesn't have valid mbuf\n"); 199 } 200 201 device_printf(adapter->pdev, "Invalid req_id: %hu\n", req_id); 202 counter_u64_add(tx_ring->tx_stats.bad_req_id, 1); 203 204 /* Trigger device reset */ 205 ena_trigger_reset(adapter, ENA_REGS_RESET_INV_TX_REQ_ID); 206 207 return (EFAULT); 208 } 209 210 /** 211 * ena_tx_cleanup - clear sent packets and corresponding descriptors 212 * @tx_ring: ring for which we want to clean packets 213 * 214 * Once packets are sent, we ask the device in a loop for no longer used 215 * descriptors. We find the related mbuf chain in a map (index in an array) 216 * and free it, then update ring state. 217 * This is performed in "endless" loop, updating ring pointers every 218 * TX_COMMIT. The first check of free descriptor is performed before the actual 219 * loop, then repeated at the loop end. 220 **/ 221 static int 222 ena_tx_cleanup(struct ena_ring *tx_ring) 223 { 224 struct ena_adapter *adapter; 225 struct ena_com_io_cq* io_cq; 226 uint16_t next_to_clean; 227 uint16_t req_id; 228 uint16_t ena_qid; 229 unsigned int total_done = 0; 230 int rc; 231 int commit = TX_COMMIT; 232 int budget = TX_BUDGET; 233 int work_done; 234 bool above_thresh; 235 236 adapter = tx_ring->que->adapter; 237 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 238 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 239 next_to_clean = tx_ring->next_to_clean; 240 241 #ifdef DEV_NETMAP 242 if (netmap_tx_irq(adapter->ifp, tx_ring->qid) != NM_IRQ_PASS) 243 return (0); 244 #endif /* DEV_NETMAP */ 245 246 do { 247 struct ena_tx_buffer *tx_info; 248 struct mbuf *mbuf; 249 250 rc = ena_com_tx_comp_req_id_get(io_cq, &req_id); 251 if (unlikely(rc != 0)) 252 break; 253 254 rc = validate_tx_req_id(tx_ring, req_id); 255 if (unlikely(rc != 0)) 256 break; 257 258 tx_info = &tx_ring->tx_buffer_info[req_id]; 259 260 mbuf = tx_info->mbuf; 261 262 tx_info->mbuf = NULL; 263 bintime_clear(&tx_info->timestamp); 264 265 bus_dmamap_sync(adapter->tx_buf_tag, tx_info->dmamap, 266 BUS_DMASYNC_POSTWRITE); 267 bus_dmamap_unload(adapter->tx_buf_tag, 268 tx_info->dmamap); 269 270 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d mbuf %p completed\n", 271 tx_ring->qid, mbuf); 272 273 m_freem(mbuf); 274 275 total_done += tx_info->tx_descs; 276 277 tx_ring->free_tx_ids[next_to_clean] = req_id; 278 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean, 279 tx_ring->ring_size); 280 281 if (unlikely(--commit == 0)) { 282 commit = TX_COMMIT; 283 /* update ring state every TX_COMMIT descriptor */ 284 tx_ring->next_to_clean = next_to_clean; 285 ena_com_comp_ack( 286 &adapter->ena_dev->io_sq_queues[ena_qid], 287 total_done); 288 ena_com_update_dev_comp_head(io_cq); 289 total_done = 0; 290 } 291 } while (likely(--budget)); 292 293 work_done = TX_BUDGET - budget; 294 295 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d done. total pkts: %d\n", 296 tx_ring->qid, work_done); 297 298 /* If there is still something to commit update ring state */ 299 if (likely(commit != TX_COMMIT)) { 300 tx_ring->next_to_clean = next_to_clean; 301 ena_com_comp_ack(&adapter->ena_dev->io_sq_queues[ena_qid], 302 total_done); 303 ena_com_update_dev_comp_head(io_cq); 304 } 305 306 /* 307 * Need to make the rings circular update visible to 308 * ena_xmit_mbuf() before checking for tx_ring->running. 309 */ 310 mb(); 311 312 above_thresh = ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 313 ENA_TX_RESUME_THRESH); 314 if (unlikely(!tx_ring->running && above_thresh)) { 315 ENA_RING_MTX_LOCK(tx_ring); 316 above_thresh = 317 ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 318 ENA_TX_RESUME_THRESH); 319 if (!tx_ring->running && above_thresh) { 320 tx_ring->running = true; 321 counter_u64_add(tx_ring->tx_stats.queue_wakeup, 1); 322 taskqueue_enqueue(tx_ring->enqueue_tq, 323 &tx_ring->enqueue_task); 324 } 325 ENA_RING_MTX_UNLOCK(tx_ring); 326 } 327 328 return (work_done); 329 } 330 331 static void 332 ena_rx_hash_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 333 struct mbuf *mbuf) 334 { 335 struct ena_adapter *adapter = rx_ring->adapter; 336 337 if (likely(ENA_FLAG_ISSET(ENA_FLAG_RSS_ACTIVE, adapter))) { 338 mbuf->m_pkthdr.flowid = ena_rx_ctx->hash; 339 340 #ifdef RSS 341 /* 342 * Hardware and software RSS are in agreement only when both are 343 * configured to Toeplitz algorithm. This driver configures 344 * that algorithm only when software RSS is enabled and uses it. 345 */ 346 if (adapter->ena_dev->rss.hash_func != ENA_ADMIN_TOEPLITZ && 347 ena_rx_ctx->l3_proto != ENA_ETH_IO_L3_PROTO_UNKNOWN) { 348 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 349 return; 350 } 351 #endif 352 353 if (ena_rx_ctx->frag && 354 (ena_rx_ctx->l3_proto != ENA_ETH_IO_L3_PROTO_UNKNOWN)) { 355 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 356 return; 357 } 358 359 switch (ena_rx_ctx->l3_proto) { 360 case ENA_ETH_IO_L3_PROTO_IPV4: 361 switch (ena_rx_ctx->l4_proto) { 362 case ENA_ETH_IO_L4_PROTO_TCP: 363 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV4); 364 break; 365 case ENA_ETH_IO_L4_PROTO_UDP: 366 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV4); 367 break; 368 default: 369 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV4); 370 } 371 break; 372 case ENA_ETH_IO_L3_PROTO_IPV6: 373 switch (ena_rx_ctx->l4_proto) { 374 case ENA_ETH_IO_L4_PROTO_TCP: 375 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV6); 376 break; 377 case ENA_ETH_IO_L4_PROTO_UDP: 378 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV6); 379 break; 380 default: 381 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV6); 382 } 383 break; 384 case ENA_ETH_IO_L3_PROTO_UNKNOWN: 385 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 386 break; 387 default: 388 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 389 } 390 } else { 391 mbuf->m_pkthdr.flowid = rx_ring->qid; 392 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 393 } 394 } 395 396 /** 397 * ena_rx_mbuf - assemble mbuf from descriptors 398 * @rx_ring: ring for which we want to clean packets 399 * @ena_bufs: buffer info 400 * @ena_rx_ctx: metadata for this packet(s) 401 * @next_to_clean: ring pointer, will be updated only upon success 402 * 403 **/ 404 static struct mbuf* 405 ena_rx_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_buf_info *ena_bufs, 406 struct ena_com_rx_ctx *ena_rx_ctx, uint16_t *next_to_clean) 407 { 408 struct mbuf *mbuf; 409 struct ena_rx_buffer *rx_info; 410 struct ena_adapter *adapter; 411 unsigned int descs = ena_rx_ctx->descs; 412 int rc; 413 uint16_t ntc, len, req_id, buf = 0; 414 415 ntc = *next_to_clean; 416 adapter = rx_ring->adapter; 417 418 len = ena_bufs[buf].len; 419 req_id = ena_bufs[buf].req_id; 420 rc = validate_rx_req_id(rx_ring, req_id); 421 if (unlikely(rc != 0)) 422 return (NULL); 423 424 rx_info = &rx_ring->rx_buffer_info[req_id]; 425 if (unlikely(rx_info->mbuf == NULL)) { 426 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 427 return (NULL); 428 } 429 430 ena_trace(ENA_DBG | ENA_RXPTH, "rx_info %p, mbuf %p, paddr %jx\n", 431 rx_info, rx_info->mbuf, (uintmax_t)rx_info->ena_buf.paddr); 432 433 bus_dmamap_sync(adapter->rx_buf_tag, rx_info->map, 434 BUS_DMASYNC_POSTREAD); 435 mbuf = rx_info->mbuf; 436 mbuf->m_flags |= M_PKTHDR; 437 mbuf->m_pkthdr.len = len; 438 mbuf->m_len = len; 439 mbuf->m_pkthdr.rcvif = rx_ring->que->adapter->ifp; 440 441 /* Fill mbuf with hash key and it's interpretation for optimization */ 442 ena_rx_hash_mbuf(rx_ring, ena_rx_ctx, mbuf); 443 444 ena_trace(ENA_DBG | ENA_RXPTH, "rx mbuf 0x%p, flags=0x%x, len: %d\n", 445 mbuf, mbuf->m_flags, mbuf->m_pkthdr.len); 446 447 /* DMA address is not needed anymore, unmap it */ 448 bus_dmamap_unload(rx_ring->adapter->rx_buf_tag, rx_info->map); 449 450 rx_info->mbuf = NULL; 451 rx_ring->free_rx_ids[ntc] = req_id; 452 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 453 454 /* 455 * While we have more than 1 descriptors for one rcvd packet, append 456 * other mbufs to the main one 457 */ 458 while (--descs) { 459 ++buf; 460 len = ena_bufs[buf].len; 461 req_id = ena_bufs[buf].req_id; 462 rc = validate_rx_req_id(rx_ring, req_id); 463 if (unlikely(rc != 0)) { 464 /* 465 * If the req_id is invalid, then the device will be 466 * reset. In that case we must free all mbufs that 467 * were already gathered. 468 */ 469 m_freem(mbuf); 470 return (NULL); 471 } 472 rx_info = &rx_ring->rx_buffer_info[req_id]; 473 474 if (unlikely(rx_info->mbuf == NULL)) { 475 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 476 /* 477 * If one of the required mbufs was not allocated yet, 478 * we can break there. 479 * All earlier used descriptors will be reallocated 480 * later and not used mbufs can be reused. 481 * The next_to_clean pointer will not be updated in case 482 * of an error, so caller should advance it manually 483 * in error handling routine to keep it up to date 484 * with hw ring. 485 */ 486 m_freem(mbuf); 487 return (NULL); 488 } 489 490 bus_dmamap_sync(adapter->rx_buf_tag, rx_info->map, 491 BUS_DMASYNC_POSTREAD); 492 if (unlikely(m_append(mbuf, len, rx_info->mbuf->m_data) == 0)) { 493 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 494 ena_trace(ENA_WARNING, "Failed to append Rx mbuf %p\n", 495 mbuf); 496 } 497 498 ena_trace(ENA_DBG | ENA_RXPTH, 499 "rx mbuf updated. len %d\n", mbuf->m_pkthdr.len); 500 501 /* Free already appended mbuf, it won't be useful anymore */ 502 bus_dmamap_unload(rx_ring->adapter->rx_buf_tag, rx_info->map); 503 m_freem(rx_info->mbuf); 504 rx_info->mbuf = NULL; 505 506 rx_ring->free_rx_ids[ntc] = req_id; 507 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 508 } 509 510 *next_to_clean = ntc; 511 512 return (mbuf); 513 } 514 515 /** 516 * ena_rx_checksum - indicate in mbuf if hw indicated a good cksum 517 **/ 518 static inline void 519 ena_rx_checksum(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 520 struct mbuf *mbuf) 521 { 522 523 /* if IP and error */ 524 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) && 525 ena_rx_ctx->l3_csum_err)) { 526 /* ipv4 checksum error */ 527 mbuf->m_pkthdr.csum_flags = 0; 528 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 529 ena_trace(ENA_DBG, "RX IPv4 header checksum error\n"); 530 return; 531 } 532 533 /* if TCP/UDP */ 534 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 535 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 536 if (ena_rx_ctx->l4_csum_err) { 537 /* TCP/UDP checksum error */ 538 mbuf->m_pkthdr.csum_flags = 0; 539 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 540 ena_trace(ENA_DBG, "RX L4 checksum error\n"); 541 } else { 542 mbuf->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 543 mbuf->m_pkthdr.csum_flags |= CSUM_IP_VALID; 544 } 545 } 546 } 547 548 /** 549 * ena_rx_cleanup - handle rx irq 550 * @arg: ring for which irq is being handled 551 **/ 552 static int 553 ena_rx_cleanup(struct ena_ring *rx_ring) 554 { 555 struct ena_adapter *adapter; 556 struct mbuf *mbuf; 557 struct ena_com_rx_ctx ena_rx_ctx; 558 struct ena_com_io_cq* io_cq; 559 struct ena_com_io_sq* io_sq; 560 if_t ifp; 561 uint16_t ena_qid; 562 uint16_t next_to_clean; 563 uint32_t refill_required; 564 uint32_t refill_threshold; 565 uint32_t do_if_input = 0; 566 unsigned int qid; 567 int rc, i; 568 int budget = RX_BUDGET; 569 #ifdef DEV_NETMAP 570 int done; 571 #endif /* DEV_NETMAP */ 572 573 adapter = rx_ring->que->adapter; 574 ifp = adapter->ifp; 575 qid = rx_ring->que->id; 576 ena_qid = ENA_IO_RXQ_IDX(qid); 577 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 578 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 579 next_to_clean = rx_ring->next_to_clean; 580 581 #ifdef DEV_NETMAP 582 if (netmap_rx_irq(adapter->ifp, rx_ring->qid, &done) != NM_IRQ_PASS) 583 return (0); 584 #endif /* DEV_NETMAP */ 585 586 ena_trace(ENA_DBG, "rx: qid %d\n", qid); 587 588 do { 589 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 590 ena_rx_ctx.max_bufs = adapter->max_rx_sgl_size; 591 ena_rx_ctx.descs = 0; 592 bus_dmamap_sync(io_cq->cdesc_addr.mem_handle.tag, 593 io_cq->cdesc_addr.mem_handle.map, BUS_DMASYNC_POSTREAD); 594 rc = ena_com_rx_pkt(io_cq, io_sq, &ena_rx_ctx); 595 596 if (unlikely(rc != 0)) 597 goto error; 598 599 if (unlikely(ena_rx_ctx.descs == 0)) 600 break; 601 602 ena_trace(ENA_DBG | ENA_RXPTH, "rx: q %d got packet from ena. " 603 "descs #: %d l3 proto %d l4 proto %d hash: %x\n", 604 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto, 605 ena_rx_ctx.l4_proto, ena_rx_ctx.hash); 606 607 /* Receive mbuf from the ring */ 608 mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs, 609 &ena_rx_ctx, &next_to_clean); 610 bus_dmamap_sync(io_cq->cdesc_addr.mem_handle.tag, 611 io_cq->cdesc_addr.mem_handle.map, BUS_DMASYNC_PREREAD); 612 /* Exit if we failed to retrieve a buffer */ 613 if (unlikely(mbuf == NULL)) { 614 for (i = 0; i < ena_rx_ctx.descs; ++i) { 615 rx_ring->free_rx_ids[next_to_clean] = 616 rx_ring->ena_bufs[i].req_id; 617 next_to_clean = 618 ENA_RX_RING_IDX_NEXT(next_to_clean, 619 rx_ring->ring_size); 620 621 } 622 break; 623 } 624 625 if (((ifp->if_capenable & IFCAP_RXCSUM) != 0) || 626 ((ifp->if_capenable & IFCAP_RXCSUM_IPV6) != 0)) { 627 ena_rx_checksum(rx_ring, &ena_rx_ctx, mbuf); 628 } 629 630 counter_enter(); 631 counter_u64_add_protected(rx_ring->rx_stats.bytes, 632 mbuf->m_pkthdr.len); 633 counter_u64_add_protected(adapter->hw_stats.rx_bytes, 634 mbuf->m_pkthdr.len); 635 counter_exit(); 636 /* 637 * LRO is only for IP/TCP packets and TCP checksum of the packet 638 * should be computed by hardware. 639 */ 640 do_if_input = 1; 641 if (((ifp->if_capenable & IFCAP_LRO) != 0) && 642 ((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) && 643 (ena_rx_ctx.l4_proto == ENA_ETH_IO_L4_PROTO_TCP)) { 644 /* 645 * Send to the stack if: 646 * - LRO not enabled, or 647 * - no LRO resources, or 648 * - lro enqueue fails 649 */ 650 if ((rx_ring->lro.lro_cnt != 0) && 651 (tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0)) 652 do_if_input = 0; 653 } 654 if (do_if_input != 0) { 655 ena_trace(ENA_DBG | ENA_RXPTH, 656 "calling if_input() with mbuf %p\n", mbuf); 657 (*ifp->if_input)(ifp, mbuf); 658 } 659 660 counter_enter(); 661 counter_u64_add_protected(rx_ring->rx_stats.cnt, 1); 662 counter_u64_add_protected(adapter->hw_stats.rx_packets, 1); 663 counter_exit(); 664 } while (--budget); 665 666 rx_ring->next_to_clean = next_to_clean; 667 668 refill_required = ena_com_free_q_entries(io_sq); 669 refill_threshold = min_t(int, 670 rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER, 671 ENA_RX_REFILL_THRESH_PACKET); 672 673 if (refill_required > refill_threshold) { 674 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 675 ena_refill_rx_bufs(rx_ring, refill_required); 676 } 677 678 tcp_lro_flush_all(&rx_ring->lro); 679 680 return (RX_BUDGET - budget); 681 682 error: 683 counter_u64_add(rx_ring->rx_stats.bad_desc_num, 1); 684 685 /* Too many desc from the device. Trigger reset */ 686 ena_trigger_reset(adapter, ENA_REGS_RESET_TOO_MANY_RX_DESCS); 687 688 return (0); 689 } 690 691 static void 692 ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct mbuf *mbuf, 693 bool disable_meta_caching) 694 { 695 struct ena_com_tx_meta *ena_meta; 696 struct ether_vlan_header *eh; 697 struct mbuf *mbuf_next; 698 u32 mss; 699 bool offload; 700 uint16_t etype; 701 int ehdrlen; 702 struct ip *ip; 703 int iphlen; 704 struct tcphdr *th; 705 int offset; 706 707 offload = false; 708 ena_meta = &ena_tx_ctx->ena_meta; 709 mss = mbuf->m_pkthdr.tso_segsz; 710 711 if (mss != 0) 712 offload = true; 713 714 if ((mbuf->m_pkthdr.csum_flags & CSUM_TSO) != 0) 715 offload = true; 716 717 if ((mbuf->m_pkthdr.csum_flags & CSUM_OFFLOAD) != 0) 718 offload = true; 719 720 if (!offload) { 721 if (disable_meta_caching) { 722 memset(ena_meta, 0, sizeof(*ena_meta)); 723 ena_tx_ctx->meta_valid = 1; 724 } else { 725 ena_tx_ctx->meta_valid = 0; 726 } 727 return; 728 } 729 730 /* Determine where frame payload starts. */ 731 eh = mtod(mbuf, struct ether_vlan_header *); 732 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 733 etype = ntohs(eh->evl_proto); 734 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 735 } else { 736 etype = ntohs(eh->evl_encap_proto); 737 ehdrlen = ETHER_HDR_LEN; 738 } 739 740 mbuf_next = m_getptr(mbuf, ehdrlen, &offset); 741 ip = (struct ip *)(mtodo(mbuf_next, offset)); 742 iphlen = ip->ip_hl << 2; 743 744 mbuf_next = m_getptr(mbuf, iphlen + ehdrlen, &offset); 745 th = (struct tcphdr *)(mtodo(mbuf_next, offset)); 746 747 if ((mbuf->m_pkthdr.csum_flags & CSUM_IP) != 0) { 748 ena_tx_ctx->l3_csum_enable = 1; 749 } 750 if ((mbuf->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 751 ena_tx_ctx->tso_enable = 1; 752 ena_meta->l4_hdr_len = (th->th_off); 753 } 754 755 switch (etype) { 756 case ETHERTYPE_IP: 757 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 758 if ((ip->ip_off & htons(IP_DF)) != 0) 759 ena_tx_ctx->df = 1; 760 break; 761 case ETHERTYPE_IPV6: 762 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 763 764 default: 765 break; 766 } 767 768 if (ip->ip_p == IPPROTO_TCP) { 769 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 770 if ((mbuf->m_pkthdr.csum_flags & 771 (CSUM_IP_TCP | CSUM_IP6_TCP)) != 0) 772 ena_tx_ctx->l4_csum_enable = 1; 773 else 774 ena_tx_ctx->l4_csum_enable = 0; 775 } else if (ip->ip_p == IPPROTO_UDP) { 776 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 777 if ((mbuf->m_pkthdr.csum_flags & 778 (CSUM_IP_UDP | CSUM_IP6_UDP)) != 0) 779 ena_tx_ctx->l4_csum_enable = 1; 780 else 781 ena_tx_ctx->l4_csum_enable = 0; 782 } else { 783 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 784 ena_tx_ctx->l4_csum_enable = 0; 785 } 786 787 ena_meta->mss = mss; 788 ena_meta->l3_hdr_len = iphlen; 789 ena_meta->l3_hdr_offset = ehdrlen; 790 ena_tx_ctx->meta_valid = 1; 791 } 792 793 static int 794 ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 795 { 796 struct ena_adapter *adapter; 797 struct mbuf *collapsed_mbuf; 798 int num_frags; 799 800 adapter = tx_ring->adapter; 801 num_frags = ena_mbuf_count(*mbuf); 802 803 /* One segment must be reserved for configuration descriptor. */ 804 if (num_frags < adapter->max_tx_sgl_size) 805 return (0); 806 counter_u64_add(tx_ring->tx_stats.collapse, 1); 807 808 collapsed_mbuf = m_collapse(*mbuf, M_NOWAIT, 809 adapter->max_tx_sgl_size - 1); 810 if (unlikely(collapsed_mbuf == NULL)) { 811 counter_u64_add(tx_ring->tx_stats.collapse_err, 1); 812 return (ENOMEM); 813 } 814 815 /* If mbuf was collapsed succesfully, original mbuf is released. */ 816 *mbuf = collapsed_mbuf; 817 818 return (0); 819 } 820 821 static int 822 ena_tx_map_mbuf(struct ena_ring *tx_ring, struct ena_tx_buffer *tx_info, 823 struct mbuf *mbuf, void **push_hdr, u16 *header_len) 824 { 825 struct ena_adapter *adapter = tx_ring->adapter; 826 struct ena_com_buf *ena_buf; 827 bus_dma_segment_t segs[ENA_BUS_DMA_SEGS]; 828 size_t iseg = 0; 829 uint32_t mbuf_head_len; 830 uint16_t offset; 831 int rc, nsegs; 832 833 mbuf_head_len = mbuf->m_len; 834 tx_info->mbuf = mbuf; 835 ena_buf = tx_info->bufs; 836 837 /* 838 * For easier maintaining of the DMA map, map the whole mbuf even if 839 * the LLQ is used. The descriptors will be filled using the segments. 840 */ 841 rc = bus_dmamap_load_mbuf_sg(adapter->tx_buf_tag, tx_info->dmamap, mbuf, 842 segs, &nsegs, BUS_DMA_NOWAIT); 843 if (unlikely((rc != 0) || (nsegs == 0))) { 844 ena_trace(ENA_WARNING, 845 "dmamap load failed! err: %d nsegs: %d\n", rc, nsegs); 846 goto dma_error; 847 } 848 849 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 850 /* 851 * When the device is LLQ mode, the driver will copy 852 * the header into the device memory space. 853 * the ena_com layer assumes the header is in a linear 854 * memory space. 855 * This assumption might be wrong since part of the header 856 * can be in the fragmented buffers. 857 * First check if header fits in the mbuf. If not, copy it to 858 * separate buffer that will be holding linearized data. 859 */ 860 *header_len = min_t(uint32_t, mbuf->m_pkthdr.len, tx_ring->tx_max_header_size); 861 862 /* If header is in linear space, just point into mbuf's data. */ 863 if (likely(*header_len <= mbuf_head_len)) { 864 *push_hdr = mbuf->m_data; 865 /* 866 * Otherwise, copy whole portion of header from multiple mbufs 867 * to intermediate buffer. 868 */ 869 } else { 870 m_copydata(mbuf, 0, *header_len, tx_ring->push_buf_intermediate_buf); 871 *push_hdr = tx_ring->push_buf_intermediate_buf; 872 873 counter_u64_add(tx_ring->tx_stats.llq_buffer_copy, 1); 874 } 875 876 ena_trace(ENA_DBG | ENA_TXPTH, 877 "mbuf: %p header_buf->vaddr: %p push_len: %d\n", 878 mbuf, *push_hdr, *header_len); 879 880 /* If packet is fitted in LLQ header, no need for DMA segments. */ 881 if (mbuf->m_pkthdr.len <= tx_ring->tx_max_header_size) { 882 return (0); 883 } else { 884 offset = tx_ring->tx_max_header_size; 885 /* 886 * As Header part is mapped to LLQ header, we can skip it and just 887 * map the residuum of the mbuf to DMA Segments. 888 */ 889 while (offset > 0) { 890 if (offset >= segs[iseg].ds_len) { 891 offset -= segs[iseg].ds_len; 892 } else { 893 ena_buf->paddr = segs[iseg].ds_addr + offset; 894 ena_buf->len = segs[iseg].ds_len - offset; 895 ena_buf++; 896 tx_info->num_of_bufs++; 897 offset = 0; 898 } 899 iseg++; 900 } 901 } 902 } else { 903 *push_hdr = NULL; 904 /* 905 * header_len is just a hint for the device. Because FreeBSD is not 906 * giving us information about packet header length and it is not 907 * guaranteed that all packet headers will be in the 1st mbuf, setting 908 * header_len to 0 is making the device ignore this value and resolve 909 * header on it's own. 910 */ 911 *header_len = 0; 912 } 913 914 /* Map rest of the mbuf */ 915 while (iseg < nsegs) { 916 ena_buf->paddr = segs[iseg].ds_addr; 917 ena_buf->len = segs[iseg].ds_len; 918 ena_buf++; 919 iseg++; 920 tx_info->num_of_bufs++; 921 } 922 923 return (0); 924 925 dma_error: 926 counter_u64_add(tx_ring->tx_stats.dma_mapping_err, 1); 927 tx_info->mbuf = NULL; 928 return (rc); 929 } 930 931 static int 932 ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 933 { 934 struct ena_adapter *adapter; 935 struct ena_tx_buffer *tx_info; 936 struct ena_com_tx_ctx ena_tx_ctx; 937 struct ena_com_dev *ena_dev; 938 struct ena_com_io_sq* io_sq; 939 void *push_hdr; 940 uint16_t next_to_use; 941 uint16_t req_id; 942 uint16_t ena_qid; 943 uint16_t header_len; 944 int rc; 945 int nb_hw_desc; 946 947 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 948 adapter = tx_ring->que->adapter; 949 ena_dev = adapter->ena_dev; 950 io_sq = &ena_dev->io_sq_queues[ena_qid]; 951 952 rc = ena_check_and_collapse_mbuf(tx_ring, mbuf); 953 if (unlikely(rc != 0)) { 954 ena_trace(ENA_WARNING, 955 "Failed to collapse mbuf! err: %d\n", rc); 956 return (rc); 957 } 958 959 ena_trace(ENA_DBG | ENA_TXPTH, "Tx: %d bytes\n", (*mbuf)->m_pkthdr.len); 960 961 next_to_use = tx_ring->next_to_use; 962 req_id = tx_ring->free_tx_ids[next_to_use]; 963 tx_info = &tx_ring->tx_buffer_info[req_id]; 964 tx_info->num_of_bufs = 0; 965 966 rc = ena_tx_map_mbuf(tx_ring, tx_info, *mbuf, &push_hdr, &header_len); 967 if (unlikely(rc != 0)) { 968 ena_trace(ENA_WARNING, "Failed to map TX mbuf\n"); 969 return (rc); 970 } 971 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 972 ena_tx_ctx.ena_bufs = tx_info->bufs; 973 ena_tx_ctx.push_header = push_hdr; 974 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 975 ena_tx_ctx.req_id = req_id; 976 ena_tx_ctx.header_len = header_len; 977 978 /* Set flags and meta data */ 979 ena_tx_csum(&ena_tx_ctx, *mbuf, adapter->disable_meta_caching); 980 981 if (tx_ring->acum_pkts == DB_THRESHOLD || 982 ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, &ena_tx_ctx)) { 983 ena_trace(ENA_DBG | ENA_TXPTH, 984 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n", 985 tx_ring->que->id); 986 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 987 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 988 tx_ring->acum_pkts = 0; 989 } 990 991 /* Prepare the packet's descriptors and send them to device */ 992 rc = ena_com_prepare_tx(io_sq, &ena_tx_ctx, &nb_hw_desc); 993 if (unlikely(rc != 0)) { 994 if (likely(rc == ENA_COM_NO_MEM)) { 995 ena_trace(ENA_DBG | ENA_TXPTH, 996 "tx ring[%d] if out of space\n", tx_ring->que->id); 997 } else { 998 device_printf(adapter->pdev, 999 "failed to prepare tx bufs\n"); 1000 } 1001 counter_u64_add(tx_ring->tx_stats.prepare_ctx_err, 1); 1002 goto dma_error; 1003 } 1004 1005 counter_enter(); 1006 counter_u64_add_protected(tx_ring->tx_stats.cnt, 1); 1007 counter_u64_add_protected(tx_ring->tx_stats.bytes, 1008 (*mbuf)->m_pkthdr.len); 1009 1010 counter_u64_add_protected(adapter->hw_stats.tx_packets, 1); 1011 counter_u64_add_protected(adapter->hw_stats.tx_bytes, 1012 (*mbuf)->m_pkthdr.len); 1013 counter_exit(); 1014 1015 tx_info->tx_descs = nb_hw_desc; 1016 getbinuptime(&tx_info->timestamp); 1017 tx_info->print_once = true; 1018 1019 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, 1020 tx_ring->ring_size); 1021 1022 /* stop the queue when no more space available, the packet can have up 1023 * to sgl_size + 2. one for the meta descriptor and one for header 1024 * (if the header is larger than tx_max_header_size). 1025 */ 1026 if (unlikely(!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 1027 adapter->max_tx_sgl_size + 2))) { 1028 ena_trace(ENA_DBG | ENA_TXPTH, "Stop queue %d\n", 1029 tx_ring->que->id); 1030 1031 tx_ring->running = false; 1032 counter_u64_add(tx_ring->tx_stats.queue_stop, 1); 1033 1034 /* There is a rare condition where this function decides to 1035 * stop the queue but meanwhile tx_cleanup() updates 1036 * next_to_completion and terminates. 1037 * The queue will remain stopped forever. 1038 * To solve this issue this function performs mb(), checks 1039 * the wakeup condition and wakes up the queue if needed. 1040 */ 1041 mb(); 1042 1043 if (ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 1044 ENA_TX_RESUME_THRESH)) { 1045 tx_ring->running = true; 1046 counter_u64_add(tx_ring->tx_stats.queue_wakeup, 1); 1047 } 1048 } 1049 1050 bus_dmamap_sync(adapter->tx_buf_tag, tx_info->dmamap, 1051 BUS_DMASYNC_PREWRITE); 1052 1053 return (0); 1054 1055 dma_error: 1056 tx_info->mbuf = NULL; 1057 bus_dmamap_unload(adapter->tx_buf_tag, tx_info->dmamap); 1058 1059 return (rc); 1060 } 1061 1062 static void 1063 ena_start_xmit(struct ena_ring *tx_ring) 1064 { 1065 struct mbuf *mbuf; 1066 struct ena_adapter *adapter = tx_ring->adapter; 1067 struct ena_com_io_sq* io_sq; 1068 int ena_qid; 1069 int ret = 0; 1070 1071 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) == 0)) 1072 return; 1073 1074 if (unlikely(!ENA_FLAG_ISSET(ENA_FLAG_LINK_UP, adapter))) 1075 return; 1076 1077 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 1078 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 1079 1080 while ((mbuf = drbr_peek(adapter->ifp, tx_ring->br)) != NULL) { 1081 ena_trace(ENA_DBG | ENA_TXPTH, "\ndequeued mbuf %p with flags %#x and" 1082 " header csum flags %#jx\n", 1083 mbuf, mbuf->m_flags, (uint64_t)mbuf->m_pkthdr.csum_flags); 1084 1085 if (unlikely(!tx_ring->running)) { 1086 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 1087 break; 1088 } 1089 1090 if (unlikely((ret = ena_xmit_mbuf(tx_ring, &mbuf)) != 0)) { 1091 if (ret == ENA_COM_NO_MEM) { 1092 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 1093 } else if (ret == ENA_COM_NO_SPACE) { 1094 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 1095 } else { 1096 m_freem(mbuf); 1097 drbr_advance(adapter->ifp, tx_ring->br); 1098 } 1099 1100 break; 1101 } 1102 1103 drbr_advance(adapter->ifp, tx_ring->br); 1104 1105 if (unlikely((if_getdrvflags(adapter->ifp) & 1106 IFF_DRV_RUNNING) == 0)) 1107 return; 1108 1109 tx_ring->acum_pkts++; 1110 1111 BPF_MTAP(adapter->ifp, mbuf); 1112 } 1113 1114 if (likely(tx_ring->acum_pkts != 0)) { 1115 /* Trigger the dma engine */ 1116 ena_com_write_sq_doorbell(io_sq); 1117 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 1118 tx_ring->acum_pkts = 0; 1119 } 1120 1121 if (unlikely(!tx_ring->running)) 1122 taskqueue_enqueue(tx_ring->que->cleanup_tq, 1123 &tx_ring->que->cleanup_task); 1124 } 1125