119aa95e4SMarcin Wojtas /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 319aa95e4SMarcin Wojtas * 419aa95e4SMarcin Wojtas * Copyright (c) 2021 Alstom Group. 519aa95e4SMarcin Wojtas * Copyright (c) 2021 Semihalf. 619aa95e4SMarcin Wojtas * 719aa95e4SMarcin Wojtas * Redistribution and use in source and binary forms, with or without 819aa95e4SMarcin Wojtas * modification, are permitted provided that the following conditions 919aa95e4SMarcin Wojtas * are met: 1019aa95e4SMarcin Wojtas * 1. Redistributions of source code must retain the above copyright 1119aa95e4SMarcin Wojtas * notice, this list of conditions and the following disclaimer. 1219aa95e4SMarcin Wojtas * 2. Redistributions in binary form must reproduce the above copyright 1319aa95e4SMarcin Wojtas * notice, this list of conditions and the following disclaimer in the 1419aa95e4SMarcin Wojtas * documentation and/or other materials provided with the distribution. 1519aa95e4SMarcin Wojtas * 1619aa95e4SMarcin Wojtas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1719aa95e4SMarcin Wojtas * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1819aa95e4SMarcin Wojtas * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1919aa95e4SMarcin Wojtas * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2019aa95e4SMarcin Wojtas * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2119aa95e4SMarcin Wojtas * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2219aa95e4SMarcin Wojtas * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2319aa95e4SMarcin Wojtas * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2419aa95e4SMarcin Wojtas * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2519aa95e4SMarcin Wojtas * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2619aa95e4SMarcin Wojtas */ 2719aa95e4SMarcin Wojtas #ifndef _ENETC_H_ 2819aa95e4SMarcin Wojtas #define _ENETC_H_ 2919aa95e4SMarcin Wojtas 3019aa95e4SMarcin Wojtas #include <sys/param.h> 3119aa95e4SMarcin Wojtas 3219aa95e4SMarcin Wojtas #include <dev/enetc/enetc_hw.h> 3319aa95e4SMarcin Wojtas 3419aa95e4SMarcin Wojtas struct enetc_softc; 3519aa95e4SMarcin Wojtas struct enetc_rx_queue { 3619aa95e4SMarcin Wojtas struct enetc_softc *sc; 3719aa95e4SMarcin Wojtas uint16_t qid; 3819aa95e4SMarcin Wojtas 3919aa95e4SMarcin Wojtas union enetc_rx_bd *ring; 4019aa95e4SMarcin Wojtas uint64_t ring_paddr; 4119aa95e4SMarcin Wojtas 4219aa95e4SMarcin Wojtas struct if_irq irq; 4319aa95e4SMarcin Wojtas bool enabled; 4419aa95e4SMarcin Wojtas }; 4519aa95e4SMarcin Wojtas 4619aa95e4SMarcin Wojtas struct enetc_tx_queue { 4719aa95e4SMarcin Wojtas struct enetc_softc *sc; 4819aa95e4SMarcin Wojtas 4919aa95e4SMarcin Wojtas union enetc_tx_bd *ring; 5019aa95e4SMarcin Wojtas uint64_t ring_paddr; 5119aa95e4SMarcin Wojtas 52a6bda3e1SKornel Duleba qidx_t cidx; 5319aa95e4SMarcin Wojtas 5419aa95e4SMarcin Wojtas struct if_irq irq; 5519aa95e4SMarcin Wojtas }; 5619aa95e4SMarcin Wojtas 5719aa95e4SMarcin Wojtas struct enetc_ctrl_queue { 5819aa95e4SMarcin Wojtas qidx_t pidx; 5919aa95e4SMarcin Wojtas 6019aa95e4SMarcin Wojtas struct iflib_dma_info dma; 6119aa95e4SMarcin Wojtas struct enetc_cbd *ring; 6219aa95e4SMarcin Wojtas 6319aa95e4SMarcin Wojtas struct if_irq irq; 6419aa95e4SMarcin Wojtas }; 6519aa95e4SMarcin Wojtas 6619aa95e4SMarcin Wojtas struct enetc_softc { 6719aa95e4SMarcin Wojtas device_t dev; 6819aa95e4SMarcin Wojtas 69cbac9a36SKornel Duleba struct mtx mii_lock; 70cbac9a36SKornel Duleba 7119aa95e4SMarcin Wojtas if_ctx_t ctx; 7219aa95e4SMarcin Wojtas if_softc_ctx_t shared; 7319aa95e4SMarcin Wojtas #define tx_num_queues shared->isc_ntxqsets 7419aa95e4SMarcin Wojtas #define rx_num_queues shared->isc_nrxqsets 7519aa95e4SMarcin Wojtas #define tx_queue_size shared->isc_ntxd[0] 7619aa95e4SMarcin Wojtas #define rx_queue_size shared->isc_nrxd[0] 7719aa95e4SMarcin Wojtas 7819aa95e4SMarcin Wojtas struct resource *regs; 7919aa95e4SMarcin Wojtas 8019aa95e4SMarcin Wojtas device_t miibus; 8119aa95e4SMarcin Wojtas 8219aa95e4SMarcin Wojtas struct enetc_tx_queue *tx_queues; 8319aa95e4SMarcin Wojtas struct enetc_rx_queue *rx_queues; 8419aa95e4SMarcin Wojtas struct enetc_ctrl_queue ctrl_queue; 8519aa95e4SMarcin Wojtas 8619aa95e4SMarcin Wojtas /* Default RX queue configuration. */ 8719aa95e4SMarcin Wojtas uint32_t rbmr; 8819aa95e4SMarcin Wojtas /* 8919aa95e4SMarcin Wojtas * Hardware VLAN hash based filtering uses a 64bit bitmap. 9019aa95e4SMarcin Wojtas * We need to know how many vids are in given position to 9119aa95e4SMarcin Wojtas * know when to remove the bit from the bitmap. 9219aa95e4SMarcin Wojtas */ 9319aa95e4SMarcin Wojtas #define VLAN_BITMAP_SIZE 64 9419aa95e4SMarcin Wojtas uint8_t vlan_bitmap[64]; 9519aa95e4SMarcin Wojtas 9619aa95e4SMarcin Wojtas struct if_irq admin_irq; 9719aa95e4SMarcin Wojtas int phy_addr; 9819aa95e4SMarcin Wojtas 9919aa95e4SMarcin Wojtas struct ifmedia fixed_ifmedia; 10019aa95e4SMarcin Wojtas bool fixed_link; 10119aa95e4SMarcin Wojtas }; 10219aa95e4SMarcin Wojtas 10319aa95e4SMarcin Wojtas #define ENETC_RD4(sc, reg) \ 10419aa95e4SMarcin Wojtas bus_read_4((sc)->regs, reg) 10519aa95e4SMarcin Wojtas #define ENETC_WR4(sc, reg, value) \ 10619aa95e4SMarcin Wojtas bus_write_4((sc)->regs, reg, value) 10719aa95e4SMarcin Wojtas 10819aa95e4SMarcin Wojtas #define ENETC_PORT_RD8(sc, reg) \ 10919aa95e4SMarcin Wojtas bus_read_8((sc)->regs, ENETC_PORT_BASE + (reg)) 11019aa95e4SMarcin Wojtas #define ENETC_PORT_RD4(sc, reg) \ 11119aa95e4SMarcin Wojtas bus_read_4((sc)->regs, ENETC_PORT_BASE + (reg)) 11219aa95e4SMarcin Wojtas #define ENETC_PORT_WR4(sc, reg, value) \ 11319aa95e4SMarcin Wojtas bus_write_4((sc)->regs, ENETC_PORT_BASE + (reg), value) 11419aa95e4SMarcin Wojtas #define ENETC_PORT_RD2(sc, reg) \ 11519aa95e4SMarcin Wojtas bus_read_2((sc)->regs, ENETC_PORT_BASE + (reg)) 11619aa95e4SMarcin Wojtas #define ENETC_PORT_WR2(sc, reg, value) \ 11719aa95e4SMarcin Wojtas bus_write_2((sc)->regs, ENETC_PORT_BASE + (reg), value) 11819aa95e4SMarcin Wojtas 11919aa95e4SMarcin Wojtas #define ENETC_TXQ_RD4(sc, q, reg) \ 12019aa95e4SMarcin Wojtas ENETC_RD4((sc), ENETC_BDR(TX, q, reg)) 12119aa95e4SMarcin Wojtas #define ENETC_TXQ_WR4(sc, q, reg, value) \ 12219aa95e4SMarcin Wojtas ENETC_WR4((sc), ENETC_BDR(TX, q, reg), value) 12319aa95e4SMarcin Wojtas #define ENETC_RXQ_RD4(sc, q, reg) \ 12419aa95e4SMarcin Wojtas ENETC_RD4((sc), ENETC_BDR(RX, q, reg)) 12519aa95e4SMarcin Wojtas #define ENETC_RXQ_WR4(sc, q, reg, value) \ 12619aa95e4SMarcin Wojtas ENETC_WR4((sc), ENETC_BDR(RX, q, reg), value) 12719aa95e4SMarcin Wojtas 12819aa95e4SMarcin Wojtas /* Device constants */ 12919aa95e4SMarcin Wojtas 13019aa95e4SMarcin Wojtas #define ENETC_MAX_FRAME_LEN 9600 13119aa95e4SMarcin Wojtas 13219aa95e4SMarcin Wojtas #define ENETC_MAX_QUEUES 4 13319aa95e4SMarcin Wojtas 13419aa95e4SMarcin Wojtas /* Max supported nr of descriptors per frame. */ 13519aa95e4SMarcin Wojtas #define ENETC_MAX_SCATTER 15 13619aa95e4SMarcin Wojtas 13719aa95e4SMarcin Wojtas /* 13819aa95e4SMarcin Wojtas * Up to 4096 transmit/receive descriptors are supported, 139f9254cc6SGordon Bergling * their number has to be a multiple of 64. 14019aa95e4SMarcin Wojtas */ 14119aa95e4SMarcin Wojtas #define ENETC_MIN_DESC 64 14219aa95e4SMarcin Wojtas #define ENETC_MAX_DESC 4096 14319aa95e4SMarcin Wojtas #define ENETC_DEFAULT_DESC 512 14419aa95e4SMarcin Wojtas #define ENETC_DESC_ALIGN 64 14519aa95e4SMarcin Wojtas 14619aa95e4SMarcin Wojtas /* Rings have to be 128B aligned. */ 14719aa95e4SMarcin Wojtas #define ENETC_RING_ALIGN 128 14819aa95e4SMarcin Wojtas 14919aa95e4SMarcin Wojtas #define ENETC_MSIX_COUNT 32 15019aa95e4SMarcin Wojtas 15119aa95e4SMarcin Wojtas #define ENETC_RX_INTR_PKT_THR 16 15219aa95e4SMarcin Wojtas 15319aa95e4SMarcin Wojtas /* Rx threshold irq timeout, 100us */ 15419aa95e4SMarcin Wojtas #define ENETC_RX_INTR_TIME_THR ((100ULL * ENETC_CLK) / 1000000ULL) 15519aa95e4SMarcin Wojtas 15619aa95e4SMarcin Wojtas #define ENETC_RX_IP_ALIGN 2 15719aa95e4SMarcin Wojtas 15819aa95e4SMarcin Wojtas #endif 159