1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2021 Alstom Group. 5 * Copyright (c) 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _ENETC_H_ 28 #define _ENETC_H_ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 35 #include <dev/enetc/enetc_hw.h> 36 37 struct enetc_softc; 38 struct enetc_rx_queue { 39 struct enetc_softc *sc; 40 uint16_t qid; 41 42 union enetc_rx_bd *ring; 43 uint64_t ring_paddr; 44 45 struct if_irq irq; 46 bool enabled; 47 }; 48 49 struct enetc_tx_queue { 50 struct enetc_softc *sc; 51 52 union enetc_tx_bd *ring; 53 uint64_t ring_paddr; 54 55 qidx_t cidx; 56 57 struct if_irq irq; 58 }; 59 60 struct enetc_ctrl_queue { 61 qidx_t pidx; 62 63 struct iflib_dma_info dma; 64 struct enetc_cbd *ring; 65 66 struct if_irq irq; 67 }; 68 69 struct enetc_softc { 70 device_t dev; 71 72 struct mtx mii_lock; 73 74 if_ctx_t ctx; 75 if_softc_ctx_t shared; 76 #define tx_num_queues shared->isc_ntxqsets 77 #define rx_num_queues shared->isc_nrxqsets 78 #define tx_queue_size shared->isc_ntxd[0] 79 #define rx_queue_size shared->isc_nrxd[0] 80 81 struct resource *regs; 82 83 device_t miibus; 84 85 struct enetc_tx_queue *tx_queues; 86 struct enetc_rx_queue *rx_queues; 87 struct enetc_ctrl_queue ctrl_queue; 88 89 /* Default RX queue configuration. */ 90 uint32_t rbmr; 91 /* 92 * Hardware VLAN hash based filtering uses a 64bit bitmap. 93 * We need to know how many vids are in given position to 94 * know when to remove the bit from the bitmap. 95 */ 96 #define VLAN_BITMAP_SIZE 64 97 uint8_t vlan_bitmap[64]; 98 99 struct if_irq admin_irq; 100 int phy_addr; 101 102 struct ifmedia fixed_ifmedia; 103 bool fixed_link; 104 }; 105 106 #define ENETC_RD4(sc, reg) \ 107 bus_read_4((sc)->regs, reg) 108 #define ENETC_WR4(sc, reg, value) \ 109 bus_write_4((sc)->regs, reg, value) 110 111 #define ENETC_PORT_RD8(sc, reg) \ 112 bus_read_8((sc)->regs, ENETC_PORT_BASE + (reg)) 113 #define ENETC_PORT_RD4(sc, reg) \ 114 bus_read_4((sc)->regs, ENETC_PORT_BASE + (reg)) 115 #define ENETC_PORT_WR4(sc, reg, value) \ 116 bus_write_4((sc)->regs, ENETC_PORT_BASE + (reg), value) 117 #define ENETC_PORT_RD2(sc, reg) \ 118 bus_read_2((sc)->regs, ENETC_PORT_BASE + (reg)) 119 #define ENETC_PORT_WR2(sc, reg, value) \ 120 bus_write_2((sc)->regs, ENETC_PORT_BASE + (reg), value) 121 122 #define ENETC_TXQ_RD4(sc, q, reg) \ 123 ENETC_RD4((sc), ENETC_BDR(TX, q, reg)) 124 #define ENETC_TXQ_WR4(sc, q, reg, value) \ 125 ENETC_WR4((sc), ENETC_BDR(TX, q, reg), value) 126 #define ENETC_RXQ_RD4(sc, q, reg) \ 127 ENETC_RD4((sc), ENETC_BDR(RX, q, reg)) 128 #define ENETC_RXQ_WR4(sc, q, reg, value) \ 129 ENETC_WR4((sc), ENETC_BDR(RX, q, reg), value) 130 131 /* Device constants */ 132 133 #define ENETC_MAX_FRAME_LEN 9600 134 135 #define ENETC_MAX_QUEUES 4 136 137 /* Max supported nr of descriptors per frame. */ 138 #define ENETC_MAX_SCATTER 15 139 140 /* 141 * Up to 4096 transmit/receive descriptors are supported, 142 * their number has to be a multiple of 64. 143 */ 144 #define ENETC_MIN_DESC 64 145 #define ENETC_MAX_DESC 4096 146 #define ENETC_DEFAULT_DESC 512 147 #define ENETC_DESC_ALIGN 64 148 149 /* Rings have to be 128B aligned. */ 150 #define ENETC_RING_ALIGN 128 151 152 #define ENETC_MSIX_COUNT 32 153 154 #define ENETC_RX_INTR_PKT_THR 16 155 156 /* Rx threshold irq timeout, 100us */ 157 #define ENETC_RX_INTR_TIME_THR ((100ULL * ENETC_CLK) / 1000000ULL) 158 159 #define ENETC_RX_IP_ALIGN 2 160 161 #endif 162