1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/malloc.h> 48 #include <sys/mbuf.h> 49 #include <sys/proc.h> 50 #include <sys/rman.h> 51 #include <sys/module.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/bpf.h> 62 #include <net/if_arp.h> 63 #include <net/if_media.h> 64 #include <net/if_vlan_var.h> 65 66 #include <machine/bus.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/et/if_etreg.h> 75 #include <dev/et/if_etvar.h> 76 77 #include "miibus_if.h" 78 79 MODULE_DEPEND(et, pci, 1, 1, 1); 80 MODULE_DEPEND(et, ether, 1, 1, 1); 81 MODULE_DEPEND(et, miibus, 1, 1, 1); 82 83 /* Tunables. */ 84 static int msi_disable = 0; 85 TUNABLE_INT("hw.et.msi_disable", &msi_disable); 86 87 #define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 88 89 static int et_probe(device_t); 90 static int et_attach(device_t); 91 static int et_detach(device_t); 92 static int et_shutdown(device_t); 93 static int et_suspend(device_t); 94 static int et_resume(device_t); 95 96 static int et_miibus_readreg(device_t, int, int); 97 static int et_miibus_writereg(device_t, int, int, int); 98 static void et_miibus_statchg(device_t); 99 100 static void et_init_locked(struct et_softc *); 101 static void et_init(void *); 102 static int et_ioctl(if_t, u_long, caddr_t); 103 static void et_start_locked(if_t); 104 static void et_start(if_t); 105 static int et_watchdog(struct et_softc *); 106 static int et_ifmedia_upd_locked(if_t); 107 static int et_ifmedia_upd(if_t); 108 static void et_ifmedia_sts(if_t, struct ifmediareq *); 109 static uint64_t et_get_counter(if_t, ift_counter); 110 111 static void et_add_sysctls(struct et_softc *); 112 static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 113 static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 114 115 static void et_intr(void *); 116 static void et_rxeof(struct et_softc *); 117 static void et_txeof(struct et_softc *); 118 119 static int et_dma_alloc(struct et_softc *); 120 static void et_dma_free(struct et_softc *); 121 static void et_dma_map_addr(void *, bus_dma_segment_t *, int, int); 122 static int et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t, 123 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, 124 const char *); 125 static void et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **, 126 bus_dmamap_t, bus_addr_t *); 127 static void et_init_tx_ring(struct et_softc *); 128 static int et_init_rx_ring(struct et_softc *); 129 static void et_free_tx_ring(struct et_softc *); 130 static void et_free_rx_ring(struct et_softc *); 131 static int et_encap(struct et_softc *, struct mbuf **); 132 static int et_newbuf_cluster(struct et_rxbuf_data *, int); 133 static int et_newbuf_hdr(struct et_rxbuf_data *, int); 134 static void et_rxbuf_discard(struct et_rxbuf_data *, int); 135 136 static void et_stop(struct et_softc *); 137 static int et_chip_init(struct et_softc *); 138 static void et_chip_attach(struct et_softc *); 139 static void et_init_mac(struct et_softc *); 140 static void et_init_rxmac(struct et_softc *); 141 static void et_init_txmac(struct et_softc *); 142 static int et_init_rxdma(struct et_softc *); 143 static int et_init_txdma(struct et_softc *); 144 static int et_start_rxdma(struct et_softc *); 145 static int et_start_txdma(struct et_softc *); 146 static int et_stop_rxdma(struct et_softc *); 147 static int et_stop_txdma(struct et_softc *); 148 static void et_reset(struct et_softc *); 149 static int et_bus_config(struct et_softc *); 150 static void et_get_eaddr(device_t, uint8_t[]); 151 static void et_setmulti(struct et_softc *); 152 static void et_tick(void *); 153 static void et_stats_update(struct et_softc *); 154 155 static const struct et_dev { 156 uint16_t vid; 157 uint16_t did; 158 const char *desc; 159 } et_devices[] = { 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 161 "Agere ET1310 Gigabit Ethernet" }, 162 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 163 "Agere ET1310 Fast Ethernet" }, 164 { 0, 0, NULL } 165 }; 166 167 static device_method_t et_methods[] = { 168 DEVMETHOD(device_probe, et_probe), 169 DEVMETHOD(device_attach, et_attach), 170 DEVMETHOD(device_detach, et_detach), 171 DEVMETHOD(device_shutdown, et_shutdown), 172 DEVMETHOD(device_suspend, et_suspend), 173 DEVMETHOD(device_resume, et_resume), 174 175 DEVMETHOD(miibus_readreg, et_miibus_readreg), 176 DEVMETHOD(miibus_writereg, et_miibus_writereg), 177 DEVMETHOD(miibus_statchg, et_miibus_statchg), 178 179 DEVMETHOD_END 180 }; 181 182 static driver_t et_driver = { 183 "et", 184 et_methods, 185 sizeof(struct et_softc) 186 }; 187 188 DRIVER_MODULE(et, pci, et_driver, 0, 0); 189 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, et, et_devices, 190 nitems(et_devices) - 1); 191 DRIVER_MODULE(miibus, et, miibus_driver, 0, 0); 192 193 static int et_rx_intr_npkts = 32; 194 static int et_rx_intr_delay = 20; /* x10 usec */ 195 static int et_tx_intr_nsegs = 126; 196 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 197 198 TUNABLE_INT("hw.et.timer", &et_timer); 199 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 200 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 201 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 202 203 static int 204 et_probe(device_t dev) 205 { 206 const struct et_dev *d; 207 uint16_t did, vid; 208 209 vid = pci_get_vendor(dev); 210 did = pci_get_device(dev); 211 212 for (d = et_devices; d->desc != NULL; ++d) { 213 if (vid == d->vid && did == d->did) { 214 device_set_desc(dev, d->desc); 215 return (BUS_PROBE_DEFAULT); 216 } 217 } 218 return (ENXIO); 219 } 220 221 static int 222 et_attach(device_t dev) 223 { 224 struct et_softc *sc; 225 if_t ifp; 226 uint8_t eaddr[ETHER_ADDR_LEN]; 227 uint32_t pmcfg; 228 int cap, error, msic; 229 230 sc = device_get_softc(dev); 231 sc->dev = dev; 232 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 233 MTX_DEF); 234 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 235 236 ifp = sc->ifp = if_alloc(IFT_ETHER); 237 if (ifp == NULL) { 238 device_printf(dev, "can not if_alloc()\n"); 239 error = ENOSPC; 240 goto fail; 241 } 242 243 /* 244 * Initialize tunables 245 */ 246 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 247 sc->sc_rx_intr_delay = et_rx_intr_delay; 248 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 249 sc->sc_timer = et_timer; 250 251 /* Enable bus mastering */ 252 pci_enable_busmaster(dev); 253 254 /* 255 * Allocate IO memory 256 */ 257 sc->sc_mem_rid = PCIR_BAR(0); 258 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 259 &sc->sc_mem_rid, RF_ACTIVE); 260 if (sc->sc_mem_res == NULL) { 261 device_printf(dev, "can't allocate IO memory\n"); 262 return (ENXIO); 263 } 264 265 msic = 0; 266 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 267 sc->sc_expcap = cap; 268 sc->sc_flags |= ET_FLAG_PCIE; 269 msic = pci_msi_count(dev); 270 if (bootverbose) 271 device_printf(dev, "MSI count: %d\n", msic); 272 } 273 if (msic > 0 && msi_disable == 0) { 274 msic = 1; 275 if (pci_alloc_msi(dev, &msic) == 0) { 276 if (msic == 1) { 277 device_printf(dev, "Using %d MSI message\n", 278 msic); 279 sc->sc_flags |= ET_FLAG_MSI; 280 } else 281 pci_release_msi(dev); 282 } 283 } 284 285 /* 286 * Allocate IRQ 287 */ 288 if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 289 sc->sc_irq_rid = 0; 290 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 291 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 292 } else { 293 sc->sc_irq_rid = 1; 294 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 295 &sc->sc_irq_rid, RF_ACTIVE); 296 } 297 if (sc->sc_irq_res == NULL) { 298 device_printf(dev, "can't allocate irq\n"); 299 error = ENXIO; 300 goto fail; 301 } 302 303 if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST) 304 sc->sc_flags |= ET_FLAG_FASTETHER; 305 306 error = et_bus_config(sc); 307 if (error) 308 goto fail; 309 310 et_get_eaddr(dev, eaddr); 311 312 /* Take PHY out of COMA and enable clocks. */ 313 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 314 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 315 pmcfg |= EM_PM_GIGEPHY_ENB; 316 CSR_WRITE_4(sc, ET_PM, pmcfg); 317 318 et_reset(sc); 319 320 error = et_dma_alloc(sc); 321 if (error) 322 goto fail; 323 324 if_setsoftc(ifp, sc); 325 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 326 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 327 if_setinitfn(ifp, et_init); 328 if_setioctlfn(ifp, et_ioctl); 329 if_setstartfn(ifp, et_start); 330 if_setgetcounterfn(ifp, et_get_counter); 331 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_VLAN_MTU); 332 if_setcapenable(ifp, if_getcapabilities(ifp)); 333 if_setsendqlen(ifp, ET_TX_NDESC - 1); 334 if_setsendqready(ifp); 335 336 et_chip_attach(sc); 337 338 error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 339 et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 340 MIIF_DOPAUSE); 341 if (error) { 342 device_printf(dev, "attaching PHYs failed\n"); 343 goto fail; 344 } 345 346 ether_ifattach(ifp, eaddr); 347 348 /* Tell the upper layer(s) we support long frames. */ 349 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 350 351 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 352 NULL, et_intr, sc, &sc->sc_irq_handle); 353 if (error) { 354 ether_ifdetach(ifp); 355 device_printf(dev, "can't setup intr\n"); 356 goto fail; 357 } 358 359 et_add_sysctls(sc); 360 361 return (0); 362 fail: 363 et_detach(dev); 364 return (error); 365 } 366 367 static int 368 et_detach(device_t dev) 369 { 370 struct et_softc *sc; 371 372 sc = device_get_softc(dev); 373 if (device_is_attached(dev)) { 374 ether_ifdetach(sc->ifp); 375 ET_LOCK(sc); 376 et_stop(sc); 377 ET_UNLOCK(sc); 378 callout_drain(&sc->sc_tick); 379 } 380 381 if (sc->sc_miibus != NULL) 382 device_delete_child(dev, sc->sc_miibus); 383 bus_generic_detach(dev); 384 385 if (sc->sc_irq_handle != NULL) 386 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 387 if (sc->sc_irq_res != NULL) 388 bus_release_resource(dev, SYS_RES_IRQ, 389 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 390 if ((sc->sc_flags & ET_FLAG_MSI) != 0) 391 pci_release_msi(dev); 392 if (sc->sc_mem_res != NULL) 393 bus_release_resource(dev, SYS_RES_MEMORY, 394 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 395 396 if (sc->ifp != NULL) 397 if_free(sc->ifp); 398 399 et_dma_free(sc); 400 401 mtx_destroy(&sc->sc_mtx); 402 403 return (0); 404 } 405 406 static int 407 et_shutdown(device_t dev) 408 { 409 struct et_softc *sc; 410 411 sc = device_get_softc(dev); 412 ET_LOCK(sc); 413 et_stop(sc); 414 ET_UNLOCK(sc); 415 return (0); 416 } 417 418 static int 419 et_miibus_readreg(device_t dev, int phy, int reg) 420 { 421 struct et_softc *sc; 422 uint32_t val; 423 int i, ret; 424 425 sc = device_get_softc(dev); 426 /* Stop any pending operations */ 427 CSR_WRITE_4(sc, ET_MII_CMD, 0); 428 429 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 430 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 431 CSR_WRITE_4(sc, ET_MII_ADDR, val); 432 433 /* Start reading */ 434 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 435 436 #define NRETRY 50 437 438 for (i = 0; i < NRETRY; ++i) { 439 val = CSR_READ_4(sc, ET_MII_IND); 440 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 441 break; 442 DELAY(50); 443 } 444 if (i == NRETRY) { 445 if_printf(sc->ifp, 446 "read phy %d, reg %d timed out\n", phy, reg); 447 ret = 0; 448 goto back; 449 } 450 451 #undef NRETRY 452 453 val = CSR_READ_4(sc, ET_MII_STAT); 454 ret = val & ET_MII_STAT_VALUE_MASK; 455 456 back: 457 /* Make sure that the current operation is stopped */ 458 CSR_WRITE_4(sc, ET_MII_CMD, 0); 459 return (ret); 460 } 461 462 static int 463 et_miibus_writereg(device_t dev, int phy, int reg, int val0) 464 { 465 struct et_softc *sc; 466 uint32_t val; 467 int i; 468 469 sc = device_get_softc(dev); 470 /* Stop any pending operations */ 471 CSR_WRITE_4(sc, ET_MII_CMD, 0); 472 473 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 474 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 475 CSR_WRITE_4(sc, ET_MII_ADDR, val); 476 477 /* Start writing */ 478 CSR_WRITE_4(sc, ET_MII_CTRL, 479 (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 480 481 #define NRETRY 100 482 483 for (i = 0; i < NRETRY; ++i) { 484 val = CSR_READ_4(sc, ET_MII_IND); 485 if ((val & ET_MII_IND_BUSY) == 0) 486 break; 487 DELAY(50); 488 } 489 if (i == NRETRY) { 490 if_printf(sc->ifp, 491 "write phy %d, reg %d timed out\n", phy, reg); 492 et_miibus_readreg(dev, phy, reg); 493 } 494 495 #undef NRETRY 496 497 /* Make sure that the current operation is stopped */ 498 CSR_WRITE_4(sc, ET_MII_CMD, 0); 499 return (0); 500 } 501 502 static void 503 et_miibus_statchg(device_t dev) 504 { 505 struct et_softc *sc; 506 struct mii_data *mii; 507 if_t ifp; 508 uint32_t cfg1, cfg2, ctrl; 509 int i; 510 511 sc = device_get_softc(dev); 512 513 mii = device_get_softc(sc->sc_miibus); 514 ifp = sc->ifp; 515 if (mii == NULL || ifp == NULL || 516 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 517 return; 518 519 sc->sc_flags &= ~ET_FLAG_LINK; 520 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 521 (IFM_ACTIVE | IFM_AVALID)) { 522 switch (IFM_SUBTYPE(mii->mii_media_active)) { 523 case IFM_10_T: 524 case IFM_100_TX: 525 sc->sc_flags |= ET_FLAG_LINK; 526 break; 527 case IFM_1000_T: 528 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 529 sc->sc_flags |= ET_FLAG_LINK; 530 break; 531 } 532 } 533 534 /* XXX Stop TX/RX MAC? */ 535 if ((sc->sc_flags & ET_FLAG_LINK) == 0) 536 return; 537 538 /* Program MACs with resolved speed/duplex/flow-control. */ 539 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 540 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 541 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 542 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 543 ET_MAC_CFG1_LOOPBACK); 544 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 545 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 546 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 547 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 548 ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 549 ET_MAC_CFG2_PREAMBLE_LEN_MASK); 550 551 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 552 cfg2 |= ET_MAC_CFG2_MODE_GMII; 553 else { 554 cfg2 |= ET_MAC_CFG2_MODE_MII; 555 ctrl |= ET_MAC_CTRL_MODE_MII; 556 } 557 558 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 559 cfg2 |= ET_MAC_CFG2_FDX; 560 /* 561 * Controller lacks automatic TX pause frame 562 * generation so it should be handled by driver. 563 * Even though driver can send pause frame with 564 * arbitrary pause time, controller does not 565 * provide a way that tells how many free RX 566 * buffers are available in controller. This 567 * limitation makes it hard to generate XON frame 568 * in time on driver side so don't enable TX flow 569 * control. 570 */ 571 #ifdef notyet 572 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 573 cfg1 |= ET_MAC_CFG1_TXFLOW; 574 #endif 575 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 576 cfg1 |= ET_MAC_CFG1_RXFLOW; 577 } else 578 ctrl |= ET_MAC_CTRL_GHDX; 579 580 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 581 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 582 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 583 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); 584 585 #define NRETRY 50 586 587 for (i = 0; i < NRETRY; ++i) { 588 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 589 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 590 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 591 break; 592 DELAY(100); 593 } 594 if (i == NRETRY) 595 if_printf(ifp, "can't enable RX/TX\n"); 596 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 597 598 #undef NRETRY 599 } 600 601 static int 602 et_ifmedia_upd_locked(if_t ifp) 603 { 604 struct et_softc *sc; 605 struct mii_data *mii; 606 struct mii_softc *miisc; 607 608 sc = if_getsoftc(ifp); 609 mii = device_get_softc(sc->sc_miibus); 610 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 611 PHY_RESET(miisc); 612 return (mii_mediachg(mii)); 613 } 614 615 static int 616 et_ifmedia_upd(if_t ifp) 617 { 618 struct et_softc *sc; 619 int res; 620 621 sc = if_getsoftc(ifp); 622 ET_LOCK(sc); 623 res = et_ifmedia_upd_locked(ifp); 624 ET_UNLOCK(sc); 625 626 return (res); 627 } 628 629 static void 630 et_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 631 { 632 struct et_softc *sc; 633 struct mii_data *mii; 634 635 sc = if_getsoftc(ifp); 636 ET_LOCK(sc); 637 if ((if_getflags(ifp) & IFF_UP) == 0) { 638 ET_UNLOCK(sc); 639 return; 640 } 641 642 mii = device_get_softc(sc->sc_miibus); 643 mii_pollstat(mii); 644 ifmr->ifm_active = mii->mii_media_active; 645 ifmr->ifm_status = mii->mii_media_status; 646 ET_UNLOCK(sc); 647 } 648 649 static void 650 et_stop(struct et_softc *sc) 651 { 652 if_t ifp; 653 654 ET_LOCK_ASSERT(sc); 655 656 ifp = sc->ifp; 657 callout_stop(&sc->sc_tick); 658 /* Disable interrupts. */ 659 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 660 661 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( 662 ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN)); 663 DELAY(100); 664 665 et_stop_rxdma(sc); 666 et_stop_txdma(sc); 667 et_stats_update(sc); 668 669 et_free_tx_ring(sc); 670 et_free_rx_ring(sc); 671 672 sc->sc_tx = 0; 673 sc->sc_tx_intr = 0; 674 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 675 676 sc->watchdog_timer = 0; 677 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 678 } 679 680 static int 681 et_bus_config(struct et_softc *sc) 682 { 683 uint32_t val, max_plsz; 684 uint16_t ack_latency, replay_timer; 685 686 /* 687 * Test whether EEPROM is valid 688 * NOTE: Read twice to get the correct value 689 */ 690 pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 691 val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 692 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 693 device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 694 return (ENXIO); 695 } 696 697 /* TODO: LED */ 698 699 if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 700 return (0); 701 702 /* 703 * Configure ACK latency and replay timer according to 704 * max playload size 705 */ 706 val = pci_read_config(sc->dev, 707 sc->sc_expcap + PCIER_DEVICE_CAP, 4); 708 max_plsz = val & PCIEM_CAP_MAX_PAYLOAD; 709 710 switch (max_plsz) { 711 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 712 ack_latency = ET_PCIV_ACK_LATENCY_128; 713 replay_timer = ET_PCIV_REPLAY_TIMER_128; 714 break; 715 716 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 717 ack_latency = ET_PCIV_ACK_LATENCY_256; 718 replay_timer = ET_PCIV_REPLAY_TIMER_256; 719 break; 720 721 default: 722 ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 723 replay_timer = pci_read_config(sc->dev, 724 ET_PCIR_REPLAY_TIMER, 2); 725 device_printf(sc->dev, "ack latency %u, replay timer %u\n", 726 ack_latency, replay_timer); 727 break; 728 } 729 if (ack_latency != 0) { 730 pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 731 pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 732 2); 733 } 734 735 /* 736 * Set L0s and L1 latency timer to 2us 737 */ 738 val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 739 val &= ~(PCIEM_LINK_CAP_L0S_EXIT | PCIEM_LINK_CAP_L1_EXIT); 740 /* L0s exit latency : 2us */ 741 val |= 0x00005000; 742 /* L1 exit latency : 2us */ 743 val |= 0x00028000; 744 pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 745 746 /* 747 * Set max read request size to 2048 bytes 748 */ 749 pci_set_max_read_req(sc->dev, 2048); 750 751 return (0); 752 } 753 754 static void 755 et_get_eaddr(device_t dev, uint8_t eaddr[]) 756 { 757 uint32_t val; 758 int i; 759 760 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 761 for (i = 0; i < 4; ++i) 762 eaddr[i] = (val >> (8 * i)) & 0xff; 763 764 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 765 for (; i < ETHER_ADDR_LEN; ++i) 766 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 767 } 768 769 static void 770 et_reset(struct et_softc *sc) 771 { 772 773 CSR_WRITE_4(sc, ET_MAC_CFG1, 774 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 775 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 776 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 777 778 CSR_WRITE_4(sc, ET_SWRST, 779 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 780 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 781 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 782 783 CSR_WRITE_4(sc, ET_MAC_CFG1, 784 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 785 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 786 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 787 /* Disable interrupts. */ 788 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 789 } 790 791 struct et_dmamap_arg { 792 bus_addr_t et_busaddr; 793 }; 794 795 static void 796 et_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 797 { 798 struct et_dmamap_arg *ctx; 799 800 if (error) 801 return; 802 803 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 804 805 ctx = arg; 806 ctx->et_busaddr = segs->ds_addr; 807 } 808 809 static int 810 et_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize, 811 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 812 const char *msg) 813 { 814 struct et_dmamap_arg ctx; 815 int error; 816 817 error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR, 818 BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL, 819 tag); 820 if (error != 0) { 821 device_printf(sc->dev, "could not create %s dma tag\n", msg); 822 return (error); 823 } 824 /* Allocate DMA'able memory for ring. */ 825 error = bus_dmamem_alloc(*tag, (void **)ring, 826 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 827 if (error != 0) { 828 device_printf(sc->dev, 829 "could not allocate DMA'able memory for %s\n", msg); 830 return (error); 831 } 832 /* Load the address of the ring. */ 833 ctx.et_busaddr = 0; 834 error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr, 835 &ctx, BUS_DMA_NOWAIT); 836 if (error != 0) { 837 device_printf(sc->dev, 838 "could not load DMA'able memory for %s\n", msg); 839 return (error); 840 } 841 *paddr = ctx.et_busaddr; 842 return (0); 843 } 844 845 static void 846 et_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 847 bus_dmamap_t map, bus_addr_t *paddr) 848 { 849 850 if (*paddr != 0) { 851 bus_dmamap_unload(*tag, map); 852 *paddr = 0; 853 } 854 if (*ring != NULL) { 855 bus_dmamem_free(*tag, *ring, map); 856 *ring = NULL; 857 } 858 if (*tag) { 859 bus_dma_tag_destroy(*tag); 860 *tag = NULL; 861 } 862 } 863 864 static int 865 et_dma_alloc(struct et_softc *sc) 866 { 867 struct et_txdesc_ring *tx_ring; 868 struct et_rxdesc_ring *rx_ring; 869 struct et_rxstat_ring *rxst_ring; 870 struct et_rxstatus_data *rxsd; 871 struct et_rxbuf_data *rbd; 872 struct et_txbuf_data *tbd; 873 struct et_txstatus_data *txsd; 874 int i, error; 875 876 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 877 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 878 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 879 &sc->sc_dtag); 880 if (error != 0) { 881 device_printf(sc->dev, "could not allocate parent dma tag\n"); 882 return (error); 883 } 884 885 /* TX ring. */ 886 tx_ring = &sc->sc_tx_ring; 887 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE, 888 &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap, 889 &tx_ring->tr_paddr, "TX ring"); 890 if (error) 891 return (error); 892 893 /* TX status block. */ 894 txsd = &sc->sc_tx_status; 895 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t), 896 &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap, 897 &txsd->txsd_paddr, "TX status block"); 898 if (error) 899 return (error); 900 901 /* RX ring 0, used as to recive small sized frames. */ 902 rx_ring = &sc->sc_rx_ring[0]; 903 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 904 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 905 &rx_ring->rr_paddr, "RX ring 0"); 906 rx_ring->rr_posreg = ET_RX_RING0_POS; 907 if (error) 908 return (error); 909 910 /* RX ring 1, used as to store normal sized frames. */ 911 rx_ring = &sc->sc_rx_ring[1]; 912 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 913 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 914 &rx_ring->rr_paddr, "RX ring 1"); 915 rx_ring->rr_posreg = ET_RX_RING1_POS; 916 if (error) 917 return (error); 918 919 /* RX stat ring. */ 920 rxst_ring = &sc->sc_rxstat_ring; 921 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE, 922 &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat, 923 &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring"); 924 if (error) 925 return (error); 926 927 /* RX status block. */ 928 rxsd = &sc->sc_rx_status; 929 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, 930 sizeof(struct et_rxstatus), &rxsd->rxsd_dtag, 931 (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap, 932 &rxsd->rxsd_paddr, "RX status block"); 933 if (error) 934 return (error); 935 936 /* Create parent DMA tag for mbufs. */ 937 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 938 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 939 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 940 &sc->sc_mbuf_dtag); 941 if (error != 0) { 942 device_printf(sc->dev, 943 "could not allocate parent dma tag for mbuf\n"); 944 return (error); 945 } 946 947 /* Create DMA tag for mini RX mbufs to use RX ring 0. */ 948 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 949 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 950 MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag); 951 if (error) { 952 device_printf(sc->dev, "could not create mini RX dma tag\n"); 953 return (error); 954 } 955 956 /* Create DMA tag for standard RX mbufs to use RX ring 1. */ 957 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 958 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 959 MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag); 960 if (error) { 961 device_printf(sc->dev, "could not create RX dma tag\n"); 962 return (error); 963 } 964 965 /* Create DMA tag for TX mbufs. */ 966 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 967 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 968 MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL, 969 &sc->sc_tx_tag); 970 if (error) { 971 device_printf(sc->dev, "could not create TX dma tag\n"); 972 return (error); 973 } 974 975 /* Initialize RX ring 0. */ 976 rbd = &sc->sc_rx_data[0]; 977 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128; 978 rbd->rbd_newbuf = et_newbuf_hdr; 979 rbd->rbd_discard = et_rxbuf_discard; 980 rbd->rbd_softc = sc; 981 rbd->rbd_ring = &sc->sc_rx_ring[0]; 982 /* Create DMA maps for mini RX buffers, ring 0. */ 983 for (i = 0; i < ET_RX_NDESC; i++) { 984 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 985 &rbd->rbd_buf[i].rb_dmap); 986 if (error) { 987 device_printf(sc->dev, 988 "could not create DMA map for mini RX mbufs\n"); 989 return (error); 990 } 991 } 992 993 /* Create a spare DMA map for mini RX buffers, ring 0. */ 994 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 995 &sc->sc_rx_mini_sparemap); 996 if (error) { 997 device_printf(sc->dev, 998 "could not create spare DMA map for mini RX mbuf\n"); 999 return (error); 1000 } 1001 1002 /* Initialize RX ring 1. */ 1003 rbd = &sc->sc_rx_data[1]; 1004 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048; 1005 rbd->rbd_newbuf = et_newbuf_cluster; 1006 rbd->rbd_discard = et_rxbuf_discard; 1007 rbd->rbd_softc = sc; 1008 rbd->rbd_ring = &sc->sc_rx_ring[1]; 1009 /* Create DMA maps for standard RX buffers, ring 1. */ 1010 for (i = 0; i < ET_RX_NDESC; i++) { 1011 error = bus_dmamap_create(sc->sc_rx_tag, 0, 1012 &rbd->rbd_buf[i].rb_dmap); 1013 if (error) { 1014 device_printf(sc->dev, 1015 "could not create DMA map for mini RX mbufs\n"); 1016 return (error); 1017 } 1018 } 1019 1020 /* Create a spare DMA map for standard RX buffers, ring 1. */ 1021 error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap); 1022 if (error) { 1023 device_printf(sc->dev, 1024 "could not create spare DMA map for RX mbuf\n"); 1025 return (error); 1026 } 1027 1028 /* Create DMA maps for TX buffers. */ 1029 tbd = &sc->sc_tx_data; 1030 for (i = 0; i < ET_TX_NDESC; i++) { 1031 error = bus_dmamap_create(sc->sc_tx_tag, 0, 1032 &tbd->tbd_buf[i].tb_dmap); 1033 if (error) { 1034 device_printf(sc->dev, 1035 "could not create DMA map for TX mbufs\n"); 1036 return (error); 1037 } 1038 } 1039 1040 return (0); 1041 } 1042 1043 static void 1044 et_dma_free(struct et_softc *sc) 1045 { 1046 struct et_txdesc_ring *tx_ring; 1047 struct et_rxdesc_ring *rx_ring; 1048 struct et_txstatus_data *txsd; 1049 struct et_rxstat_ring *rxst_ring; 1050 struct et_rxbuf_data *rbd; 1051 struct et_txbuf_data *tbd; 1052 int i; 1053 1054 /* Destroy DMA maps for mini RX buffers, ring 0. */ 1055 rbd = &sc->sc_rx_data[0]; 1056 for (i = 0; i < ET_RX_NDESC; i++) { 1057 if (rbd->rbd_buf[i].rb_dmap) { 1058 bus_dmamap_destroy(sc->sc_rx_mini_tag, 1059 rbd->rbd_buf[i].rb_dmap); 1060 rbd->rbd_buf[i].rb_dmap = NULL; 1061 } 1062 } 1063 if (sc->sc_rx_mini_sparemap) { 1064 bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap); 1065 sc->sc_rx_mini_sparemap = NULL; 1066 } 1067 if (sc->sc_rx_mini_tag) { 1068 bus_dma_tag_destroy(sc->sc_rx_mini_tag); 1069 sc->sc_rx_mini_tag = NULL; 1070 } 1071 1072 /* Destroy DMA maps for standard RX buffers, ring 1. */ 1073 rbd = &sc->sc_rx_data[1]; 1074 for (i = 0; i < ET_RX_NDESC; i++) { 1075 if (rbd->rbd_buf[i].rb_dmap) { 1076 bus_dmamap_destroy(sc->sc_rx_tag, 1077 rbd->rbd_buf[i].rb_dmap); 1078 rbd->rbd_buf[i].rb_dmap = NULL; 1079 } 1080 } 1081 if (sc->sc_rx_sparemap) { 1082 bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap); 1083 sc->sc_rx_sparemap = NULL; 1084 } 1085 if (sc->sc_rx_tag) { 1086 bus_dma_tag_destroy(sc->sc_rx_tag); 1087 sc->sc_rx_tag = NULL; 1088 } 1089 1090 /* Destroy DMA maps for TX buffers. */ 1091 tbd = &sc->sc_tx_data; 1092 for (i = 0; i < ET_TX_NDESC; i++) { 1093 if (tbd->tbd_buf[i].tb_dmap) { 1094 bus_dmamap_destroy(sc->sc_tx_tag, 1095 tbd->tbd_buf[i].tb_dmap); 1096 tbd->tbd_buf[i].tb_dmap = NULL; 1097 } 1098 } 1099 if (sc->sc_tx_tag) { 1100 bus_dma_tag_destroy(sc->sc_tx_tag); 1101 sc->sc_tx_tag = NULL; 1102 } 1103 1104 /* Destroy mini RX ring, ring 0. */ 1105 rx_ring = &sc->sc_rx_ring[0]; 1106 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1107 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1108 /* Destroy standard RX ring, ring 1. */ 1109 rx_ring = &sc->sc_rx_ring[1]; 1110 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1111 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1112 /* Destroy RX stat ring. */ 1113 rxst_ring = &sc->sc_rxstat_ring; 1114 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1115 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1116 /* Destroy RX status block. */ 1117 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1118 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1119 /* Destroy TX ring. */ 1120 tx_ring = &sc->sc_tx_ring; 1121 et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc, 1122 tx_ring->tr_dmap, &tx_ring->tr_paddr); 1123 /* Destroy TX status block. */ 1124 txsd = &sc->sc_tx_status; 1125 et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status, 1126 txsd->txsd_dmap, &txsd->txsd_paddr); 1127 1128 /* Destroy the parent tag. */ 1129 if (sc->sc_dtag) { 1130 bus_dma_tag_destroy(sc->sc_dtag); 1131 sc->sc_dtag = NULL; 1132 } 1133 } 1134 1135 static void 1136 et_chip_attach(struct et_softc *sc) 1137 { 1138 uint32_t val; 1139 1140 /* 1141 * Perform minimal initialization 1142 */ 1143 1144 /* Disable loopback */ 1145 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1146 1147 /* Reset MAC */ 1148 CSR_WRITE_4(sc, ET_MAC_CFG1, 1149 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1150 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1151 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1152 1153 /* 1154 * Setup half duplex mode 1155 */ 1156 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1157 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1158 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1159 ET_MAC_HDX_EXC_DEFER; 1160 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1161 1162 /* Clear MAC control */ 1163 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1164 1165 /* Reset MII */ 1166 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1167 1168 /* Bring MAC out of reset state */ 1169 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1170 1171 /* Enable memory controllers */ 1172 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1173 } 1174 1175 static void 1176 et_intr(void *xsc) 1177 { 1178 struct et_softc *sc; 1179 if_t ifp; 1180 uint32_t status; 1181 1182 sc = xsc; 1183 ET_LOCK(sc); 1184 ifp = sc->ifp; 1185 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1186 goto done; 1187 1188 status = CSR_READ_4(sc, ET_INTR_STATUS); 1189 if ((status & ET_INTRS) == 0) 1190 goto done; 1191 1192 /* Disable further interrupts. */ 1193 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 1194 1195 if (status & (ET_INTR_RXDMA_ERROR | ET_INTR_TXDMA_ERROR)) { 1196 device_printf(sc->dev, "DMA error(0x%08x) -- resetting\n", 1197 status); 1198 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1199 et_init_locked(sc); 1200 ET_UNLOCK(sc); 1201 return; 1202 } 1203 if (status & ET_INTR_RXDMA) 1204 et_rxeof(sc); 1205 if (status & (ET_INTR_TXDMA | ET_INTR_TIMER)) 1206 et_txeof(sc); 1207 if (status & ET_INTR_TIMER) 1208 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1209 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1210 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1211 if (!if_sendq_empty(ifp)) 1212 et_start_locked(ifp); 1213 } 1214 done: 1215 ET_UNLOCK(sc); 1216 } 1217 1218 static void 1219 et_init_locked(struct et_softc *sc) 1220 { 1221 if_t ifp; 1222 int error; 1223 1224 ET_LOCK_ASSERT(sc); 1225 1226 ifp = sc->ifp; 1227 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1228 return; 1229 1230 et_stop(sc); 1231 et_reset(sc); 1232 1233 et_init_tx_ring(sc); 1234 error = et_init_rx_ring(sc); 1235 if (error) 1236 return; 1237 1238 error = et_chip_init(sc); 1239 if (error) 1240 goto fail; 1241 1242 /* 1243 * Start TX/RX DMA engine 1244 */ 1245 error = et_start_rxdma(sc); 1246 if (error) 1247 return; 1248 1249 error = et_start_txdma(sc); 1250 if (error) 1251 return; 1252 1253 /* Enable interrupts. */ 1254 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1255 1256 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1257 1258 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1259 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1260 1261 sc->sc_flags &= ~ET_FLAG_LINK; 1262 et_ifmedia_upd_locked(ifp); 1263 1264 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1265 1266 fail: 1267 if (error) 1268 et_stop(sc); 1269 } 1270 1271 static void 1272 et_init(void *xsc) 1273 { 1274 struct et_softc *sc = xsc; 1275 1276 ET_LOCK(sc); 1277 et_init_locked(sc); 1278 ET_UNLOCK(sc); 1279 } 1280 1281 static int 1282 et_ioctl(if_t ifp, u_long cmd, caddr_t data) 1283 { 1284 struct et_softc *sc; 1285 struct mii_data *mii; 1286 struct ifreq *ifr; 1287 int error, mask, max_framelen; 1288 1289 sc = if_getsoftc(ifp); 1290 ifr = (struct ifreq *)data; 1291 error = 0; 1292 1293 /* XXX LOCKSUSED */ 1294 switch (cmd) { 1295 case SIOCSIFFLAGS: 1296 ET_LOCK(sc); 1297 if (if_getflags(ifp) & IFF_UP) { 1298 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1299 if ((if_getflags(ifp) ^ sc->sc_if_flags) & 1300 (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1301 et_setmulti(sc); 1302 } else { 1303 et_init_locked(sc); 1304 } 1305 } else { 1306 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1307 et_stop(sc); 1308 } 1309 sc->sc_if_flags = if_getflags(ifp); 1310 ET_UNLOCK(sc); 1311 break; 1312 1313 case SIOCSIFMEDIA: 1314 case SIOCGIFMEDIA: 1315 mii = device_get_softc(sc->sc_miibus); 1316 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1317 break; 1318 1319 case SIOCADDMULTI: 1320 case SIOCDELMULTI: 1321 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1322 ET_LOCK(sc); 1323 et_setmulti(sc); 1324 ET_UNLOCK(sc); 1325 } 1326 break; 1327 1328 case SIOCSIFMTU: 1329 ET_LOCK(sc); 1330 #if 0 1331 if (sc->sc_flags & ET_FLAG_JUMBO) 1332 max_framelen = ET_JUMBO_FRAMELEN; 1333 else 1334 #endif 1335 max_framelen = MCLBYTES - 1; 1336 1337 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1338 error = EOPNOTSUPP; 1339 ET_UNLOCK(sc); 1340 break; 1341 } 1342 1343 if (if_getmtu(ifp) != ifr->ifr_mtu) { 1344 if_setmtu(ifp, ifr->ifr_mtu); 1345 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1346 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1347 et_init_locked(sc); 1348 } 1349 } 1350 ET_UNLOCK(sc); 1351 break; 1352 1353 case SIOCSIFCAP: 1354 ET_LOCK(sc); 1355 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1356 if ((mask & IFCAP_TXCSUM) != 0 && 1357 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1358 if_togglecapenable(ifp, IFCAP_TXCSUM); 1359 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 1360 if_sethwassistbits(ifp, ET_CSUM_FEATURES, 0); 1361 else 1362 if_sethwassistbits(ifp, 0, ET_CSUM_FEATURES); 1363 } 1364 ET_UNLOCK(sc); 1365 break; 1366 1367 default: 1368 error = ether_ioctl(ifp, cmd, data); 1369 break; 1370 } 1371 return (error); 1372 } 1373 1374 static void 1375 et_start_locked(if_t ifp) 1376 { 1377 struct et_softc *sc; 1378 struct mbuf *m_head = NULL; 1379 struct et_txdesc_ring *tx_ring; 1380 struct et_txbuf_data *tbd; 1381 uint32_t tx_ready_pos; 1382 int enq; 1383 1384 sc = if_getsoftc(ifp); 1385 ET_LOCK_ASSERT(sc); 1386 1387 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1388 IFF_DRV_RUNNING || 1389 (sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) != 1390 (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) 1391 return; 1392 1393 /* 1394 * Driver does not request TX completion interrupt for every 1395 * queued frames to prevent generating excessive interrupts. 1396 * This means driver may wait for TX completion interrupt even 1397 * though some frames were successfully transmitted. Reclaiming 1398 * transmitted frames will ensure driver see all available 1399 * descriptors. 1400 */ 1401 tbd = &sc->sc_tx_data; 1402 if (tbd->tbd_used > (ET_TX_NDESC * 2) / 3) 1403 et_txeof(sc); 1404 1405 for (enq = 0; !if_sendq_empty(ifp); ) { 1406 if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) { 1407 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1408 break; 1409 } 1410 1411 m_head = if_dequeue(ifp); 1412 if (m_head == NULL) 1413 break; 1414 1415 if (et_encap(sc, &m_head)) { 1416 if (m_head == NULL) { 1417 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1418 break; 1419 } 1420 if_sendq_prepend(ifp, m_head); 1421 if (tbd->tbd_used > 0) 1422 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1423 break; 1424 } 1425 enq++; 1426 ETHER_BPF_MTAP(ifp, m_head); 1427 } 1428 1429 if (enq > 0) { 1430 tx_ring = &sc->sc_tx_ring; 1431 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1432 BUS_DMASYNC_PREWRITE); 1433 tx_ready_pos = tx_ring->tr_ready_index & 1434 ET_TX_READY_POS_INDEX_MASK; 1435 if (tx_ring->tr_ready_wrap) 1436 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1437 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1438 sc->watchdog_timer = 5; 1439 } 1440 } 1441 1442 static void 1443 et_start(if_t ifp) 1444 { 1445 struct et_softc *sc; 1446 1447 sc = if_getsoftc(ifp); 1448 ET_LOCK(sc); 1449 et_start_locked(ifp); 1450 ET_UNLOCK(sc); 1451 } 1452 1453 static int 1454 et_watchdog(struct et_softc *sc) 1455 { 1456 uint32_t status; 1457 1458 ET_LOCK_ASSERT(sc); 1459 1460 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1461 return (0); 1462 1463 bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap, 1464 BUS_DMASYNC_POSTREAD); 1465 status = le32toh(*(sc->sc_tx_status.txsd_status)); 1466 if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n", 1467 status); 1468 1469 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 1470 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING); 1471 et_init_locked(sc); 1472 return (EJUSTRETURN); 1473 } 1474 1475 static int 1476 et_stop_rxdma(struct et_softc *sc) 1477 { 1478 1479 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1480 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1481 1482 DELAY(5); 1483 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1484 if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1485 return (ETIMEDOUT); 1486 } 1487 return (0); 1488 } 1489 1490 static int 1491 et_stop_txdma(struct et_softc *sc) 1492 { 1493 1494 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1495 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1496 return (0); 1497 } 1498 1499 static void 1500 et_free_tx_ring(struct et_softc *sc) 1501 { 1502 struct et_txbuf_data *tbd; 1503 struct et_txbuf *tb; 1504 int i; 1505 1506 tbd = &sc->sc_tx_data; 1507 for (i = 0; i < ET_TX_NDESC; ++i) { 1508 tb = &tbd->tbd_buf[i]; 1509 if (tb->tb_mbuf != NULL) { 1510 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 1511 BUS_DMASYNC_POSTWRITE); 1512 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1513 m_freem(tb->tb_mbuf); 1514 tb->tb_mbuf = NULL; 1515 } 1516 } 1517 } 1518 1519 static void 1520 et_free_rx_ring(struct et_softc *sc) 1521 { 1522 struct et_rxbuf_data *rbd; 1523 struct et_rxdesc_ring *rx_ring; 1524 struct et_rxbuf *rb; 1525 int i; 1526 1527 /* Ring 0 */ 1528 rx_ring = &sc->sc_rx_ring[0]; 1529 rbd = &sc->sc_rx_data[0]; 1530 for (i = 0; i < ET_RX_NDESC; ++i) { 1531 rb = &rbd->rbd_buf[i]; 1532 if (rb->rb_mbuf != NULL) { 1533 bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap, 1534 BUS_DMASYNC_POSTREAD); 1535 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 1536 m_freem(rb->rb_mbuf); 1537 rb->rb_mbuf = NULL; 1538 } 1539 } 1540 1541 /* Ring 1 */ 1542 rx_ring = &sc->sc_rx_ring[1]; 1543 rbd = &sc->sc_rx_data[1]; 1544 for (i = 0; i < ET_RX_NDESC; ++i) { 1545 rb = &rbd->rbd_buf[i]; 1546 if (rb->rb_mbuf != NULL) { 1547 bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap, 1548 BUS_DMASYNC_POSTREAD); 1549 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 1550 m_freem(rb->rb_mbuf); 1551 rb->rb_mbuf = NULL; 1552 } 1553 } 1554 } 1555 1556 static u_int 1557 et_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1558 { 1559 uint32_t h, *hp, *hash = arg; 1560 1561 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 1562 h = (h & 0x3f800000) >> 23; 1563 1564 hp = &hash[0]; 1565 if (h >= 32 && h < 64) { 1566 h -= 32; 1567 hp = &hash[1]; 1568 } else if (h >= 64 && h < 96) { 1569 h -= 64; 1570 hp = &hash[2]; 1571 } else if (h >= 96) { 1572 h -= 96; 1573 hp = &hash[3]; 1574 } 1575 *hp |= (1 << h); 1576 1577 return (1); 1578 } 1579 1580 static void 1581 et_setmulti(struct et_softc *sc) 1582 { 1583 if_t ifp; 1584 uint32_t hash[4] = { 0, 0, 0, 0 }; 1585 uint32_t rxmac_ctrl, pktfilt; 1586 int i, count; 1587 1588 ET_LOCK_ASSERT(sc); 1589 ifp = sc->ifp; 1590 1591 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1592 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1593 1594 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1595 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) { 1596 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1597 goto back; 1598 } 1599 1600 count = if_foreach_llmaddr(ifp, et_hash_maddr, &hash); 1601 1602 for (i = 0; i < 4; ++i) 1603 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1604 1605 if (count > 0) 1606 pktfilt |= ET_PKTFILT_MCAST; 1607 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1608 back: 1609 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1610 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1611 } 1612 1613 static int 1614 et_chip_init(struct et_softc *sc) 1615 { 1616 if_t ifp; 1617 uint32_t rxq_end; 1618 int error, frame_len, rxmem_size; 1619 1620 ifp = sc->ifp; 1621 /* 1622 * Split 16Kbytes internal memory between TX and RX 1623 * according to frame length. 1624 */ 1625 frame_len = ET_FRAMELEN(if_getmtu(ifp)); 1626 if (frame_len < 2048) { 1627 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1628 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1629 rxmem_size = ET_MEM_SIZE / 2; 1630 } else { 1631 rxmem_size = ET_MEM_SIZE - 1632 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1633 } 1634 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1635 1636 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1637 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1638 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1639 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1640 1641 /* No loopback */ 1642 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1643 1644 /* Clear MSI configure */ 1645 if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1646 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1647 1648 /* Disable timer */ 1649 CSR_WRITE_4(sc, ET_TIMER, 0); 1650 1651 /* Initialize MAC */ 1652 et_init_mac(sc); 1653 1654 /* Enable memory controllers */ 1655 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1656 1657 /* Initialize RX MAC */ 1658 et_init_rxmac(sc); 1659 1660 /* Initialize TX MAC */ 1661 et_init_txmac(sc); 1662 1663 /* Initialize RX DMA engine */ 1664 error = et_init_rxdma(sc); 1665 if (error) 1666 return (error); 1667 1668 /* Initialize TX DMA engine */ 1669 error = et_init_txdma(sc); 1670 if (error) 1671 return (error); 1672 1673 return (0); 1674 } 1675 1676 static void 1677 et_init_tx_ring(struct et_softc *sc) 1678 { 1679 struct et_txdesc_ring *tx_ring; 1680 struct et_txbuf_data *tbd; 1681 struct et_txstatus_data *txsd; 1682 1683 tx_ring = &sc->sc_tx_ring; 1684 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1685 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1686 BUS_DMASYNC_PREWRITE); 1687 1688 tbd = &sc->sc_tx_data; 1689 tbd->tbd_start_index = 0; 1690 tbd->tbd_start_wrap = 0; 1691 tbd->tbd_used = 0; 1692 1693 txsd = &sc->sc_tx_status; 1694 bzero(txsd->txsd_status, sizeof(uint32_t)); 1695 bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1696 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1697 } 1698 1699 static int 1700 et_init_rx_ring(struct et_softc *sc) 1701 { 1702 struct et_rxstatus_data *rxsd; 1703 struct et_rxstat_ring *rxst_ring; 1704 struct et_rxbuf_data *rbd; 1705 int i, error, n; 1706 1707 for (n = 0; n < ET_RX_NRING; ++n) { 1708 rbd = &sc->sc_rx_data[n]; 1709 for (i = 0; i < ET_RX_NDESC; ++i) { 1710 error = rbd->rbd_newbuf(rbd, i); 1711 if (error) { 1712 if_printf(sc->ifp, "%d ring %d buf, " 1713 "newbuf failed: %d\n", n, i, error); 1714 return (error); 1715 } 1716 } 1717 } 1718 1719 rxsd = &sc->sc_rx_status; 1720 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1721 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1722 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1723 1724 rxst_ring = &sc->sc_rxstat_ring; 1725 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1726 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1727 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1728 1729 return (0); 1730 } 1731 1732 static int 1733 et_init_rxdma(struct et_softc *sc) 1734 { 1735 struct et_rxstatus_data *rxsd; 1736 struct et_rxstat_ring *rxst_ring; 1737 struct et_rxdesc_ring *rx_ring; 1738 int error; 1739 1740 error = et_stop_rxdma(sc); 1741 if (error) { 1742 if_printf(sc->ifp, "can't init RX DMA engine\n"); 1743 return (error); 1744 } 1745 1746 /* 1747 * Install RX status 1748 */ 1749 rxsd = &sc->sc_rx_status; 1750 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1751 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1752 1753 /* 1754 * Install RX stat ring 1755 */ 1756 rxst_ring = &sc->sc_rxstat_ring; 1757 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1758 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1759 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1760 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1761 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1762 1763 /* Match ET_RXSTAT_POS */ 1764 rxst_ring->rsr_index = 0; 1765 rxst_ring->rsr_wrap = 0; 1766 1767 /* 1768 * Install the 2nd RX descriptor ring 1769 */ 1770 rx_ring = &sc->sc_rx_ring[1]; 1771 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1772 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1773 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1774 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1775 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1776 1777 /* Match ET_RX_RING1_POS */ 1778 rx_ring->rr_index = 0; 1779 rx_ring->rr_wrap = 1; 1780 1781 /* 1782 * Install the 1st RX descriptor ring 1783 */ 1784 rx_ring = &sc->sc_rx_ring[0]; 1785 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1786 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1787 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1788 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1789 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1790 1791 /* Match ET_RX_RING0_POS */ 1792 rx_ring->rr_index = 0; 1793 rx_ring->rr_wrap = 1; 1794 1795 /* 1796 * RX intr moderation 1797 */ 1798 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1799 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1800 1801 return (0); 1802 } 1803 1804 static int 1805 et_init_txdma(struct et_softc *sc) 1806 { 1807 struct et_txdesc_ring *tx_ring; 1808 struct et_txstatus_data *txsd; 1809 int error; 1810 1811 error = et_stop_txdma(sc); 1812 if (error) { 1813 if_printf(sc->ifp, "can't init TX DMA engine\n"); 1814 return (error); 1815 } 1816 1817 /* 1818 * Install TX descriptor ring 1819 */ 1820 tx_ring = &sc->sc_tx_ring; 1821 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1822 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1823 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1824 1825 /* 1826 * Install TX status 1827 */ 1828 txsd = &sc->sc_tx_status; 1829 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1830 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1831 1832 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1833 1834 /* Match ET_TX_READY_POS */ 1835 tx_ring->tr_ready_index = 0; 1836 tx_ring->tr_ready_wrap = 0; 1837 1838 return (0); 1839 } 1840 1841 static void 1842 et_init_mac(struct et_softc *sc) 1843 { 1844 if_t ifp; 1845 const uint8_t *eaddr; 1846 uint32_t val; 1847 1848 /* Reset MAC */ 1849 CSR_WRITE_4(sc, ET_MAC_CFG1, 1850 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1851 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1852 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1853 1854 /* 1855 * Setup inter packet gap 1856 */ 1857 val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1858 (88 << ET_IPG_NONB2B_2_SHIFT) | 1859 (80 << ET_IPG_MINIFG_SHIFT) | 1860 (96 << ET_IPG_B2B_SHIFT); 1861 CSR_WRITE_4(sc, ET_IPG, val); 1862 1863 /* 1864 * Setup half duplex mode 1865 */ 1866 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1867 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1868 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1869 ET_MAC_HDX_EXC_DEFER; 1870 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1871 1872 /* Clear MAC control */ 1873 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1874 1875 /* Reset MII */ 1876 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1877 1878 /* 1879 * Set MAC address 1880 */ 1881 ifp = sc->ifp; 1882 eaddr = if_getlladdr(ifp); 1883 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1884 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1885 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1886 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1887 1888 /* Set max frame length */ 1889 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(if_getmtu(ifp))); 1890 1891 /* Bring MAC out of reset state */ 1892 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1893 } 1894 1895 static void 1896 et_init_rxmac(struct et_softc *sc) 1897 { 1898 if_t ifp; 1899 const uint8_t *eaddr; 1900 uint32_t val; 1901 int i; 1902 1903 /* Disable RX MAC and WOL */ 1904 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1905 1906 /* 1907 * Clear all WOL related registers 1908 */ 1909 for (i = 0; i < 3; ++i) 1910 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1911 for (i = 0; i < 20; ++i) 1912 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1913 1914 /* 1915 * Set WOL source address. XXX is this necessary? 1916 */ 1917 ifp = sc->ifp; 1918 eaddr = if_getlladdr(ifp); 1919 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1920 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1921 val = (eaddr[0] << 8) | eaddr[1]; 1922 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1923 1924 /* Clear packet filters */ 1925 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1926 1927 /* No ucast filtering */ 1928 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1929 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1930 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1931 1932 if (ET_FRAMELEN(if_getmtu(ifp)) > ET_RXMAC_CUT_THRU_FRMLEN) { 1933 /* 1934 * In order to transmit jumbo packets greater than 1935 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1936 * RX MAC and RX DMA needs to be reduced in size to 1937 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1938 * order to implement this, we must use "cut through" 1939 * mode in the RX MAC, which chops packets down into 1940 * segments. In this case we selected 256 bytes, 1941 * since this is the size of the PCI-Express TLP's 1942 * that the ET1310 uses. 1943 */ 1944 val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1945 ET_RXMAC_MC_SEGSZ_ENABLE; 1946 } else { 1947 val = 0; 1948 } 1949 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1950 1951 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1952 1953 /* Initialize RX MAC management register */ 1954 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1955 1956 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1957 1958 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1959 ET_RXMAC_MGT_PASS_ECRC | 1960 ET_RXMAC_MGT_PASS_ELEN | 1961 ET_RXMAC_MGT_PASS_ETRUNC | 1962 ET_RXMAC_MGT_CHECK_PKT); 1963 1964 /* 1965 * Configure runt filtering (may not work on certain chip generation) 1966 */ 1967 val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1968 ET_PKTFILT_MINLEN_MASK; 1969 val |= ET_PKTFILT_FRAG; 1970 CSR_WRITE_4(sc, ET_PKTFILT, val); 1971 1972 /* Enable RX MAC but leave WOL disabled */ 1973 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1974 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1975 1976 /* 1977 * Setup multicast hash and allmulti/promisc mode 1978 */ 1979 et_setmulti(sc); 1980 } 1981 1982 static void 1983 et_init_txmac(struct et_softc *sc) 1984 { 1985 1986 /* Disable TX MAC and FC(?) */ 1987 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1988 1989 /* 1990 * Initialize pause time. 1991 * This register should be set before XON/XOFF frame is 1992 * sent by driver. 1993 */ 1994 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT); 1995 1996 /* Enable TX MAC but leave FC(?) diabled */ 1997 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1998 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1999 } 2000 2001 static int 2002 et_start_rxdma(struct et_softc *sc) 2003 { 2004 uint32_t val; 2005 2006 val = (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 2007 ET_RXDMA_CTRL_RING0_ENABLE; 2008 val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 2009 ET_RXDMA_CTRL_RING1_ENABLE; 2010 2011 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 2012 2013 DELAY(5); 2014 2015 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 2016 if_printf(sc->ifp, "can't start RX DMA engine\n"); 2017 return (ETIMEDOUT); 2018 } 2019 return (0); 2020 } 2021 2022 static int 2023 et_start_txdma(struct et_softc *sc) 2024 { 2025 2026 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 2027 return (0); 2028 } 2029 2030 static void 2031 et_rxeof(struct et_softc *sc) 2032 { 2033 struct et_rxstatus_data *rxsd; 2034 struct et_rxstat_ring *rxst_ring; 2035 struct et_rxbuf_data *rbd; 2036 struct et_rxdesc_ring *rx_ring; 2037 struct et_rxstat *st; 2038 if_t ifp; 2039 struct mbuf *m; 2040 uint32_t rxstat_pos, rxring_pos; 2041 uint32_t rxst_info1, rxst_info2, rxs_stat_ring; 2042 int buflen, buf_idx, npost[2], ring_idx; 2043 int rxst_index, rxst_wrap; 2044 2045 ET_LOCK_ASSERT(sc); 2046 2047 ifp = sc->ifp; 2048 rxsd = &sc->sc_rx_status; 2049 rxst_ring = &sc->sc_rxstat_ring; 2050 2051 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2052 return; 2053 2054 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2055 BUS_DMASYNC_POSTREAD); 2056 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2057 BUS_DMASYNC_POSTREAD); 2058 2059 npost[0] = npost[1] = 0; 2060 rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 2061 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 2062 rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 2063 ET_RXS_STATRING_INDEX_SHIFT; 2064 2065 while (rxst_index != rxst_ring->rsr_index || 2066 rxst_wrap != rxst_ring->rsr_wrap) { 2067 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2068 break; 2069 2070 MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 2071 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 2072 rxst_info1 = le32toh(st->rxst_info1); 2073 rxst_info2 = le32toh(st->rxst_info2); 2074 buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 2075 ET_RXST_INFO2_LEN_SHIFT; 2076 buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 2077 ET_RXST_INFO2_BUFIDX_SHIFT; 2078 ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 2079 ET_RXST_INFO2_RINGIDX_SHIFT; 2080 2081 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 2082 rxst_ring->rsr_index = 0; 2083 rxst_ring->rsr_wrap ^= 1; 2084 } 2085 rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 2086 if (rxst_ring->rsr_wrap) 2087 rxstat_pos |= ET_RXSTAT_POS_WRAP; 2088 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 2089 2090 if (ring_idx >= ET_RX_NRING) { 2091 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2092 if_printf(ifp, "invalid ring index %d\n", ring_idx); 2093 continue; 2094 } 2095 if (buf_idx >= ET_RX_NDESC) { 2096 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2097 if_printf(ifp, "invalid buf index %d\n", buf_idx); 2098 continue; 2099 } 2100 2101 rbd = &sc->sc_rx_data[ring_idx]; 2102 m = rbd->rbd_buf[buf_idx].rb_mbuf; 2103 if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){ 2104 /* Discard errored frame. */ 2105 rbd->rbd_discard(rbd, buf_idx); 2106 } else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) { 2107 /* No available mbufs, discard it. */ 2108 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2109 rbd->rbd_discard(rbd, buf_idx); 2110 } else { 2111 buflen -= ETHER_CRC_LEN; 2112 if (buflen < ETHER_HDR_LEN) { 2113 m_freem(m); 2114 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2115 } else { 2116 m->m_pkthdr.len = m->m_len = buflen; 2117 m->m_pkthdr.rcvif = ifp; 2118 ET_UNLOCK(sc); 2119 if_input(ifp, m); 2120 ET_LOCK(sc); 2121 } 2122 } 2123 2124 rx_ring = &sc->sc_rx_ring[ring_idx]; 2125 if (buf_idx != rx_ring->rr_index) { 2126 if_printf(ifp, 2127 "WARNING!! ring %d, buf_idx %d, rr_idx %d\n", 2128 ring_idx, buf_idx, rx_ring->rr_index); 2129 } 2130 2131 MPASS(rx_ring->rr_index < ET_RX_NDESC); 2132 if (++rx_ring->rr_index == ET_RX_NDESC) { 2133 rx_ring->rr_index = 0; 2134 rx_ring->rr_wrap ^= 1; 2135 } 2136 rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2137 if (rx_ring->rr_wrap) 2138 rxring_pos |= ET_RX_RING_POS_WRAP; 2139 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2140 } 2141 2142 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2143 BUS_DMASYNC_PREREAD); 2144 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2145 BUS_DMASYNC_PREREAD); 2146 } 2147 2148 static int 2149 et_encap(struct et_softc *sc, struct mbuf **m0) 2150 { 2151 struct et_txdesc_ring *tx_ring; 2152 struct et_txbuf_data *tbd; 2153 struct et_txdesc *td; 2154 struct mbuf *m; 2155 bus_dma_segment_t segs[ET_NSEG_MAX]; 2156 bus_dmamap_t map; 2157 uint32_t csum_flags, last_td_ctrl2; 2158 int error, i, idx, first_idx, last_idx, nsegs; 2159 2160 tx_ring = &sc->sc_tx_ring; 2161 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2162 tbd = &sc->sc_tx_data; 2163 first_idx = tx_ring->tr_ready_index; 2164 map = tbd->tbd_buf[first_idx].tb_dmap; 2165 2166 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs, 2167 0); 2168 if (error == EFBIG) { 2169 m = m_collapse(*m0, M_NOWAIT, ET_NSEG_MAX); 2170 if (m == NULL) { 2171 m_freem(*m0); 2172 *m0 = NULL; 2173 return (ENOMEM); 2174 } 2175 *m0 = m; 2176 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, 2177 &nsegs, 0); 2178 if (error != 0) { 2179 m_freem(*m0); 2180 *m0 = NULL; 2181 return (error); 2182 } 2183 } else if (error != 0) 2184 return (error); 2185 2186 /* Check for descriptor overruns. */ 2187 if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) { 2188 bus_dmamap_unload(sc->sc_tx_tag, map); 2189 return (ENOBUFS); 2190 } 2191 bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2192 2193 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2194 sc->sc_tx += nsegs; 2195 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2196 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2197 last_td_ctrl2 |= ET_TDCTRL2_INTR; 2198 } 2199 2200 m = *m0; 2201 csum_flags = 0; 2202 if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2203 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2204 csum_flags |= ET_TDCTRL2_CSUM_IP; 2205 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2206 csum_flags |= ET_TDCTRL2_CSUM_UDP; 2207 else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2208 csum_flags |= ET_TDCTRL2_CSUM_TCP; 2209 } 2210 last_idx = -1; 2211 for (i = 0; i < nsegs; ++i) { 2212 idx = (first_idx + i) % ET_TX_NDESC; 2213 td = &tx_ring->tr_desc[idx]; 2214 td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2215 td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2216 td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2217 if (i == nsegs - 1) { 2218 /* Last frag */ 2219 td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2220 last_idx = idx; 2221 } else 2222 td->td_ctrl2 = htole32(csum_flags); 2223 2224 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2225 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2226 tx_ring->tr_ready_index = 0; 2227 tx_ring->tr_ready_wrap ^= 1; 2228 } 2229 } 2230 td = &tx_ring->tr_desc[first_idx]; 2231 /* First frag */ 2232 td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); 2233 2234 MPASS(last_idx >= 0); 2235 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2236 tbd->tbd_buf[last_idx].tb_dmap = map; 2237 tbd->tbd_buf[last_idx].tb_mbuf = m; 2238 2239 tbd->tbd_used += nsegs; 2240 MPASS(tbd->tbd_used <= ET_TX_NDESC); 2241 2242 return (0); 2243 } 2244 2245 static void 2246 et_txeof(struct et_softc *sc) 2247 { 2248 struct et_txdesc_ring *tx_ring; 2249 struct et_txbuf_data *tbd; 2250 struct et_txbuf *tb; 2251 if_t ifp; 2252 uint32_t tx_done; 2253 int end, wrap; 2254 2255 ET_LOCK_ASSERT(sc); 2256 2257 ifp = sc->ifp; 2258 tx_ring = &sc->sc_tx_ring; 2259 tbd = &sc->sc_tx_data; 2260 2261 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2262 return; 2263 2264 if (tbd->tbd_used == 0) 2265 return; 2266 2267 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2268 BUS_DMASYNC_POSTWRITE); 2269 2270 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2271 end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2272 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2273 2274 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2275 MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2276 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2277 if (tb->tb_mbuf != NULL) { 2278 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 2279 BUS_DMASYNC_POSTWRITE); 2280 bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap); 2281 m_freem(tb->tb_mbuf); 2282 tb->tb_mbuf = NULL; 2283 } 2284 2285 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2286 tbd->tbd_start_index = 0; 2287 tbd->tbd_start_wrap ^= 1; 2288 } 2289 2290 MPASS(tbd->tbd_used > 0); 2291 tbd->tbd_used--; 2292 } 2293 2294 if (tbd->tbd_used == 0) 2295 sc->watchdog_timer = 0; 2296 if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC) 2297 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2298 } 2299 2300 static void 2301 et_tick(void *xsc) 2302 { 2303 struct et_softc *sc; 2304 struct mii_data *mii; 2305 2306 sc = xsc; 2307 ET_LOCK_ASSERT(sc); 2308 mii = device_get_softc(sc->sc_miibus); 2309 2310 mii_tick(mii); 2311 et_stats_update(sc); 2312 if (et_watchdog(sc) == EJUSTRETURN) 2313 return; 2314 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2315 } 2316 2317 static int 2318 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx) 2319 { 2320 struct et_softc *sc; 2321 struct et_rxdesc *desc; 2322 struct et_rxbuf *rb; 2323 struct mbuf *m; 2324 bus_dma_segment_t segs[1]; 2325 bus_dmamap_t dmap; 2326 int nsegs; 2327 2328 MPASS(buf_idx < ET_RX_NDESC); 2329 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2330 if (m == NULL) 2331 return (ENOBUFS); 2332 m->m_len = m->m_pkthdr.len = MCLBYTES; 2333 m_adj(m, ETHER_ALIGN); 2334 2335 sc = rbd->rbd_softc; 2336 rb = &rbd->rbd_buf[buf_idx]; 2337 2338 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m, 2339 segs, &nsegs, 0) != 0) { 2340 m_freem(m); 2341 return (ENOBUFS); 2342 } 2343 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2344 2345 if (rb->rb_mbuf != NULL) { 2346 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, 2347 BUS_DMASYNC_POSTREAD); 2348 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 2349 } 2350 dmap = rb->rb_dmap; 2351 rb->rb_dmap = sc->sc_rx_sparemap; 2352 sc->sc_rx_sparemap = dmap; 2353 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2354 2355 rb->rb_mbuf = m; 2356 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2357 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2358 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2359 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2360 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2361 BUS_DMASYNC_PREWRITE); 2362 return (0); 2363 } 2364 2365 static void 2366 et_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx) 2367 { 2368 struct et_rxdesc *desc; 2369 2370 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2371 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2372 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2373 BUS_DMASYNC_PREWRITE); 2374 } 2375 2376 static int 2377 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx) 2378 { 2379 struct et_softc *sc; 2380 struct et_rxdesc *desc; 2381 struct et_rxbuf *rb; 2382 struct mbuf *m; 2383 bus_dma_segment_t segs[1]; 2384 bus_dmamap_t dmap; 2385 int nsegs; 2386 2387 MPASS(buf_idx < ET_RX_NDESC); 2388 MGETHDR(m, M_NOWAIT, MT_DATA); 2389 if (m == NULL) 2390 return (ENOBUFS); 2391 m->m_len = m->m_pkthdr.len = MHLEN; 2392 m_adj(m, ETHER_ALIGN); 2393 2394 sc = rbd->rbd_softc; 2395 rb = &rbd->rbd_buf[buf_idx]; 2396 2397 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap, 2398 m, segs, &nsegs, 0) != 0) { 2399 m_freem(m); 2400 return (ENOBUFS); 2401 } 2402 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2403 2404 if (rb->rb_mbuf != NULL) { 2405 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, 2406 BUS_DMASYNC_POSTREAD); 2407 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 2408 } 2409 dmap = rb->rb_dmap; 2410 rb->rb_dmap = sc->sc_rx_mini_sparemap; 2411 sc->sc_rx_mini_sparemap = dmap; 2412 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2413 2414 rb->rb_mbuf = m; 2415 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2416 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2417 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2418 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2419 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2420 BUS_DMASYNC_PREWRITE); 2421 return (0); 2422 } 2423 2424 #define ET_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2425 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2426 #define ET_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2427 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2428 2429 /* 2430 * Create sysctl tree 2431 */ 2432 static void 2433 et_add_sysctls(struct et_softc * sc) 2434 { 2435 struct sysctl_ctx_list *ctx; 2436 struct sysctl_oid_list *children, *parent; 2437 struct sysctl_oid *tree; 2438 struct et_hw_stats *stats; 2439 2440 ctx = device_get_sysctl_ctx(sc->dev); 2441 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2442 2443 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2444 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2445 et_sysctl_rx_intr_npkts, "I", "RX IM, # packets per RX interrupt"); 2446 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2447 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2448 et_sysctl_rx_intr_delay, "I", 2449 "RX IM, RX interrupt delay (x10 usec)"); 2450 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2451 CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2452 "TX IM, # segments per TX interrupt"); 2453 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2454 CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2455 2456 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 2457 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ET statistics"); 2458 parent = SYSCTL_CHILDREN(tree); 2459 2460 /* TX/RX statistics. */ 2461 stats = &sc->sc_stats; 2462 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_64", &stats->pkts_64, 2463 "0 to 64 bytes frames"); 2464 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_65_127", &stats->pkts_65, 2465 "65 to 127 bytes frames"); 2466 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_128_255", &stats->pkts_128, 2467 "128 to 255 bytes frames"); 2468 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_256_511", &stats->pkts_256, 2469 "256 to 511 bytes frames"); 2470 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_512_1023", &stats->pkts_512, 2471 "512 to 1023 bytes frames"); 2472 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1024_1518", &stats->pkts_1024, 2473 "1024 to 1518 bytes frames"); 2474 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1519_1522", &stats->pkts_1519, 2475 "1519 to 1522 bytes frames"); 2476 2477 /* RX statistics. */ 2478 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2479 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 2480 children = SYSCTL_CHILDREN(tree); 2481 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2482 &stats->rx_bytes, "Good bytes"); 2483 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2484 &stats->rx_frames, "Good frames"); 2485 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2486 &stats->rx_crcerrs, "CRC errors"); 2487 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2488 &stats->rx_mcast, "Multicast frames"); 2489 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2490 &stats->rx_bcast, "Broadcast frames"); 2491 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2492 &stats->rx_control, "Control frames"); 2493 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2494 &stats->rx_pause, "Pause frames"); 2495 ET_SYSCTL_STAT_ADD32(ctx, children, "unknown_control", 2496 &stats->rx_unknown_control, "Unknown control frames"); 2497 ET_SYSCTL_STAT_ADD32(ctx, children, "align_errs", 2498 &stats->rx_alignerrs, "Alignment errors"); 2499 ET_SYSCTL_STAT_ADD32(ctx, children, "len_errs", 2500 &stats->rx_lenerrs, "Frames with length mismatched"); 2501 ET_SYSCTL_STAT_ADD32(ctx, children, "code_errs", 2502 &stats->rx_codeerrs, "Frames with code error"); 2503 ET_SYSCTL_STAT_ADD32(ctx, children, "cs_errs", 2504 &stats->rx_cserrs, "Frames with carrier sense error"); 2505 ET_SYSCTL_STAT_ADD32(ctx, children, "runts", 2506 &stats->rx_runts, "Too short frames"); 2507 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2508 &stats->rx_oversize, "Oversized frames"); 2509 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2510 &stats->rx_fragments, "Fragmented frames"); 2511 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2512 &stats->rx_jabbers, "Frames with jabber error"); 2513 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2514 &stats->rx_drop, "Dropped frames"); 2515 2516 /* TX statistics. */ 2517 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2518 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 2519 children = SYSCTL_CHILDREN(tree); 2520 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2521 &stats->tx_bytes, "Good bytes"); 2522 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2523 &stats->tx_frames, "Good frames"); 2524 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2525 &stats->tx_mcast, "Multicast frames"); 2526 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2527 &stats->tx_bcast, "Broadcast frames"); 2528 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2529 &stats->tx_pause, "Pause frames"); 2530 ET_SYSCTL_STAT_ADD32(ctx, children, "deferred", 2531 &stats->tx_deferred, "Deferred frames"); 2532 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_deferred", 2533 &stats->tx_excess_deferred, "Excessively deferred frames"); 2534 ET_SYSCTL_STAT_ADD32(ctx, children, "single_colls", 2535 &stats->tx_single_colls, "Single collisions"); 2536 ET_SYSCTL_STAT_ADD32(ctx, children, "multi_colls", 2537 &stats->tx_multi_colls, "Multiple collisions"); 2538 ET_SYSCTL_STAT_ADD32(ctx, children, "late_colls", 2539 &stats->tx_late_colls, "Late collisions"); 2540 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_colls", 2541 &stats->tx_excess_colls, "Excess collisions"); 2542 ET_SYSCTL_STAT_ADD32(ctx, children, "total_colls", 2543 &stats->tx_total_colls, "Total collisions"); 2544 ET_SYSCTL_STAT_ADD32(ctx, children, "pause_honored", 2545 &stats->tx_pause_honored, "Honored pause frames"); 2546 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2547 &stats->tx_drop, "Dropped frames"); 2548 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2549 &stats->tx_jabbers, "Frames with jabber errors"); 2550 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2551 &stats->tx_crcerrs, "Frames with CRC errors"); 2552 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2553 &stats->tx_control, "Control frames"); 2554 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2555 &stats->tx_oversize, "Oversized frames"); 2556 ET_SYSCTL_STAT_ADD32(ctx, children, "undersize", 2557 &stats->tx_undersize, "Undersized frames"); 2558 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2559 &stats->tx_fragments, "Fragmented frames"); 2560 } 2561 2562 #undef ET_SYSCTL_STAT_ADD32 2563 #undef ET_SYSCTL_STAT_ADD64 2564 2565 static int 2566 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2567 { 2568 struct et_softc *sc; 2569 if_t ifp; 2570 int error, v; 2571 2572 sc = arg1; 2573 ifp = sc->ifp; 2574 v = sc->sc_rx_intr_npkts; 2575 error = sysctl_handle_int(oidp, &v, 0, req); 2576 if (error || req->newptr == NULL) 2577 goto back; 2578 if (v <= 0) { 2579 error = EINVAL; 2580 goto back; 2581 } 2582 2583 if (sc->sc_rx_intr_npkts != v) { 2584 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2585 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2586 sc->sc_rx_intr_npkts = v; 2587 } 2588 back: 2589 return (error); 2590 } 2591 2592 static int 2593 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2594 { 2595 struct et_softc *sc; 2596 if_t ifp; 2597 int error, v; 2598 2599 sc = arg1; 2600 ifp = sc->ifp; 2601 v = sc->sc_rx_intr_delay; 2602 error = sysctl_handle_int(oidp, &v, 0, req); 2603 if (error || req->newptr == NULL) 2604 goto back; 2605 if (v <= 0) { 2606 error = EINVAL; 2607 goto back; 2608 } 2609 2610 if (sc->sc_rx_intr_delay != v) { 2611 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2612 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2613 sc->sc_rx_intr_delay = v; 2614 } 2615 back: 2616 return (error); 2617 } 2618 2619 static void 2620 et_stats_update(struct et_softc *sc) 2621 { 2622 struct et_hw_stats *stats; 2623 2624 stats = &sc->sc_stats; 2625 stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64); 2626 stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127); 2627 stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255); 2628 stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511); 2629 stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023); 2630 stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518); 2631 stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522); 2632 2633 stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES); 2634 stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES); 2635 stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR); 2636 stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST); 2637 stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST); 2638 stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL); 2639 stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE); 2640 stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL); 2641 stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR); 2642 stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR); 2643 stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR); 2644 stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR); 2645 stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT); 2646 stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE); 2647 stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG); 2648 stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER); 2649 stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP); 2650 2651 stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES); 2652 stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES); 2653 stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST); 2654 stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST); 2655 stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE); 2656 stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER); 2657 stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER); 2658 stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL); 2659 stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL); 2660 stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL); 2661 stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL); 2662 stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL); 2663 stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR); 2664 stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP); 2665 stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER); 2666 stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR); 2667 stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL); 2668 stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE); 2669 stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE); 2670 stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG); 2671 } 2672 2673 static uint64_t 2674 et_get_counter(if_t ifp, ift_counter cnt) 2675 { 2676 struct et_softc *sc; 2677 struct et_hw_stats *stats; 2678 2679 sc = if_getsoftc(ifp); 2680 stats = &sc->sc_stats; 2681 2682 switch (cnt) { 2683 case IFCOUNTER_OPACKETS: 2684 return (stats->tx_frames); 2685 case IFCOUNTER_COLLISIONS: 2686 return (stats->tx_total_colls); 2687 case IFCOUNTER_OERRORS: 2688 return (stats->tx_drop + stats->tx_jabbers + 2689 stats->tx_crcerrs + stats->tx_excess_deferred + 2690 stats->tx_late_colls); 2691 case IFCOUNTER_IPACKETS: 2692 return (stats->rx_frames); 2693 case IFCOUNTER_IERRORS: 2694 return (stats->rx_crcerrs + stats->rx_alignerrs + 2695 stats->rx_lenerrs + stats->rx_codeerrs + stats->rx_cserrs + 2696 stats->rx_runts + stats->rx_jabbers + stats->rx_drop); 2697 default: 2698 return (if_get_counter_default(ifp, cnt)); 2699 } 2700 } 2701 2702 static int 2703 et_suspend(device_t dev) 2704 { 2705 struct et_softc *sc; 2706 uint32_t pmcfg; 2707 2708 sc = device_get_softc(dev); 2709 ET_LOCK(sc); 2710 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) != 0) 2711 et_stop(sc); 2712 /* Diable all clocks and put PHY into COMA. */ 2713 pmcfg = CSR_READ_4(sc, ET_PM); 2714 pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | 2715 ET_PM_RXCLK_GATE); 2716 pmcfg |= ET_PM_PHY_SW_COMA; 2717 CSR_WRITE_4(sc, ET_PM, pmcfg); 2718 ET_UNLOCK(sc); 2719 return (0); 2720 } 2721 2722 static int 2723 et_resume(device_t dev) 2724 { 2725 struct et_softc *sc; 2726 uint32_t pmcfg; 2727 2728 sc = device_get_softc(dev); 2729 ET_LOCK(sc); 2730 /* Take PHY out of COMA and enable clocks. */ 2731 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 2732 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 2733 pmcfg |= EM_PM_GIGEPHY_ENB; 2734 CSR_WRITE_4(sc, ET_PM, pmcfg); 2735 if ((if_getflags(sc->ifp) & IFF_UP) != 0) 2736 et_init_locked(sc); 2737 ET_UNLOCK(sc); 2738 return (0); 2739 } 2740