1 /*- 2 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.3 2007/10/23 14:28:42 sephe Exp $ 35 * $FreeBSD$ 36 */ 37 /*- 38 * Portions of this code is derived from NetBSD which is covered by 39 * the following license: 40 * 41 * Copyright (c) 2004, 2005 David Young. All rights reserved. 42 * 43 * Programmed for NetBSD by David Young. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. The name of David Young may not be used to endorse or promote 54 * products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 58 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 59 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 60 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 61 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 62 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 63 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 65 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 67 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 68 * OF SUCH DAMAGE. 69 * 70 * $DragonFly: src/sys/sys/bitops.h,v 1.1 2007/10/14 04:15:17 sephe Exp $ 71 */ 72 73 #ifndef _IF_ETREG_H 74 #define _IF_ETREG_H 75 76 #define ET_MEM_TXSIZE_EX 182 77 #define ET_MEM_RXSIZE_MIN 608 78 #define ET_MEM_RXSIZE_DEFAULT 11216 79 #define ET_MEM_SIZE 16384 80 #define ET_MEM_UNIT 16 81 82 /* 83 * PCI registers 84 * 85 * ET_PCIV_ACK_LATENCY_{128,256} are from 86 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-5 87 * 88 * ET_PCIV_REPLAY_TIMER_{128,256} are from 89 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4 90 */ 91 #define ET_PCIR_BAR PCIR_BAR(0) 92 93 #define ET_PCIR_DEVICE_CAPS 0x4c 94 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */ 95 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0 96 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1 97 98 #define ET_PCIR_DEVICE_CTRL 0x50 99 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */ 100 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000 101 102 #define ET_PCIR_MAC_ADDR0 0xa4 103 #define ET_PCIR_MAC_ADDR1 0xa8 104 105 #define ET_PCIR_EEPROM_STATUS 0xb2 /* XXX undocumented */ 106 #define ET_PCIM_EEPROM_STATUS_ERROR 0x4c 107 108 #define ET_PCIR_ACK_LATENCY 0xc0 109 #define ET_PCIV_ACK_LATENCY_128 237 110 #define ET_PCIV_ACK_LATENCY_256 416 111 112 #define ET_PCIR_REPLAY_TIMER 0xc2 113 #define ET_REPLAY_TIMER_RX_L0S_ADJ 250 /* XXX infered from default */ 114 #define ET_PCIV_REPLAY_TIMER_128 (711 + ET_REPLAY_TIMER_RX_L0S_ADJ) 115 #define ET_PCIV_REPLAY_TIMER_256 (1248 + ET_REPLAY_TIMER_RX_L0S_ADJ) 116 117 #define ET_PCIR_L0S_L1_LATENCY 0xcf 118 119 /* 120 * CSR 121 */ 122 #define ET_TXQUEUE_START 0x0000 123 #define ET_TXQUEUE_END 0x0004 124 #define ET_RXQUEUE_START 0x0008 125 #define ET_RXQUEUE_END 0x000c 126 #define ET_QUEUE_ADDR(addr) (((addr) / ET_MEM_UNIT) - 1) 127 #define ET_QUEUE_ADDR_START 0 128 #define ET_QUEUE_ADDR_END ET_QUEUE_ADDR(ET_MEM_SIZE) 129 130 #define ET_PM 0x0010 131 #define ET_PM_SYSCLK_GATE 0x00000008 132 #define ET_PM_TXCLK_GATE 0x00000010 133 #define ET_PM_RXCLK_GATE 0x00000020 134 135 #define ET_INTR_STATUS 0x0018 136 #define ET_INTR_MASK 0x001c 137 138 #define ET_SWRST 0x0028 139 #define ET_SWRST_TXDMA 0x00000001 140 #define ET_SWRST_RXDMA 0x00000002 141 #define ET_SWRST_TXMAC 0x00000004 142 #define ET_SWRST_RXMAC 0x00000008 143 #define ET_SWRST_MAC 0x00000010 144 #define ET_SWRST_MAC_STAT 0x00000020 145 #define ET_SWRST_MMC 0x00000040 146 #define ET_SWRST_SELFCLR_DISABLE 0x80000000 147 148 #define ET_MSI_CFG 0x0030 149 150 #define ET_LOOPBACK 0x0034 151 152 #define ET_TIMER 0x0038 153 154 #define ET_TXDMA_CTRL 0x1000 155 #define ET_TXDMA_CTRL_HALT 0x00000001 156 #define ET_TXDMA_CTRL_CACHE_THR_MASK 0x000000F0 157 #define ET_TXDMA_CTRL_SINGLE_EPKT 0x00000100 /* ??? */ 158 159 #define ET_TX_RING_HI 0x1004 160 #define ET_TX_RING_LO 0x1008 161 #define ET_TX_RING_CNT 0x100c 162 163 #define ET_TX_STATUS_HI 0x101c 164 #define ET_TX_STATUS_LO 0x1020 165 166 #define ET_TX_READY_POS 0x1024 167 #define ET_TX_READY_POS_INDEX_MASK 0x000003FF 168 #define ET_TX_READY_POS_WRAP 0x00000400 169 170 #define ET_TX_DONE_POS 0x1060 171 #define ET_TX_DONE_POS_INDEX_MASK 0x0000003FF 172 #define ET_TX_DONE_POS_WRAP 0x000000400 173 174 #define ET_RXDMA_CTRL 0x2000 175 #define ET_RXDMA_CTRL_HALT 0x00000001 176 #define ET_RXDMA_CTRL_RING0_SIZE_MASK 0x00000300 177 #define ET_RXDMA_CTRL_RING0_128 0x00000000 /* 127 */ 178 #define ET_RXDMA_CTRL_RING0_256 0x00000100 /* 255 */ 179 #define ET_RXDMA_CTRL_RING0_512 0x00000200 /* 511 */ 180 #define ET_RXDMA_CTRL_RING0_1024 0x00000300 /* 1023 */ 181 #define ET_RXDMA_CTRL_RING0_ENABLE 0x00000400 182 #define ET_RXDMA_CTRL_RING1_SIZE_MASK 0x00001800 183 #define ET_RXDMA_CTRL_RING1_2048 0x00000000 /* 2047 */ 184 #define ET_RXDMA_CTRL_RING1_4096 0x00000800 /* 4095 */ 185 #define ET_RXDMA_CTRL_RING1_8192 0x00001000 /* 8191 */ 186 #define ET_RXDMA_CTRL_RING1_16384 0x00001800 /* 16383 (9022?) */ 187 #define ET_RXDMA_CTRL_RING1_ENABLE 0x00002000 188 #define ET_RXDMA_CTRL_HALTED 0x00020000 189 190 #define ET_RX_STATUS_LO 0x2004 191 #define ET_RX_STATUS_HI 0x2008 192 193 #define ET_RX_INTR_NPKTS 0x200c 194 #define ET_RX_INTR_DELAY 0x2010 195 196 #define ET_RXSTAT_LO 0x2020 197 #define ET_RXSTAT_HI 0x2024 198 #define ET_RXSTAT_CNT 0x2028 199 200 #define ET_RXSTAT_POS 0x2030 201 #define ET_RXSTAT_POS_INDEX_MASK 0x00000FFF 202 #define ET_RXSTAT_POS_WRAP 0x00001000 203 204 #define ET_RXSTAT_MINCNT 0x2038 205 206 #define ET_RX_RING0_LO 0x203c 207 #define ET_RX_RING0_HI 0x2040 208 #define ET_RX_RING0_CNT 0x2044 209 210 #define ET_RX_RING0_POS 0x204c 211 #define ET_RX_RING0_POS_INDEX_MASK 0x000003FF 212 #define ET_RX_RING0_POS_WRAP 0x00000400 213 214 #define ET_RX_RING0_MINCNT 0x2054 215 216 #define ET_RX_RING1_LO 0x2058 217 #define ET_RX_RING1_HI 0x205c 218 #define ET_RX_RING1_CNT 0x2060 219 220 #define ET_RX_RING1_POS 0x2068 221 #define ET_RX_RING1_POS_INDEX 0x000003FF 222 #define ET_RX_RING1_POS_WRAP 0x00000400 223 224 #define ET_RX_RING1_MINCNT 0x2070 225 226 #define ET_TXMAC_CTRL 0x3000 227 #define ET_TXMAC_CTRL_ENABLE 0x00000001 228 #define ET_TXMAC_CTRL_FC_DISABLE 0x00000008 229 230 #define ET_TXMAC_FLOWCTRL 0x3010 231 232 #define ET_RXMAC_CTRL 0x4000 233 #define ET_RXMAC_CTRL_ENABLE 0x00000001 234 #define ET_RXMAC_CTRL_NO_PKTFILT 0x00000004 235 #define ET_RXMAC_CTRL_WOL_DISABLE 0x00000008 236 237 #define ET_WOL_CRC 0x4004 238 #define ET_WOL_SA_LO 0x4010 239 #define ET_WOL_SA_HI 0x4014 240 #define ET_WOL_MASK 0x4018 241 242 #define ET_UCAST_FILTADDR1 0x4068 243 #define ET_UCAST_FILTADDR2 0x406c 244 #define ET_UCAST_FILTADDR3 0x4070 245 246 #define ET_MULTI_HASH 0x4074 247 248 #define ET_PKTFILT 0x4084 249 #define ET_PKTFILT_BCAST 0x00000001 250 #define ET_PKTFILT_MCAST 0x00000002 251 #define ET_PKTFILT_UCAST 0x00000004 252 #define ET_PKTFILT_FRAG 0x00000008 253 #define ET_PKTFILT_MINLEN_MASK 0x007F0000 254 #define ET_PKTFILT_MINLEN_SHIFT 16 255 256 #define ET_RXMAC_MC_SEGSZ 0x4088 257 #define ET_RXMAC_MC_SEGSZ_ENABLE 0x00000001 258 #define ET_RXMAC_MC_SEGSZ_FC 0x00000002 259 #define ET_RXMAC_MC_SEGSZ_MAX_MASK 0x000003FC 260 #define ET_RXMAC_SEGSZ(segsz) ((segsz) / ET_MEM_UNIT) 261 #define ET_RXMAC_CUT_THRU_FRMLEN 8074 262 263 #define ET_RXMAC_MC_WATERMARK 0x408c 264 #define ET_RXMAC_SPACE_AVL 0x4094 265 266 #define ET_RXMAC_MGT 0x4098 267 #define ET_RXMAC_MGT_PASS_ECRC 0x00000010 268 #define ET_RXMAC_MGT_PASS_ELEN 0x00000020 269 #define ET_RXMAC_MGT_PASS_ETRUNC 0x00010000 270 #define ET_RXMAC_MGT_CHECK_PKT 0x00020000 271 272 #define ET_MAC_CFG1 0x5000 273 #define ET_MAC_CFG1_TXEN 0x00000001 274 #define ET_MAC_CFG1_SYNC_TXEN 0x00000002 275 #define ET_MAC_CFG1_RXEN 0x00000004 276 #define ET_MAC_CFG1_SYNC_RXEN 0x00000008 277 #define ET_MAC_CFG1_TXFLOW 0x00000010 278 #define ET_MAC_CFG1_RXFLOW 0x00000020 279 #define ET_MAC_CFG1_LOOPBACK 0x00000100 280 #define ET_MAC_CFG1_RST_TXFUNC 0x00010000 281 #define ET_MAC_CFG1_RST_RXFUNC 0x00020000 282 #define ET_MAC_CFG1_RST_TXMC 0x00040000 283 #define ET_MAC_CFG1_RST_RXMC 0x00080000 284 #define ET_MAC_CFG1_SIM_RST 0x40000000 285 #define ET_MAC_CFG1_SOFT_RST 0x80000000 286 287 #define ET_MAC_CFG2 0x5004 288 #define ET_MAC_CFG2_FDX 0x00000001 289 #define ET_MAC_CFG2_CRC 0x00000002 290 #define ET_MAC_CFG2_PADCRC 0x00000004 291 #define ET_MAC_CFG2_LENCHK 0x00000010 292 #define ET_MAC_CFG2_BIGFRM 0x00000020 293 #define ET_MAC_CFG2_MODE_MII 0x00000100 294 #define ET_MAC_CFG2_MODE_GMII 0x00000200 295 #define ET_MAC_CFG2_PREAMBLE_LEN_MASK 0x0000F000 296 #define ET_MAC_CFG2_PREAMBLE_LEN_SHIFT 12 297 298 #define ET_IPG 0x5008 299 #define ET_IPG_B2B_MASK 0x0000007F 300 #define ET_IPG_MINIFG_MASK 0x0000FF00 301 #define ET_IPG_NONB2B_2_MASK 0x007F0000 302 #define ET_IPG_NONB2B_1_MASK 0x7F000000 303 #define ET_IPG_B2B_SHIFT 0 304 #define ET_IPG_MINIFG_SHIFT 8 305 #define ET_IPG_NONB2B_2_SHIFT 16 306 #define ET_IPG_NONB2B_1_SHIFT 24 307 308 #define ET_MAC_HDX 0x500c 309 #define ET_MAC_HDX_COLLWIN_MASK 0x000003FF 310 #define ET_MAC_HDX_REXMIT_MAX_MASK 0x0000F000 311 #define ET_MAC_HDX_EXC_DEFER 0x00010000 312 #define ET_MAC_HDX_NOBACKOFF 0x00020000 313 #define ET_MAC_HDX_BP_NOBACKOFF 0x00040000 314 #define ET_MAC_HDX_ALT_BEB 0x00080000 315 #define ET_MAC_HDX_ALT_BEB_TRUNC_MASK 0x00F00000 316 #define ET_MAC_HDX_COLLWIN_SHIFT 0 317 #define ET_MAC_HDX_REXMIT_MAX_SHIFT 12 318 #define ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT 20 319 320 #define ET_MAX_FRMLEN 0x5010 321 322 #define ET_MII_CFG 0x5020 323 #define ET_MII_CFG_CLKRST 0x00000007 324 #define ET_MII_CFG_PREAMBLE_SUP 0x00000010 325 #define ET_MII_CFG_SCAN_AUTOINC 0x00000020 326 #define ET_MII_CFG_RST 0x80000000 327 328 #define ET_MII_CMD 0x5024 329 #define ET_MII_CMD_READ 0x00000001 330 331 #define ET_MII_ADDR 0x5028 332 #define ET_MII_ADDR_REG_MASK 0x0000001F 333 #define ET_MII_ADDR_PHY_MASK 0x00001F00 334 #define ET_MII_ADDR_REG_SHIFT 0 335 #define ET_MII_ADDR_PHY_SHIFT 8 336 337 #define ET_MII_CTRL 0x502c 338 #define ET_MII_CTRL_VALUE_MASK 0x0000FFFF 339 #define ET_MII_CTRL_VALUE_SHIFT 0 340 341 #define ET_MII_STAT 0x5030 342 #define ET_MII_STAT_VALUE_MASK 0x0000FFFF 343 344 #define ET_MII_IND 0x5034 345 #define ET_MII_IND_BUSY 0x00000001 346 #define ET_MII_IND_INVALID 0x00000004 347 348 #define ET_MAC_CTRL 0x5038 349 #define ET_MAC_CTRL_MODE_MII 0x01000000 350 #define ET_MAC_CTRL_LHDX 0x02000000 351 #define ET_MAC_CTRL_GHDX 0x04000000 352 353 #define ET_MAC_ADDR1 0x5040 354 #define ET_MAC_ADDR2 0x5044 355 356 #define ET_MMC_CTRL 0x7000 357 #define ET_MMC_CTRL_ENABLE 0x00000001 358 #define ET_MMC_CTRL_ARB_DISABLE 0x00000002 359 #define ET_MMC_CTRL_RXMAC_DISABLE 0x00000004 360 #define ET_MMC_CTRL_TXMAC_DISABLE 0x00000008 361 #define ET_MMC_CTRL_TXDMA_DISABLE 0x00000010 362 #define ET_MMC_CTRL_RXDMA_DISABLE 0x00000020 363 #define ET_MMC_CTRL_FORCE_CE 0x00000040 364 365 /* 366 * Interrupts 367 */ 368 #define ET_INTR_TXEOF 0x00000008 369 #define ET_INTR_TXDMA_ERROR 0x00000010 370 #define ET_INTR_RXEOF 0x00000020 371 #define ET_INTR_RXRING0_LOW 0x00000040 372 #define ET_INTR_RXRING1_LOW 0x00000080 373 #define ET_INTR_RXSTAT_LOW 0x00000100 374 #define ET_INTR_RXDMA_ERROR 0x00000200 375 #define ET_INTR_TIMER 0x00004000 376 #define ET_INTR_WOL 0x00008000 377 #define ET_INTR_PHY 0x00010000 378 #define ET_INTR_TXMAC 0x00020000 379 #define ET_INTR_RXMAC 0x00040000 380 #define ET_INTR_MAC_STATS 0x00080000 381 #define ET_INTR_SLAVE_TO 0x00100000 382 383 #define ET_INTRS (ET_INTR_TXEOF | \ 384 ET_INTR_RXEOF | \ 385 ET_INTR_TIMER) 386 387 /* 388 * RX ring position uses same layout 389 */ 390 #define ET_RX_RING_POS_INDEX_MASK 0x000003FF 391 #define ET_RX_RING_POS_WRAP 0x00000400 392 393 /* 394 * PCI IDs 395 */ 396 #define PCI_VENDOR_LUCENT 0x11c1 397 #define PCI_PRODUCT_LUCENT_ET1310 0xed00 /* ET1310 10/100/1000M Ethernet */ 398 #define PCI_PRODUCT_LUCENT_ET1310_FAST 0xed01 /* ET1310 10/100M Ethernet */ 399 400 #endif /* !_IF_ETREG_H */ 401