1e388de98SAdrian Chadd /*-
24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
3e388de98SAdrian Chadd *
4e388de98SAdrian Chadd * Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
5e388de98SAdrian Chadd *
6e388de98SAdrian Chadd * Redistribution and use in source and binary forms, with or without
7e388de98SAdrian Chadd * modification, are permitted provided that the following conditions
8e388de98SAdrian Chadd * are met:
9e388de98SAdrian Chadd * 1. Redistributions of source code must retain the above copyright
10e388de98SAdrian Chadd * notice, this list of conditions and the following disclaimer.
11e388de98SAdrian Chadd * 2. Redistributions in binary form must reproduce the above copyright
12e388de98SAdrian Chadd * notice, this list of conditions and the following disclaimer in the
13e388de98SAdrian Chadd * documentation and/or other materials provided with the distribution.
14e388de98SAdrian Chadd *
15e388de98SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16e388de98SAdrian Chadd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17e388de98SAdrian Chadd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18e388de98SAdrian Chadd * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19e388de98SAdrian Chadd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20e388de98SAdrian Chadd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21e388de98SAdrian Chadd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22e388de98SAdrian Chadd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23e388de98SAdrian Chadd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24e388de98SAdrian Chadd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25e388de98SAdrian Chadd * SUCH DAMAGE.
26e388de98SAdrian Chadd */
27e388de98SAdrian Chadd
28e388de98SAdrian Chadd #include <sys/param.h>
29e388de98SAdrian Chadd #include <sys/bus.h>
30e388de98SAdrian Chadd #include <sys/errno.h>
31e388de98SAdrian Chadd #include <sys/kernel.h>
32e388de98SAdrian Chadd #include <sys/malloc.h>
33e388de98SAdrian Chadd #include <sys/module.h>
34e388de98SAdrian Chadd #include <sys/socket.h>
35e388de98SAdrian Chadd #include <sys/sockio.h>
36e388de98SAdrian Chadd #include <sys/sysctl.h>
37e388de98SAdrian Chadd #include <sys/systm.h>
38e388de98SAdrian Chadd
39e388de98SAdrian Chadd #include <net/if.h>
40e388de98SAdrian Chadd #include <net/if_var.h>
41e388de98SAdrian Chadd #include <net/if_arp.h>
42e388de98SAdrian Chadd #include <net/ethernet.h>
43e388de98SAdrian Chadd #include <net/if_dl.h>
44e388de98SAdrian Chadd #include <net/if_media.h>
45e388de98SAdrian Chadd #include <net/if_types.h>
46e388de98SAdrian Chadd
47e388de98SAdrian Chadd #include <machine/bus.h>
48e388de98SAdrian Chadd #include <dev/iicbus/iic.h>
49e388de98SAdrian Chadd #include <dev/iicbus/iiconf.h>
50e388de98SAdrian Chadd #include <dev/iicbus/iicbus.h>
51e388de98SAdrian Chadd #include <dev/mii/mii.h>
52e388de98SAdrian Chadd #include <dev/mii/miivar.h>
53e388de98SAdrian Chadd #include <dev/mdio/mdio.h>
54be82b3a0SEmmanuel Vadot #include <dev/clk/clk.h>
551f469a9fSEmmanuel Vadot #include <dev/hwreset/hwreset.h>
56e388de98SAdrian Chadd
57e388de98SAdrian Chadd #include <dev/fdt/fdt_common.h>
58e388de98SAdrian Chadd #include <dev/ofw/ofw_bus.h>
59e388de98SAdrian Chadd #include <dev/ofw/ofw_bus_subr.h>
60e388de98SAdrian Chadd
61e388de98SAdrian Chadd #include <dev/etherswitch/etherswitch.h>
62e388de98SAdrian Chadd
63e388de98SAdrian Chadd #include <dev/etherswitch/ar40xx/ar40xx_var.h>
64e388de98SAdrian Chadd #include <dev/etherswitch/ar40xx/ar40xx_reg.h>
65e388de98SAdrian Chadd #include <dev/etherswitch/ar40xx/ar40xx_hw.h>
66e388de98SAdrian Chadd #include <dev/etherswitch/ar40xx/ar40xx_hw_atu.h>
67e388de98SAdrian Chadd #include <dev/etherswitch/ar40xx/ar40xx_debug.h>
68e388de98SAdrian Chadd
69e388de98SAdrian Chadd #include "mdio_if.h"
70e388de98SAdrian Chadd #include "miibus_if.h"
71e388de98SAdrian Chadd #include "etherswitch_if.h"
72e388de98SAdrian Chadd
73e388de98SAdrian Chadd int
ar40xx_hw_atu_wait_busy(struct ar40xx_softc * sc)74e388de98SAdrian Chadd ar40xx_hw_atu_wait_busy(struct ar40xx_softc *sc)
75e388de98SAdrian Chadd {
76e388de98SAdrian Chadd int ret;
77e388de98SAdrian Chadd
78e388de98SAdrian Chadd ret = ar40xx_hw_wait_bit(sc, AR40XX_REG_ATU_FUNC,
79e388de98SAdrian Chadd AR40XX_ATU_FUNC_BUSY, 0);
80e388de98SAdrian Chadd return (ret);
81e388de98SAdrian Chadd }
82e388de98SAdrian Chadd
83e388de98SAdrian Chadd int
ar40xx_hw_atu_flush_all(struct ar40xx_softc * sc)84e388de98SAdrian Chadd ar40xx_hw_atu_flush_all(struct ar40xx_softc *sc)
85e388de98SAdrian Chadd {
86e388de98SAdrian Chadd int ret;
87e388de98SAdrian Chadd
88e388de98SAdrian Chadd AR40XX_LOCK_ASSERT(sc);
89e388de98SAdrian Chadd
90e388de98SAdrian Chadd AR40XX_DPRINTF(sc, AR40XX_DBG_ATU_OP, "%s: called\n", __func__);
91e388de98SAdrian Chadd ret = ar40xx_hw_atu_wait_busy(sc);
92e388de98SAdrian Chadd if (ret != 0)
93e388de98SAdrian Chadd return (ret);
94e388de98SAdrian Chadd
95e388de98SAdrian Chadd AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC,
96e388de98SAdrian Chadd AR40XX_ATU_FUNC_OP_FLUSH
97e388de98SAdrian Chadd | AR40XX_ATU_FUNC_BUSY);
98e388de98SAdrian Chadd AR40XX_REG_BARRIER_WRITE(sc);
99e388de98SAdrian Chadd
100e388de98SAdrian Chadd return (ret);
101e388de98SAdrian Chadd }
102e388de98SAdrian Chadd
103e388de98SAdrian Chadd int
ar40xx_hw_atu_flush_port(struct ar40xx_softc * sc,int port)104e388de98SAdrian Chadd ar40xx_hw_atu_flush_port(struct ar40xx_softc *sc, int port)
105e388de98SAdrian Chadd {
106e388de98SAdrian Chadd uint32_t val;
107e388de98SAdrian Chadd int ret;
108e388de98SAdrian Chadd
109e388de98SAdrian Chadd AR40XX_LOCK_ASSERT(sc);
110e388de98SAdrian Chadd
111e388de98SAdrian Chadd AR40XX_DPRINTF(sc, AR40XX_DBG_ATU_OP, "%s: called, port=%d\n",
112e388de98SAdrian Chadd __func__, port);
113e388de98SAdrian Chadd
114e388de98SAdrian Chadd if (port >= AR40XX_NUM_PORTS) {
115e388de98SAdrian Chadd return (EINVAL);
116e388de98SAdrian Chadd }
117e388de98SAdrian Chadd
118e388de98SAdrian Chadd ret = ar40xx_hw_atu_wait_busy(sc);
119e388de98SAdrian Chadd if (ret != 0)
120e388de98SAdrian Chadd return (ret);
121e388de98SAdrian Chadd
122e388de98SAdrian Chadd val = AR40XX_ATU_FUNC_OP_FLUSH_UNICAST;
123e388de98SAdrian Chadd val |= (port << AR40XX_ATU_FUNC_PORT_NUM_S)
124e388de98SAdrian Chadd & AR40XX_ATU_FUNC_PORT_NUM;
125e388de98SAdrian Chadd
126e388de98SAdrian Chadd AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC,
127e388de98SAdrian Chadd val | AR40XX_ATU_FUNC_BUSY);
128e388de98SAdrian Chadd AR40XX_REG_BARRIER_WRITE(sc);
129e388de98SAdrian Chadd
130e388de98SAdrian Chadd return (0);
131e388de98SAdrian Chadd }
132e388de98SAdrian Chadd
133e388de98SAdrian Chadd int
ar40xx_hw_atu_fetch_entry(struct ar40xx_softc * sc,etherswitch_atu_entry_t * e,int atu_fetch_op)134e388de98SAdrian Chadd ar40xx_hw_atu_fetch_entry(struct ar40xx_softc *sc, etherswitch_atu_entry_t *e,
135e388de98SAdrian Chadd int atu_fetch_op)
136e388de98SAdrian Chadd {
137e388de98SAdrian Chadd uint32_t ret0, ret1, ret2, val;
138e388de98SAdrian Chadd int ret;
139e388de98SAdrian Chadd
140e388de98SAdrian Chadd AR40XX_LOCK_ASSERT(sc);
141e388de98SAdrian Chadd
142e388de98SAdrian Chadd switch (atu_fetch_op) {
143e388de98SAdrian Chadd case 0:
144e388de98SAdrian Chadd /* Initialise things for the first fetch */
145e388de98SAdrian Chadd
146e388de98SAdrian Chadd AR40XX_DPRINTF(sc, AR40XX_DBG_ATU_OP,
147e388de98SAdrian Chadd "%s: initializing\n", __func__);
148e388de98SAdrian Chadd
149e388de98SAdrian Chadd ret = ar40xx_hw_atu_wait_busy(sc);
150e388de98SAdrian Chadd if (ret != 0)
151e388de98SAdrian Chadd return (ret);
152e388de98SAdrian Chadd
153e388de98SAdrian Chadd AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC,
154e388de98SAdrian Chadd AR40XX_ATU_FUNC_OP_GET_NEXT);
155e388de98SAdrian Chadd AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA0, 0);
156e388de98SAdrian Chadd AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA1, 0);
157e388de98SAdrian Chadd AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA2, 0);
158e388de98SAdrian Chadd AR40XX_REG_BARRIER_WRITE(sc);
159e388de98SAdrian Chadd
160e388de98SAdrian Chadd return (0);
161e388de98SAdrian Chadd case 1:
162e388de98SAdrian Chadd AR40XX_DPRINTF(sc, AR40XX_DBG_ATU_OP,
163e388de98SAdrian Chadd "%s: reading next\n", __func__);
164e388de98SAdrian Chadd /*
165e388de98SAdrian Chadd * Attempt to read the next address entry; don't modify what
166e388de98SAdrian Chadd * is there in these registers as its used for the next fetch
167e388de98SAdrian Chadd */
168e388de98SAdrian Chadd ret = ar40xx_hw_atu_wait_busy(sc);
169e388de98SAdrian Chadd if (ret != 0)
170e388de98SAdrian Chadd return (ret);
171e388de98SAdrian Chadd
172e388de98SAdrian Chadd /* Begin the next read event; not modifying anything */
173e388de98SAdrian Chadd AR40XX_REG_BARRIER_READ(sc);
174e388de98SAdrian Chadd val = AR40XX_REG_READ(sc, AR40XX_REG_ATU_FUNC);
175e388de98SAdrian Chadd val |= AR40XX_ATU_FUNC_BUSY;
176e388de98SAdrian Chadd AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC, val);
177e388de98SAdrian Chadd AR40XX_REG_BARRIER_WRITE(sc);
178e388de98SAdrian Chadd
179e388de98SAdrian Chadd /* Wait for it to complete */
180e388de98SAdrian Chadd ret = ar40xx_hw_atu_wait_busy(sc);
181e388de98SAdrian Chadd if (ret != 0)
182e388de98SAdrian Chadd return (ret);
183e388de98SAdrian Chadd
184e388de98SAdrian Chadd /* Fetch the ethernet address and ATU status */
185e388de98SAdrian Chadd AR40XX_REG_BARRIER_READ(sc);
186e388de98SAdrian Chadd ret0 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA0);
187e388de98SAdrian Chadd ret1 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA1);
188e388de98SAdrian Chadd ret2 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA2);
189e388de98SAdrian Chadd
190e388de98SAdrian Chadd /* If the status is zero, then we're done */
191e388de98SAdrian Chadd if (MS(ret2, AR40XX_ATU_FUNC_DATA2_STATUS) == 0)
192e388de98SAdrian Chadd return (ENOENT);
193e388de98SAdrian Chadd
194e388de98SAdrian Chadd /* MAC address */
195e388de98SAdrian Chadd e->es_macaddr[5] = MS(ret0, AR40XX_ATU_DATA0_MAC_ADDR3);
196e388de98SAdrian Chadd e->es_macaddr[4] = MS(ret0, AR40XX_ATU_DATA0_MAC_ADDR2);
197e388de98SAdrian Chadd e->es_macaddr[3] = MS(ret0, AR40XX_ATU_DATA0_MAC_ADDR1);
198e388de98SAdrian Chadd e->es_macaddr[2] = MS(ret0, AR40XX_ATU_DATA0_MAC_ADDR0);
199e388de98SAdrian Chadd e->es_macaddr[0] = MS(ret1, AR40XX_ATU_DATA1_MAC_ADDR5);
200e388de98SAdrian Chadd e->es_macaddr[1] = MS(ret1, AR40XX_ATU_DATA1_MAC_ADDR4);
201e388de98SAdrian Chadd
202e388de98SAdrian Chadd /* Bitmask of ports this entry is for */
203e388de98SAdrian Chadd e->es_portmask = MS(ret1, AR40XX_ATU_DATA1_DEST_PORT);
204e388de98SAdrian Chadd
205e388de98SAdrian Chadd /* TODO: other flags that are interesting */
206e388de98SAdrian Chadd
207e388de98SAdrian Chadd AR40XX_DPRINTF(sc, AR40XX_DBG_ATU_OP,
208e388de98SAdrian Chadd "%s: MAC %6D portmask 0x%08x\n",
209e388de98SAdrian Chadd __func__,
210e388de98SAdrian Chadd e->es_macaddr, ":", e->es_portmask);
211e388de98SAdrian Chadd return (0);
212e388de98SAdrian Chadd default:
213e388de98SAdrian Chadd return (EINVAL);
214e388de98SAdrian Chadd }
215e388de98SAdrian Chadd return (EINVAL);
216e388de98SAdrian Chadd }
217