xref: /freebsd/sys/dev/firewire/fwphyreg.h (revision 81ad6265)
1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
3  *
4  * Copyright (C) 2003
5  * 	Hidetoshi Shimokawa. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *
18  *	This product includes software developed by Hidetoshi Shimokawa.
19  *
20  * 4. Neither the name of the author nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  * $FreeBSD$
37  */
38 
39 /*
40  * IEEE 1394a
41  * Figure 5B - 1
42  */
43 struct phyreg_base {
44 #if BYTE_ORDER == BIG_ENDIAN
45 	uint8_t	phy_id:6,
46 		r:1,
47 		cps:1;
48 	uint8_t	rhb:1,
49 		ibr:1,
50 		gap_count:6;
51 	uint8_t	extended:3,
52 		num_ports:5;
53 	uint8_t	phy_speed:3,
54 		:1,
55 		delay:4;
56 	uint8_t	lctrl:1,
57 		c:1,
58 		jitter:3,
59 		pwr_class:3;
60 	uint8_t	wdie:1,
61 		isbr:1,
62 		ctoi:1,
63 		cpsi:1,
64 		stoi:1,
65 		pei:1,
66 		eaa:1,
67 		emc:1;
68 	uint8_t	legacy_spd:3,
69 		blink:1,
70 		bridge:2,
71 		:2;
72 	uint8_t	page_select:3,
73 		:1,
74 		port_select:4;
75 #else
76 	uint8_t	cps:1,
77 		r:1,
78 		phy_id:6;
79 	uint8_t	gap_count:6,
80 		ibr:1,
81 		rhb:1;
82 	uint8_t	num_ports:5,
83 		extended:3;
84 	uint8_t	delay:4,
85 		:1,
86 		phy_speed:3;
87 	uint8_t	pwr_class:3,
88 		jitter:3,
89 		c:1,
90 		lctrl:1;
91 	uint8_t	emc:1,
92 		eaa:1,
93 		pei:1,
94 		stoi:1,
95 		cpsi:1,
96 		ctoi:1,
97 		isbr:1,
98 		wdie:1;
99 	uint8_t	:2,
100 		bridge:2,
101 		blink:1,
102 		legacy_spd:3;
103 	uint8_t	port_select:4,
104 		:1,
105 		page_select:3;
106 #endif
107 };
108 
109 /*
110  * IEEE 1394a
111  * Figure 5B - 2
112  */
113 struct phyreg_page0 {
114 #if BYTE_ORDER == BIG_ENDIAN
115 	uint8_t	astat:2,
116 		bstat:2,
117 		ch:1,
118 		con:1,
119 		rxok:1,
120 		dis:1;
121 	uint8_t	negotiated_speed:3,
122 		pie:1,
123 		fault:1,
124 		stanby_fault:1,
125 		disscrm:1,
126 		b_only:1;
127 	uint8_t	dc_connected:1,
128 		max_port_speed:3,
129 		lpp:1,
130 		cable_speed:3;
131 	uint8_t	connection_unreliable:1,
132 		:3,
133 		beta_mode:1,
134 		:3;
135 	uint8_t	port_error;
136 	uint8_t	:5,
137 		loop_disable:1,
138 		in_standby:1,
139 		hard_disable:1;
140 	uint8_t	:8;
141 	uint8_t	:8;
142 #else
143 	uint8_t	dis:1,
144 		rxok:1,
145 		con:1,
146 		ch:1,
147 		bstat:2,
148 		astat:2;
149 	uint8_t	b_only:1,
150 		disscrm:1,
151 		stanby_fault:1,
152 		fault:1,
153 		pie:1,
154 		negotiated_speed:3;
155 	uint8_t	cable_speed:3,
156 		lpp:1,
157 		max_port_speed:3,
158 		dc_connected:1;
159 	uint8_t	:3,
160 		beta_mode:1,
161 		:3,
162 		connection_unreliable:1;
163 	uint8_t	port_error;
164 	uint8_t	hard_disable:1,
165 		in_standby:1,
166 		loop_disable:1,
167 		:5;
168 	uint8_t	:8;
169 	uint8_t	:8;
170 #endif
171 };
172 
173 /*
174  * IEEE 1394a
175  * Figure 5B - 3
176  */
177 struct phyreg_page1 {
178 	uint8_t	compliance;
179 	uint8_t	:8;
180 	uint8_t	vendor_id[3];
181 	uint8_t	product_id[3];
182 };
183