xref: /freebsd/sys/dev/fxp/if_fxpvar.h (revision 0957b409)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 1995, David Greenman
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice unmodified, this list of conditions, and the following
12  *    disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $FreeBSD$
30  */
31 
32 /*
33  * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
34  * Ethernet driver
35  */
36 
37 /*
38  * Number of transmit control blocks. This determines the number
39  * of transmit buffers that can be chained in the CB list.
40  * This must be a power of two.
41  */
42 #define FXP_NTXCB       128
43 #define	FXP_NTXCB_HIWAT	((FXP_NTXCB * 7) / 10)
44 
45 /*
46  * Maximum size of a DMA segment.
47  */
48 #define	FXP_TSO_SEGSIZE	4096
49 
50 /*
51  * Size of the TxCB list.
52  */
53 #define FXP_TXCB_SZ	(FXP_NTXCB * sizeof(struct fxp_cb_tx))
54 
55 /*
56  * Macro to obtain the DMA address of a virtual address in the
57  * TxCB list based on the base DMA address of the TxCB list.
58  */
59 #define FXP_TXCB_DMA_ADDR(sc, addr)					\
60 	(sc->fxp_desc.cbl_addr + (uintptr_t)addr -			\
61 	(uintptr_t)sc->fxp_desc.cbl_list)
62 
63 /*
64  * Number of completed TX commands at which point an interrupt
65  * will be generated to garbage collect the attached buffers.
66  * Must be at least one less than FXP_NTXCB, and should be
67  * enough less so that the transmitter doesn't becomes idle
68  * during the buffer rundown (which would reduce performance).
69  */
70 #define FXP_CXINT_THRESH 120
71 
72 /*
73  * TxCB list index mask. This is used to do list wrap-around.
74  */
75 #define FXP_TXCB_MASK   (FXP_NTXCB - 1)
76 
77 /*
78  * Number of receive frame area buffers. These are large so chose
79  * wisely.
80  */
81 #ifdef DEVICE_POLLING
82 #define FXP_NRFABUFS	192
83 #else
84 #define FXP_NRFABUFS    64
85 #endif
86 
87 /*
88  * Maximum number of seconds that the receiver can be idle before we
89  * assume it's dead and attempt to reset it by reprogramming the
90  * multicast filter. This is part of a work-around for a bug in the
91  * NIC. See fxp_stats_update().
92  */
93 #define FXP_MAX_RX_IDLE 15
94 
95 /*
96  * Default maximum time, in microseconds, that an interrupt may be delayed
97  * in an attempt to coalesce interrupts.  This is only effective if the Intel
98  * microcode is loaded, and may be changed via either loader tunables or
99  * sysctl.  See also the CPUSAVER_DWORD entry in rcvbundl.h.
100  */
101 #define TUNABLE_INT_DELAY 1000
102 
103 /*
104  * Default number of packets that will be bundled, before an interrupt is
105  * generated.  This is only effective if the Intel microcode is loaded, and
106  * may be changed via either loader tunables or sysctl.  This may not be
107  * present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD
108  * entry in rcvbundl.h.
109  */
110 #define TUNABLE_BUNDLE_MAX 6
111 
112 #define	FXP_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
113 #define	FXP_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
114 #define	FXP_LOCK_ASSERT(_sc, _what)	mtx_assert(&(_sc)->sc_mtx, (_what))
115 
116 /*
117  * Structures to handle TX and RX descriptors.
118  */
119 struct fxp_rx {
120 	struct fxp_rx *rx_next;
121 	struct mbuf *rx_mbuf;
122 	bus_dmamap_t rx_map;
123 	uint32_t rx_addr;
124 };
125 
126 struct fxp_tx {
127 	struct fxp_tx *tx_next;
128 	struct fxp_cb_tx *tx_cb;
129 	struct mbuf *tx_mbuf;
130 	bus_dmamap_t tx_map;
131 };
132 
133 struct fxp_desc_list {
134 	struct fxp_rx rx_list[FXP_NRFABUFS];
135 	struct fxp_tx tx_list[FXP_NTXCB];
136 	struct fxp_tx mcs_tx;
137 	struct fxp_rx *rx_head;
138 	struct fxp_rx *rx_tail;
139 	struct fxp_tx *tx_first;
140 	struct fxp_tx *tx_last;
141 	struct fxp_rfa *rfa_list;
142 	struct fxp_cb_tx *cbl_list;
143 	uint32_t cbl_addr;
144 	bus_dma_tag_t rx_tag;
145 };
146 
147 struct fxp_ident {
148 	uint16_t	vendor;
149 	uint16_t	device;
150 	int16_t		revid;		/* -1 matches anything */
151 	uint8_t		ich;
152 	const char	*name;
153 };
154 
155 struct fxp_hwstats {
156 	uint32_t tx_good;
157 	uint32_t tx_maxcols;
158 	uint32_t tx_latecols;
159 	uint32_t tx_underruns;
160 	uint32_t tx_lostcrs;
161 	uint32_t tx_deffered;
162 	uint32_t tx_single_collisions;
163 	uint32_t tx_multiple_collisions;
164 	uint32_t tx_total_collisions;
165 	uint32_t tx_pause;
166 	uint32_t tx_tco;
167 	uint32_t rx_good;
168 	uint32_t rx_crc_errors;
169 	uint32_t rx_alignment_errors;
170 	uint32_t rx_rnr_errors;
171 	uint32_t rx_overrun_errors;
172 	uint32_t rx_cdt_errors;
173 	uint32_t rx_shortframes;
174 	uint32_t rx_pause;
175 	uint32_t rx_controls;
176 	uint32_t rx_tco;
177 };
178 
179 /*
180  * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
181  *	 for functional grouping.
182  */
183 struct fxp_softc {
184 	void *ifp;			/* per-interface network data */
185 	struct resource	*fxp_res[2];	/* I/O and IRQ resources */
186 	struct resource_spec *fxp_spec;	/* the resource spec we used */
187 	void *ih;			/* interrupt handler cookie */
188 	const struct fxp_ident *ident;
189 	struct mtx sc_mtx;
190 	bus_dma_tag_t fxp_txmtag;	/* bus DMA tag for Tx mbufs */
191 	bus_dma_tag_t fxp_rxmtag;	/* bus DMA tag for Rx mbufs */
192 	bus_dma_tag_t fxp_stag;		/* bus DMA tag for stats */
193 	bus_dmamap_t fxp_smap;		/* bus DMA map for stats */
194 	bus_dma_tag_t cbl_tag;		/* DMA tag for the TxCB list */
195 	bus_dmamap_t cbl_map;		/* DMA map for the TxCB list */
196 	bus_dma_tag_t mcs_tag;		/* DMA tag for the multicast setup */
197 	bus_dmamap_t mcs_map;		/* DMA map for the multicast setup */
198 	bus_dmamap_t spare_map;		/* spare DMA map */
199 	struct fxp_desc_list fxp_desc;	/* descriptors management struct */
200 	int maxtxseg;			/* maximum # of TX segments */
201 	int maxsegsize;			/* maximum size of a TX segment */
202 	int tx_queued;			/* # of active TxCB's */
203 	struct fxp_stats *fxp_stats;	/* Pointer to interface stats */
204 	uint32_t stats_addr;		/* DMA address of the stats structure */
205 	struct fxp_hwstats fxp_hwstats;
206 	int rx_idle_secs;		/* # of seconds RX has been idle */
207 	struct callout stat_ch;		/* stat callout */
208 	int watchdog_timer;		/* seconds until chip reset */
209 	struct fxp_cb_mcs *mcsp;	/* Pointer to mcast setup descriptor */
210 	uint32_t mcs_addr;		/* DMA address of the multicast cmd */
211 	struct ifmedia sc_media;	/* media information */
212 	device_t miibus;
213 	device_t dev;
214 	int tunable_int_delay;		/* interrupt delay value for ucode */
215 	int tunable_bundle_max;		/* max # frames per interrupt (ucode) */
216 	int rnr;			/* RNR events */
217 	int eeprom_size;		/* size of serial EEPROM */
218 	int suspended;			/* 0 = normal  1 = suspended or dead */
219 	int cu_resume_bug;
220 	int revision;
221 	int flags;
222 	int if_flags;
223 	uint8_t rfa_size;
224 	uint32_t tx_cmd;
225 	uint16_t eeprom[256];
226 };
227 
228 #define FXP_FLAG_MWI_ENABLE	0x0001	/* MWI enable */
229 #define FXP_FLAG_READ_ALIGN	0x0002	/* align read access with cacheline */
230 #define FXP_FLAG_WRITE_ALIGN	0x0004	/* end write on cacheline */
231 #define FXP_FLAG_EXT_TXCB	0x0008	/* enable use of extended TXCB */
232 #define FXP_FLAG_SERIAL_MEDIA	0x0010	/* 10Mbps serial interface */
233 #define FXP_FLAG_LONG_PKT_EN	0x0020	/* enable long packet reception */
234 #define FXP_FLAG_CU_RESUME_BUG	0x0080	/* requires workaround for CU_RESUME */
235 #define FXP_FLAG_UCODE		0x0100	/* ucode is loaded */
236 #define FXP_FLAG_DEFERRED_RNR	0x0200	/* DEVICE_POLLING deferred RNR */
237 #define FXP_FLAG_EXT_RFA	0x0400	/* extended RFDs for csum offload */
238 #define FXP_FLAG_SAVE_BAD	0x0800	/* save bad pkts: bad size, CRC, etc */
239 #define FXP_FLAG_82559_RXCSUM	0x1000	/* 82559 compatible RX checksum */
240 #define FXP_FLAG_WOLCAP		0x2000	/* WOL capability */
241 #define FXP_FLAG_WOL		0x4000	/* WOL active */
242 #define FXP_FLAG_RXBUG		0x8000	/* Rx lock-up bug */
243 #define FXP_FLAG_NO_UCODE	0x10000	/* ucode is not applicable */
244 
245 /* Macros to ease CSR access. */
246 #define	CSR_READ_1(sc, reg)		bus_read_1(sc->fxp_res[0], reg)
247 #define	CSR_READ_2(sc, reg)		bus_read_2(sc->fxp_res[0], reg)
248 #define	CSR_READ_4(sc, reg)		bus_read_4(sc->fxp_res[0], reg)
249 #define	CSR_WRITE_1(sc, reg, val)	bus_write_1(sc->fxp_res[0], reg, val)
250 #define	CSR_WRITE_2(sc, reg, val)	bus_write_2(sc->fxp_res[0], reg, val)
251 #define	CSR_WRITE_4(sc, reg, val)	bus_write_4(sc->fxp_res[0], reg, val)
252