1 /*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * All rights reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gemreg.h,v 1.9 2006/11/24 13:01:07 martin Exp 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _IF_GEMREG_H 33 #define _IF_GEMREG_H 34 35 /* register definitions for Apple GMAC, Sun ERI and Sun GEM */ 36 37 /* 38 * First bank: this registers live at the start of the PCI 39 * mapping, and at the start of the second bank of the SBus 40 * version. 41 */ 42 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */ 43 #define GEM_CONFIG 0x0004 /* config reg */ 44 #define GEM_STATUS 0x000c /* status reg */ 45 /* Note: Reading the status reg clears bits 0-6. */ 46 #define GEM_INTMASK 0x0010 47 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */ 48 #define GEM_STATUS_ALIAS 0x001c 49 50 /* Bits in GEM_SEB register */ 51 #define GEM_SEB_ARB 0x00000002 /* Arbitration status */ 52 #define GEM_SEB_RXWON 0x00000004 53 54 /* Bits in GEM_CONFIG register */ 55 #define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */ 56 #define GEM_CONFIG_BURST_INF 0x00000001 /* infinite for entire packet */ 57 #define GEM_CONFIG_TXDMA_LIMIT 0x0000003e 58 #define GEM_CONFIG_RXDMA_LIMIT 0x000007c0 59 /* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */ 60 #define GEM_CONFIG_RONPAULBIT 0x00000800 /* after infinite burst use */ 61 /* memory read multiple for */ 62 /* PCI commands */ 63 #define GEM_CONFIG_BUG2FIX 0x00001000 /* fix RX hang after overflow */ 64 65 #define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 66 #define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 67 68 /* Top part of GEM_STATUS has TX completion information */ 69 #define GEM_STATUS_TX_COMPLETION_MASK 0xfff80000 /* TX completion reg. */ 70 #define GEM_STATUS_TX_COMPLETION_SHFT 19 71 72 /* 73 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs 74 * Bits 0-6 auto-clear when read. 75 */ 76 #define GEM_INTR_TX_INTME 0x00000001 /* Frame w/INTME bit set sent */ 77 #define GEM_INTR_TX_EMPTY 0x00000002 /* TX ring empty */ 78 #define GEM_INTR_TX_DONE 0x00000004 /* TX complete */ 79 #define GEM_INTR_RX_DONE 0x00000010 /* Got a packet */ 80 #define GEM_INTR_RX_NOBUF 0x00000020 81 #define GEM_INTR_RX_TAG_ERR 0x00000040 82 #define GEM_INTR_PERR 0x00000080 /* Parity error */ 83 #define GEM_INTR_PCS 0x00002000 /* Physical Code Sub-layer */ 84 #define GEM_INTR_TX_MAC 0x00004000 85 #define GEM_INTR_RX_MAC 0x00008000 86 #define GEM_INTR_MAC_CONTROL 0x00010000 /* MAC control interrupt */ 87 #define GEM_INTR_MIF 0x00020000 88 #define GEM_INTR_BERR 0x00040000 /* Bus error interrupt */ 89 #define GEM_INTR_BITS "\177\020" \ 90 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 91 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 92 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ 93 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" 94 95 /* 96 * Second bank: this registers live at offset 0x1000 of the PCI 97 * mapping, and at the start of the first bank of the SBus 98 * version. 99 */ 100 #define GEM_PCI_BANK2_OFFSET 0x1000 101 #define GEM_PCI_BANK2_SIZE 0x14 102 /* This is the same as the GEM_STATUS reg but reading it does not clear bits. */ 103 #define GEM_PCI_ERROR_STATUS 0x0000 /* PCI error status */ 104 #define GEM_PCI_ERROR_MASK 0x0004 /* PCI error mask */ 105 #define GEM_PCI_BIF_CONFIG 0x0008 /* PCI BIF configuration */ 106 #define GEM_PCI_BIF_DIAG 0x000c /* PCI BIF diagnostic */ 107 108 #define GEM_SBUS_BIF_RESET 0x0000 /* SBus BIF only software reset */ 109 #define GEM_SBUS_CONFIG 0x0004 /* SBus IO configuration */ 110 #define GEM_SBUS_STATUS 0x0008 /* SBus IO status */ 111 #define GEM_SBUS_REVISION 0x000c /* SBus revision ID */ 112 113 #define GEM_RESET 0x0010 /* software reset */ 114 115 /* GEM_PCI_ERROR_STATUS and GEM_PCI_ERROR_MASK error bits */ 116 #define GEM_PCI_ERR_STAT_BADACK 0x00000001 /* No ACK64# */ 117 #define GEM_PCI_ERR_STAT_DTRTO 0x00000002 /* Delayed xaction timeout */ 118 #define GEM_PCI_ERR_STAT_OTHERS 0x00000004 119 #define GEM_PCI_ERR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0" 120 121 /* GEM_PCI_BIF_CONFIG register bits */ 122 #define GEM_PCI_BIF_CNF_SLOWCLK 0x00000001 /* Parity error timing */ 123 #define GEM_PCI_BIF_CNF_HOST_64 0x00000002 /* 64-bit host */ 124 #define GEM_PCI_BIF_CNF_B64D_DS 0x00000004 /* no 64-bit data cycle */ 125 #define GEM_PCI_BIF_CNF_M66EN 0x00000008 126 #define GEM_PCI_BIF_CNF_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ 127 "b\2B64DIS\0b\3M66EN\0\0" 128 129 /* GEM_PCI_BIF_DIAG register bits */ 130 #define GEN_PCI_BIF_DIAG_BC_SM 0x007f0000 /* burst ctrl. state machine */ 131 #define GEN_PCI_BIF_DIAG_SM 0xff000000 /* BIF state machine */ 132 133 /* Bits in GEM_SBUS_CONFIG register */ 134 #define GEM_SBUS_CFG_BURST_32 0x00000001 /* 32 byte bursts */ 135 #define GEM_SBUS_CFG_BURST_64 0x00000002 /* 64 byte bursts */ 136 #define GEM_SBUS_CFG_BURST_128 0x00000004 /* 128 byte bursts */ 137 #define GEM_SBUS_CFG_64BIT 0x00000008 /* extended transfer mode */ 138 #define GEM_SBUS_CFG_PARITY 0x00000200 /* enable parity checking */ 139 140 /* GEM_SBUS_STATUS register bits */ 141 #define GEM_SBUS_STATUS_LERR 0x00000001 /* LERR from SBus slave */ 142 #define GEM_SBUS_STATUS_SACK 0x00000002 /* size ack. error */ 143 #define GEM_SBUS_STATUS_EACK 0x00000004 /* SBus ctrl. or slave error */ 144 #define GEM_SBUS_STATUS_MPARITY 0x00000008 /* SBus master parity error */ 145 146 /* GEM_RESET register bits -- TX and RX self clear when complete. */ 147 #define GEM_RESET_TX 0x00000001 /* Reset TX half. */ 148 #define GEM_RESET_RX 0x00000002 /* Reset RX half. */ 149 #define GEM_RESET_PCI_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */ 150 151 /* The rest of the registers live in the first bank again. */ 152 153 /* TX DMA registers */ 154 #define GEM_TX_KICK 0x2000 /* Write last valid desc + 1 */ 155 #define GEM_TX_CONFIG 0x2004 156 #define GEM_TX_RING_PTR_LO 0x2008 157 #define GEM_TX_RING_PTR_HI 0x200c 158 159 #define GEM_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */ 160 #define GEM_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */ 161 #define GEM_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */ 162 #define GEM_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */ 163 #define GEM_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */ 164 165 #define GEM_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */ 166 #define GEM_TX_DATA_PTR_LO 0x2030 167 #define GEM_TX_DATA_PTR_HI 0x2034 168 169 #define GEM_TX_COMPLETION 0x2100 170 #define GEM_TX_FIFO_ADDRESS 0x2104 171 #define GEM_TX_FIFO_TAG 0x2108 172 #define GEM_TX_FIFO_DATA_LO 0x210c 173 #define GEM_TX_FIFO_DATA_HI_T1 0x2110 174 #define GEM_TX_FIFO_DATA_HI_T0 0x2114 175 #define GEM_TX_FIFO_SIZE 0x2118 176 #define GEM_TX_DEBUG 0x3028 177 178 /* GEM_TX_CONFIG register bits */ 179 #define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 180 #define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 181 #define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 182 #define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 183 184 #define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 185 #define GEM_RING_SZ_64 (1<<1) 186 #define GEM_RING_SZ_128 (2<<1) 187 #define GEM_RING_SZ_256 (3<<1) 188 #define GEM_RING_SZ_512 (4<<1) 189 #define GEM_RING_SZ_1024 (5<<1) 190 #define GEM_RING_SZ_2048 (6<<1) 191 #define GEM_RING_SZ_4096 (7<<1) 192 #define GEM_RING_SZ_8192 (8<<1) 193 194 /* GEM_TX_COMPLETION register bits */ 195 #define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 196 197 /* RX DMA registers */ 198 #define GEM_RX_CONFIG 0x4000 199 #define GEM_RX_RING_PTR_LO 0x4004 /* 64-bits unaligned GAK! */ 200 #define GEM_RX_RING_PTR_HI 0x4008 /* 64-bits unaligned GAK! */ 201 202 #define GEM_RX_FIFO_WR_PTR 0x400c /* FIFO write pointer */ 203 #define GEM_RX_FIFO_SDWR_PTR 0x4010 /* FIFO shadow write pointer */ 204 #define GEM_RX_FIFO_RD_PTR 0x4014 /* FIFO read pointer */ 205 #define GEM_RX_FIFO_PKT_CNT 0x4018 /* FIFO packet counter */ 206 207 #define GEM_RX_STATE_MACHINE 0x401c /* ERX state machine reg */ 208 #define GEM_RX_PAUSE_THRESH 0x4020 209 210 #define GEM_RX_DATA_PTR_LO 0x4024 /* ERX state machine reg */ 211 #define GEM_RX_DATA_PTR_HI 0x4028 /* Damn thing is unaligned */ 212 213 #define GEM_RX_KICK 0x4100 /* Write last valid desc + 1 */ 214 #define GEM_RX_COMPLETION 0x4104 /* First pending desc */ 215 #define GEM_RX_BLANKING 0x4108 /* Interrupt blanking reg */ 216 217 #define GEM_RX_FIFO_ADDRESS 0x410c 218 #define GEM_RX_FIFO_TAG 0x4110 219 #define GEM_RX_FIFO_DATA_LO 0x4114 220 #define GEM_RX_FIFO_DATA_HI_T1 0x4118 221 #define GEM_RX_FIFO_DATA_HI_T0 0x411c 222 #define GEM_RX_FIFO_SIZE 0x4120 223 224 /* GEM_RX_CONFIG register bits */ 225 #define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 226 #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 227 #define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 228 #define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 229 #define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 230 #define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 231 232 #define GEM_THRSH_64 0 233 #define GEM_THRSH_128 1 234 #define GEM_THRSH_256 2 235 #define GEM_THRSH_512 3 236 #define GEM_THRSH_1024 4 237 #define GEM_THRSH_2048 5 238 239 #define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 240 #define GEM_RX_CONFIG_FBOFF_SHFT 10 241 #define GEM_RX_CONFIG_CXM_START_SHFT 13 242 243 /* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 244 #define GEM_RX_PTH_XOFF_THRESH 0x000001ff 245 #define GEM_RX_PTH_XON_THRESH 0x001ff000 246 247 /* GEM_RX_BLANKING register bits */ 248 #define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 249 #define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */ 250 #define GEM_RX_BLANKING_TIME_SHIFT 12 251 /* One tick is 2048 PCI clocks, or 16us at 66MHz */ 252 253 /* GEM_MAC registers */ 254 #define GEM_MAC_TXRESET 0x6000 /* Store 1, cleared when done */ 255 #define GEM_MAC_RXRESET 0x6004 /* ditto */ 256 #define GEM_MAC_SEND_PAUSE_CMD 0x6008 257 #define GEM_MAC_TX_STATUS 0x6010 258 #define GEM_MAC_RX_STATUS 0x6014 259 #define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */ 260 #define GEM_MAC_TX_MASK 0x6020 /* TX MAC mask register */ 261 #define GEM_MAC_RX_MASK 0x6024 262 #define GEM_MAC_CONTROL_MASK 0x6028 263 #define GEM_MAC_TX_CONFIG 0x6030 264 #define GEM_MAC_RX_CONFIG 0x6034 265 #define GEM_MAC_CONTROL_CONFIG 0x6038 266 #define GEM_MAC_XIF_CONFIG 0x603c 267 #define GEM_MAC_IPG0 0x6040 /* inter packet gap 0 */ 268 #define GEM_MAC_IPG1 0x6044 /* inter packet gap 1 */ 269 #define GEM_MAC_IPG2 0x6048 /* inter packet gap 2 */ 270 #define GEM_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */ 271 #define GEM_MAC_MAC_MIN_FRAME 0x6050 272 #define GEM_MAC_MAC_MAX_FRAME 0x6054 273 #define GEM_MAC_PREAMBLE_LEN 0x6058 274 #define GEM_MAC_JAM_SIZE 0x605c 275 #define GEM_MAC_ATTEMPT_LIMIT 0x6060 276 #define GEM_MAC_CONTROL_TYPE 0x6064 277 278 #define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 279 #define GEM_MAC_ADDR1 0x6084 280 #define GEM_MAC_ADDR2 0x6088 281 #define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 282 #define GEM_MAC_ADDR4 0x6090 283 #define GEM_MAC_ADDR5 0x6094 284 #define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 285 #define GEM_MAC_ADDR7 0x609c 286 #define GEM_MAC_ADDR8 0x60a0 287 288 #define GEM_MAC_ADDR_FILTER0 0x60a4 289 #define GEM_MAC_ADDR_FILTER1 0x60a8 290 #define GEM_MAC_ADDR_FILTER2 0x60ac 291 #define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address filter mask 1,2 */ 292 #define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address filter mask 0 reg */ 293 294 #define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 295 #define GEM_MAC_HASH1 0x60c4 296 #define GEM_MAC_HASH2 0x60c8 297 #define GEM_MAC_HASH3 0x60cc 298 #define GEM_MAC_HASH4 0x60d0 299 #define GEM_MAC_HASH5 0x60d4 300 #define GEM_MAC_HASH6 0x60d8 301 #define GEM_MAC_HASH7 0x60dc 302 #define GEM_MAC_HASH8 0x60e0 303 #define GEM_MAC_HASH9 0x60e4 304 #define GEM_MAC_HASH10 0x60e8 305 #define GEM_MAC_HASH11 0x60ec 306 #define GEM_MAC_HASH12 0x60f0 307 #define GEM_MAC_HASH13 0x60f4 308 #define GEM_MAC_HASH14 0x60f8 309 #define GEM_MAC_HASH15 0x60fc 310 311 #define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal collision counter */ 312 #define GEM_MAC_FIRST_COLL_CNT 0x6104 /* 1st successful collision cntr */ 313 #define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess collision counter */ 314 #define GEM_MAC_LATE_COLL_CNT 0x610c /* Late collision counter */ 315 #define GEM_MAC_DEFER_TMR_CNT 0x6110 /* defer timer counter */ 316 #define GEM_MAC_PEAK_ATTEMPTS 0x6114 317 #define GEM_MAC_RX_FRAME_COUNT 0x6118 318 #define GEM_MAC_RX_LEN_ERR_CNT 0x611c 319 #define GEM_MAC_RX_ALIGN_ERR 0x6120 320 #define GEM_MAC_RX_CRC_ERR_CNT 0x6124 321 #define GEM_MAC_RX_CODE_VIOL 0x6128 322 #define GEM_MAC_RANDOM_SEED 0x6130 323 #define GEM_MAC_MAC_STATE 0x6134 /* MAC state machine reg */ 324 325 /* GEM_MAC_SEND_PAUSE_CMD register bits */ 326 #define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 327 #define GEM_MAC_PAUSE_CMD_SEND 0x00010000 328 329 /* GEM_MAC_TX_STATUS and _MASK register bits */ 330 #define GEM_MAC_TX_XMIT_DONE 0x00000001 331 #define GEM_MAC_TX_UNDERRUN 0x00000002 332 #define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 333 #define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */ 334 #define GEM_MAC_TX_ECC_EXP 0x00000010 335 #define GEM_MAC_TX_LCC_EXP 0x00000020 336 #define GEM_MAC_TX_FCC_EXP 0x00000040 337 #define GEM_MAC_TX_DEFER_EXP 0x00000080 338 #define GEM_MAC_TX_PEAK_EXP 0x00000100 339 340 /* GEM_MAC_RX_STATUS and _MASK register bits */ 341 #define GEM_MAC_RX_DONE 0x00000001 342 #define GEM_MAC_RX_OVERFLOW 0x00000002 343 #define GEM_MAC_RX_FRAME_CNT 0x00000004 344 #define GEM_MAC_RX_ALIGN_EXP 0x00000008 345 #define GEM_MAC_RX_CRC_EXP 0x00000010 346 #define GEM_MAC_RX_LEN_EXP 0x00000020 347 #define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation */ 348 349 /* GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register bits */ 350 #define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 351 #define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 352 #define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 353 #define GEM_MAC_PAUSE_TIME_SLTS 0xffff0000 /* pause time in slots */ 354 #define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0" 355 356 #define GEM_MAC_PAUSE_TIME_SHFT 16 357 #define GEM_MAC_PAUSE_TIME(x) \ 358 (((x) & GEM_MAC_PAUSE_TIME_SLTS) >> GEM_MAC_PAUSE_TIME_SHFT) 359 360 /* GEM_MAC_XIF_CONFIG register bits */ 361 #define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */ 362 #define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */ 363 #define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 364 #define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 365 #define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 366 #define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 367 #define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 368 #define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \ 369 "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \ 370 "b\6FDLED\0\0" 371 372 /* 373 * GEM_MAC_SLOT_TIME register 374 * The slot time is used as PAUSE time unit, value depends on whether carrier 375 * extension is enabled. 376 */ 377 #define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200 378 #define GEM_MAC_SLOT_TIME_NORMAL 0x40 379 380 /* GEM_MAC_TX_CONFIG register bits */ 381 #define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 382 #define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 383 #define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ 384 #define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend RX-to-TX IPG */ 385 #define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 386 #define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 387 #define GEM_MAC_TX_NO_BACKOFF 0x00000040 388 #define GEM_MAC_TX_SLOWDOWN 0x00000080 389 #define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 390 #define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 391 /* Carrier Extension is required for half duplex Gbps operation. */ 392 #define GEM_MAC_TX_CONFIG_BITS "\177\020" \ 393 "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \ 394 "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \ 395 "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \ 396 "b\x9TXCARREXT\0\0" 397 398 /* GEM_MAC_RX_CONFIG register bits */ 399 #define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 400 #define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 401 #define GEM_MAC_RX_STRIP_CRC 0x00000004 402 #define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 403 #define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 404 #define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 405 #define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 406 #define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */ 407 #define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 408 /* 409 * Carrier Extension enables reception of packet bursts generated by 410 * senders with carrier extension enabled. 411 */ 412 #define GEM_MAC_RX_CONFIG_BITS "\177\020" \ 413 "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \ 414 "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \ 415 "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0" 416 417 /* GEM_MAC_CONTROL_CONFIG bits */ 418 #define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 419 #define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 420 #define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 421 #define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" 422 423 /* 424 * MIF registers 425 * Bit bang registers use low bit only. 426 */ 427 #define GEM_MIF_BB_CLOCK 0x6200 /* bit bang clock */ 428 #define GEM_MIF_BB_DATA 0x6204 /* bit bang data */ 429 #define GEM_MIF_BB_OUTPUT_ENAB 0x6208 430 #define GEM_MIF_FRAME 0x620c /* MIF frame - ctl and data */ 431 #define GEM_MIF_CONFIG 0x6210 432 #define GEM_MIF_MASK 0x6214 433 #define GEM_MIF_STATUS 0x6218 434 #define GEM_MIF_STATE_MACHINE 0x621c 435 436 /* GEM_MIF_FRAME bits */ 437 #define GEM_MIF_FRAME_DATA 0x0000ffff 438 #define GEM_MIF_FRAME_TA0 0x00010000 /* TA LSB, 1 for completion */ 439 #define GEM_MIF_FRAME_TA1 0x00020000 /* TA MSB, 1 for instruction */ 440 #define GEM_MIF_FRAME_REG_ADDR 0x007c0000 441 #define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* PHY address */ 442 #define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 443 #define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 444 445 #define GEM_MIF_FRAME_READ 0x60020000 446 #define GEM_MIF_FRAME_WRITE 0x50020000 447 448 #define GEM_MIF_REG_SHIFT 18 449 #define GEM_MIF_PHY_SHIFT 23 450 451 /* GEM_MIF_CONFIG register bits */ 452 #define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0: MDIO_0 */ 453 #define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 454 #define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 455 #define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 456 #define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 attached/data */ 457 #define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 attached/data */ 458 #define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 459 /* MDI0 is the onboard transceiver, MDI1 is external, PHYAD for both is 0. */ 460 #define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ 461 "b\x8MDIO0\0b\x9MDIO1\0\0" 462 463 /* GEM_MIF_STATUS and GEM_MIF_MASK bits */ 464 #define GEM_MIF_POLL_STATUS_MASK 0x0000ffff /* polling status */ 465 #define GEM_MIF_POLL_STATUS_SHFT 0 466 #define GEM_MIF_POLL_DATA_MASK 0xffff0000 /* polling data */ 467 #define GEM_MIF_POLL_DATA_SHFT 8 468 /* 469 * The Basic part is the last value read in the POLL field of the config 470 * register. 471 * The status part indicates the bits that have changed. 472 */ 473 474 /* GEM PCS/Serial link registers */ 475 /* DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. */ 476 #define GEM_MII_CONTROL 0x9000 477 #define GEM_MII_STATUS 0x9004 478 #define GEM_MII_ANAR 0x9008 /* MII advertisement reg */ 479 #define GEM_MII_ANLPAR 0x900c /* Link Partner Ability Reg */ 480 #define GEM_MII_CONFIG 0x9010 481 #define GEM_MII_STATE_MACHINE 0x9014 482 #define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */ 483 #define GEM_MII_DATAPATH_MODE 0x9050 484 #define GEM_MII_SLINK_CONTROL 0x9054 /* Serial link control */ 485 #define GEM_MII_OUTPUT_SELECT 0x9058 486 #define GEM_MII_SLINK_STATUS 0x905c /* Serialink status */ 487 488 /* GEM_MII_CONTROL bits - PCS "BMCR" (Basic Mode Control Reg) */ 489 #define GEM_MII_CONTROL_1000M 0x00000040 /* 1000Mbps speed select */ 490 #define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 491 #define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full-duplex, always 0 */ 492 #define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto-negotiation */ 493 #define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate PHY from MII */ 494 #define GEM_MII_CONTROL_POWERDN 0x00000800 /* power down */ 495 #define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto-negotiation enable */ 496 #define GEM_MII_CONTROL_10_100M 0x00002000 /* 10/100Mbps speed select */ 497 #define GEM_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */ 498 #define GEM_MII_CONTROL_RESET 0x00008000 /* Reset PCS. */ 499 #define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \ 500 "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \ 501 "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0" 502 503 /* GEM_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */ 504 #define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended capability */ 505 #define GEM_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */ 506 #define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status */ 507 #define GEM_MII_STATUS_ACFG 0x00000008 /* can auto-negotiate */ 508 #define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 509 #define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */ 510 #define GEM_MII_STATUS_EXTENDED 0x00000100 /* extended status */ 511 #define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \ 512 "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0\0" 513 514 /* GEM_MII_ANAR and GEM_MII_ANLPAR reg bits */ 515 #define GEM_MII_ANEG_FDUPLX 0x00000020 /* full-duplex */ 516 #define GEM_MII_ANEG_HDUPLX 0x00000040 /* half-duplex */ 517 #define GEM_MII_ANEG_PAUSE 0x00000080 /* symmetric PAUSE */ 518 #define GEM_MII_ANEG_ASM_DIR 0x00000100 /* asymmetric PAUSE */ 519 #define GEM_MII_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */ 520 #define GEM_MII_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */ 521 #define GEM_MII_ANEG_RFLT_MASK \ 522 (CAS_PCS_ANEG_RFLT_FAIL | CAS_PCS_ANEG_RFLT_OFF) 523 #define GEM_MII_ANEG_ACK 0x00004000 /* acknowledge */ 524 #define GEM_MII_ANEG_NP 0x00008000 /* next page */ 525 #define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \ 526 "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \ 527 "\b\xfNPBIT\0\0" 528 529 /* GEM_MII_CONFIG reg */ 530 #define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS. */ 531 #define GEM_MII_CONFIG_SDO 0x00000002 /* signal detect override */ 532 #define GEM_MII_CONFIG_SDL 0x00000004 /* signal detect active-low */ 533 #define GEM_MII_CONFIG_JS_NORM 0x00000000 /* jitter study - normal op. */ 534 #define GEM_MII_CONFIG_JS_HF 0x00000008 /* jitter study - HF test */ 535 #define GEM_MII_CONFIG_JS_LF 0x00000010 /* jitter study - LF test */ 536 #define GEM_MII_CONFIG_JS_MASK \ 537 (GEM_MII_CONFIG_JS_HF | GEM_MII_CONFIG_JS_LF) 538 #define GEM_MII_CONFIG_ANTO 0x00000020 /* auto-neg. timer override */ 539 #define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0" 540 541 /* 542 * GEM_MII_INTERRUP_STATUS reg 543 * No mask register; mask with the global interrupt mask register. 544 */ 545 #define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */ 546 547 /* GEM_MII_DATAPATH_MODE reg */ 548 #define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Serialink */ 549 #define GEM_MII_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */ 550 #define GEM_MII_DATAPATH_MII 0x00000004 /* GMII/MII */ 551 #define GEM_MII_DATAPATH_GMIIOE 0x00000008 /* serial output on GMII en. */ 552 #define GEM_MII_DATAPATH_BITS "\177\020" \ 553 "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3GMIIOE\0\0" 554 555 /* GEM_MII_SLINK_CONTROL reg */ 556 #define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at SL, logic 557 * reversed for SERDES */ 558 #define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 559 #define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock to reference clock */ 560 #define GEM_MII_SLINK_EMPHASIS 0x00000018 /* enable emphasis */ 561 #define GEM_MII_SLINK_SELFTEST 0x000001c0 /* self-test */ 562 #define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down Serialink. */ 563 #define GEM_MII_SLINK_RX_ZERO 0x00000c00 /* PLL input to Serialink. */ 564 #define GEM_MII_SLINK_RX_POLE 0x00003000 /* PLL input to Serialink. */ 565 #define GEM_MII_SLINK_TX_ZERO 0x0000c000 /* PLL input to Serialink. */ 566 #define GEM_MII_SLINK_TX_POLE 0x00030000 /* PLL input to Serialink. */ 567 #define GEM_MII_SLINK_CONTROL_BITS \ 568 "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \ 569 "\0b\3EMPHASIS\0b\x9PWRDWN\0\0" 570 571 /* GEM_MII_SLINK_STATUS reg */ 572 #define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 573 #define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us w/ lockrefn */ 574 #define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 575 #define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 576 577 /* 578 * PCI Expansion ROM runtime access 579 * Sun GEMs map a 1MB space for the PCI Expansion ROM as the second half 580 * of the first register bank, although they only support up to 64KB ROMs. 581 */ 582 #define GEM_PCI_ROM_OFFSET 0x100000 583 #define GEM_PCI_ROM_SIZE 0x10000 584 585 /* Wired PHY addresses */ 586 #define GEM_PHYAD_INTERNAL 1 587 #define GEM_PHYAD_EXTERNAL 0 588 589 /* 590 * descriptor table structures 591 */ 592 struct gem_desc { 593 uint64_t gd_flags; 594 uint64_t gd_addr; 595 }; 596 597 /* Transmit flags */ 598 #define GEM_TD_BUFSIZE 0x0000000000007fffULL 599 #define GEM_TD_CXSUM_START 0x00000000001f8000ULL /* Cxsum start offset */ 600 #define GEM_TD_CXSUM_STARTSHFT 15 601 #define GEM_TD_CXSUM_STUFF 0x000000001fe00000ULL /* Cxsum stuff offset */ 602 #define GEM_TD_CXSUM_STUFFSHFT 21 603 #define GEM_TD_CXSUM_ENABLE 0x0000000020000000ULL /* Cxsum generation enable */ 604 #define GEM_TD_END_OF_PACKET 0x0000000040000000ULL 605 #define GEM_TD_START_OF_PACKET 0x0000000080000000ULL 606 #define GEM_TD_INTERRUPT_ME 0x0000000100000000ULL /* Interrupt me now */ 607 #define GEM_TD_NO_CRC 0x0000000200000000ULL /* do not insert crc */ 608 /* 609 * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF, 610 * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group. 611 */ 612 613 /* Receive flags */ 614 #define GEM_RD_CHECKSUM 0x000000000000ffffULL /* is the complement */ 615 #define GEM_RD_BUFSIZE 0x000000007fff0000ULL 616 #define GEM_RD_OWN 0x0000000080000000ULL /* 1 - owned by h/w */ 617 #define GEM_RD_HASHVAL 0x0ffff00000000000ULL 618 #define GEM_RD_HASH_PASS 0x1000000000000000ULL /* passed hash filter */ 619 #define GEM_RD_ALTERNATE_MAC 0x2000000000000000ULL /* Alternate MAC adrs */ 620 #define GEM_RD_BAD_CRC 0x4000000000000000ULL 621 622 #define GEM_RD_BUFSHIFT 16 623 #define GEM_RD_BUFLEN(x) (((x) & GEM_RD_BUFSIZE) >> GEM_RD_BUFSHIFT) 624 625 #endif 626