1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2023 Google LLC 5 * 6 * Redistribution and use in source and binary forms, with or without modification, 7 * are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, this 10 * list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3. Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 #ifndef _GVE_FBSD_H 32 #define _GVE_FBSD_H 33 34 #include "gve_desc.h" 35 #include "gve_plat.h" 36 #include "gve_register.h" 37 38 #ifndef PCI_VENDOR_ID_GOOGLE 39 #define PCI_VENDOR_ID_GOOGLE 0x1ae0 40 #endif 41 42 #define PCI_DEV_ID_GVNIC 0x0042 43 #define GVE_REGISTER_BAR 0 44 #define GVE_DOORBELL_BAR 2 45 46 /* Driver can alloc up to 2 segments for the header and 2 for the payload. */ 47 #define GVE_TX_MAX_DESCS 4 48 #define GVE_TX_BUFRING_ENTRIES 4096 49 50 #define ADMINQ_SIZE PAGE_SIZE 51 52 #define GVE_DEFAULT_RX_BUFFER_SIZE 2048 53 /* Each RX bounce buffer page can fit two packet buffers. */ 54 #define GVE_DEFAULT_RX_BUFFER_OFFSET (PAGE_SIZE / 2) 55 56 /* 57 * Number of descriptors per queue page list. 58 * Page count AKA QPL size can be derived by dividing the number of elements in 59 * a page by the number of descriptors available. 60 */ 61 #define GVE_QPL_DIVISOR 16 62 63 static MALLOC_DEFINE(M_GVE, "gve", "gve allocations"); 64 65 struct gve_dma_handle { 66 bus_addr_t bus_addr; 67 void *cpu_addr; 68 bus_dma_tag_t tag; 69 bus_dmamap_t map; 70 }; 71 72 union gve_tx_desc { 73 struct gve_tx_pkt_desc pkt; /* first desc for a packet */ 74 struct gve_tx_mtd_desc mtd; /* optional metadata descriptor */ 75 struct gve_tx_seg_desc seg; /* subsequent descs for a packet */ 76 }; 77 78 /* Tracks the memory in the fifo occupied by a segment of a packet */ 79 struct gve_tx_iovec { 80 uint32_t iov_offset; /* offset into this segment */ 81 uint32_t iov_len; /* length */ 82 uint32_t iov_padding; /* padding associated with this segment */ 83 }; 84 85 /* Tracks allowed and current queue settings */ 86 struct gve_queue_config { 87 uint16_t max_queues; 88 uint16_t num_queues; /* current */ 89 }; 90 91 struct gve_irq_db { 92 __be32 index; 93 } __aligned(CACHE_LINE_SIZE); 94 95 /* 96 * GVE_QUEUE_FORMAT_UNSPECIFIED must be zero since 0 is the default value 97 * when the entire configure_device_resources command is zeroed out and the 98 * queue_format is not specified. 99 */ 100 enum gve_queue_format { 101 GVE_QUEUE_FORMAT_UNSPECIFIED = 0x0, 102 GVE_GQI_RDA_FORMAT = 0x1, 103 GVE_GQI_QPL_FORMAT = 0x2, 104 GVE_DQO_RDA_FORMAT = 0x3, 105 }; 106 107 enum gve_state_flags_bit { 108 GVE_STATE_FLAG_ADMINQ_OK, 109 GVE_STATE_FLAG_RESOURCES_OK, 110 GVE_STATE_FLAG_QPLREG_OK, 111 GVE_STATE_FLAG_RX_RINGS_OK, 112 GVE_STATE_FLAG_TX_RINGS_OK, 113 GVE_STATE_FLAG_QUEUES_UP, 114 GVE_STATE_FLAG_LINK_UP, 115 GVE_STATE_FLAG_DO_RESET, 116 GVE_STATE_FLAG_IN_RESET, 117 GVE_NUM_STATE_FLAGS /* Not part of the enum space */ 118 }; 119 120 BITSET_DEFINE(gve_state_flags, GVE_NUM_STATE_FLAGS); 121 122 #define GVE_DEVICE_STATUS_RESET (0x1 << 1) 123 #define GVE_DEVICE_STATUS_LINK_STATUS (0x1 << 2) 124 125 #define GVE_RING_LOCK(ring) mtx_lock(&(ring)->ring_mtx) 126 #define GVE_RING_TRYLOCK(ring) mtx_trylock(&(ring)->ring_mtx) 127 #define GVE_RING_UNLOCK(ring) mtx_unlock(&(ring)->ring_mtx) 128 #define GVE_RING_ASSERT(ring) mtx_assert(&(ring)->ring_mtx, MA_OWNED) 129 130 #define GVE_IFACE_LOCK_INIT(lock) sx_init(&lock, "gve interface lock") 131 #define GVE_IFACE_LOCK_DESTROY(lock) sx_destroy(&lock) 132 #define GVE_IFACE_LOCK_LOCK(lock) sx_xlock(&lock) 133 #define GVE_IFACE_LOCK_UNLOCK(lock) sx_unlock(&lock) 134 #define GVE_IFACE_LOCK_ASSERT(lock) sx_assert(&lock, SA_XLOCKED) 135 136 struct gve_queue_page_list { 137 uint32_t id; 138 uint32_t num_dmas; 139 uint32_t num_pages; 140 vm_offset_t kva; 141 vm_page_t *pages; 142 struct gve_dma_handle *dmas; 143 }; 144 145 struct gve_irq { 146 struct resource *res; 147 void *cookie; 148 }; 149 150 struct gve_rx_slot_page_info { 151 void *page_address; 152 vm_page_t page; 153 uint32_t page_offset; 154 uint16_t pad; 155 }; 156 157 /* 158 * A single received packet split across multiple buffers may be 159 * reconstructed using the information in this structure. 160 */ 161 struct gve_rx_ctx { 162 /* head and tail of mbuf chain for the current packet */ 163 struct mbuf *mbuf_head; 164 struct mbuf *mbuf_tail; 165 uint32_t total_size; 166 uint8_t frag_cnt; 167 bool drop_pkt; 168 }; 169 170 struct gve_ring_com { 171 struct gve_priv *priv; 172 uint32_t id; 173 174 /* 175 * BAR2 offset for this ring's doorbell and the 176 * counter-array offset for this ring's counter. 177 * Acquired from the device individually for each 178 * queue in the queue_create adminq command. 179 */ 180 struct gve_queue_resources *q_resources; 181 struct gve_dma_handle q_resources_mem; 182 183 /* Byte offset into BAR2 where this ring's 4-byte irq doorbell lies. */ 184 uint32_t irq_db_offset; 185 /* Byte offset into BAR2 where this ring's 4-byte doorbell lies. */ 186 uint32_t db_offset; 187 /* 188 * Index, not byte-offset, into the counter array where this ring's 189 * 4-byte counter lies. 190 */ 191 uint32_t counter_idx; 192 193 /* 194 * The index of the MSIX vector that was assigned to 195 * this ring in `gve_alloc_irqs`. 196 * 197 * It is passed to the device in the queue_create adminq 198 * command. 199 * 200 * Additionally, this also serves as the index into 201 * `priv->irq_db_indices` where this ring's irq doorbell's 202 * BAR2 offset, `irq_db_idx`, can be found. 203 */ 204 int ntfy_id; 205 206 /* 207 * The fixed bounce buffer for this ring. 208 * Once allocated, has to be offered to the device 209 * over the register-page-list adminq command. 210 */ 211 struct gve_queue_page_list *qpl; 212 213 struct task cleanup_task; 214 struct taskqueue *cleanup_tq; 215 } __aligned(CACHE_LINE_SIZE); 216 217 struct gve_rxq_stats { 218 counter_u64_t rbytes; 219 counter_u64_t rpackets; 220 counter_u64_t rx_dropped_pkt; 221 counter_u64_t rx_copybreak_cnt; 222 counter_u64_t rx_frag_flip_cnt; 223 counter_u64_t rx_frag_copy_cnt; 224 counter_u64_t rx_dropped_pkt_desc_err; 225 counter_u64_t rx_dropped_pkt_mbuf_alloc_fail; 226 }; 227 228 #define NUM_RX_STATS (sizeof(struct gve_rxq_stats) / sizeof(counter_u64_t)) 229 230 /* power-of-2 sized receive ring */ 231 struct gve_rx_ring { 232 struct gve_ring_com com; 233 struct gve_dma_handle desc_ring_mem; 234 struct gve_dma_handle data_ring_mem; 235 236 /* accessed in the receive hot path */ 237 struct { 238 struct gve_rx_desc *desc_ring; 239 union gve_rx_data_slot *data_ring; 240 struct gve_rx_slot_page_info *page_info; 241 242 struct gve_rx_ctx ctx; 243 struct lro_ctrl lro; 244 uint8_t seq_no; /* helps traverse the descriptor ring */ 245 uint32_t cnt; /* free-running total number of completed packets */ 246 uint32_t fill_cnt; /* free-running total number of descs and buffs posted */ 247 uint32_t mask; /* masks the cnt and fill_cnt to the size of the ring */ 248 struct gve_rxq_stats stats; 249 } __aligned(CACHE_LINE_SIZE); 250 251 } __aligned(CACHE_LINE_SIZE); 252 253 /* 254 * A contiguous representation of the pages composing the Tx bounce buffer. 255 * The xmit taskqueue and the completion taskqueue both simultaneously use it. 256 * Both operate on `available`: the xmit tq lowers it and the completion tq 257 * raises it. `head` is the last location written at and so only the xmit tq 258 * uses it. 259 */ 260 struct gve_tx_fifo { 261 vm_offset_t base; /* address of base of FIFO */ 262 uint32_t size; /* total size */ 263 volatile int available; /* how much space is still available */ 264 uint32_t head; /* offset to write at */ 265 }; 266 267 struct gve_tx_buffer_state { 268 struct mbuf *mbuf; 269 struct gve_tx_iovec iov[GVE_TX_MAX_DESCS]; 270 }; 271 272 struct gve_txq_stats { 273 counter_u64_t tbytes; 274 counter_u64_t tpackets; 275 counter_u64_t tso_packet_cnt; 276 counter_u64_t tx_dropped_pkt; 277 counter_u64_t tx_dropped_pkt_nospace_device; 278 counter_u64_t tx_dropped_pkt_nospace_bufring; 279 counter_u64_t tx_dropped_pkt_vlan; 280 }; 281 282 #define NUM_TX_STATS (sizeof(struct gve_txq_stats) / sizeof(counter_u64_t)) 283 284 /* power-of-2 sized transmit ring */ 285 struct gve_tx_ring { 286 struct gve_ring_com com; 287 struct gve_dma_handle desc_ring_mem; 288 289 struct task xmit_task; 290 struct taskqueue *xmit_tq; 291 292 /* accessed in the transmit hot path */ 293 struct { 294 union gve_tx_desc *desc_ring; 295 struct gve_tx_buffer_state *info; 296 struct buf_ring *br; 297 298 struct gve_tx_fifo fifo; 299 struct mtx ring_mtx; 300 301 uint32_t req; /* free-running total number of packets written to the nic */ 302 uint32_t done; /* free-running total number of completed packets */ 303 uint32_t mask; /* masks the req and done to the size of the ring */ 304 struct gve_txq_stats stats; 305 } __aligned(CACHE_LINE_SIZE); 306 307 } __aligned(CACHE_LINE_SIZE); 308 309 struct gve_priv { 310 if_t ifp; 311 device_t dev; 312 struct ifmedia media; 313 314 uint8_t mac[ETHER_ADDR_LEN]; 315 316 struct gve_dma_handle aq_mem; 317 318 struct resource *reg_bar; /* BAR0 */ 319 struct resource *db_bar; /* BAR2 */ 320 struct resource *msix_table; 321 322 uint32_t mgmt_msix_idx; 323 uint32_t rx_copybreak; 324 325 uint16_t num_event_counters; 326 uint16_t default_num_queues; 327 uint16_t tx_desc_cnt; 328 uint16_t rx_desc_cnt; 329 uint16_t rx_pages_per_qpl; 330 uint64_t max_registered_pages; 331 uint64_t num_registered_pages; 332 uint32_t supported_features; 333 uint16_t max_mtu; 334 335 struct gve_dma_handle counter_array_mem; 336 __be32 *counters; 337 struct gve_dma_handle irqs_db_mem; 338 struct gve_irq_db *irq_db_indices; 339 340 enum gve_queue_format queue_format; 341 struct gve_queue_page_list *qpls; 342 struct gve_queue_config tx_cfg; 343 struct gve_queue_config rx_cfg; 344 uint32_t num_queues; 345 346 struct gve_irq *irq_tbl; 347 struct gve_tx_ring *tx; 348 struct gve_rx_ring *rx; 349 350 /* 351 * Admin queue - see gve_adminq.h 352 * Since AQ cmds do not run in steady state, 32 bit counters suffice 353 */ 354 struct gve_adminq_command *adminq; 355 vm_paddr_t adminq_bus_addr; 356 uint32_t adminq_mask; /* masks prod_cnt to adminq size */ 357 uint32_t adminq_prod_cnt; /* free-running count of AQ cmds executed */ 358 uint32_t adminq_cmd_fail; /* free-running count of AQ cmds failed */ 359 uint32_t adminq_timeouts; /* free-running count of AQ cmds timeouts */ 360 /* free-running count of each distinct AQ cmd executed */ 361 uint32_t adminq_describe_device_cnt; 362 uint32_t adminq_cfg_device_resources_cnt; 363 uint32_t adminq_register_page_list_cnt; 364 uint32_t adminq_unregister_page_list_cnt; 365 uint32_t adminq_create_tx_queue_cnt; 366 uint32_t adminq_create_rx_queue_cnt; 367 uint32_t adminq_destroy_tx_queue_cnt; 368 uint32_t adminq_destroy_rx_queue_cnt; 369 uint32_t adminq_dcfg_device_resources_cnt; 370 uint32_t adminq_set_driver_parameter_cnt; 371 uint32_t adminq_verify_driver_compatibility_cnt; 372 373 uint32_t interface_up_cnt; 374 uint32_t interface_down_cnt; 375 uint32_t reset_cnt; 376 377 struct task service_task; 378 struct taskqueue *service_tq; 379 380 struct gve_state_flags state_flags; 381 struct sx gve_iface_lock; 382 }; 383 384 static inline bool 385 gve_get_state_flag(struct gve_priv *priv, int pos) 386 { 387 return (BIT_ISSET(GVE_NUM_STATE_FLAGS, pos, &priv->state_flags)); 388 } 389 390 static inline void 391 gve_set_state_flag(struct gve_priv *priv, int pos) 392 { 393 BIT_SET_ATOMIC(GVE_NUM_STATE_FLAGS, pos, &priv->state_flags); 394 } 395 396 static inline void 397 gve_clear_state_flag(struct gve_priv *priv, int pos) 398 { 399 BIT_CLR_ATOMIC(GVE_NUM_STATE_FLAGS, pos, &priv->state_flags); 400 } 401 402 /* Defined in gve_main.c */ 403 void gve_schedule_reset(struct gve_priv *priv); 404 405 /* Register access functions defined in gve_utils.c */ 406 uint32_t gve_reg_bar_read_4(struct gve_priv *priv, bus_size_t offset); 407 void gve_reg_bar_write_4(struct gve_priv *priv, bus_size_t offset, uint32_t val); 408 void gve_db_bar_write_4(struct gve_priv *priv, bus_size_t offset, uint32_t val); 409 410 /* QPL (Queue Page List) functions defined in gve_qpl.c */ 411 int gve_alloc_qpls(struct gve_priv *priv); 412 void gve_free_qpls(struct gve_priv *priv); 413 int gve_register_qpls(struct gve_priv *priv); 414 int gve_unregister_qpls(struct gve_priv *priv); 415 416 /* TX functions defined in gve_tx.c */ 417 int gve_alloc_tx_rings(struct gve_priv *priv); 418 void gve_free_tx_rings(struct gve_priv *priv); 419 int gve_create_tx_rings(struct gve_priv *priv); 420 int gve_destroy_tx_rings(struct gve_priv *priv); 421 int gve_tx_intr(void *arg); 422 int gve_xmit_ifp(if_t ifp, struct mbuf *mbuf); 423 void gve_qflush(if_t ifp); 424 void gve_xmit_tq(void *arg, int pending); 425 void gve_tx_cleanup_tq(void *arg, int pending); 426 427 /* RX functions defined in gve_rx.c */ 428 int gve_alloc_rx_rings(struct gve_priv *priv); 429 void gve_free_rx_rings(struct gve_priv *priv); 430 int gve_create_rx_rings(struct gve_priv *priv); 431 int gve_destroy_rx_rings(struct gve_priv *priv); 432 int gve_rx_intr(void *arg); 433 void gve_rx_cleanup_tq(void *arg, int pending); 434 435 /* DMA functions defined in gve_utils.c */ 436 int gve_dma_alloc_coherent(struct gve_priv *priv, int size, int align, 437 struct gve_dma_handle *dma); 438 void gve_dma_free_coherent(struct gve_dma_handle *dma); 439 int gve_dmamap_create(struct gve_priv *priv, int size, int align, 440 struct gve_dma_handle *dma); 441 void gve_dmamap_destroy(struct gve_dma_handle *dma); 442 443 /* IRQ functions defined in gve_utils.c */ 444 void gve_free_irqs(struct gve_priv *priv); 445 int gve_alloc_irqs(struct gve_priv *priv); 446 void gve_unmask_all_queue_irqs(struct gve_priv *priv); 447 void gve_mask_all_queue_irqs(struct gve_priv *priv); 448 449 /* Systcl functions defined in gve_sysctl.c*/ 450 void gve_setup_sysctl(struct gve_priv *priv); 451 void gve_accum_stats(struct gve_priv *priv, uint64_t *rpackets, 452 uint64_t *rbytes, uint64_t *rx_dropped_pkt, uint64_t *tpackets, 453 uint64_t *tbytes, uint64_t *tx_dropped_pkt); 454 455 /* Stats functions defined in gve_utils.c */ 456 void gve_alloc_counters(counter_u64_t *stat, int num_stats); 457 void gve_free_counters(counter_u64_t *stat, int num_stats); 458 459 #endif /* _GVE_FBSD_H_ */ 460