1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003-2008 Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 /* Support for the AMD K7 and later processors */ 35 36 #include <sys/param.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/mutex.h> 40 #include <sys/pcpu.h> 41 #include <sys/pmc.h> 42 #include <sys/pmckern.h> 43 #include <sys/smp.h> 44 #include <sys/systm.h> 45 46 #include <machine/cpu.h> 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #ifdef HWPMC_DEBUG 52 enum pmc_class amd_pmc_class; 53 #endif 54 55 #define OVERFLOW_WAIT_COUNT 50 56 57 DPCPU_DEFINE_STATIC(uint32_t, nmi_counter); 58 59 /* AMD K7 & K8 PMCs */ 60 struct amd_descr { 61 struct pmc_descr pm_descr; /* "base class" */ 62 uint32_t pm_evsel; /* address of EVSEL register */ 63 uint32_t pm_perfctr; /* address of PERFCTR register */ 64 }; 65 66 static struct amd_descr amd_pmcdesc[AMD_NPMCS] = 67 { 68 { 69 .pm_descr = 70 { 71 .pd_name = "", 72 .pd_class = -1, 73 .pd_caps = AMD_PMC_CAPS, 74 .pd_width = 48 75 }, 76 .pm_evsel = AMD_PMC_EVSEL_0, 77 .pm_perfctr = AMD_PMC_PERFCTR_0 78 }, 79 { 80 .pm_descr = 81 { 82 .pd_name = "", 83 .pd_class = -1, 84 .pd_caps = AMD_PMC_CAPS, 85 .pd_width = 48 86 }, 87 .pm_evsel = AMD_PMC_EVSEL_1, 88 .pm_perfctr = AMD_PMC_PERFCTR_1 89 }, 90 { 91 .pm_descr = 92 { 93 .pd_name = "", 94 .pd_class = -1, 95 .pd_caps = AMD_PMC_CAPS, 96 .pd_width = 48 97 }, 98 .pm_evsel = AMD_PMC_EVSEL_2, 99 .pm_perfctr = AMD_PMC_PERFCTR_2 100 }, 101 { 102 .pm_descr = 103 { 104 .pd_name = "", 105 .pd_class = -1, 106 .pd_caps = AMD_PMC_CAPS, 107 .pd_width = 48 108 }, 109 .pm_evsel = AMD_PMC_EVSEL_3, 110 .pm_perfctr = AMD_PMC_PERFCTR_3 111 }, 112 { 113 .pm_descr = 114 { 115 .pd_name = "", 116 .pd_class = -1, 117 .pd_caps = AMD_PMC_CAPS, 118 .pd_width = 48 119 }, 120 .pm_evsel = AMD_PMC_EVSEL_4, 121 .pm_perfctr = AMD_PMC_PERFCTR_4 122 }, 123 { 124 .pm_descr = 125 { 126 .pd_name = "", 127 .pd_class = -1, 128 .pd_caps = AMD_PMC_CAPS, 129 .pd_width = 48 130 }, 131 .pm_evsel = AMD_PMC_EVSEL_5, 132 .pm_perfctr = AMD_PMC_PERFCTR_5 133 }, 134 { 135 .pm_descr = 136 { 137 .pd_name = "", 138 .pd_class = -1, 139 .pd_caps = AMD_PMC_CAPS, 140 .pd_width = 48 141 }, 142 .pm_evsel = AMD_PMC_EVSEL_EP_L3_0, 143 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_0 144 }, 145 { 146 .pm_descr = 147 { 148 .pd_name = "", 149 .pd_class = -1, 150 .pd_caps = AMD_PMC_CAPS, 151 .pd_width = 48 152 }, 153 .pm_evsel = AMD_PMC_EVSEL_EP_L3_1, 154 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_1 155 }, 156 { 157 .pm_descr = 158 { 159 .pd_name = "", 160 .pd_class = -1, 161 .pd_caps = AMD_PMC_CAPS, 162 .pd_width = 48 163 }, 164 .pm_evsel = AMD_PMC_EVSEL_EP_L3_2, 165 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_2 166 }, 167 { 168 .pm_descr = 169 { 170 .pd_name = "", 171 .pd_class = -1, 172 .pd_caps = AMD_PMC_CAPS, 173 .pd_width = 48 174 }, 175 .pm_evsel = AMD_PMC_EVSEL_EP_L3_3, 176 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_3 177 }, 178 { 179 .pm_descr = 180 { 181 .pd_name = "", 182 .pd_class = -1, 183 .pd_caps = AMD_PMC_CAPS, 184 .pd_width = 48 185 }, 186 .pm_evsel = AMD_PMC_EVSEL_EP_L3_4, 187 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_4 188 }, 189 { 190 .pm_descr = 191 { 192 .pd_name = "", 193 .pd_class = -1, 194 .pd_caps = AMD_PMC_CAPS, 195 .pd_width = 48 196 }, 197 .pm_evsel = AMD_PMC_EVSEL_EP_L3_5, 198 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_5 199 }, 200 { 201 .pm_descr = 202 { 203 .pd_name = "", 204 .pd_class = -1, 205 .pd_caps = AMD_PMC_CAPS, 206 .pd_width = 48 207 }, 208 .pm_evsel = AMD_PMC_EVSEL_EP_DF_0, 209 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_0 210 }, 211 { 212 .pm_descr = 213 { 214 .pd_name = "", 215 .pd_class = -1, 216 .pd_caps = AMD_PMC_CAPS, 217 .pd_width = 48 218 }, 219 .pm_evsel = AMD_PMC_EVSEL_EP_DF_1, 220 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_1 221 }, 222 { 223 .pm_descr = 224 { 225 .pd_name = "", 226 .pd_class = -1, 227 .pd_caps = AMD_PMC_CAPS, 228 .pd_width = 48 229 }, 230 .pm_evsel = AMD_PMC_EVSEL_EP_DF_2, 231 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_2 232 }, 233 { 234 .pm_descr = 235 { 236 .pd_name = "", 237 .pd_class = -1, 238 .pd_caps = AMD_PMC_CAPS, 239 .pd_width = 48 240 }, 241 .pm_evsel = AMD_PMC_EVSEL_EP_DF_3, 242 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_3 243 } 244 }; 245 246 struct amd_event_code_map { 247 enum pmc_event pe_ev; /* enum value */ 248 uint16_t pe_code; /* encoded event mask */ 249 uint8_t pe_mask; /* bits allowed in unit mask */ 250 }; 251 252 const struct amd_event_code_map amd_event_codes[] = { 253 #if defined(__i386__) /* 32 bit Athlon (K7) only */ 254 { PMC_EV_K7_DC_ACCESSES, 0x40, 0 }, 255 { PMC_EV_K7_DC_MISSES, 0x41, 0 }, 256 { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI }, 257 { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI }, 258 { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI }, 259 { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 }, 260 { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 }, 261 { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 }, 262 263 { PMC_EV_K7_IC_FETCHES, 0x80, 0 }, 264 { PMC_EV_K7_IC_MISSES, 0x81, 0 }, 265 266 { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 }, 267 { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 }, 268 269 { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 }, 270 { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 }, 271 { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 }, 272 { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 }, 273 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 }, 274 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 }, 275 { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 }, 276 { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 }, 277 { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 }, 278 { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 }, 279 { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 }, 280 #endif 281 282 { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F }, 283 { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 }, 284 { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 }, 285 286 { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F }, 287 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE, 288 0x21, 0x00 }, 289 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 }, 290 { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 }, 291 { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 }, 292 { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 }, 293 { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 }, 294 { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 }, 295 296 { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 }, 297 { PMC_EV_K8_DC_MISS, 0x41, 0x00 }, 298 { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F }, 299 { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F }, 300 { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F }, 301 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 }, 302 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 }, 303 { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 }, 304 { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 }, 305 { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 }, 306 { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 }, 307 { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 }, 308 { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 }, 309 310 { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 }, 311 { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F }, 312 { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 }, 313 { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 }, 314 315 { PMC_EV_K8_IC_FETCH, 0x80, 0x00 }, 316 { PMC_EV_K8_IC_MISS, 0x81, 0x00 }, 317 { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 }, 318 { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 }, 319 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 }, 320 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 }, 321 { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 }, 322 { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 }, 323 { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 }, 324 { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 }, 325 326 { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 }, 327 { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 }, 328 { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 }, 329 { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 }, 330 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 }, 331 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 }, 332 { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 }, 333 { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 }, 334 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 }, 335 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 }, 336 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE, 337 0xCA, 0x00 }, 338 { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F }, 339 { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS, 340 0xCC, 0x07 }, 341 { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 }, 342 { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 }, 343 { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 }, 344 345 { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 }, 346 { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 }, 347 { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE, 348 0xD2, 0x00 }, 349 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 }, 350 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 }, 351 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL, 352 0xD5, 0x00 }, 353 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL, 354 0xD6, 0x00 }, 355 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 }, 356 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 }, 357 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET, 358 0xD9, 0x00 }, 359 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING, 360 0xDA, 0x00 }, 361 { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F }, 362 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 }, 363 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 }, 364 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 }, 365 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 }, 366 367 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 }, 368 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 }, 369 { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED, 370 0xE2, 0x00 }, 371 { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 }, 372 { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F }, 373 { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F }, 374 { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F }, 375 { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F }, 376 { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F }, 377 { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F } 378 379 }; 380 381 const int amd_event_codes_size = nitems(amd_event_codes); 382 383 /* 384 * Per-processor information 385 */ 386 387 struct amd_cpu { 388 struct pmc_hw pc_amdpmcs[AMD_NPMCS]; 389 }; 390 391 static struct amd_cpu **amd_pcpu; 392 393 /* 394 * read a pmc register 395 */ 396 397 static int 398 amd_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v) 399 { 400 enum pmc_mode mode; 401 const struct amd_descr *pd; 402 pmc_value_t tmp; 403 404 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 405 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 406 KASSERT(ri >= 0 && ri < AMD_NPMCS, 407 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 408 KASSERT(amd_pcpu[cpu], 409 ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu)); 410 411 pd = &amd_pmcdesc[ri]; 412 mode = PMC_TO_MODE(pm); 413 414 PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class); 415 416 #ifdef HWPMC_DEBUG 417 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 418 ("[amd,%d] unknown PMC class (%d)", __LINE__, 419 pd->pm_descr.pd_class)); 420 #endif 421 422 tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */ 423 PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp); 424 if (PMC_IS_SAMPLING_MODE(mode)) { 425 /* 426 * Clamp value to 0 if the counter just overflowed, 427 * otherwise the returned reload count would wrap to a 428 * huge value. 429 */ 430 if ((tmp & (1ULL << 47)) == 0) 431 tmp = 0; 432 else { 433 /* Sign extend 48 bit value to 64 bits. */ 434 tmp = (pmc_value_t) ((int64_t)(tmp << 16) >> 16); 435 tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 436 } 437 } 438 *v = tmp; 439 440 PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v); 441 442 return 0; 443 } 444 445 /* 446 * Write a PMC MSR. 447 */ 448 449 static int 450 amd_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v) 451 { 452 const struct amd_descr *pd; 453 enum pmc_mode mode; 454 455 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 456 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 457 KASSERT(ri >= 0 && ri < AMD_NPMCS, 458 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 459 460 pd = &amd_pmcdesc[ri]; 461 mode = PMC_TO_MODE(pm); 462 463 #ifdef HWPMC_DEBUG 464 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 465 ("[amd,%d] unknown PMC class (%d)", __LINE__, 466 pd->pm_descr.pd_class)); 467 #endif 468 469 /* use 2's complement of the count for sampling mode PMCs */ 470 if (PMC_IS_SAMPLING_MODE(mode)) 471 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 472 473 PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v); 474 475 /* write the PMC value */ 476 wrmsr(pd->pm_perfctr, v); 477 return 0; 478 } 479 480 /* 481 * configure hardware pmc according to the configuration recorded in 482 * pmc 'pm'. 483 */ 484 485 static int 486 amd_config_pmc(int cpu, int ri, struct pmc *pm) 487 { 488 struct pmc_hw *phw; 489 490 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 491 492 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 493 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 494 KASSERT(ri >= 0 && ri < AMD_NPMCS, 495 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 496 497 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 498 499 KASSERT(pm == NULL || phw->phw_pmc == NULL, 500 ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 501 __LINE__, pm, phw->phw_pmc)); 502 503 phw->phw_pmc = pm; 504 return 0; 505 } 506 507 /* 508 * Retrieve a configured PMC pointer from hardware state. 509 */ 510 511 static int 512 amd_get_config(int cpu, int ri, struct pmc **ppm) 513 { 514 *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 515 516 return 0; 517 } 518 519 /* 520 * Machine dependent actions taken during the context switch in of a 521 * thread. 522 */ 523 524 static int 525 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 526 { 527 (void) pc; 528 529 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 530 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0); 531 532 /* enable the RDPMC instruction if needed */ 533 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 534 load_cr4(rcr4() | CR4_PCE); 535 536 return 0; 537 } 538 539 /* 540 * Machine dependent actions taken during the context switch out of a 541 * thread. 542 */ 543 544 static int 545 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 546 { 547 (void) pc; 548 (void) pp; /* can be NULL */ 549 550 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ? 551 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0); 552 553 /* always turn off the RDPMC instruction */ 554 load_cr4(rcr4() & ~CR4_PCE); 555 556 return 0; 557 } 558 559 /* 560 * Check if a given allocation is feasible. 561 */ 562 563 static int 564 amd_allocate_pmc(int cpu, int ri, struct pmc *pm, 565 const struct pmc_op_pmcallocate *a) 566 { 567 int i; 568 uint64_t allowed_unitmask, caps, config, unitmask; 569 enum pmc_event pe; 570 const struct pmc_descr *pd; 571 572 (void) cpu; 573 574 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 575 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 576 KASSERT(ri >= 0 && ri < AMD_NPMCS, 577 ("[amd,%d] illegal row index %d", __LINE__, ri)); 578 579 pd = &amd_pmcdesc[ri].pm_descr; 580 581 /* check class match */ 582 if (pd->pd_class != a->pm_class) 583 return EINVAL; 584 585 caps = pm->pm_caps; 586 587 PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps); 588 589 if((ri >= 0 && ri < 6) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_CORE)) 590 return EINVAL; 591 if((ri >= 6 && ri < 12) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_L3_CACHE)) 592 return EINVAL; 593 if((ri >= 12 && ri < 16) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_DATA_FABRIC)) 594 return EINVAL; 595 596 if (strlen(pmc_cpuid) != 0) { 597 pm->pm_md.pm_amd.pm_amd_evsel = 598 a->pm_md.pm_amd.pm_amd_config; 599 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, a->pm_md.pm_amd.pm_amd_config); 600 return (0); 601 } 602 603 pe = a->pm_ev; 604 605 /* map ev to the correct event mask code */ 606 config = allowed_unitmask = 0; 607 for (i = 0; i < amd_event_codes_size; i++) 608 if (amd_event_codes[i].pe_ev == pe) { 609 config = 610 AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code); 611 allowed_unitmask = 612 AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask); 613 break; 614 } 615 if (i == amd_event_codes_size) 616 return EINVAL; 617 618 unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK; 619 if (unitmask & ~allowed_unitmask) /* disallow reserved bits */ 620 return EINVAL; 621 622 if (unitmask && (caps & PMC_CAP_QUALIFIER)) 623 config |= unitmask; 624 625 if (caps & PMC_CAP_THRESHOLD) 626 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK; 627 628 /* set at least one of the 'usr' or 'os' caps */ 629 if (caps & PMC_CAP_USER) 630 config |= AMD_PMC_USR; 631 if (caps & PMC_CAP_SYSTEM) 632 config |= AMD_PMC_OS; 633 if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0) 634 config |= (AMD_PMC_USR|AMD_PMC_OS); 635 636 if (caps & PMC_CAP_EDGE) 637 config |= AMD_PMC_EDGE; 638 if (caps & PMC_CAP_INVERT) 639 config |= AMD_PMC_INVERT; 640 if (caps & PMC_CAP_INTERRUPT) 641 config |= AMD_PMC_INT; 642 643 pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */ 644 645 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config); 646 647 return 0; 648 } 649 650 /* 651 * Release machine dependent state associated with a PMC. This is a 652 * no-op on this architecture. 653 * 654 */ 655 656 /* ARGSUSED0 */ 657 static int 658 amd_release_pmc(int cpu, int ri, struct pmc *pmc) 659 { 660 #ifdef HWPMC_DEBUG 661 const struct amd_descr *pd; 662 #endif 663 struct pmc_hw *phw __diagused; 664 665 (void) pmc; 666 667 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 668 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 669 KASSERT(ri >= 0 && ri < AMD_NPMCS, 670 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 671 672 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 673 674 KASSERT(phw->phw_pmc == NULL, 675 ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 676 677 #ifdef HWPMC_DEBUG 678 pd = &amd_pmcdesc[ri]; 679 if (pd->pm_descr.pd_class == amd_pmc_class) 680 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 681 ("[amd,%d] PMC %d released while active", __LINE__, ri)); 682 #endif 683 684 return 0; 685 } 686 687 /* 688 * start a PMC. 689 */ 690 691 static int 692 amd_start_pmc(int cpu, int ri, struct pmc *pm) 693 { 694 uint64_t config; 695 const struct amd_descr *pd; 696 697 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 698 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 699 KASSERT(ri >= 0 && ri < AMD_NPMCS, 700 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 701 702 pd = &amd_pmcdesc[ri]; 703 704 PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri); 705 706 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 707 ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__, 708 ri, cpu, pd->pm_descr.pd_name)); 709 710 /* turn on the PMC ENABLE bit */ 711 config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE; 712 713 PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config); 714 715 wrmsr(pd->pm_evsel, config); 716 return 0; 717 } 718 719 /* 720 * Stop a PMC. 721 */ 722 723 static int 724 amd_stop_pmc(int cpu, int ri, struct pmc *pm) 725 { 726 const struct amd_descr *pd; 727 uint64_t config; 728 int i; 729 730 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 731 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 732 KASSERT(ri >= 0 && ri < AMD_NPMCS, 733 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 734 735 pd = &amd_pmcdesc[ri]; 736 737 KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel), 738 ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped", 739 __LINE__, ri, cpu, pd->pm_descr.pd_name)); 740 741 PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri); 742 743 /* turn off the PMC ENABLE bit */ 744 config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE; 745 wrmsr(pd->pm_evsel, config); 746 747 /* 748 * Due to NMI latency on newer AMD processors 749 * NMI interrupts are ignored, which leads to 750 * panic or messages based on kernel configuration 751 */ 752 753 /* Wait for the count to be reset */ 754 for (i = 0; i < OVERFLOW_WAIT_COUNT; i++) { 755 if (rdmsr(pd->pm_perfctr) & (1 << (pd->pm_descr.pd_width - 1))) 756 break; 757 758 DELAY(1); 759 } 760 761 return 0; 762 } 763 764 /* 765 * Interrupt handler. This function needs to return '1' if the 766 * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed 767 * to sleep or do anything a 'fast' interrupt handler is not allowed 768 * to do. 769 */ 770 771 static int 772 amd_intr(struct trapframe *tf) 773 { 774 int i, error, retval, cpu; 775 uint64_t config, evsel, perfctr; 776 struct pmc *pm; 777 struct amd_cpu *pac; 778 pmc_value_t v; 779 uint32_t active = 0, count = 0; 780 781 cpu = curcpu; 782 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 783 ("[amd,%d] out of range CPU %d", __LINE__, cpu)); 784 785 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf, 786 TRAPF_USERMODE(tf)); 787 788 retval = 0; 789 790 pac = amd_pcpu[cpu]; 791 792 /* 793 * look for all PMCs that have interrupted: 794 * - look for a running, sampling PMC which has overflowed 795 * and which has a valid 'struct pmc' association 796 * 797 * If found, we call a helper to process the interrupt. 798 * 799 * PMCs interrupting at the same time are collapsed into 800 * a single interrupt. Check all the valid pmcs for 801 * overflow. 802 */ 803 804 for (i = 0; i < AMD_CORE_NPMCS; i++) { 805 806 if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL || 807 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 808 continue; 809 } 810 811 /* Consider pmc with valid handle as active */ 812 active++; 813 814 if (!AMD_PMC_HAS_OVERFLOWED(i)) 815 continue; 816 817 retval = 1; /* Found an interrupting PMC. */ 818 819 if (pm->pm_state != PMC_STATE_RUNNING) 820 continue; 821 822 /* Stop the PMC, reload count. */ 823 evsel = amd_pmcdesc[i].pm_evsel; 824 perfctr = amd_pmcdesc[i].pm_perfctr; 825 v = pm->pm_sc.pm_reloadcount; 826 config = rdmsr(evsel); 827 828 KASSERT((config & ~AMD_PMC_ENABLE) == 829 (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE), 830 ("[amd,%d] config mismatch reg=0x%jx pm=0x%jx", __LINE__, 831 (uintmax_t)config, (uintmax_t)pm->pm_md.pm_amd.pm_amd_evsel)); 832 833 wrmsr(evsel, config & ~AMD_PMC_ENABLE); 834 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v)); 835 836 /* Restart the counter if logging succeeded. */ 837 error = pmc_process_interrupt(PMC_HR, pm, tf); 838 if (error == 0) 839 wrmsr(evsel, config); 840 } 841 842 /* 843 * Due to NMI latency, there can be a scenario in which 844 * multiple pmcs gets serviced in an earlier NMI and we 845 * do not find an overflow in the subsequent NMI. 846 * 847 * For such cases we keep a per-cpu count of active NMIs 848 * and compare it with min(active pmcs, 2) to determine 849 * if this NMI was for a pmc overflow which was serviced 850 * in an earlier request or should be ignored. 851 */ 852 853 if (retval) { 854 DPCPU_SET(nmi_counter, min(2, active)); 855 } else { 856 if ((count = DPCPU_GET(nmi_counter))) { 857 retval = 1; 858 DPCPU_SET(nmi_counter, --count); 859 } 860 } 861 862 if (retval) 863 counter_u64_add(pmc_stats.pm_intr_processed, 1); 864 else 865 counter_u64_add(pmc_stats.pm_intr_ignored, 1); 866 867 PMCDBG1(MDP,INT,2, "retval=%d", retval); 868 return (retval); 869 } 870 871 /* 872 * describe a PMC 873 */ 874 static int 875 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 876 { 877 const struct amd_descr *pd; 878 struct pmc_hw *phw; 879 880 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 881 ("[amd,%d] illegal CPU %d", __LINE__, cpu)); 882 KASSERT(ri >= 0 && ri < AMD_NPMCS, 883 ("[amd,%d] row-index %d out of range", __LINE__, ri)); 884 885 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 886 pd = &amd_pmcdesc[ri]; 887 888 strlcpy(pi->pm_name, pd->pm_descr.pd_name, sizeof(pi->pm_name)); 889 pi->pm_class = pd->pm_descr.pd_class; 890 891 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 892 pi->pm_enabled = TRUE; 893 *ppmc = phw->phw_pmc; 894 } else { 895 pi->pm_enabled = FALSE; 896 *ppmc = NULL; 897 } 898 899 return 0; 900 } 901 902 /* 903 * i386 specific entry points 904 */ 905 906 /* 907 * return the MSR address of the given PMC. 908 */ 909 910 static int 911 amd_get_msr(int ri, uint32_t *msr) 912 { 913 KASSERT(ri >= 0 && ri < AMD_NPMCS, 914 ("[amd,%d] ri %d out of range", __LINE__, ri)); 915 916 *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0; 917 918 return (0); 919 } 920 921 /* 922 * processor dependent initialization. 923 */ 924 925 static int 926 amd_pcpu_init(struct pmc_mdep *md, int cpu) 927 { 928 int classindex, first_ri, n; 929 struct pmc_cpu *pc; 930 struct amd_cpu *pac; 931 struct pmc_hw *phw; 932 933 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 934 ("[amd,%d] insane cpu number %d", __LINE__, cpu)); 935 936 PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu); 937 938 amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC, 939 M_WAITOK|M_ZERO); 940 941 /* 942 * Set the content of the hardware descriptors to a known 943 * state and initialize pointers in the MI per-cpu descriptor. 944 */ 945 pc = pmc_pcpu[cpu]; 946 #if defined(__amd64__) 947 classindex = PMC_MDEP_CLASS_INDEX_K8; 948 #elif defined(__i386__) 949 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? 950 PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7; 951 #endif 952 first_ri = md->pmd_classdep[classindex].pcd_ri; 953 954 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__)); 955 956 for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) { 957 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 958 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n); 959 phw->phw_pmc = NULL; 960 pc->pc_hwpmcs[n + first_ri] = phw; 961 } 962 963 return (0); 964 } 965 966 967 /* 968 * processor dependent cleanup prior to the KLD 969 * being unloaded 970 */ 971 972 static int 973 amd_pcpu_fini(struct pmc_mdep *md, int cpu) 974 { 975 int classindex, first_ri, i; 976 uint32_t evsel; 977 struct pmc_cpu *pc; 978 struct amd_cpu *pac; 979 980 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 981 ("[amd,%d] insane cpu number (%d)", __LINE__, cpu)); 982 983 PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu); 984 985 /* 986 * First, turn off all PMCs on this CPU. 987 */ 988 for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */ 989 evsel = rdmsr(AMD_PMC_EVSEL_0 + i); 990 evsel &= ~AMD_PMC_ENABLE; 991 wrmsr(AMD_PMC_EVSEL_0 + i, evsel); 992 } 993 994 /* 995 * Next, free up allocated space. 996 */ 997 if ((pac = amd_pcpu[cpu]) == NULL) 998 return (0); 999 1000 amd_pcpu[cpu] = NULL; 1001 1002 #ifdef HWPMC_DEBUG 1003 for (i = 0; i < AMD_NPMCS; i++) { 1004 KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL, 1005 ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i)); 1006 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i), 1007 ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i)); 1008 } 1009 #endif 1010 1011 pc = pmc_pcpu[cpu]; 1012 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__)); 1013 1014 #if defined(__amd64__) 1015 classindex = PMC_MDEP_CLASS_INDEX_K8; 1016 #elif defined(__i386__) 1017 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 : 1018 PMC_MDEP_CLASS_INDEX_K7; 1019 #endif 1020 first_ri = md->pmd_classdep[classindex].pcd_ri; 1021 1022 /* 1023 * Reset pointers in the MI 'per-cpu' state. 1024 */ 1025 for (i = 0; i < AMD_NPMCS; i++) { 1026 pc->pc_hwpmcs[i + first_ri] = NULL; 1027 } 1028 1029 1030 free(pac, M_PMC); 1031 1032 return (0); 1033 } 1034 1035 /* 1036 * Initialize ourselves. 1037 */ 1038 1039 struct pmc_mdep * 1040 pmc_amd_initialize(void) 1041 { 1042 int classindex, error, i, ncpus; 1043 struct pmc_classdep *pcd; 1044 enum pmc_cputype cputype; 1045 struct pmc_mdep *pmc_mdep; 1046 enum pmc_class class; 1047 int family, model, stepping; 1048 char *name; 1049 1050 /* 1051 * The presence of hardware performance counters on the AMD 1052 * Athlon, Duron or later processors, is _not_ indicated by 1053 * any of the processor feature flags set by the 'CPUID' 1054 * instruction, so we only check the 'instruction family' 1055 * field returned by CPUID for instruction family >= 6. 1056 */ 1057 1058 name = NULL; 1059 family = CPUID_TO_FAMILY(cpu_id); 1060 model = CPUID_TO_MODEL(cpu_id); 1061 stepping = CPUID_TO_STEPPING(cpu_id); 1062 1063 if (family == 0x18) 1064 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "HygonGenuine-%d-%02X-%X", 1065 family, model, stepping); 1066 else 1067 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "AuthenticAMD-%d-%02X-%X", 1068 family, model, stepping); 1069 1070 switch (cpu_id & 0xF00) { 1071 #if defined(__i386__) 1072 case 0x600: /* Athlon(tm) processor */ 1073 classindex = PMC_MDEP_CLASS_INDEX_K7; 1074 cputype = PMC_CPU_AMD_K7; 1075 class = PMC_CLASS_K7; 1076 name = "K7"; 1077 break; 1078 #endif 1079 case 0xF00: /* Athlon64/Opteron processor */ 1080 classindex = PMC_MDEP_CLASS_INDEX_K8; 1081 cputype = PMC_CPU_AMD_K8; 1082 class = PMC_CLASS_K8; 1083 name = "K8"; 1084 break; 1085 1086 default: 1087 (void) printf("pmc: Unknown AMD CPU %x %d-%d.\n", cpu_id, (cpu_id & 0xF00) >> 8, model); 1088 return NULL; 1089 } 1090 1091 #ifdef HWPMC_DEBUG 1092 amd_pmc_class = class; 1093 #endif 1094 1095 /* 1096 * Allocate space for pointers to PMC HW descriptors and for 1097 * the MDEP structure used by MI code. 1098 */ 1099 amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC, 1100 M_WAITOK|M_ZERO); 1101 1102 /* 1103 * These processors have two classes of PMCs: the TSC and 1104 * programmable PMCs. 1105 */ 1106 pmc_mdep = pmc_mdep_alloc(2); 1107 1108 pmc_mdep->pmd_cputype = cputype; 1109 1110 ncpus = pmc_cpu_max(); 1111 1112 /* Initialize the TSC. */ 1113 error = pmc_tsc_initialize(pmc_mdep, ncpus); 1114 if (error) 1115 goto error; 1116 1117 /* Initialize AMD K7 and K8 PMC handling. */ 1118 pcd = &pmc_mdep->pmd_classdep[classindex]; 1119 1120 pcd->pcd_caps = AMD_PMC_CAPS; 1121 pcd->pcd_class = class; 1122 pcd->pcd_num = AMD_NPMCS; 1123 pcd->pcd_ri = pmc_mdep->pmd_npmc; 1124 pcd->pcd_width = 48; 1125 1126 /* fill in the correct pmc name and class */ 1127 for (i = 0; i < AMD_NPMCS; i++) { 1128 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name, 1129 sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d", 1130 name, i); 1131 amd_pmcdesc[i].pm_descr.pd_class = class; 1132 } 1133 1134 pcd->pcd_allocate_pmc = amd_allocate_pmc; 1135 pcd->pcd_config_pmc = amd_config_pmc; 1136 pcd->pcd_describe = amd_describe; 1137 pcd->pcd_get_config = amd_get_config; 1138 pcd->pcd_get_msr = amd_get_msr; 1139 pcd->pcd_pcpu_fini = amd_pcpu_fini; 1140 pcd->pcd_pcpu_init = amd_pcpu_init; 1141 pcd->pcd_read_pmc = amd_read_pmc; 1142 pcd->pcd_release_pmc = amd_release_pmc; 1143 pcd->pcd_start_pmc = amd_start_pmc; 1144 pcd->pcd_stop_pmc = amd_stop_pmc; 1145 pcd->pcd_write_pmc = amd_write_pmc; 1146 1147 pmc_mdep->pmd_intr = amd_intr; 1148 pmc_mdep->pmd_switch_in = amd_switch_in; 1149 pmc_mdep->pmd_switch_out = amd_switch_out; 1150 1151 pmc_mdep->pmd_npmc += AMD_NPMCS; 1152 1153 PMCDBG0(MDP,INI,0,"amd-initialize"); 1154 1155 return (pmc_mdep); 1156 1157 error: 1158 if (error) { 1159 free(pmc_mdep, M_PMC); 1160 pmc_mdep = NULL; 1161 } 1162 1163 return (NULL); 1164 } 1165 1166 /* 1167 * Finalization code for AMD CPUs. 1168 */ 1169 1170 void 1171 pmc_amd_finalize(struct pmc_mdep *md) 1172 { 1173 #if defined(INVARIANTS) 1174 int classindex, i, ncpus, pmcclass; 1175 #endif 1176 1177 pmc_tsc_finalize(md); 1178 1179 KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer", 1180 __LINE__)); 1181 1182 #if defined(INVARIANTS) 1183 switch (md->pmd_cputype) { 1184 #if defined(__i386__) 1185 case PMC_CPU_AMD_K7: 1186 classindex = PMC_MDEP_CLASS_INDEX_K7; 1187 pmcclass = PMC_CLASS_K7; 1188 break; 1189 #endif 1190 default: 1191 classindex = PMC_MDEP_CLASS_INDEX_K8; 1192 pmcclass = PMC_CLASS_K8; 1193 } 1194 1195 KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass, 1196 ("[amd,%d] pmc class mismatch", __LINE__)); 1197 1198 ncpus = pmc_cpu_max(); 1199 1200 for (i = 0; i < ncpus; i++) 1201 KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu", 1202 __LINE__)); 1203 #endif 1204 1205 free(amd_pcpu, M_PMC); 1206 amd_pcpu = NULL; 1207 } 1208