1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003-2008 Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* Support for the AMD K7 and later processors */ 37 38 #include <sys/param.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/mutex.h> 42 #include <sys/pcpu.h> 43 #include <sys/pmc.h> 44 #include <sys/pmckern.h> 45 #include <sys/smp.h> 46 #include <sys/systm.h> 47 48 #include <machine/cpu.h> 49 #include <machine/cpufunc.h> 50 #include <machine/md_var.h> 51 #include <machine/specialreg.h> 52 53 #ifdef HWPMC_DEBUG 54 enum pmc_class amd_pmc_class; 55 #endif 56 57 #define OVERFLOW_WAIT_COUNT 50 58 59 DPCPU_DEFINE_STATIC(uint32_t, nmi_counter); 60 61 /* AMD K7 & K8 PMCs */ 62 struct amd_descr { 63 struct pmc_descr pm_descr; /* "base class" */ 64 uint32_t pm_evsel; /* address of EVSEL register */ 65 uint32_t pm_perfctr; /* address of PERFCTR register */ 66 }; 67 68 static struct amd_descr amd_pmcdesc[AMD_NPMCS] = 69 { 70 { 71 .pm_descr = 72 { 73 .pd_name = "", 74 .pd_class = -1, 75 .pd_caps = AMD_PMC_CAPS, 76 .pd_width = 48 77 }, 78 .pm_evsel = AMD_PMC_EVSEL_0, 79 .pm_perfctr = AMD_PMC_PERFCTR_0 80 }, 81 { 82 .pm_descr = 83 { 84 .pd_name = "", 85 .pd_class = -1, 86 .pd_caps = AMD_PMC_CAPS, 87 .pd_width = 48 88 }, 89 .pm_evsel = AMD_PMC_EVSEL_1, 90 .pm_perfctr = AMD_PMC_PERFCTR_1 91 }, 92 { 93 .pm_descr = 94 { 95 .pd_name = "", 96 .pd_class = -1, 97 .pd_caps = AMD_PMC_CAPS, 98 .pd_width = 48 99 }, 100 .pm_evsel = AMD_PMC_EVSEL_2, 101 .pm_perfctr = AMD_PMC_PERFCTR_2 102 }, 103 { 104 .pm_descr = 105 { 106 .pd_name = "", 107 .pd_class = -1, 108 .pd_caps = AMD_PMC_CAPS, 109 .pd_width = 48 110 }, 111 .pm_evsel = AMD_PMC_EVSEL_3, 112 .pm_perfctr = AMD_PMC_PERFCTR_3 113 }, 114 { 115 .pm_descr = 116 { 117 .pd_name = "", 118 .pd_class = -1, 119 .pd_caps = AMD_PMC_CAPS, 120 .pd_width = 48 121 }, 122 .pm_evsel = AMD_PMC_EVSEL_4, 123 .pm_perfctr = AMD_PMC_PERFCTR_4 124 }, 125 { 126 .pm_descr = 127 { 128 .pd_name = "", 129 .pd_class = -1, 130 .pd_caps = AMD_PMC_CAPS, 131 .pd_width = 48 132 }, 133 .pm_evsel = AMD_PMC_EVSEL_5, 134 .pm_perfctr = AMD_PMC_PERFCTR_5 135 }, 136 { 137 .pm_descr = 138 { 139 .pd_name = "", 140 .pd_class = -1, 141 .pd_caps = AMD_PMC_CAPS, 142 .pd_width = 48 143 }, 144 .pm_evsel = AMD_PMC_EVSEL_EP_L3_0, 145 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_0 146 }, 147 { 148 .pm_descr = 149 { 150 .pd_name = "", 151 .pd_class = -1, 152 .pd_caps = AMD_PMC_CAPS, 153 .pd_width = 48 154 }, 155 .pm_evsel = AMD_PMC_EVSEL_EP_L3_1, 156 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_1 157 }, 158 { 159 .pm_descr = 160 { 161 .pd_name = "", 162 .pd_class = -1, 163 .pd_caps = AMD_PMC_CAPS, 164 .pd_width = 48 165 }, 166 .pm_evsel = AMD_PMC_EVSEL_EP_L3_2, 167 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_2 168 }, 169 { 170 .pm_descr = 171 { 172 .pd_name = "", 173 .pd_class = -1, 174 .pd_caps = AMD_PMC_CAPS, 175 .pd_width = 48 176 }, 177 .pm_evsel = AMD_PMC_EVSEL_EP_L3_3, 178 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_3 179 }, 180 { 181 .pm_descr = 182 { 183 .pd_name = "", 184 .pd_class = -1, 185 .pd_caps = AMD_PMC_CAPS, 186 .pd_width = 48 187 }, 188 .pm_evsel = AMD_PMC_EVSEL_EP_L3_4, 189 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_4 190 }, 191 { 192 .pm_descr = 193 { 194 .pd_name = "", 195 .pd_class = -1, 196 .pd_caps = AMD_PMC_CAPS, 197 .pd_width = 48 198 }, 199 .pm_evsel = AMD_PMC_EVSEL_EP_L3_5, 200 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_5 201 }, 202 { 203 .pm_descr = 204 { 205 .pd_name = "", 206 .pd_class = -1, 207 .pd_caps = AMD_PMC_CAPS, 208 .pd_width = 48 209 }, 210 .pm_evsel = AMD_PMC_EVSEL_EP_DF_0, 211 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_0 212 }, 213 { 214 .pm_descr = 215 { 216 .pd_name = "", 217 .pd_class = -1, 218 .pd_caps = AMD_PMC_CAPS, 219 .pd_width = 48 220 }, 221 .pm_evsel = AMD_PMC_EVSEL_EP_DF_1, 222 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_1 223 }, 224 { 225 .pm_descr = 226 { 227 .pd_name = "", 228 .pd_class = -1, 229 .pd_caps = AMD_PMC_CAPS, 230 .pd_width = 48 231 }, 232 .pm_evsel = AMD_PMC_EVSEL_EP_DF_2, 233 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_2 234 }, 235 { 236 .pm_descr = 237 { 238 .pd_name = "", 239 .pd_class = -1, 240 .pd_caps = AMD_PMC_CAPS, 241 .pd_width = 48 242 }, 243 .pm_evsel = AMD_PMC_EVSEL_EP_DF_3, 244 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_3 245 } 246 }; 247 248 struct amd_event_code_map { 249 enum pmc_event pe_ev; /* enum value */ 250 uint16_t pe_code; /* encoded event mask */ 251 uint8_t pe_mask; /* bits allowed in unit mask */ 252 }; 253 254 const struct amd_event_code_map amd_event_codes[] = { 255 #if defined(__i386__) /* 32 bit Athlon (K7) only */ 256 { PMC_EV_K7_DC_ACCESSES, 0x40, 0 }, 257 { PMC_EV_K7_DC_MISSES, 0x41, 0 }, 258 { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI }, 259 { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI }, 260 { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI }, 261 { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 }, 262 { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 }, 263 { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 }, 264 265 { PMC_EV_K7_IC_FETCHES, 0x80, 0 }, 266 { PMC_EV_K7_IC_MISSES, 0x81, 0 }, 267 268 { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 }, 269 { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 }, 270 271 { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 }, 272 { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 }, 273 { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 }, 274 { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 }, 275 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 }, 276 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 }, 277 { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 }, 278 { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 }, 279 { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 }, 280 { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 }, 281 { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 }, 282 #endif 283 284 { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F }, 285 { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 }, 286 { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 }, 287 288 { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F }, 289 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE, 290 0x21, 0x00 }, 291 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 }, 292 { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 }, 293 { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 }, 294 { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 }, 295 { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 }, 296 { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 }, 297 298 { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 }, 299 { PMC_EV_K8_DC_MISS, 0x41, 0x00 }, 300 { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F }, 301 { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F }, 302 { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F }, 303 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 }, 304 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 }, 305 { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 }, 306 { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 }, 307 { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 }, 308 { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 }, 309 { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 }, 310 { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 }, 311 312 { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 }, 313 { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F }, 314 { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 }, 315 { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 }, 316 317 { PMC_EV_K8_IC_FETCH, 0x80, 0x00 }, 318 { PMC_EV_K8_IC_MISS, 0x81, 0x00 }, 319 { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 }, 320 { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 }, 321 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 }, 322 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 }, 323 { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 }, 324 { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 }, 325 { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 }, 326 { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 }, 327 328 { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 }, 329 { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 }, 330 { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 }, 331 { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 }, 332 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 }, 333 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 }, 334 { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 }, 335 { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 }, 336 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 }, 337 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 }, 338 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE, 339 0xCA, 0x00 }, 340 { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F }, 341 { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS, 342 0xCC, 0x07 }, 343 { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 }, 344 { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 }, 345 { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 }, 346 347 { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 }, 348 { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 }, 349 { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE, 350 0xD2, 0x00 }, 351 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 }, 352 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 }, 353 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL, 354 0xD5, 0x00 }, 355 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL, 356 0xD6, 0x00 }, 357 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 }, 358 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 }, 359 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET, 360 0xD9, 0x00 }, 361 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING, 362 0xDA, 0x00 }, 363 { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F }, 364 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 }, 365 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 }, 366 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 }, 367 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 }, 368 369 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 }, 370 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 }, 371 { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED, 372 0xE2, 0x00 }, 373 { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 }, 374 { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F }, 375 { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F }, 376 { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F }, 377 { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F }, 378 { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F }, 379 { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F } 380 381 }; 382 383 const int amd_event_codes_size = nitems(amd_event_codes); 384 385 /* 386 * Per-processor information 387 */ 388 389 struct amd_cpu { 390 struct pmc_hw pc_amdpmcs[AMD_NPMCS]; 391 }; 392 393 static struct amd_cpu **amd_pcpu; 394 395 /* 396 * read a pmc register 397 */ 398 399 static int 400 amd_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v) 401 { 402 enum pmc_mode mode; 403 const struct amd_descr *pd; 404 pmc_value_t tmp; 405 406 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 407 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 408 KASSERT(ri >= 0 && ri < AMD_NPMCS, 409 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 410 KASSERT(amd_pcpu[cpu], 411 ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu)); 412 413 pd = &amd_pmcdesc[ri]; 414 mode = PMC_TO_MODE(pm); 415 416 PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class); 417 418 #ifdef HWPMC_DEBUG 419 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 420 ("[amd,%d] unknown PMC class (%d)", __LINE__, 421 pd->pm_descr.pd_class)); 422 #endif 423 424 tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */ 425 PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp); 426 if (PMC_IS_SAMPLING_MODE(mode)) { 427 /* 428 * Clamp value to 0 if the counter just overflowed, 429 * otherwise the returned reload count would wrap to a 430 * huge value. 431 */ 432 if ((tmp & (1ULL << 47)) == 0) 433 tmp = 0; 434 else { 435 /* Sign extend 48 bit value to 64 bits. */ 436 tmp = (pmc_value_t) ((int64_t)(tmp << 16) >> 16); 437 tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 438 } 439 } 440 *v = tmp; 441 442 PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v); 443 444 return 0; 445 } 446 447 /* 448 * Write a PMC MSR. 449 */ 450 451 static int 452 amd_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v) 453 { 454 const struct amd_descr *pd; 455 enum pmc_mode mode; 456 457 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 458 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 459 KASSERT(ri >= 0 && ri < AMD_NPMCS, 460 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 461 462 pd = &amd_pmcdesc[ri]; 463 mode = PMC_TO_MODE(pm); 464 465 #ifdef HWPMC_DEBUG 466 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 467 ("[amd,%d] unknown PMC class (%d)", __LINE__, 468 pd->pm_descr.pd_class)); 469 #endif 470 471 /* use 2's complement of the count for sampling mode PMCs */ 472 if (PMC_IS_SAMPLING_MODE(mode)) 473 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 474 475 PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v); 476 477 /* write the PMC value */ 478 wrmsr(pd->pm_perfctr, v); 479 return 0; 480 } 481 482 /* 483 * configure hardware pmc according to the configuration recorded in 484 * pmc 'pm'. 485 */ 486 487 static int 488 amd_config_pmc(int cpu, int ri, struct pmc *pm) 489 { 490 struct pmc_hw *phw; 491 492 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 493 494 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 495 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 496 KASSERT(ri >= 0 && ri < AMD_NPMCS, 497 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 498 499 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 500 501 KASSERT(pm == NULL || phw->phw_pmc == NULL, 502 ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 503 __LINE__, pm, phw->phw_pmc)); 504 505 phw->phw_pmc = pm; 506 return 0; 507 } 508 509 /* 510 * Retrieve a configured PMC pointer from hardware state. 511 */ 512 513 static int 514 amd_get_config(int cpu, int ri, struct pmc **ppm) 515 { 516 *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 517 518 return 0; 519 } 520 521 /* 522 * Machine dependent actions taken during the context switch in of a 523 * thread. 524 */ 525 526 static int 527 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 528 { 529 (void) pc; 530 531 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 532 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0); 533 534 /* enable the RDPMC instruction if needed */ 535 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 536 load_cr4(rcr4() | CR4_PCE); 537 538 return 0; 539 } 540 541 /* 542 * Machine dependent actions taken during the context switch out of a 543 * thread. 544 */ 545 546 static int 547 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 548 { 549 (void) pc; 550 (void) pp; /* can be NULL */ 551 552 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ? 553 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0); 554 555 /* always turn off the RDPMC instruction */ 556 load_cr4(rcr4() & ~CR4_PCE); 557 558 return 0; 559 } 560 561 /* 562 * Check if a given allocation is feasible. 563 */ 564 565 static int 566 amd_allocate_pmc(int cpu, int ri, struct pmc *pm, 567 const struct pmc_op_pmcallocate *a) 568 { 569 int i; 570 uint64_t allowed_unitmask, caps, config, unitmask; 571 enum pmc_event pe; 572 const struct pmc_descr *pd; 573 574 (void) cpu; 575 576 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 577 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 578 KASSERT(ri >= 0 && ri < AMD_NPMCS, 579 ("[amd,%d] illegal row index %d", __LINE__, ri)); 580 581 pd = &amd_pmcdesc[ri].pm_descr; 582 583 /* check class match */ 584 if (pd->pd_class != a->pm_class) 585 return EINVAL; 586 587 caps = pm->pm_caps; 588 589 PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps); 590 591 if((ri >= 0 && ri < 6) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_CORE)) 592 return EINVAL; 593 if((ri >= 6 && ri < 12) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_L3_CACHE)) 594 return EINVAL; 595 if((ri >= 12 && ri < 16) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_DATA_FABRIC)) 596 return EINVAL; 597 598 if (strlen(pmc_cpuid) != 0) { 599 pm->pm_md.pm_amd.pm_amd_evsel = 600 a->pm_md.pm_amd.pm_amd_config; 601 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, a->pm_md.pm_amd.pm_amd_config); 602 return (0); 603 } 604 605 pe = a->pm_ev; 606 607 /* map ev to the correct event mask code */ 608 config = allowed_unitmask = 0; 609 for (i = 0; i < amd_event_codes_size; i++) 610 if (amd_event_codes[i].pe_ev == pe) { 611 config = 612 AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code); 613 allowed_unitmask = 614 AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask); 615 break; 616 } 617 if (i == amd_event_codes_size) 618 return EINVAL; 619 620 unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK; 621 if (unitmask & ~allowed_unitmask) /* disallow reserved bits */ 622 return EINVAL; 623 624 if (unitmask && (caps & PMC_CAP_QUALIFIER)) 625 config |= unitmask; 626 627 if (caps & PMC_CAP_THRESHOLD) 628 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK; 629 630 /* set at least one of the 'usr' or 'os' caps */ 631 if (caps & PMC_CAP_USER) 632 config |= AMD_PMC_USR; 633 if (caps & PMC_CAP_SYSTEM) 634 config |= AMD_PMC_OS; 635 if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0) 636 config |= (AMD_PMC_USR|AMD_PMC_OS); 637 638 if (caps & PMC_CAP_EDGE) 639 config |= AMD_PMC_EDGE; 640 if (caps & PMC_CAP_INVERT) 641 config |= AMD_PMC_INVERT; 642 if (caps & PMC_CAP_INTERRUPT) 643 config |= AMD_PMC_INT; 644 645 pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */ 646 647 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config); 648 649 return 0; 650 } 651 652 /* 653 * Release machine dependent state associated with a PMC. This is a 654 * no-op on this architecture. 655 * 656 */ 657 658 /* ARGSUSED0 */ 659 static int 660 amd_release_pmc(int cpu, int ri, struct pmc *pmc) 661 { 662 #ifdef HWPMC_DEBUG 663 const struct amd_descr *pd; 664 #endif 665 struct pmc_hw *phw __diagused; 666 667 (void) pmc; 668 669 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 670 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 671 KASSERT(ri >= 0 && ri < AMD_NPMCS, 672 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 673 674 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 675 676 KASSERT(phw->phw_pmc == NULL, 677 ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 678 679 #ifdef HWPMC_DEBUG 680 pd = &amd_pmcdesc[ri]; 681 if (pd->pm_descr.pd_class == amd_pmc_class) 682 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 683 ("[amd,%d] PMC %d released while active", __LINE__, ri)); 684 #endif 685 686 return 0; 687 } 688 689 /* 690 * start a PMC. 691 */ 692 693 static int 694 amd_start_pmc(int cpu, int ri, struct pmc *pm) 695 { 696 uint64_t config; 697 const struct amd_descr *pd; 698 699 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 700 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 701 KASSERT(ri >= 0 && ri < AMD_NPMCS, 702 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 703 704 pd = &amd_pmcdesc[ri]; 705 706 PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri); 707 708 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 709 ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__, 710 ri, cpu, pd->pm_descr.pd_name)); 711 712 /* turn on the PMC ENABLE bit */ 713 config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE; 714 715 PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config); 716 717 wrmsr(pd->pm_evsel, config); 718 return 0; 719 } 720 721 /* 722 * Stop a PMC. 723 */ 724 725 static int 726 amd_stop_pmc(int cpu, int ri, struct pmc *pm) 727 { 728 const struct amd_descr *pd; 729 uint64_t config; 730 int i; 731 732 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 733 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 734 KASSERT(ri >= 0 && ri < AMD_NPMCS, 735 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 736 737 pd = &amd_pmcdesc[ri]; 738 739 KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel), 740 ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped", 741 __LINE__, ri, cpu, pd->pm_descr.pd_name)); 742 743 PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri); 744 745 /* turn off the PMC ENABLE bit */ 746 config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE; 747 wrmsr(pd->pm_evsel, config); 748 749 /* 750 * Due to NMI latency on newer AMD processors 751 * NMI interrupts are ignored, which leads to 752 * panic or messages based on kernel configuration 753 */ 754 755 /* Wait for the count to be reset */ 756 for (i = 0; i < OVERFLOW_WAIT_COUNT; i++) { 757 if (rdmsr(pd->pm_perfctr) & (1 << (pd->pm_descr.pd_width - 1))) 758 break; 759 760 DELAY(1); 761 } 762 763 return 0; 764 } 765 766 /* 767 * Interrupt handler. This function needs to return '1' if the 768 * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed 769 * to sleep or do anything a 'fast' interrupt handler is not allowed 770 * to do. 771 */ 772 773 static int 774 amd_intr(struct trapframe *tf) 775 { 776 int i, error, retval, cpu; 777 uint64_t config, evsel, perfctr; 778 struct pmc *pm; 779 struct amd_cpu *pac; 780 pmc_value_t v; 781 uint32_t active = 0, count = 0; 782 783 cpu = curcpu; 784 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 785 ("[amd,%d] out of range CPU %d", __LINE__, cpu)); 786 787 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf, 788 TRAPF_USERMODE(tf)); 789 790 retval = 0; 791 792 pac = amd_pcpu[cpu]; 793 794 /* 795 * look for all PMCs that have interrupted: 796 * - look for a running, sampling PMC which has overflowed 797 * and which has a valid 'struct pmc' association 798 * 799 * If found, we call a helper to process the interrupt. 800 * 801 * PMCs interrupting at the same time are collapsed into 802 * a single interrupt. Check all the valid pmcs for 803 * overflow. 804 */ 805 806 for (i = 0; i < AMD_CORE_NPMCS; i++) { 807 808 if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL || 809 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 810 continue; 811 } 812 813 /* Consider pmc with valid handle as active */ 814 active++; 815 816 if (!AMD_PMC_HAS_OVERFLOWED(i)) 817 continue; 818 819 retval = 1; /* Found an interrupting PMC. */ 820 821 if (pm->pm_state != PMC_STATE_RUNNING) 822 continue; 823 824 /* Stop the PMC, reload count. */ 825 evsel = amd_pmcdesc[i].pm_evsel; 826 perfctr = amd_pmcdesc[i].pm_perfctr; 827 v = pm->pm_sc.pm_reloadcount; 828 config = rdmsr(evsel); 829 830 KASSERT((config & ~AMD_PMC_ENABLE) == 831 (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE), 832 ("[amd,%d] config mismatch reg=0x%jx pm=0x%jx", __LINE__, 833 (uintmax_t)config, (uintmax_t)pm->pm_md.pm_amd.pm_amd_evsel)); 834 835 wrmsr(evsel, config & ~AMD_PMC_ENABLE); 836 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v)); 837 838 /* Restart the counter if logging succeeded. */ 839 error = pmc_process_interrupt(PMC_HR, pm, tf); 840 if (error == 0) 841 wrmsr(evsel, config); 842 } 843 844 /* 845 * Due to NMI latency, there can be a scenario in which 846 * multiple pmcs gets serviced in an earlier NMI and we 847 * do not find an overflow in the subsequent NMI. 848 * 849 * For such cases we keep a per-cpu count of active NMIs 850 * and compare it with min(active pmcs, 2) to determine 851 * if this NMI was for a pmc overflow which was serviced 852 * in an earlier request or should be ignored. 853 */ 854 855 if (retval) { 856 DPCPU_SET(nmi_counter, min(2, active)); 857 } else { 858 if ((count = DPCPU_GET(nmi_counter))) { 859 retval = 1; 860 DPCPU_SET(nmi_counter, --count); 861 } 862 } 863 864 if (retval) 865 counter_u64_add(pmc_stats.pm_intr_processed, 1); 866 else 867 counter_u64_add(pmc_stats.pm_intr_ignored, 1); 868 869 PMCDBG1(MDP,INT,2, "retval=%d", retval); 870 return (retval); 871 } 872 873 /* 874 * describe a PMC 875 */ 876 static int 877 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 878 { 879 const struct amd_descr *pd; 880 struct pmc_hw *phw; 881 882 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 883 ("[amd,%d] illegal CPU %d", __LINE__, cpu)); 884 KASSERT(ri >= 0 && ri < AMD_NPMCS, 885 ("[amd,%d] row-index %d out of range", __LINE__, ri)); 886 887 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 888 pd = &amd_pmcdesc[ri]; 889 890 strlcpy(pi->pm_name, pd->pm_descr.pd_name, sizeof(pi->pm_name)); 891 pi->pm_class = pd->pm_descr.pd_class; 892 893 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 894 pi->pm_enabled = TRUE; 895 *ppmc = phw->phw_pmc; 896 } else { 897 pi->pm_enabled = FALSE; 898 *ppmc = NULL; 899 } 900 901 return 0; 902 } 903 904 /* 905 * i386 specific entry points 906 */ 907 908 /* 909 * return the MSR address of the given PMC. 910 */ 911 912 static int 913 amd_get_msr(int ri, uint32_t *msr) 914 { 915 KASSERT(ri >= 0 && ri < AMD_NPMCS, 916 ("[amd,%d] ri %d out of range", __LINE__, ri)); 917 918 *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0; 919 920 return (0); 921 } 922 923 /* 924 * processor dependent initialization. 925 */ 926 927 static int 928 amd_pcpu_init(struct pmc_mdep *md, int cpu) 929 { 930 int classindex, first_ri, n; 931 struct pmc_cpu *pc; 932 struct amd_cpu *pac; 933 struct pmc_hw *phw; 934 935 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 936 ("[amd,%d] insane cpu number %d", __LINE__, cpu)); 937 938 PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu); 939 940 amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC, 941 M_WAITOK|M_ZERO); 942 943 /* 944 * Set the content of the hardware descriptors to a known 945 * state and initialize pointers in the MI per-cpu descriptor. 946 */ 947 pc = pmc_pcpu[cpu]; 948 #if defined(__amd64__) 949 classindex = PMC_MDEP_CLASS_INDEX_K8; 950 #elif defined(__i386__) 951 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? 952 PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7; 953 #endif 954 first_ri = md->pmd_classdep[classindex].pcd_ri; 955 956 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__)); 957 958 for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) { 959 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 960 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n); 961 phw->phw_pmc = NULL; 962 pc->pc_hwpmcs[n + first_ri] = phw; 963 } 964 965 return (0); 966 } 967 968 969 /* 970 * processor dependent cleanup prior to the KLD 971 * being unloaded 972 */ 973 974 static int 975 amd_pcpu_fini(struct pmc_mdep *md, int cpu) 976 { 977 int classindex, first_ri, i; 978 uint32_t evsel; 979 struct pmc_cpu *pc; 980 struct amd_cpu *pac; 981 982 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 983 ("[amd,%d] insane cpu number (%d)", __LINE__, cpu)); 984 985 PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu); 986 987 /* 988 * First, turn off all PMCs on this CPU. 989 */ 990 for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */ 991 evsel = rdmsr(AMD_PMC_EVSEL_0 + i); 992 evsel &= ~AMD_PMC_ENABLE; 993 wrmsr(AMD_PMC_EVSEL_0 + i, evsel); 994 } 995 996 /* 997 * Next, free up allocated space. 998 */ 999 if ((pac = amd_pcpu[cpu]) == NULL) 1000 return (0); 1001 1002 amd_pcpu[cpu] = NULL; 1003 1004 #ifdef HWPMC_DEBUG 1005 for (i = 0; i < AMD_NPMCS; i++) { 1006 KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL, 1007 ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i)); 1008 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i), 1009 ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i)); 1010 } 1011 #endif 1012 1013 pc = pmc_pcpu[cpu]; 1014 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__)); 1015 1016 #if defined(__amd64__) 1017 classindex = PMC_MDEP_CLASS_INDEX_K8; 1018 #elif defined(__i386__) 1019 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 : 1020 PMC_MDEP_CLASS_INDEX_K7; 1021 #endif 1022 first_ri = md->pmd_classdep[classindex].pcd_ri; 1023 1024 /* 1025 * Reset pointers in the MI 'per-cpu' state. 1026 */ 1027 for (i = 0; i < AMD_NPMCS; i++) { 1028 pc->pc_hwpmcs[i + first_ri] = NULL; 1029 } 1030 1031 1032 free(pac, M_PMC); 1033 1034 return (0); 1035 } 1036 1037 /* 1038 * Initialize ourselves. 1039 */ 1040 1041 struct pmc_mdep * 1042 pmc_amd_initialize(void) 1043 { 1044 int classindex, error, i, ncpus; 1045 struct pmc_classdep *pcd; 1046 enum pmc_cputype cputype; 1047 struct pmc_mdep *pmc_mdep; 1048 enum pmc_class class; 1049 int family, model, stepping; 1050 char *name; 1051 1052 /* 1053 * The presence of hardware performance counters on the AMD 1054 * Athlon, Duron or later processors, is _not_ indicated by 1055 * any of the processor feature flags set by the 'CPUID' 1056 * instruction, so we only check the 'instruction family' 1057 * field returned by CPUID for instruction family >= 6. 1058 */ 1059 1060 name = NULL; 1061 family = CPUID_TO_FAMILY(cpu_id); 1062 model = CPUID_TO_MODEL(cpu_id); 1063 stepping = CPUID_TO_STEPPING(cpu_id); 1064 1065 if (family == 0x18) 1066 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "HygonGenuine-%d-%02X-%X", 1067 family, model, stepping); 1068 else 1069 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "AuthenticAMD-%d-%02X-%X", 1070 family, model, stepping); 1071 1072 switch (cpu_id & 0xF00) { 1073 #if defined(__i386__) 1074 case 0x600: /* Athlon(tm) processor */ 1075 classindex = PMC_MDEP_CLASS_INDEX_K7; 1076 cputype = PMC_CPU_AMD_K7; 1077 class = PMC_CLASS_K7; 1078 name = "K7"; 1079 break; 1080 #endif 1081 case 0xF00: /* Athlon64/Opteron processor */ 1082 classindex = PMC_MDEP_CLASS_INDEX_K8; 1083 cputype = PMC_CPU_AMD_K8; 1084 class = PMC_CLASS_K8; 1085 name = "K8"; 1086 break; 1087 1088 default: 1089 (void) printf("pmc: Unknown AMD CPU %x %d-%d.\n", cpu_id, (cpu_id & 0xF00) >> 8, model); 1090 return NULL; 1091 } 1092 1093 #ifdef HWPMC_DEBUG 1094 amd_pmc_class = class; 1095 #endif 1096 1097 /* 1098 * Allocate space for pointers to PMC HW descriptors and for 1099 * the MDEP structure used by MI code. 1100 */ 1101 amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC, 1102 M_WAITOK|M_ZERO); 1103 1104 /* 1105 * These processors have two classes of PMCs: the TSC and 1106 * programmable PMCs. 1107 */ 1108 pmc_mdep = pmc_mdep_alloc(2); 1109 1110 pmc_mdep->pmd_cputype = cputype; 1111 1112 ncpus = pmc_cpu_max(); 1113 1114 /* Initialize the TSC. */ 1115 error = pmc_tsc_initialize(pmc_mdep, ncpus); 1116 if (error) 1117 goto error; 1118 1119 /* Initialize AMD K7 and K8 PMC handling. */ 1120 pcd = &pmc_mdep->pmd_classdep[classindex]; 1121 1122 pcd->pcd_caps = AMD_PMC_CAPS; 1123 pcd->pcd_class = class; 1124 pcd->pcd_num = AMD_NPMCS; 1125 pcd->pcd_ri = pmc_mdep->pmd_npmc; 1126 pcd->pcd_width = 48; 1127 1128 /* fill in the correct pmc name and class */ 1129 for (i = 0; i < AMD_NPMCS; i++) { 1130 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name, 1131 sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d", 1132 name, i); 1133 amd_pmcdesc[i].pm_descr.pd_class = class; 1134 } 1135 1136 pcd->pcd_allocate_pmc = amd_allocate_pmc; 1137 pcd->pcd_config_pmc = amd_config_pmc; 1138 pcd->pcd_describe = amd_describe; 1139 pcd->pcd_get_config = amd_get_config; 1140 pcd->pcd_get_msr = amd_get_msr; 1141 pcd->pcd_pcpu_fini = amd_pcpu_fini; 1142 pcd->pcd_pcpu_init = amd_pcpu_init; 1143 pcd->pcd_read_pmc = amd_read_pmc; 1144 pcd->pcd_release_pmc = amd_release_pmc; 1145 pcd->pcd_start_pmc = amd_start_pmc; 1146 pcd->pcd_stop_pmc = amd_stop_pmc; 1147 pcd->pcd_write_pmc = amd_write_pmc; 1148 1149 pmc_mdep->pmd_intr = amd_intr; 1150 pmc_mdep->pmd_switch_in = amd_switch_in; 1151 pmc_mdep->pmd_switch_out = amd_switch_out; 1152 1153 pmc_mdep->pmd_npmc += AMD_NPMCS; 1154 1155 PMCDBG0(MDP,INI,0,"amd-initialize"); 1156 1157 return (pmc_mdep); 1158 1159 error: 1160 if (error) { 1161 free(pmc_mdep, M_PMC); 1162 pmc_mdep = NULL; 1163 } 1164 1165 return (NULL); 1166 } 1167 1168 /* 1169 * Finalization code for AMD CPUs. 1170 */ 1171 1172 void 1173 pmc_amd_finalize(struct pmc_mdep *md) 1174 { 1175 #if defined(INVARIANTS) 1176 int classindex, i, ncpus, pmcclass; 1177 #endif 1178 1179 pmc_tsc_finalize(md); 1180 1181 KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer", 1182 __LINE__)); 1183 1184 #if defined(INVARIANTS) 1185 switch (md->pmd_cputype) { 1186 #if defined(__i386__) 1187 case PMC_CPU_AMD_K7: 1188 classindex = PMC_MDEP_CLASS_INDEX_K7; 1189 pmcclass = PMC_CLASS_K7; 1190 break; 1191 #endif 1192 default: 1193 classindex = PMC_MDEP_CLASS_INDEX_K8; 1194 pmcclass = PMC_CLASS_K8; 1195 } 1196 1197 KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass, 1198 ("[amd,%d] pmc class mismatch", __LINE__)); 1199 1200 ncpus = pmc_cpu_max(); 1201 1202 for (i = 0; i < ncpus; i++) 1203 KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu", 1204 __LINE__)); 1205 #endif 1206 1207 free(amd_pcpu, M_PMC); 1208 amd_pcpu = NULL; 1209 } 1210