1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by the University of Cambridge Computer 6 * Laboratory with support from ARM Ltd. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/pmc.h> 34 #include <sys/pmckern.h> 35 36 #include <machine/pmc_mdep.h> 37 #include <machine/cpu.h> 38 39 #include "opt_acpi.h" 40 41 static int arm64_npmcs; 42 43 struct arm64_event_code_map { 44 enum pmc_event pe_ev; 45 uint8_t pe_code; 46 }; 47 48 /* 49 * Per-processor information. 50 */ 51 struct arm64_cpu { 52 struct pmc_hw *pc_arm64pmcs; 53 }; 54 55 static struct arm64_cpu **arm64_pcpu; 56 57 /* 58 * Interrupt Enable Set Register 59 */ 60 static __inline void 61 arm64_interrupt_enable(uint32_t pmc) 62 { 63 uint32_t reg; 64 65 reg = (1 << pmc); 66 WRITE_SPECIALREG(pmintenset_el1, reg); 67 68 isb(); 69 } 70 71 /* 72 * Interrupt Clear Set Register 73 */ 74 static __inline void 75 arm64_interrupt_disable(uint32_t pmc) 76 { 77 uint32_t reg; 78 79 reg = (1 << pmc); 80 WRITE_SPECIALREG(pmintenclr_el1, reg); 81 82 isb(); 83 } 84 85 /* 86 * Counter Set Enable Register 87 */ 88 static __inline void 89 arm64_counter_enable(unsigned int pmc) 90 { 91 uint32_t reg; 92 93 reg = (1 << pmc); 94 WRITE_SPECIALREG(pmcntenset_el0, reg); 95 96 isb(); 97 } 98 99 /* 100 * Counter Clear Enable Register 101 */ 102 static __inline void 103 arm64_counter_disable(unsigned int pmc) 104 { 105 uint32_t reg; 106 107 reg = (1 << pmc); 108 WRITE_SPECIALREG(pmcntenclr_el0, reg); 109 110 isb(); 111 } 112 113 /* 114 * Performance Monitors Control Register 115 */ 116 static uint32_t 117 arm64_pmcr_read(void) 118 { 119 uint32_t reg; 120 121 reg = READ_SPECIALREG(pmcr_el0); 122 123 return (reg); 124 } 125 126 static void 127 arm64_pmcr_write(uint32_t reg) 128 { 129 130 WRITE_SPECIALREG(pmcr_el0, reg); 131 132 isb(); 133 } 134 135 /* 136 * Performance Count Register N 137 */ 138 static uint32_t 139 arm64_pmcn_read(unsigned int pmc) 140 { 141 142 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 143 144 WRITE_SPECIALREG(pmselr_el0, pmc); 145 146 isb(); 147 148 return (READ_SPECIALREG(pmxevcntr_el0)); 149 } 150 151 static void 152 arm64_pmcn_write(unsigned int pmc, uint32_t reg) 153 { 154 155 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 156 157 WRITE_SPECIALREG(pmselr_el0, pmc); 158 WRITE_SPECIALREG(pmxevcntr_el0, reg); 159 160 isb(); 161 } 162 163 static int 164 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm, 165 const struct pmc_op_pmcallocate *a) 166 { 167 uint32_t config; 168 enum pmc_event pe; 169 170 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 171 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 172 KASSERT(ri >= 0 && ri < arm64_npmcs, 173 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 174 175 if (a->pm_class != PMC_CLASS_ARMV8) { 176 return (EINVAL); 177 } 178 pe = a->pm_ev; 179 180 /* Adjust the config value if needed. */ 181 config = a->pm_md.pm_md_config; 182 if ((a->pm_md.pm_md_flags & PM_MD_RAW_EVENT) == 0) { 183 config = (uint32_t)pe - PMC_EV_ARMV8_FIRST; 184 if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST)) 185 return (EINVAL); 186 } 187 188 switch (a->pm_caps & (PMC_CAP_SYSTEM | PMC_CAP_USER)) { 189 case PMC_CAP_SYSTEM: 190 config |= PMEVTYPER_U; 191 break; 192 case PMC_CAP_USER: 193 config |= PMEVTYPER_P; 194 break; 195 default: 196 /* 197 * Trace both USER and SYSTEM if none are specified 198 * (default setting) or if both flags are specified 199 * (user explicitly requested both qualifiers). 200 */ 201 break; 202 } 203 204 pm->pm_md.pm_arm64.pm_arm64_evsel = config; 205 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config); 206 207 return (0); 208 } 209 210 211 static int 212 arm64_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v) 213 { 214 pmc_value_t tmp; 215 register_t s; 216 int reg; 217 218 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 219 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 220 KASSERT(ri >= 0 && ri < arm64_npmcs, 221 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 222 223 /* 224 * Ensure we don't get interrupted while updating the overflow count. 225 */ 226 s = intr_disable(); 227 tmp = arm64_pmcn_read(ri); 228 reg = (1 << ri); 229 if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) { 230 /* Clear Overflow Flag */ 231 WRITE_SPECIALREG(pmovsclr_el0, reg); 232 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 233 234 /* Reread counter in case we raced. */ 235 tmp = arm64_pmcn_read(ri); 236 } 237 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 238 intr_restore(s); 239 240 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp); 241 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 242 /* 243 * Clamp value to 0 if the counter just overflowed, 244 * otherwise the returned reload count would wrap to a 245 * huge value. 246 */ 247 if ((tmp & (1ull << 63)) == 0) 248 tmp = 0; 249 else 250 tmp = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 251 } 252 *v = tmp; 253 254 return (0); 255 } 256 257 static int 258 arm64_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v) 259 { 260 261 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 262 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 263 KASSERT(ri >= 0 && ri < arm64_npmcs, 264 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 265 266 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 267 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 268 269 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v); 270 271 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 272 arm64_pmcn_write(ri, v); 273 274 return (0); 275 } 276 277 static int 278 arm64_config_pmc(int cpu, int ri, struct pmc *pm) 279 { 280 struct pmc_hw *phw; 281 282 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 283 284 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 285 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 286 KASSERT(ri >= 0 && ri < arm64_npmcs, 287 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 288 289 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 290 291 KASSERT(pm == NULL || phw->phw_pmc == NULL, 292 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 293 __LINE__, pm, phw->phw_pmc)); 294 295 phw->phw_pmc = pm; 296 297 return (0); 298 } 299 300 static int 301 arm64_start_pmc(int cpu, int ri, struct pmc *pm) 302 { 303 uint32_t config; 304 305 config = pm->pm_md.pm_arm64.pm_arm64_evsel; 306 307 /* 308 * Configure the event selection. 309 */ 310 WRITE_SPECIALREG(pmselr_el0, ri); 311 WRITE_SPECIALREG(pmxevtyper_el0, config); 312 313 isb(); 314 315 /* 316 * Enable the PMC. 317 */ 318 arm64_interrupt_enable(ri); 319 arm64_counter_enable(ri); 320 321 return (0); 322 } 323 324 static int 325 arm64_stop_pmc(int cpu, int ri, struct pmc *pm __unused) 326 { 327 /* 328 * Disable the PMCs. 329 */ 330 arm64_counter_disable(ri); 331 arm64_interrupt_disable(ri); 332 333 return (0); 334 } 335 336 static int 337 arm64_release_pmc(int cpu, int ri, struct pmc *pmc) 338 { 339 struct pmc_hw *phw __diagused; 340 341 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 342 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 343 KASSERT(ri >= 0 && ri < arm64_npmcs, 344 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 345 346 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 347 KASSERT(phw->phw_pmc == NULL, 348 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 349 350 return (0); 351 } 352 353 static int 354 arm64_intr(struct trapframe *tf) 355 { 356 int retval, ri; 357 struct pmc *pm; 358 int error; 359 int reg, cpu; 360 361 cpu = curcpu; 362 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 363 ("[arm64,%d] CPU %d out of range", __LINE__, cpu)); 364 365 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *)tf, 366 TRAPF_USERMODE(tf)); 367 368 retval = 0; 369 370 for (ri = 0; ri < arm64_npmcs; ri++) { 371 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 372 if (pm == NULL) 373 continue; 374 /* Check if counter is overflowed */ 375 reg = (1 << ri); 376 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0) 377 continue; 378 /* Clear Overflow Flag */ 379 WRITE_SPECIALREG(pmovsclr_el0, reg); 380 381 isb(); 382 383 retval = 1; /* Found an interrupting PMC. */ 384 385 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 386 387 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 388 continue; 389 390 if (pm->pm_state != PMC_STATE_RUNNING) 391 continue; 392 393 error = pmc_process_interrupt(PMC_HR, pm, tf); 394 if (error) 395 arm64_stop_pmc(cpu, ri, pm); 396 397 /* Reload sampling count */ 398 arm64_write_pmc(cpu, ri, pm, pm->pm_sc.pm_reloadcount); 399 } 400 401 return (retval); 402 } 403 404 static int 405 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 406 { 407 struct pmc_hw *phw; 408 409 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 410 ("[arm64,%d], illegal CPU %d", __LINE__, cpu)); 411 KASSERT(ri >= 0 && ri < arm64_npmcs, 412 ("[arm64,%d] row-index %d out of range", __LINE__, ri)); 413 414 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 415 416 snprintf(pi->pm_name, sizeof(pi->pm_name), "ARMV8-%d", ri); 417 pi->pm_class = PMC_CLASS_ARMV8; 418 419 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 420 pi->pm_enabled = TRUE; 421 *ppmc = phw->phw_pmc; 422 } else { 423 pi->pm_enabled = FALSE; 424 *ppmc = NULL; 425 } 426 427 return (0); 428 } 429 430 static int 431 arm64_get_config(int cpu, int ri, struct pmc **ppm) 432 { 433 434 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 435 436 return (0); 437 } 438 439 static int 440 arm64_pcpu_init(struct pmc_mdep *md, int cpu) 441 { 442 struct arm64_cpu *pac; 443 struct pmc_hw *phw; 444 struct pmc_cpu *pc; 445 uint64_t pmcr; 446 int first_ri; 447 int i; 448 449 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 450 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu)); 451 PMCDBG0(MDP, INI, 1, "arm64-pcpu-init"); 452 453 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC, 454 M_WAITOK | M_ZERO); 455 456 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs, 457 M_PMC, M_WAITOK | M_ZERO); 458 pc = pmc_pcpu[cpu]; 459 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri; 460 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__)); 461 462 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) { 463 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 464 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 465 phw->phw_pmc = NULL; 466 pc->pc_hwpmcs[i + first_ri] = phw; 467 } 468 469 /* 470 * Disable all counters and overflow interrupts. Upon reset they are in 471 * an undefined state. 472 * 473 * Don't issue an isb here, just wait for the one in arm64_pmcr_write() 474 * to make the writes visible. 475 */ 476 WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff); 477 WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff); 478 479 /* Enable unit */ 480 pmcr = arm64_pmcr_read(); 481 pmcr |= PMCR_E; 482 arm64_pmcr_write(pmcr); 483 484 return (0); 485 } 486 487 static int 488 arm64_pcpu_fini(struct pmc_mdep *md, int cpu) 489 { 490 uint32_t pmcr; 491 492 PMCDBG0(MDP, INI, 1, "arm64-pcpu-fini"); 493 494 pmcr = arm64_pmcr_read(); 495 pmcr &= ~PMCR_E; 496 arm64_pmcr_write(pmcr); 497 498 free(arm64_pcpu[cpu]->pc_arm64pmcs, M_PMC); 499 free(arm64_pcpu[cpu], M_PMC); 500 arm64_pcpu[cpu] = NULL; 501 502 return (0); 503 } 504 505 struct pmc_mdep * 506 pmc_arm64_initialize(void) 507 { 508 struct pmc_mdep *pmc_mdep; 509 struct pmc_classdep *pcd; 510 int classes, idcode, impcode; 511 int reg; 512 uint64_t midr; 513 514 reg = arm64_pmcr_read(); 515 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; 516 impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT; 517 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT; 518 519 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); 520 521 /* 522 * Write the CPU model to kern.hwpmc.cpuid. 523 * 524 * We zero the variant and revision fields. 525 * 526 * TODO: how to handle differences between cores due to big.LITTLE? 527 * For now, just use MIDR from CPU 0. 528 */ 529 midr = (uint64_t)(pcpu_find(0)->pc_midr); 530 midr &= ~(CPU_VAR_MASK | CPU_REV_MASK); 531 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr); 532 533 /* 534 * Allocate space for pointers to PMC HW descriptors and for 535 * the MDEP structure used by MI code. 536 */ 537 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(), 538 M_PMC, M_WAITOK | M_ZERO); 539 540 /* One AArch64 CPU class */ 541 classes = 1; 542 543 #ifdef DEV_ACPI 544 /* Query presence of optional classes and set max class. */ 545 if (pmc_cmn600_nclasses() > 0) 546 classes = MAX(classes, PMC_MDEP_CLASS_INDEX_CMN600); 547 if (pmc_dmc620_nclasses() > 0) 548 classes = MAX(classes, PMC_MDEP_CLASS_INDEX_DMC620_C); 549 #endif 550 551 pmc_mdep = pmc_mdep_alloc(classes); 552 553 switch(impcode) { 554 case PMCR_IMP_ARM: 555 switch (idcode) { 556 case PMCR_IDCODE_CORTEX_A76: 557 case PMCR_IDCODE_NEOVERSE_N1: 558 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76; 559 break; 560 case PMCR_IDCODE_CORTEX_A57: 561 case PMCR_IDCODE_CORTEX_A72: 562 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57; 563 break; 564 default: 565 case PMCR_IDCODE_CORTEX_A53: 566 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 567 break; 568 } 569 break; 570 default: 571 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 572 break; 573 } 574 575 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8]; 576 pcd->pcd_caps = ARMV8_PMC_CAPS; 577 pcd->pcd_class = PMC_CLASS_ARMV8; 578 pcd->pcd_num = arm64_npmcs; 579 pcd->pcd_ri = pmc_mdep->pmd_npmc; 580 pcd->pcd_width = 32; 581 582 pcd->pcd_allocate_pmc = arm64_allocate_pmc; 583 pcd->pcd_config_pmc = arm64_config_pmc; 584 pcd->pcd_pcpu_fini = arm64_pcpu_fini; 585 pcd->pcd_pcpu_init = arm64_pcpu_init; 586 pcd->pcd_describe = arm64_describe; 587 pcd->pcd_get_config = arm64_get_config; 588 pcd->pcd_read_pmc = arm64_read_pmc; 589 pcd->pcd_release_pmc = arm64_release_pmc; 590 pcd->pcd_start_pmc = arm64_start_pmc; 591 pcd->pcd_stop_pmc = arm64_stop_pmc; 592 pcd->pcd_write_pmc = arm64_write_pmc; 593 594 pmc_mdep->pmd_intr = arm64_intr; 595 pmc_mdep->pmd_npmc += arm64_npmcs; 596 597 #ifdef DEV_ACPI 598 if (pmc_cmn600_nclasses() > 0) 599 pmc_cmn600_initialize(pmc_mdep); 600 if (pmc_dmc620_nclasses() > 0) { 601 pmc_dmc620_initialize_cd2(pmc_mdep); 602 pmc_dmc620_initialize_c(pmc_mdep); 603 } 604 #endif 605 606 return (pmc_mdep); 607 } 608 609 void 610 pmc_arm64_finalize(struct pmc_mdep *md) 611 { 612 PMCDBG0(MDP, INI, 1, "arm64-finalize"); 613 614 free(arm64_pcpu, M_PMC); 615 } 616